Successive approximation register type analog-digital converter and signal conversion method

Abstract

The application discloses a successive approximation register type analog-digital converter and a signal conversion method. The analog-digital converter comprises a resistive digital-analog converter, a capacitive digital-analog converter, a comparator, a successive approximation logic circuit, a storage circuit and a correction circuit. The resistive digital-analog converter comprises a plurality of resistors and generates a plurality of node voltages. The capacitive digital-analog converter samples an input signal in a first mode and samples a pair of correction sampling signals corresponding to two node voltages of a selected resistor in a second mode. The comparator generates a comparison result according to its output. The successive approximation logic circuit generates a first and a second bit code according to the comparison result in the first mode and generates first information corresponding to the selected resistor in the second mode. The storage circuit stores weight information of each resistor. The correction circuit corrects an original output code according to the first and second bit codes and the weight information to generate a corrected output code. The application can effectively correct non-linear errors caused by element mismatch without adding extra analog circuits, thereby improving the conversion precision of the analog-digital converter.

Description

Technical Field

[0001] This application relates to the field of analog-to-digital converter technology, specifically to a successive approximation register-type analog-to-digital converter and signal conversion method with resistance weight extraction and digital correction functions. Background Technology

[0002] Successive Approximation Register (SAR) analog-to-digital converters (ADCs) are widely used in various signal processing systems due to their advantages such as low power consumption, small size, and the ability to achieve medium to high resolution. To balance resolution and chip area, related technologies can adopt a hybrid architecture, such as using a resistive ADC for high-order conversion and a capacitive ADC for low-order conversion.

[0003] However, due to limitations in semiconductor manufacturing processes, the actual resistance values ​​of resistors in resistive digital-to-analog converters and the actual capacitance values ​​of capacitors in capacitive digital-to-analog converters may deviate from their ideal design values, resulting in component mismatch. Because component mismatch is random, it is difficult to compensate for it with a fixed offset during the circuit design stage, which may worsen the nonlinearity error of the analog-to-digital converter and limit its conversion accuracy.

[0004] While linearity can be improved by adding correction circuitry or performing front-end calibration procedures, such approaches typically increase analog circuit area, power consumption, or test and calibration costs. Summary of the Invention

[0005] This application provides a successive approximation register-type analog-to-digital converter and signal conversion method with resistance weight extraction and digital correction functions, thereby at least partially solving the above-mentioned technical problems.

[0006] In some embodiments, a successive approximation register-type analog-to-digital converter (ADC) includes a resistive ADC, a capacitive ADC, a comparator, successive approximation logic circuitry, a storage circuit, and a correction circuit. The resistive ADC includes multiple resistors that generate multiple node voltages. The capacitive ADC samples an input signal in a normal conversion mode and samples a pair of correction sampling signals in a weight extraction mode, wherein the pair of correction sampling signals corresponds to two node voltages among the multiple node voltages that are associated with a selected resistor among the multiple resistors. The comparator generates a comparison result based on an output of the capacitive ADC. In the normal conversion mode, the successive approximation logic circuitry generates a high-order bit and a low-order bit based on the comparison result, wherein the high-order bit is used to control the resistive ADC, and the low-order bit is used to control the capacitive ADC. The storage circuit stores multiple weight information corresponding to the multiple resistors, wherein in the weight extraction mode, the successive approximation logic circuitry generates a first piece of information among the multiple weight information corresponding to the selected resistor based on the comparison result. In the normal conversion mode, the correction circuit corrects the original output code formed by the high-order code and the low-order code according to the high-order code, the low-order code and the multiple weight information to generate a corrected output code.

[0007] In some embodiments, the signal conversion method includes: Step 1: In a weight extraction mode, for a selected resistor among a plurality of resistors of a resistive digital-to-analog converter, a pair of correction sampling signals corresponding to two node voltages of the selected resistor are sampled by a capacitive digital-to-analog converter, and a difference between the pair of correction sampling signals is converted into a first piece of weight information corresponding to the selected resistor according to a comparison result generated by a comparator based on the pair of correction sampling signals; Step 2: Step 1 is repeated to obtain the plurality of weight information corresponding to the plurality of resistors, and the plurality of weight information is stored in a storage circuit; Step 3: In a normal conversion mode, an original output code formed by a high-order bit code and a low-order bit code is obtained by the resistive digital-to-analog converter, the capacitive digital-to-analog converter and the comparator according to an input signal; and Step 4: The original output code is corrected according to the high-order bit code, the low-order bit code and the plurality of weight information to generate a corrected output code.

[0008] The exemplary embodiments disclosed in this application will be described in detail below with reference to the accompanying drawings, so as to describe the features, implementation and effects of the disclosure of this application. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a schematic diagram of the structure of a successive approximation register-type analog-to-digital converter provided by an exemplary embodiment of this disclosure; Figure 2 This is an exemplary embodiment provided by the present disclosure. Figure 1 A schematic diagram of the structure of a resistive digital-to-analog converter and a capacitive digital-to-analog converter; Figure 3 This is an exemplary embodiment provided by the present disclosure. Figure 2 A schematic diagram of the switching circuit in the diagram; Figure 4A This is an exemplary embodiment provided by the present disclosure. Figure 1 A flowchart illustrating the weight extraction mode of a successive approximation register-type analog-to-digital converter. Figure 4B This is an exemplary embodiment provided by the present disclosure. Figure 1 A flowchart illustrating the process of a successive approximation register-type analog-to-digital converter performing normal conversion mode; Figure 5 This is an exemplary embodiment provided by the present disclosure. Figure 1 A schematic diagram of the operation flow of the correction circuit in the diagram; Figure 6 This is a schematic flowchart of a signal conversion method provided by an exemplary embodiment of this disclosure.

[0011] Explanation of icon numbers: 100. Successive approximation register-type analog-to-digital converter; 110. Resistive digital-to-analog converter; 120. Capacitive digital-to-analog converter; 130. Comparator; 140. Successive approximation logic circuit; 150. Storage circuit; 160. Correction circuit; 170. Register; DO, corrected output code; LSB, low-order bit code; MSB, high-order bit code; SC, extract control word; SO, comparison result; VN, VP, input signals; WI, weight information. Detailed Implementation

[0012] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0013] In this application, "coupled" or "connected" refers to direct physical or electrical contact between two or more components, or indirect physical or electrical contact between two or more components, or mutual operation or interaction between two or more components. The term "circuit" as used in this application refers to a device consisting of at least one transistor and / or at least one active component connected to passive components in a certain manner to process signals.

[0014] It should be noted that the terms used in this application have their common meanings in the art. The definitions of the above terms in general dictionaries and any related discussions in this application are merely illustrative and are not intended to limit the scope and meaning of this application. Similarly, this application is not limited to the various embodiments shown in this specification.

[0015] Figure 1 This is a schematic diagram of a successive approximation register-type analog-to-digital converter 100 according to some embodiments of this application. The successive approximation register-type analog-to-digital converter 100 includes a resistive digital-to-analog converter 110, a capacitive digital-to-analog converter 120, a comparator 130, a successive approximation logic circuit 140, a storage circuit 150, a correction circuit 160, and a register 170. The successive approximation register-type analog-to-digital converter 100 has a normal conversion mode and a weight extraction mode.

[0016] The resistive digital-to-analog converter 110 includes multiple resistors and multiple switches (such as...) Figure 2 (As shown). These resistors are used to generate multiple node voltages. In normal conversion mode, these switches are controlled by the high-order MSB generated by the successive approximation logic circuit 140; in weight extraction mode, these switches are controlled by register 170 or a corresponding control signal to select a reference resistor and / or a selected resistor. The node voltages generated by the resistive digital-to-analog converter 110 (e.g., ...) Figure 2 The multiple node voltages (VR0 to VRn) are transmitted to the capacitive digital-to-analog converter 120 via at least one corresponding switch of the multiple switches.

[0017] The output of the capacitive digital-to-analog converter 120 is coupled to the input of the comparator 130. The comparator 130 generates a comparison result SO based on the output of the capacitive digital-to-analog converter 120 and transmits this result SO to the successive approximation logic circuit 140. In normal conversion mode, the successive approximation logic circuit 140 sequentially generates the high-order bit (MSB) and low-order bit (LSB) based on the comparison result SO. The MSB controls the resistive digital-to-analog converter 110, and the LSB controls the capacitive digital-to-analog converter 120. In weight extraction mode, the successive approximation logic circuit 140 sequentially updates the extraction control word SC based on the comparison result SO and generates the first information (i.e., the weight information of the selected resistor) of multiple weight information WIs.

[0018] In some embodiments, during a transition phase of the weight extraction mode, the successive approximation logic circuit 140 sequentially updates the extraction control word SC, the capacitive digital-to-analog converter 120 switches at least one capacitor in the capacitive digital-to-analog converter 120 to receive a corresponding voltage from a plurality of reference voltages according to the extraction control word SC, and the comparator 130 generates a comparison result SO based on an output generated by the capacitive digital-to-analog converter 120 in response to the extraction control word SC, so that the successive approximation logic circuit 140 determines first information of the selected resistor based on the comparison result SO, and the plurality of reference voltages are the voltages across a reference resistor among the plurality of resistors.

[0019] Storage circuit 150 is coupled to successive approximation logic circuit 140 and stores multiple weight information WI corresponding to multiple resistors in resistive digital-to-analog converter 110. In some embodiments, storage circuit 150 may be implemented by memory, registers, or a combination thereof. Correction circuit 160 is coupled to storage circuit 150 and receives the high-order bit (MSB) and low-order bit (LSB) generated by successive approximation logic circuit 140. In normal conversion mode, correction circuit 160 corrects the original output code formed by the MSB and LSB according to the MSB, LSB, and multiple weight information WI to generate a corrected output code DO. In some embodiments, the combination of the MSB and LSB forms the aforementioned original output code; therefore, correction circuit 160 may also receive this original output code from successive approximation logic circuit 140 and correct it accordingly. In some embodiments, each of successive approximation logic circuit 140 and correction circuit 160 may be implemented by digital logic circuits. In some embodiments, the successive approximation logic circuit 140 and the correction circuit 160 may be integrated into a digital control circuit, but this application is not limited thereto.

[0020] In some embodiments, in normal conversion mode, the correction circuit 160 obtains a resistive conversion correction value corresponding to the resistive digital-to-analog converter 110 based on the high-order bit (MSB) and multiple weight information (WI). In some embodiments, in normal conversion mode, the correction circuit 160 also obtains a capacitive conversion correction value corresponding to the capacitive digital-to-analog converter 120 based on the low-order bit (LSB), the weight information (WI) of a target resistor corresponding to the high-order bit (MSB) among the multiple resistors, and an ideal weight for each of the multiple resistors, and generates a corrected output code DO based on the resistive conversion correction value and the capacitive conversion correction value. In some embodiments, the correction circuit 160 further performs a proportional correction on the sum of the resistive conversion correction value and the capacitive conversion correction value based on the ratio of the sum of the ideal weights of the multiple resistors to the sum of the actual weights of the multiple resistors to generate the corrected output code DO. The operation of the correction circuit 160 will be discussed below in conjunction with... Figure 5 Further explanation.

[0021] Register 170 is used to set the operating mode of the successive approximation register-type analog-to-digital converter 100, allowing it to switch between a normal conversion mode and a weight extraction mode. In other embodiments, the control function of register 170 can also be integrated into the successive approximation logic circuit 140, and the successive approximation logic circuit 140 can directly control the above-mentioned operating mode switching, but this application is not limited to this.

[0022] In weight extraction mode, the actual weights of each resistor in the resistive digital-to-analog converter 110 are determined sequentially and stored as multiple weight information WIs. In normal conversion mode, the correction circuit 160 can use the multiple weight information WIs stored in the storage circuit 150 to digitally correct the original output code formed by the high-order bit code MSB and the low-order bit code LSB, thereby generating a corrected output code DO. In this way, nonlinear errors caused by random component mismatch can be corrected without adding too much additional analog circuitry. Specific related operations will be explained in conjunction with the following figures.

[0023] Figure 2 Provided according to some embodiments of this application Figure 1The diagram shows the structure of a resistive digital-to-analog converter 110 and a capacitive digital-to-analog converter 120. The resistive digital-to-analog converter 110 includes first resistors R1 to nth resistors Rn, which are sequentially connected in series between a reference voltage terminal (receiving the reference voltage VREF) and a ground terminal (receiving the ground voltage), where n can be a positive integer greater than 1. The first resistors R1 to nth resistors Rn are sequentially connected in series to generate multiple node voltages VR0 to VRn, and each resistor in the first resistors R1 to nth resistors Rn is connected between two adjacent nodes corresponding to the multiple node voltages VR0 to VRn. For example, the two ends of the i-th resistor Ri generate node voltage VRi-1 and node voltage VRi, respectively. In one specific embodiment, the resistive digital-to-analog converter 110 may include 32 resistors connected in series (i.e., n is 32), which can correspond to a 5-bit high-order conversion, but this application is not limited to this.

[0024] The resistive digital-to-analog converter 110 also includes a plurality of switches 112 corresponding to the plurality of nodes. The plurality of node voltages VR0 to VRn are transmitted to the capacitive digital-to-analog converter 120 via their respective switches 112. The plurality of switches 112 are controlled by the high-order bit code MSB in normal conversion mode and by the control signal of register 170 in weight extraction mode. In normal conversion mode, by turning on the corresponding switch 112, a selected voltage from the plurality of node voltages VR0 to VRn is output as a high-level reference voltage VREFH and a low-level reference voltage VREFL. In weight extraction mode, by turning on the corresponding two switches 112, a reference resistor (e.g., the i-th resistor Ri) can be selected from the first resistor R1 to the n-th resistor Rn, and the node voltages across the reference resistor (e.g., node voltage VRi and node voltage VRi-1) are output as the high-level reference voltage VREFH and the low-level reference voltage VREFL.

[0025] The capacitive digital-to-analog converter 120 includes two symmetrical capacitor arrays 122 and 124 and multiple switching circuits S1 to St. Each capacitor array 122 (or 124) contains multiple capacitors C1 to Ct and multiple switching circuits S1 to St. The capacitance values ​​of the multiple capacitors C1 to Ct have a binary weighted relationship. The first terminals of the multiple capacitors C1 to Ct are connected to the input terminal of comparator 130. The second terminals of the multiple capacitors C1 to Ct selectively receive an input signal VP (or input signal VN) or a selected voltage (selected by the high-order bit code MSB) from multiple node voltages VR0 to VRn via the multiple switching circuits S1 to St. The multiple switching circuits S1 to St selectively transmit one of the aforementioned signals or voltages to the second terminals of the multiple capacitors C1 to Ct.

[0026] The two inputs of comparator 130 are coupled to capacitor arrays 122 and 124 respectively, and generate a comparison result SO based on the potential difference between the two inputs. Successive approximation logic circuit 140 executes a successive approximation register algorithm based on the comparison result SO to generate the high-order bit (MSB) and low-order bit (LSB). In a specific embodiment, when the resistive digital-to-analog converter 110 has 5-bit resolution and a single capacitor array has 7-bit resolution, the successive approximation register type analog-to-digital converter can achieve an overall resolution of 12 bits. Ideally, under the above conditions, the ideal weight of each resistor from the first resistor R1 to the nth resistor Rn corresponds to the full-scale code number of the capacitor array, i.e., 128, and the sum of the ideal weights of all resistors from the first resistor R1 to the nth resistor Rn corresponds to 4096 (i.e., 32). 128).

[0027] Figure 3 Provided according to some embodiments of this application Figure 2 A schematic diagram of the switching circuit St in the diagram. For ease of explanation, Figure 3 The following explanation uses the switching circuit St corresponding to capacitor Ct as an example. It should be understood that the implementation methods for other switching circuits can be referred to... Figure 3 Understood. In some embodiments, the switching circuit St is used to form a sampling path and a reference voltage transmission path. Specifically, the switching circuit St may include a first switch SW1, a second switch SW2, and a third switch SW3. In some embodiments, the first switch SW1, the second switch SW2, and the third switch SW3 may be controlled by an internal control signal in register 170.

[0028] The first switch SW1 is used to determine whether the second terminal of capacitor Ct is connected to sampling path P1 or reference voltage transmission path P2. When the first switch SW1 is switched to sampling path P1, the successive approximation register type analog-to-digital converter 100 is in the sampling stage. When the first switch SW1 is switched to reference voltage transmission path P2, the successive approximation register type analog-to-digital converter 100 is in the conversion stage.

[0029] The second switch SW2 is set in sampling path P1 and can select the sampling target during the sampling phase. In normal conversion mode, the second switch SW2 transmits the input signal VP (or input signal VN) to the second terminal of capacitor Ct. In weight extraction mode, the second switch SW2 transmits one of the corresponding two node voltages (equivalent to a pair of correction sampling signals) across the selected resistor to the second terminal of capacitor Ct. The third switch SW3 is set in reference voltage transmission path P2. Figure 3As shown, the multiple reference voltages used in the conversion stage are the high-level reference voltage VREFH and the low-level reference voltage VREFL generated by the resistive digital-to-analog converter 110. The third switch SW3 transmits one corresponding reference voltage (determined by the low-order code LSB in the normal conversion mode and by the extraction control word SC in the weight extraction mode) from the high-level reference voltage VREFH and the low-level reference voltage VREFL to the second terminal of the capacitor Ct. Specifically, in the normal conversion mode, two corresponding switches 112 in the resistive digital-to-analog converter 110 are turned on according to the high-order code MSB to output two corresponding node voltages from multiple node voltages VR0 to VRn as the high-level reference voltage VREFH and the low-level reference voltage VREFL (i.e., the multiple reference voltages used in the conversion stage of the normal conversion mode). In weighted extraction mode, the two corresponding switches 112 in the resistive digital-to-analog converter 110 are turned on according to the control signal of the register 170, so as to output the two node voltages VRi and VRi-1 on both ends of the selected reference resistor (e.g., resistor Ri) as high-level reference voltage VREFH and low-level reference voltage VREFL, respectively. The capacitive digital-to-analog converter 120 then switches the received reference voltage according to the extraction control word SC.

[0030] Accordingly, it can be understood that during the sampling phase of normal conversion mode, the capacitive digital-to-analog converter 120 samples the input signals VP and VN via sampling path P1. During the conversion phase of normal conversion mode, the capacitive digital-to-analog converter 120 receives at least one node voltage specified by the high-order bit code MSB from a plurality of node voltages via reference voltage transmission path P2, so that the capacitive digital-to-analog converter 120 converts the input signals VP and VN. Furthermore, during the sampling phase of weight extraction mode, the capacitive digital-to-analog converter 120 samples the pair of correction sampling signals (equivalent to the node voltages across the selected resistor) via sampling path P1. During the conversion phase of weight extraction mode, the capacitive digital-to-analog converter 120 selectively receives a plurality of reference voltages (which are two node voltages related to the reference resistor Ri, for example, two node voltages VRi and VRi-1 across the reference resistor Ri) via reference voltage transmission path P2 according to the extraction control word SC.

[0031] Figure 4A Provided according to some embodiments of this application Figure 1 The flowchart illustrates the operation of the successive approximation register-type analog-to-digital converter 100 in weight extraction mode. In some embodiments, in weight extraction mode, the actual weights of each resistor in the resistive digital-to-analog converter 110 are determined sequentially.

[0032] In step S401, before weight extraction, one of the first resistors R1 to the nth resistor Rn is used as a reference resistor, and the two node voltages across this reference resistor are used as the high-level reference voltage VREFH and the low-level reference voltage VREFL, respectively. For example, the reference resistor is set to the i-th resistor Ri, and the node voltages VRi and VRi-1 across the i-th resistor Ri are output as the high-level reference voltage VREFH and the low-level reference voltage VREFL, respectively. Furthermore, throughout the entire weight extraction process, the high-level reference voltage VREFH and the low-level reference voltage VREFL remain constant; that is, the reference resistor is fixed after selection. When extracting the weight information WI of different resistors, only the selected resistor (i.e., the resistor whose weight is to be measured) is changed, and the input signals VP and VN transmitted to the sampling path are adjusted to the node voltages across the selected resistor. In this way, the weight of each resistor can be measured using the same reference resistor as a reference. In some embodiments, the reference resistor is used to provide a fixed reference voltage in the weight extraction mode, while the selected resistor refers to the resistor from which weight information is currently being extracted; the reference resistor and the selected resistor may be the same resistor or different resistors.

[0033] In step S402, register 170 sets the successive approximation register-type analog-to-digital converter 100 to enter weight extraction mode. In step S403, during the sampling phase, the corresponding multiple switches 112 are turned on to select a resistor from the first resistor R1 to the nth resistor Rn as the selected resistor. The first switch SW1 opens the sampling path P1, and the second switch SW2 receives the node voltages across the selected resistor and uses these node voltages as input signals VP and VN, causing the capacitive digital-to-analog converter 120 to sample the node voltages across the selected resistor via the sampling path P1. Under this condition, the two node voltages across the selected resistor can be used as input signals VP and VN (forming a pair of correction sampling signals), and the difference between the pair of correction sampling signals corresponds to the weight of the selected resistor.

[0034] In step S404, during the conversion phase, the first switch SW1 conducts the reference voltage transmission path P2, and the third switch SW3 receives the two node voltages across the reference resistor as the high-level reference voltage VREFH and the low-level reference voltage VREFL. This allows the successive approximation register-type analog-to-digital converter 100 to perform analog-to-digital conversion on the sampled node voltages across the selected resistor to generate the extraction control word SC. Specifically, during the conversion phase, the comparator 130 generates a comparison result SO based on the currently sampled node voltages across the selected resistor (i.e., a pair of correction sampling signals), and the successive approximation logic circuit 140 updates the extraction control word SC sequentially based on the comparison result SO. The capacitive digital-to-analog converter 120 switches the received reference voltage based on the extraction control word SC, causing the comparator 130 to update the comparison result SO. Thus, the successive approximation logic circuit 140 updates the extraction control word SC sequentially based on the comparison result SO until the extraction control word SC corresponds to the difference between the pair of correction sampling signals, and the final value of the extraction control word SC is used as the weight information WI of the selected resistor.

[0035] That is, in the weight extraction mode, one of the first resistors R1 to the nth resistor Rn is selected as the selected resistor. The capacitive digital-to-analog converter 120 samples the pair of correction sampling signals, and the successive approximation logic circuit 140 converts a difference between the pair of correction sampling signals into weight information for the selected resistor based on the comparison result SO corresponding to the pair of correction sampling signals. The above operation process is illustrated below with a specific example. If the first resistor R1 is used as the reference resistor, the high-level reference voltage VREFH is fixed as the node voltage VR1, and the low-level reference voltage VREFL is fixed as the node voltage VR0. When extracting the weight of the first resistor R1, the two switches 112 connected to the first resistor R1 are turned on, so that the node voltage VR1 can be output as the input signal VP and the node voltage VR0 can be output as the input signal VN. Similarly, when extracting the weight of the second resistor R2, the high-level reference voltage VREFH and the low-level reference voltage VREFL remain unchanged, while the two switches connected to the second resistor R2 are turned on, so that the node voltage VR2 can be output as the input signal VP and the node voltage VR1 can be output as the input signal VN; the extraction method for the other resistors is similar.

[0036] In step S405, the successive approximation logic circuit 140 writes the weight information WI into the storage circuit 150. In step S406, the successive approximation logic circuit 140 determines whether the weight information WI for all resistors has been determined. If not, step S408 is executed to select the next resistor as the selected resistor, and step S403 is executed again. If yes, step S407 is executed. In step S407, the storage circuit 150 has stored multiple weight information WIs corresponding to the multiple resistors respectively. Under this condition, the multiple weight information WIs can be used for subsequent correction of the normal conversion mode.

[0037] Figure 4B Provided according to some embodiments of this application Figure 1 The flowchart illustrates the operation of the successive approximation register-type analog-to-digital converter 100 in normal conversion mode. In normal conversion mode, the converter 100 performs analog-to-digital conversion on the input signals VP and VN, and calibrates the conversion result using the aforementioned extracted weight information WI to generate an accurate digital output.

[0038] In step S410, during the sampling phase, register 170 sets the successive approximation register-type analog-to-digital converter 100 to enter normal conversion mode, the first switch SW1 turns on the sampling path P1, and the second switch SW2 selects to receive the input signal VP and the input signal VN, so that the capacitive digital-to-analog converter 120 samples the input signal VP and the input signal VN.

[0039] In step S411, during the conversion stage, the successive approximation register-type analog-to-digital converter 100 performs analog-to-digital conversion on the sampled input signals VP and VN to generate a high-order bit (MSB) and a low-order bit (LSB) to form the original output code. Specifically, the successive approximation logic circuit 140 can sequentially generate the high-order bit (MSB) according to the comparison result SO of the comparator 130 to control the resistive digital-to-analog converter 110, thereby selecting at least one node voltage from the plurality of node voltages. The first switch SW1 conducts the reference voltage transmission path P2, and the third switch SW3 receives the node voltage specified by the high-order bit (MSB), allowing the capacitive digital-to-analog converter 120 to receive the node voltage. Next, the successive approximation logic circuit 140 controls the capacitive digital-to-analog converter 120 again according to the comparison result SO to determine the low-order bit (LSB). In this way, the high-order bit (MSB) and the low-order bit (LSB) can be combined to form the aforementioned original output code.

[0040] That is, in the sampling phase of the normal conversion mode, the capacitive digital-to-analog converter 120 samples the input signal VP and the input signal VN. Then, in the conversion phase of the normal conversion mode, the successive approximation logic circuit 140 controls the resistive digital-to-analog converter 110 according to the comparison result SO to select at least one node voltage from the plurality of node voltages and determine the high-order bit code MSB, and controls the capacitive digital-to-analog converter 120 according to the comparison result SO to determine the low-order bit code LSB.

[0041] In step S412, the correction circuit 160 reads multiple weight information WIs from the storage circuit 150 and performs digital correction on the aforementioned original output code to output the corrected output code DO. For detailed operational logic of the correction stage, please refer to... Figure 5 Explanation.

[0042] Figure 5 Provided according to some embodiments of this application Figure 1 The operation flowchart of the correction circuit 160 is shown below. In step S501, the correction circuit 160 distinguishes the original output code into the high-order code MSB (whose decimal value is denoted as x) and the low-order code LSB (whose value is denoted as y), wherein the high-order code MSB is obtained by the switching resistor digital-to-analog converter 110 and the low-order code LSB is obtained by the switching capacitor digital-to-analog converter 120.

[0043] In step S502, the correction circuit 160 obtains the corresponding number of resistors x according to the high-order code MSB, and sums the weight information WI corresponding to each resistor from the first resistor R1 to the x-th resistor Rx to determine the resistive conversion correction value (denoted as CODERDAC) corresponding to the resistive digital-to-analog converter 110. In some embodiments, when the value x is 0, the resistive conversion correction value CODERDAC can be 0, and the target resistor corresponding to the low-order code LSB can be the first resistor R1.

[0044] In step S503, the correction circuit 160 multiplies the low-order code LSB by a weight ratio z to determine the capacitive conversion correction value (denoted as CODECDAC) corresponding to the capacitive digital-to-analog converter 120. The weight ratio z is the ratio of the weight information WI of a target resistor corresponding to the high-order code MSB (e.g., if the decimal value of the high-order code MSB is x, then the target resistor is the (x+1)th resistor Rx+1) to the ideal weight. That is, CODECDAC = y × z, where z is the actual weight of the (x+1)th resistor Rx+1 divided by the ideal weight, and the actual weight is represented by the weight information WI. For example, continuing the previous example, when a capacitor array corresponds to 7 bits, the ideal weight of the resistor is 128; if the equivalent code value of the low-order code LSB is 127.5, the weight ratio z is the actual weight of the resistor Rx+1 divided by 128, and the capacitive conversion correction value is 127.5 multiplied by the weight ratio z.

[0045] In step S504, the correction circuit 160 scales the sum of the aforementioned resistive conversion correction value CODERDAC and capacitive conversion correction value CODECDAC by a scaling factor k, and takes the nearest integer of the scaling result to generate the corrected output code DO. The scaling factor k is the ratio of the ideal weight sum of the first resistor R1 to the nth resistor Rn to the actual weight sum of the plurality of resistors. For example, in the aforementioned example, the ideal weight sum is 4096.

[0046] In some embodiments, the corrected output code DO can be expressed as DO = round[(CODERDAC + CODECDAC) × k]. By replacing the ideal weights with the actual weights of each resistor in the above calculation, the nonlinear error caused by random mismatch in the resistive digital-to-analog converter 110 can be calibrated in the digital domain, thereby improving the linearity of the output data generated by the successive approximation register-type analog-to-digital converter 100.

[0047] Figure 6 This is a schematic flowchart of a signal conversion method 600 provided in this application. In some embodiments, the signal conversion method 600 may be performed by the aforementioned successive approximation register-type analog-to-digital converter 100, but this application is not limited thereto.

[0048] In step S610, in a weight extraction mode, for a selected resistor among a plurality of resistors of a resistive digital-to-analog converter, a pair of correction sampling signals corresponding to the two node voltages of the selected resistor are sampled by a capacitive digital-to-analog converter, and a difference between the pair of correction sampling signals is converted into a first information corresponding to the selected resistor among a plurality of weight information based on a comparison result generated by a comparator based on the pair of correction sampling signals.

[0049] In step S620, step S610 is repeated to obtain the weight information corresponding to the plurality of resistors respectively, and the weight information is stored in a storage circuit.

[0050] In step S630, in a normal conversion mode, the resistive digital-to-analog converter, the capacitive digital-to-analog converter, and the comparator obtain an original output code formed by a high-order code and a low-order code based on an input signal.

[0051] In step S640, the original output code is corrected based on the high-order code, the low-order code, and the multiple weight information to generate a corrected output code.

[0052] The above operations can be understood by referring to the descriptions of the foregoing embodiments, and therefore will not be repeated here. Figure 4A , Figure 4B , Figure 5 and Figure 6 The operations described herein are merely examples and are not intended to limit the execution to the order shown in these examples. Without departing from the mode and scope of operation of the various embodiments of this application, these operations may be appropriately added, replaced, omitted, executed in a different order, or executed simultaneously or partially simultaneously.

[0053] In summary, the successive approximation register-type analog-to-digital converter 100 and signal conversion method 600 provided in some embodiments of this application can extract the actual weights of each resistor in a resistive digital-to-analog converter by reusing a capacitive digital-to-analog converter, and digitally correct the original output code using this weight information during normal conversion. In this way, nonlinear errors caused by random component mismatch can be effectively corrected without significantly increasing additional analog circuitry, thereby improving the conversion accuracy and linearity of the analog-to-digital converter.

[0054] However, these embodiments are not intended to limit this application. Those skilled in the art can make variations to the technical features of this application based on its explicit or implicit content. All such variations may fall within the scope of patent protection sought by this application. In other words, the scope of patent protection of this application shall be determined by the scope of the patent application as defined in this specification.

Claims

1. A successive approximation register-type analog-to-digital converter, characterized in that, Include: A resistive digital-to-analog converter comprising multiple resistors, wherein the multiple resistors generate multiple node voltages; A capacitive digital-to-analog converter samples an input signal in a normal conversion mode and samples a pair of correction sampling signals in a weight extraction mode, wherein the pair of correction sampling signals respectively correspond to two node voltages among the plurality of node voltages that are related to a selected resistor among the plurality of resistors; A comparator that generates a comparison result based on an output of the capacitive digital-to-analog converter; A successive approximation logic circuit generates a high-order code and a low-order code based on the comparison result in the normal conversion mode, wherein the high-order code is used to control the resistive digital-to-analog converter and the low-order code is used to control the capacitive digital-to-analog converter. A storage circuit stores multiple weight information corresponding to the plurality of resistors, wherein the successive approximation logic circuit generates, in the weight extraction mode, a first piece of information corresponding to the selected resistor from the plurality of weight information based on the comparison result; and A correction circuit, in the normal conversion mode, corrects an original output code formed by the high-order code and the low-order code according to the high-order code, the low-order code and the multiple weight information, so as to generate a corrected output code.

2. The successive approximation register-type analog-to-digital converter according to claim 1, characterized in that, The plurality of resistors are connected in series to generate the plurality of node voltages, and each of the plurality of resistors is connected between two adjacent nodes corresponding to the plurality of node voltages.

3. The successive approximation register-type analog-to-digital converter according to claim 1, characterized in that, In a sampling phase of the normal conversion mode, the capacitive digital-to-analog converter samples the input signal, and in a conversion phase of the normal conversion mode, the successive approximation logic circuit controls the resistive digital-to-analog converter according to the comparison result to select at least one node voltage from the plurality of node voltages and determine the high-order code, and controls the capacitive digital-to-analog converter according to the comparison result to determine the low-order code.

4. The successive approximation register-type analog-to-digital converter according to claim 1, characterized in that, In the weight extraction mode, one of the plurality of resistors is selected as the selected resistor, the capacitive digital-to-analog converter samples the pair of correction sampling signals, and the successive approximation logic circuit converts a difference between the pair of correction sampling signals into the first information based on the comparison result corresponding to the pair of correction sampling signals.

5. The successive approximation register-type analog-to-digital converter according to claim 4, characterized in that, In a transition phase of the weight extraction mode, the successive approximation logic circuit sequentially updates an extraction control word, the capacitive digital-to-analog converter switches at least one capacitor in the capacitive digital-to-analog converter according to the extraction control word to receive a corresponding voltage from a plurality of reference voltages, and the comparator generates the comparison result based on an output generated by the capacitive digital-to-analog converter in response to the extraction control word, so that the successive approximation logic circuit determines the first information of the selected resistor based on the comparison result, and the plurality of reference voltages are the voltages across a reference resistor from the plurality of resistors.

6. The successive approximation register-type analog-to-digital converter according to claim 1, characterized in that, The capacitive digital-to-analog converter includes: A switching circuit is used to form a sampling path and a reference voltage transmission path; In one sampling phase of the normal conversion mode, the capacitive digital-to-analog converter samples the input signal via the sampling path, and in one conversion phase of the normal conversion mode, the capacitive digital-to-analog converter receives at least one node voltage specified by the high-order code from the plurality of node voltages via the reference voltage transmission path, so that the capacitive digital-to-analog converter converts the input signal. In a sampling phase of the weight extraction mode, the capacitive digital-to-analog converter samples the pair of corrected sampling signals via the sampling path, and in a conversion phase of the weight extraction mode, the capacitive digital-to-analog converter selectively receives one of a plurality of reference voltages via the reference voltage transmission path according to an extraction control word, wherein the plurality of reference voltages are two node voltages related to a reference resistor among the plurality of resistors.

7. The successive approximation register-type analog-to-digital converter according to claim 1, characterized in that, In the normal conversion mode, the correction circuit obtains a resistive conversion correction value corresponding to the resistive digital-to-analog converter based on the high-order code and the multiple weight information.

8. The successive approximation register-type analog-to-digital converter according to claim 7, characterized in that, In the normal conversion mode, the correction circuit also obtains a capacitive conversion correction value corresponding to the capacitive digital-to-analog converter based on the low-order code, the weight information of a target resistor corresponding to the high-order code among the plurality of resistors, and the ideal weight of each of the plurality of resistors, and generates the corrected output code based on the resistive conversion correction value and the capacitive conversion correction value.

9. The successive approximation register-type analog-to-digital converter according to claim 8, characterized in that, The correction circuit further performs a proportional correction on the sum of the resistive conversion correction value and the capacitive conversion correction value based on the ratio of the ideal weight sum of the plurality of resistors to the actual weight sum of the plurality of resistors, so as to generate the corrected output code.

10. A signal conversion method applied to a successive approximation register-type analog-to-digital converter, the successive approximation register-type analog-to-digital converter comprising a resistive digital-to-analog converter, a capacitive digital-to-analog converter, a comparator, a successive approximation logic circuit, and a correction circuit, characterized in that, The method includes: Step 1: In a weighted extraction mode, for a selected resistor among the multiple resistors of the resistive digital-to-analog converter, a pair of corrected sampling signals corresponding to the two node voltages of the selected resistor are sampled by the capacitive digital-to-analog converter. Based on a comparison result generated by the comparator based on the pair of corrected sampling signals, a difference between the pair of corrected sampling signals is converted into a first piece of information corresponding to the selected resistor among multiple weight information. Step 2: Repeat step 1 to obtain the weight information corresponding to the multiple resistors, and store the weight information in a storage circuit; Step 3: In a normal conversion mode, the resistive digital-to-analog converter, the capacitive digital-to-analog converter, and the comparator obtain an original output code formed by a high-order bit and a low-order bit based on an input signal; and Step 4: Based on the high-order code, the low-order code, and the multiple weight information, correct the original output code to generate a corrected output code.

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