Analog-to-digital converter, control method of analog-to-digital converter, computer readable storage medium and computer program product

Abstract

The application provides an analog-to-digital converter, a control method of the analog-to-digital converter, a computer readable storage medium and a computer program product. The analog-to-digital converter comprises a voltage compression module, and the voltage compression module comprises a common-mode circuit comprising a first switch, a plurality of second switches, a first capacitor, a second capacitor and a third capacitor. The first switch is located on a connection line between the second capacitor, one second switch is located on a connection line between a first reference voltage input end and one end of the first capacitor, one second switch is located on a connection line between the other end of the first capacitor and the first input end, one second switch is located on a connection line between one end of the third capacitor and the second input end, one second switch is located on a connection line between a second reference voltage input end and the other end of the third capacitor, one end of the first capacitor is connected with a first output end, and the other end of the third capacitor is connected with a second output end, thereby solving the problem of low precision of the analog-to-digital converter caused by the absence of a common-mode voltage.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and more specifically, to an analog-to-digital converter, a control method for the analog-to-digital converter, a computer-readable storage medium, and a computer program product. Background Technology

[0002] Currently, existing solutions include using resistors and capacitors to divide the voltage to the capacitor array to increase the input range, or using additional circuit modules to add to the core module of the analog-to-digital converter to increase its input range, or disregarding the error caused by the input range and using digital circuits for code value calibration instead.

[0003] However, the solutions in the existing technology / related patents have the following problems:

[0004] In existing solutions, if a simple capacitor-resistor voltage divider scheme is used, it lacks a stable common-mode voltage. Therefore, when the analog-to-digital converter (ADC) uses a low-voltage input, the internal comparator operates at a low speed, resulting in data errors and a decrease in the ADC's signal-to-noise ratio.

[0005] Existing solutions using complex pure digital nonlinear calibration schemes require at least one calibration analog-to-digital converter to provide the necessary digital calibration information. Therefore, the cost of this scheme is double that of traditional methods. Furthermore, pure digital nonlinear calibration, being detached from the circuit design itself and relying on mathematical fitting, can only approximate the data to a certain extent, rather than representing the most stable circuit data, resulting in larger errors compared to hybrid analog-to-digital calibration schemes. Summary of the Invention

[0006] The main objective of this application is to provide an analog-to-digital converter, an analog-to-digital converter control method, a computer-readable storage medium, and a computer program product, so as to at least solve the problem of low accuracy of analog-to-digital converters due to the lack of common-mode voltage in the prior art.

[0007] To achieve the above objectives, according to one aspect of this application, an analog-to-digital converter (ADC) is provided, the ADC including a voltage scaling module, the voltage scaling module including: a common-mode circuit including a first switch, a plurality of second switches, a first capacitor, a second capacitor, and a third capacitor, the first switch being located on the connection line between the two ends of the second capacitor, one second switch being located on the connection line between a first reference voltage input terminal and one end of the first capacitor, one second switch being located on the connection line between the other end of the first capacitor and a first input terminal, one second switch being located on the connection line between one end of the third capacitor and a second input terminal, one second switch being located on the connection line between a second reference voltage input terminal and the other end of the third capacitor, one end of the first capacitor being connected to a first output terminal, the other end of the third capacitor being connected to a second output terminal, and the capacitances of the first capacitor and the third capacitor being equal.

[0008] Optionally, the analog-to-digital converter further includes: a calibration circuit comprising a plurality of third switches and a plurality of fourth switches, wherein one third switch is located on the connection line between a third reference voltage input terminal and one end of the first capacitor, one third switch is located on the connection line between one end of the third capacitor and a ground terminal, one third switch is located on the connection line between the other end of the first capacitor and the first output terminal, one third switch is located on the connection line between a fourth reference voltage input terminal and the second output terminal, one fourth switch is located on the connection line between a fifth reference voltage input terminal and the other end of the third capacitor, one fourth switch is located on the connection line between the other end of the first capacitor and a ground terminal, one fourth switch is located on the connection line between one end of the third capacitor and the second output terminal, and one fourth switch is located on the connection line between a sixth reference voltage input terminal and the first output terminal.

[0009] Optionally, the analog-to-digital converter further includes a plurality of calibration switches, one first switch connected in series with one calibration switch, one second switch connected in series with one calibration switch, one calibration switch located on the connection line between the first output terminal and one end of the first capacitor, and one calibration switch located on the connection line between the second output terminal and the other end of the third capacitor.

[0010] According to another aspect of this application, a control method for an analog-to-digital converter is provided, applicable to the digital-to-analog converter, the method comprising: controlling each of the second switches to close and the first switch to open, such that an analog voltage signal is input to the first input terminal and the second input terminal; controlling each of the second switches to close and the first switch to open, such that a common-mode analog voltage signal is output to the first output terminal and the second output terminal.

[0011] Optionally, the analog-to-digital converter further includes a calibration circuit, which includes multiple third switches and multiple fourth switches. One third switch is located on the connection line between the third reference voltage input terminal and one end of the first capacitor; one third switch is located on the connection line between one end of the third capacitor and the ground terminal; one third switch is located on the connection line between the other end of the first capacitor and the first output terminal; one third switch is located on the connection line between the fourth reference voltage input terminal and the second output terminal; one fourth switch is located on the connection line between the fifth reference voltage input terminal and the other end of the third capacitor; and one fourth switch is located on the connection line between the other end of the first capacitor and the ground terminal. On the connection line of the terminal, one of the fourth switches is located on the connection line between one end of the third capacitor and the second output terminal, and another of the fourth switches is located on the connection line between the sixth reference voltage input terminal and the first output terminal. Before controlling each of the second switches to close and the first switch to open, the method further includes: controlling each of the third switches to close and each of the fourth switches to open, and calculating the mismatch coefficient of the common-mode analog voltage signal output by the first output terminal to obtain a first mismatch coefficient; controlling each of the third switches to open and each of the fourth switches to close, and calculating the mismatch coefficient of the common-mode analog voltage signal output by the second output terminal to obtain a second mismatch coefficient.

[0012] Optionally, the method further includes: calibrating the common-mode analog voltage signal output from the first output terminal using the first mismatch coefficient to obtain a first calibrated common-mode analog voltage signal; and calibrating the common-mode analog voltage signal output from the second output terminal using the second mismatch coefficient to obtain a second calibrated common-mode analog voltage signal.

[0013] Optionally, calculating the mismatch coefficient of the common-mode analog voltage signal output from the first output terminal to obtain the first mismatch coefficient includes: obtaining the voltage value output by the analog-to-digital converter when each of the third switches is closed and each of the fourth switches is open to obtain a first actual voltage value; obtaining the voltage value of the analog-to-digital converter output when each of the third switches is closed and each of the fourth switches is open to obtain a first theoretical voltage value; and calculating the ratio of the first actual voltage value to the first theoretical voltage value to obtain the first mismatch coefficient.

[0014] Optionally, calculating the mismatch coefficient of the common-mode analog voltage signal output from the second output terminal to obtain the second mismatch coefficient includes: obtaining the voltage value output by the analog-to-digital converter when each of the third switches is open and each of the fourth switches is closed to obtain the second actual voltage value; obtaining the voltage value of the analog-to-digital converter output when each of the third switches is open and each of the fourth switches is closed to obtain the second theoretical voltage value; and calculating the ratio of the second actual voltage value to the second theoretical voltage value to obtain the second mismatch coefficient.

[0015] According to another aspect of this application, a computer-readable storage medium is provided, the computer-readable storage medium including a stored program, wherein, when the program is executed, it controls the device on which the computer-readable storage medium is located to perform any of the methods described.

[0016] According to another aspect of this application, a computer program product is provided, comprising a computer program that, when executed by a processor, implements any of the methods described.

[0017] By applying the technical solution of this application, in the above-mentioned analog-to-digital converter, when multiple second switches are closed and the first switch is open, analog voltages are input to the first input terminal and the second input terminal, making the voltage of the second capacitor equal to the input analog voltage. When multiple second switches are open and the first switch is closed, the second capacitor is short-circuited, and charge transfer occurs between the first capacitor and the third capacitor, making the outputs of the first input terminal and the second input terminal symmetrical to the reference voltage. This ensures that the first output terminal and the second output terminal output a common-mode analog voltage signal, solving the problem of low accuracy of analog-to-digital converters due to the lack of common-mode voltage in the prior art. Attached Figure Description

[0018] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0019] Figure 1 A structural block diagram of an analog-to-digital converter provided in an embodiment of this application is shown;

[0020] Figure 2 A circuit diagram of a prior art voltage scaling module is shown;

[0021] Figure 3 A circuit diagram of a voltage scaling module according to an embodiment of this application is shown;

[0022] Figure 4 A flowchart of a control method for an analog-to-digital converter provided in an embodiment of this application is shown;

[0023] Figure 5 A timing diagram of a voltage scaling module provided according to an embodiment of this application is shown;

[0024] Figure 6 A circuit diagram is shown with the calibration switch of a voltage scaling module open according to an embodiment of this application;

[0025] Figure 7 It shows Figure 6The circuit diagram showing the third switch closed and the fourth switch open.

[0026] Figure 8 It shows Figure 6 The circuit diagram showing the third switch open and the fourth switch closed.

[0027] Figure 9 A circuit diagram is shown showing the calibration switch closed, the third switch open, and the fourth switch open of a voltage scaling module according to an embodiment of this application;

[0028] Figure 10 It shows Figure 9 A circuit diagram showing the first switch closed and the second switch open.

[0029] Figure 11 It shows Figure 9 A circuit diagram showing the first switch open and the second switch closed.

[0030] Figure 12 It shows Figure 9 A schematic diagram of the circuit simulation results;

[0031] Figure 13 A schematic diagram of a control device for an analog-to-digital converter provided in an embodiment of this application is shown. Detailed Implementation

[0032] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0033] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0034] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0035] As described in the background section, the lack of a common-mode voltage in the prior art leads to low accuracy of analog-to-digital converters. To address this issue, embodiments of this application provide an analog-to-digital converter, a control method for the analog-to-digital converter, a computer-readable storage medium, and a computer program product.

[0036] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0037] Commonly used analog-to-digital converters in industry, such as Figure 1 As shown, its analog-to-digital converter consists of an analog-to-digital converter input module, a voltage scaling module, a sample-and-hold module, a digital-to-analog converter, a reference voltage, a comparator, a successive approximation switch control module, and an analog-to-digital converter output module.

[0038] The common architecture of voltage scaling modules in existing analog-to-digital converters is as follows: Figure 2 As shown, it uses two capacitors of different capacitance values ​​to divide the voltage to obtain the input of the analog-to-digital converter. In practical applications, the input common-mode voltage is also reduced after voltage division, causing the original common-mode voltage to disappear. This affects the comparator's comparison accuracy and speed. To achieve the same comparison speed and accuracy as before voltage division, the comparator design becomes significantly more difficult. Furthermore, it lacks circuit calibration to address capacitor mismatch caused by temperature effects, manufacturing effects, etc., making it unsuitable for high-precision applications. This can be summarized in two points: First, voltage division lowers the common-mode point, limiting the input range and drastically increasing comparator design complexity. Second, the lack of a calibration module or over-reliance on purely digital calibration schemes consumes significant hardware resources and greatly increases circuit complexity. Additionally, the range that nonlinear calibration can calibrate is very limited, failing to achieve similar results to linear calibration.

[0039] This embodiment provides an analog-to-digital converter, which includes a voltage scaling module, such as... Figure 3 As shown, the voltage scaling module described above includes:

[0040] A common-mode circuit includes a first switch (Sample), multiple second switches (Samples), a first capacitor C1, a second capacitor C2, and a third capacitor C3. The first switch (Sample) is located on the connection line between the two ends of the second capacitor C2. One of the second switches (Samples) is located on the connection line between the first reference voltage input terminal Vcc / 2 and one end of the first capacitor C1. Another of the second switches (Samples) is located on the connection line between the other end of the first capacitor C1 and the first input terminal VIN_P. One of the second switches (Samples) is located on the connection line between one end of the third capacitor C3 and the second input terminal VIN_N. Another of the second switches (Samples) is located on the connection line between the second reference voltage input terminal Vcc / 2 and the other end of the third capacitor C3. One end of the first capacitor C1 is connected to the first output terminal VIN_P1, and the other end of the third capacitor C3 is connected to the second output terminal VIN_N1. The capacitances of the first capacitor C1 and the third capacitor C3 are equal.

[0041] In the aforementioned analog-to-digital converter (ADC), when multiple second switches are closed and the first switch is open, analog voltages are input to the first and second input terminals, making the voltage of the second capacitor equal to the input analog voltage. When multiple second switches are open and the first switch is closed, the second capacitor is short-circuited, and charge transfer occurs between the first and third capacitors. This results in the outputs of the first and second input terminals being symmetrical to the reference voltage, ensuring that the first and second output terminals output a common-mode analog voltage signal. This solves the problem of low accuracy in ADCs due to the lack of a common-mode voltage in existing technologies. Furthermore, a stable common-mode point ensures that the ADC design complexity is not excessive, reducing the comparator's power consumption and meeting the low-power application requirements of an ADC.

[0042] To achieve calibration, one alternative implementation is as follows: Figure 3 As shown, the aforementioned analog-to-digital converter also includes:

[0043] The calibration circuit includes multiple third switches Cal_A and multiple fourth switches Cal_B. One of the third switches Cal_A is located on the connection line between the third reference voltage input terminal Vcc and one end of the first capacitor C1; one of the third switches Cal_A is located on the connection line between one end of the third capacitor C3 and the ground terminal; one of the third switches Cal_A is located on the connection line between the other end of the first capacitor C1 and the first output terminal VIN_P1; and one of the third switches Cal_B is located on the connection line between the fourth reference voltage input terminal Vcc / 2 and the second output terminal VIN_P1. On the connection line of the output terminal VIN_N1, one of the aforementioned fourth switches Cal_B is located on the connection line between the fifth reference voltage input terminal Vcc and the other end of the aforementioned third capacitor C3; one of the aforementioned fourth switches Cal_B is located on the connection line between the other end of the aforementioned first capacitor C1 and the ground terminal; one of the aforementioned fourth switches Cal_B is located on the connection line between one end of the aforementioned third capacitor C3 and the aforementioned second output terminal VIN_N1; and one of the aforementioned fourth switches Cal_B is located on the connection line between the sixth reference voltage input terminal Vcc / 2 and the aforementioned first output terminal VIN_P1.

[0044] In the aforementioned analog-to-digital converter, when multiple third switches Cal_A are closed and multiple fourth switches Cal_B are open, the first capacitor C1 and the second capacitor C2 are connected in series to divide the voltage at the third reference voltage input terminal Vcc. The first output terminal VIN_P1 outputs the voltage at the common terminal of the first capacitor C1 and the second capacitor C2, and the second output terminal VIN_N1 outputs the voltage at the fourth reference voltage input terminal Vcc / 2. The actual voltage is compared with the theoretical voltage to resolve the mismatch between the first and second capacitors caused by temperature effects, manufacturing effects, etc. When multiple third switches Cal_A are open and multiple fourth switches Cal_B are closed, the second capacitor C2 and the third capacitor C3 are connected in series to divide the voltage at the fifth reference voltage input terminal Vcc. The first output terminal VIN_P1 outputs the voltage at the sixth reference voltage input terminal Vcc / 2, and the second output terminal VIN_N1 outputs the voltage at the common terminal of the second capacitor C2 and the third capacitor C3. The actual voltage is compared with the theoretical voltage to resolve the mismatch between the second and third capacitors caused by temperature effects, manufacturing effects, etc.

[0045] To switch between the common-mode circuit and the calibration circuit, one alternative implementation is as follows: Figure 3As shown, the analog-to-digital converter also includes multiple calibration switches ~Cal_start. One of the first switches ~Sample is connected in series with one of the calibration switches ~Cal_start, and one of the second switches ~Sample is connected in series with one of the calibration switches ~Cal_start. One of the calibration switches ~Cal_start is located on the connection line between the first output terminal VIN_P1 and one end of the first capacitor C1, and one of the calibration switches ~Cal_start is located on the connection line between the second output terminal VIN_N1 and the other end of the third capacitor C3.

[0046] In the aforementioned analog-to-digital converter, when multiple calibration switches ~Cal_start are open, the common-mode circuit cannot work, but the calibration circuit can work to perform calibration. After calibration is completed, when multiple calibration switches ~Cal_start are closed, the common-mode circuit works to output a common-mode analog voltage signal.

[0047] This embodiment provides a control method for an analog-to-digital converter that runs on a mobile terminal, computer terminal, or similar computing device. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Also, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0048] Figure 4 This is a flowchart of a control method for an analog-to-digital converter according to an embodiment of this application. Figure 4 As shown, the method includes the following steps:

[0049] Step S101: Control each of the second switches to close and the first switch to open, so that the first input terminal and the second input terminal receive analog voltage signals;

[0050] Step S102: Control each of the second switches to close and the first switch to open, so that the first output terminal and the second output terminal output common-mode analog voltage signals.

[0051] In this embodiment, the control method for the analog-to-digital converter described above, when multiple second switches are closed and the first switch is open, analog voltages are input to the first and second input terminals, making the voltage of the second capacitor equal to the input analog voltage. When multiple second switches are open and the first switch is closed, the second capacitor is short-circuited, and charge transfer occurs between the first and third capacitors. This results in the outputs of the first and second input terminals being symmetrical to the reference voltage, thus ensuring that the first and second output terminals output common-mode analog voltage signals. This solves the problem of low accuracy in existing analog-to-digital converters due to the lack of a common-mode voltage. Furthermore, a stable output common-mode point ensures that the design complexity of the analog-to-digital converter is not excessive, reducing the power consumption of the comparator and meeting the low-power application requirements of an analog-to-digital converter.

[0052] To calculate the mismatch factor, in one optional embodiment, the analog-to-digital converter further includes a calibration circuit. This calibration circuit includes multiple third switches Cal_A and multiple fourth switches Cal_B. One third switch Cal_A is located on the connection line between the third reference voltage input terminal Vcc and one end of the first capacitor C1; one third switch Cal_A is located on the connection line between one end of the third capacitor C3 and the ground terminal; one third switch Cal_A is located on the connection line between the other end of the first capacitor C1 and the first output terminal VIN_P1; and one third switch Cal_B is located on the connection line between the fourth reference voltage input terminal Vcc / 2 and the first... On the connection line of the second output terminal VIN_N1, one of the aforementioned fourth switches Cal_B is located on the connection line between the fifth reference voltage input terminal Vcc and the other end of the aforementioned third capacitor C3; one of the aforementioned fourth switches Cal_B is located on the connection line between the other end of the aforementioned first capacitor C1 and the ground terminal; one of the aforementioned fourth switches Cal_B is located on the connection line between one end of the aforementioned third capacitor C3 and the aforementioned second output terminal VIN_N1; one of the aforementioned fourth switches Cal_B is located on the connection line between the sixth reference voltage input terminal Vcc / 2 and the aforementioned first output terminal VIN_P1. Before controlling each of the aforementioned second switches to close and the aforementioned first switch to open, the above method further includes:

[0053] Step S201: Control each of the above-mentioned third switches to close and each of the above-mentioned fourth switches to open, and calculate the mismatch coefficient of the above-mentioned common-mode analog voltage signal output from the above-mentioned first output terminal to obtain the first mismatch coefficient;

[0054] Step S202: Control each of the aforementioned third switches to open and each of the aforementioned fourth switches to close, and calculate the mismatch coefficient of the aforementioned common-mode analog voltage signal output from the aforementioned second output terminal to obtain the second mismatch coefficient.

[0055] In the above embodiments, when multiple third switches Cal_A are closed and multiple fourth switches Cal_B are open, the first capacitor C1 and the second capacitor C2 are connected in series to divide the voltage at the third reference voltage input terminal Vcc. The first output terminal VIN_P1 outputs the voltage at the common terminal of the first capacitor C1 and the second capacitor C2, and the second output terminal VIN_N1 outputs the voltage at the fourth reference voltage input terminal Vcc / 2. The actual voltage is compared with the theoretical voltage to determine the first mismatch coefficient to resolve the mismatch between the first capacitor and the second capacitor caused by temperature effects, manufacturing effects, etc. When multiple third switches Cal_A are open and multiple fourth switches Cal_B are closed, the second capacitor C2 and the third capacitor C3 are connected in series to divide the voltage at the fifth reference voltage input terminal Vcc. The first output terminal VIN_P1 outputs the voltage at the sixth reference voltage input terminal Vcc / 2, and the second output terminal VIN_N1 outputs the voltage at the common terminal of the second capacitor C2 and the third capacitor C3. The actual voltage is compared with the theoretical voltage to determine the second mismatch coefficient to resolve the mismatch between the second capacitor and the third capacitor caused by temperature effects, manufacturing effects, etc.

[0056] To achieve calibration, in one optional implementation, the method further includes:

[0057] Step S301: The common-mode analog voltage signal output from the first output terminal is calibrated using the first mismatch coefficient to obtain a first calibrated common-mode analog voltage signal.

[0058] Step S302: The common-mode analog voltage signal output from the second output terminal is calibrated using the second mismatch coefficient to obtain a second calibrated common-mode analog voltage signal.

[0059] In the above embodiments, the mismatch between the first capacitor and the second capacitor caused by temperature effects, manufacturing effects, etc., results in an inaccurate common-mode analog voltage signal output from the first output terminal. The common-mode analog voltage signal output from the first output terminal is calibrated using a first mismatch coefficient to obtain a first calibrated common-mode analog voltage signal, thereby solving the mismatch problem. Similarly, the mismatch between the second capacitor and the third capacitor caused by temperature effects, manufacturing effects, etc., results in an inaccurate common-mode analog voltage signal output from the second output terminal. The common-mode analog voltage signal output from the second output terminal is calibrated using a second mismatch coefficient to obtain a second calibrated common-mode analog voltage signal, thereby solving the mismatch problem.

[0060] In an optional implementation, to calculate the first mismatch coefficient, step S201 above includes:

[0061] Step S2011: Obtain the voltage value output by the analog-to-digital converter when each of the third switches is closed and each of the fourth switches is open, and obtain the first actual voltage value.

[0062] Step S2012: Obtain the voltage value of the analog-to-digital converter output when each of the third switches is closed and each of the fourth switches is open, and obtain the first theoretical voltage value.

[0063] Step S2013: Calculate the ratio of the first actual voltage value to the first theoretical voltage value to obtain the first mismatch coefficient.

[0064] In the above embodiment, taking the capacitance value of the first capacitor as C and the capacitance value of the second capacitor as nC as an example, if there is no circuit mismatch, the first theoretical voltage value output by the analog-to-digital converter is Vcc / 2-Vcc / (n+1); if there is a circuit mismatch, the first actual voltage value output by the analog-to-digital converter is Vcc / 2-k1. Vcc / (n+1), where k1 is the process mismatch coefficient of the first capacitor and the second capacitor. The first mismatch coefficient is calculated to be (n-1) / (n+1-2k1).

[0065] In an optional implementation, to calculate the second mismatch coefficient, step S202 above includes:

[0066] Step S2021: Obtain the voltage value output by the analog-to-digital converter when each of the third switches is open and each of the fourth switches is closed, and obtain the second actual voltage value;

[0067] Step S2022: Obtain the voltage value of the analog-to-digital converter when each of the third switches is open and closed and each of the fourth switches is closed, and obtain the second theoretical voltage value.

[0068] Step S2023: Calculate the ratio of the second actual voltage value to the second theoretical voltage value to obtain the second mismatch coefficient.

[0069] In the above implementation, taking the capacitance value of the third capacitor as C and the capacitance value of the second capacitor as nC as an example, if there is no circuit mismatch, the first theoretical voltage value output by the analog-to-digital converter is Vcc / 2 - Vcc / (n+1); if there is a circuit mismatch, the first actual voltage value output by the analog-to-digital converter is Vcc / 2 - k2. Vcc / (n+1), where k2 is the process mismatch coefficient between the second capacitor and the third capacitor, and the second mismatch coefficient is calculated to be (n-1) / (n+1-2k2).

[0070] To enable those skilled in the art to better understand the technical solution of this application, the implementation process of the control method for the analog-to-digital converter of this application will be described in detail below with reference to specific embodiments.

[0071] This embodiment relates to a specific control method for an analog-to-digital converter, including the following steps:

[0072] In the voltage scaling module circuit of the analog-to-digital converter, VIN_P is 2V, VIN_N is 0V, the power supply Vcc is 5V, the capacitance of the first capacitor is C, the capacitance of the second capacitor is nC, the capacitance of the third capacitor is C, and n can be adjusted to adjust the scaling factor of the voltage scaling module.

[0073] like Figure 5 As shown, the circuit execution sequence is as follows: control Cal_start is high (calibration switch ~Cal_start is off) -> control signal Cal_A is high, control signal Cal_B is low (third switch Cal_A is closed, fourth switch Cal_B is off) -> control signal Cal_A is low, control signal Cal_B is high (third switch Cal_A is off, fourth switch Cal_B is closed) -> control signal Cal_A is low, control signal Cal_B is low (third switch Cal_A is off, fourth switch Cal_B is off), control signal Cal_start is low (calibration switch ~Cal_Start is closed) -> control signal SAMPLE is low (first switch Sample is off, second switch ~Sample is closed) -> control signal SAMPLE is high (first switch Sample is closed, second switch ~Sample is off).

[0074] The circuit execution sequence is as follows: Cal_start is set to a high level, causing the calibration switch ~Cal_start to disconnect. The circuit is as follows: Figure 6 As shown, when control signal Cal_A is high and control signal Cal_B is low, the third switch Cal_A is closed and the fourth switch Cal_B is open. The circuit is as follows. Figure 7 As shown, to obtain the first mismatch coefficient through calibration, control signal Cal_A is at a low level and control signal Cal_B is at a high level, causing the third switch Cal_A to open and the fourth switch Cal_B to close. The circuit is as follows. Figure 8 As shown, the second mismatch coefficient is obtained through calibration. After calibration, control signals Cal_A and Cal_B are both low, causing the third switch Cal_A and the fourth switch Cal_B to open. Control signal Cal_start is low, causing the calibration switch ~Cal_Start to close. The circuit is as follows. Figure 9 As shown, when the control signal SAMPLE is low, the first switch Sample is open and the second switch Sample is closed. The circuit is as follows. Figure 10 As shown, capacitor C1 has its upper plate connected to Vcc / 2 and its lower plate connected to VIN_P, with a charge Q of (Vcc / 2 - VIN_P)C. Capacitor nC2 has its upper plate connected to VIN_P and its lower plate connected to VIN_N, with a charge Q of (VIN_P - VIN_N). The lower plate of capacitor C3 is connected to Vcc / 2, and the upper plate is connected to VIN_N. The charge Q on C3 is (Vcc / 2 - VIN_N)C. VIN_P1 and VIN_N1 output 2.5V. The control signal SAMPLE is high, causing the first switch Sample to close and the second switch ~Sample to open. The circuit is as follows: Figure 11 As shown, charge transfer occurs between capacitors.

[0075] Simulation results are as follows Figure 12 As shown, when the control signal SAMPLE is low, the first switch Sample is open and the second switch ~Sample is closed, and VIN_P1 and VIN_N1 output 2.5V. When the control signal SAMPLE is high, the first switch Sample is closed and the second switch ~Sample is open, the output of VIN_P1 becomes 1.5V and the output of VIN_N1 becomes 3.5V. The output is symmetrical about half of 5V, 2.5V, which means that the common mode is Vcc / 2.

[0076] This application also provides a control device for an analog-to-digital converter. It should be noted that the control device for the analog-to-digital converter in this application can be used to execute the control method for the analog-to-digital converter provided in this application. This device is used to implement the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0077] The control device for the analog-to-digital converter provided in the embodiments of this application will be described below.

[0078] Figure 13 This is a schematic diagram of a control device for an analog-to-digital converter according to an embodiment of this application. Figure 13 As shown, the device includes:

[0079] The first control unit 10 is used to control the closing of each of the second switches and the opening of the first switches, so that analog voltage signals are input to the first input terminal and the second input terminal.

[0080] The second control unit 10 is used to control the closing of each of the second switches and the opening of the first switch, so that the first output terminal and the second output terminal output common-mode analog voltage signals.

[0081] In this embodiment, in the control device of the aforementioned analog-to-digital converter, when multiple second switches are closed and the first switch is open, analog voltages are input to the first and second input terminals, making the voltage of the second capacitor equal to the input analog voltage. When multiple second switches are open and the first switch is closed, the second capacitor is short-circuited, and charge transfer occurs between the first and third capacitors. This makes the outputs of the first and second input terminals symmetrical to the reference voltage, thus ensuring that the first and second output terminals output common-mode analog voltage signals. This solves the problem of low accuracy in existing analog-to-digital converters due to the lack of common-mode voltage. Furthermore, a stable output common-mode point ensures that the design complexity of the analog-to-digital converter is not excessive, reducing the power consumption of the comparator and meeting the low-power application requirements of an analog-to-digital converter.

[0082] To calculate the mismatch factor, in one optional embodiment, the analog-to-digital converter further includes a calibration circuit. This calibration circuit includes multiple third switches Cal_A and multiple fourth switches Cal_B. One third switch Cal_A is located on the connection line between the third reference voltage input terminal Vcc and one end of the first capacitor C1; one third switch Cal_A is located on the connection line between one end of the third capacitor C3 and the ground terminal; one third switch Cal_A is located on the connection line between the other end of the first capacitor C1 and the first output terminal VIN_P1; and one third switch Cal_B is located on the connection line between the fourth reference voltage input terminal Vcc and the ground terminal. On the connection line between input terminal Vcc / 2 and the second output terminal VIN_N1, one of the fourth switches Cal_B is located on the connection line between the fifth reference voltage input terminal Vcc and the other end of the third capacitor C3; one of the fourth switches Cal_B is located on the connection line between the other end of the first capacitor C1 and the ground terminal; one of the fourth switches Cal_B is located on the connection line between one end of the third capacitor C3 and the second output terminal VIN_N1; one of the fourth switches Cal_B is located on the connection line between the sixth reference voltage input terminal Vcc / 2 and the first output terminal VIN_P1. The device further includes:

[0083] The third control unit is used to control the closing of each of the above-mentioned second switches and the opening of each of the above-mentioned fourth switches before controlling the closing of each of the above-mentioned second switches and the opening of the above-mentioned first switches, and to calculate the mismatch coefficient of the above-mentioned common-mode analog voltage signal output from the above-mentioned first output terminal to obtain the first mismatch coefficient.

[0084] The fourth control unit is used to control each of the aforementioned third switches to open and each of the aforementioned fourth switches to close, and to calculate the mismatch coefficient of the aforementioned common-mode analog voltage signal output from the aforementioned second output terminal to obtain the second mismatch coefficient.

[0085] In the above embodiments, when multiple third switches Cal_A are closed and multiple fourth switches Cal_B are open, the first capacitor C1 and the second capacitor C2 are connected in series to divide the voltage at the third reference voltage input terminal Vcc. The first output terminal VIN_P1 outputs the voltage at the common terminal of the first capacitor C1 and the second capacitor C2, and the second output terminal VIN_N1 outputs the voltage at the fourth reference voltage input terminal Vcc / 2. The actual voltage is compared with the theoretical voltage to determine the first mismatch coefficient to resolve the mismatch between the first capacitor and the second capacitor caused by temperature effects, manufacturing effects, etc. When multiple third switches Cal_A are open and multiple fourth switches Cal_B are closed, the second capacitor C2 and the third capacitor C3 are connected in series to divide the voltage at the fifth reference voltage input terminal Vcc. The first output terminal VIN_P1 outputs the voltage at the sixth reference voltage input terminal Vcc / 2, and the second output terminal VIN_N1 outputs the voltage at the common terminal of the second capacitor C2 and the third capacitor C3. The actual voltage is compared with the theoretical voltage to determine the second mismatch coefficient to resolve the mismatch between the second capacitor and the third capacitor caused by temperature effects, manufacturing effects, etc.

[0086] To achieve calibration, in one optional embodiment, the above-mentioned apparatus further includes:

[0087] The first calibration module is used to calibrate the common-mode analog voltage signal output from the first output terminal using the first mismatch coefficient to obtain a first calibration common-mode analog voltage signal.

[0088] The second calibration module is used to calibrate the common-mode analog voltage signal output from the second output terminal using the second mismatch coefficient to obtain a second calibrated common-mode analog voltage signal.

[0089] In the above embodiments, the mismatch between the first capacitor and the second capacitor caused by temperature effects, manufacturing effects, etc., results in an inaccurate common-mode analog voltage signal output from the first output terminal. The common-mode analog voltage signal output from the first output terminal is calibrated using a first mismatch coefficient to obtain a first calibrated common-mode analog voltage signal, thereby solving the mismatch problem. Similarly, the mismatch between the second capacitor and the third capacitor caused by temperature effects, manufacturing effects, etc., results in an inaccurate common-mode analog voltage signal output from the second output terminal. The common-mode analog voltage signal output from the second output terminal is calibrated using a second mismatch coefficient to obtain a second calibrated common-mode analog voltage signal, thereby solving the mismatch problem.

[0090] In one optional implementation, to calculate the first mismatch coefficient, the third control unit includes:

[0091] The first acquisition module is used to acquire the voltage value output by the analog-to-digital converter when each of the third switches is closed and each of the fourth switches is open, and to obtain the first actual voltage value.

[0092] The second acquisition module is used to acquire the voltage value output by the analog-to-digital converter when each of the third switches is closed and each of the fourth switches is open, and to obtain the first theoretical voltage value.

[0093] The first calculation module is used to calculate the ratio of the first actual voltage value to the first theoretical voltage value to obtain the first mismatch coefficient.

[0094] In the above embodiment, taking the capacitance value of the first capacitor as C and the capacitance value of the second capacitor as nC as an example, if there is no circuit mismatch, the first theoretical voltage value output by the analog-to-digital converter is Vcc / 2-Vcc / (n+1); if there is a circuit mismatch, the first actual voltage value output by the analog-to-digital converter is Vcc / 2-k1. Vcc / (n+1), where k1 is the process mismatch coefficient of the first capacitor and the second capacitor. The first mismatch coefficient is calculated to be (n-1) / (n+1-2k1).

[0095] In one optional implementation, to calculate the second mismatch coefficient, the fourth control unit includes:

[0096] The third acquisition module is used to acquire the voltage value output by the analog-to-digital converter when each of the aforementioned third switches is open and each of the aforementioned fourth switches is closed, and to obtain the second actual voltage value.

[0097] The fourth acquisition module is used to acquire the voltage value output by the analog-to-digital converter when each of the third switches is open and closed and each of the fourth switches is closed, and to obtain the second theoretical voltage value.

[0098] The second calculation module is used to calculate the ratio of the second actual voltage value to the second theoretical voltage value to obtain the second mismatch coefficient.

[0099] In the above implementation, taking the capacitance value of the third capacitor as C and the capacitance value of the second capacitor as nC as an example, if there is no circuit mismatch, the first theoretical voltage value output by the analog-to-digital converter is Vcc / 2 - Vcc / (n+1); if there is a circuit mismatch, the first actual voltage value output by the analog-to-digital converter is Vcc / 2 - k2. Vcc / (n+1), where k2 is the process mismatch coefficient between the second capacitor and the third capacitor, and the second mismatch coefficient is calculated to be (n-1) / (n+1-2k2).

[0100] The control device for the aforementioned analog-to-digital converter includes a processor and a memory. The first and second computing units, etc., are stored as program units in the memory, and the processor executes these program units to achieve the corresponding functions. All of the above modules reside in the same processor; alternatively, the modules may be located in different processors in any combination.

[0101] The processor contains a core, which retrieves the corresponding program unit from memory. One or more cores can be configured, and adjusting core parameters can address the problem of low analog-to-digital converter accuracy caused by the lack of common-mode voltage in existing technologies.

[0102] The memory may include non-permanent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM, and the memory includes at least one memory chip.

[0103] This invention provides a computer-readable storage medium including a stored program, wherein, when the program is executed, it controls the device containing the computer-readable storage medium to perform the control method for the analog-to-digital converter.

[0104] Specifically, the control methods for analog-to-digital converters include:

[0105] Step S101: Control each of the second switches to close and the first switch to open, so that the first input terminal and the second input terminal receive analog voltage signals;

[0106] Step S102: Control each of the second switches to close and the first switch to open, so that the first output terminal and the second output terminal output common-mode analog voltage signals.

[0107] This invention provides a processor for running a program, wherein the program executes the control method for the analog-to-digital converter.

[0108] Specifically, the control methods for analog-to-digital converters include:

[0109] Step S101: Control each of the second switches to close and the first switch to open, so that the first input terminal and the second input terminal receive analog voltage signals;

[0110] Step S102: Control each of the second switches to close and the first switch to open, so that the first output terminal and the second output terminal output common-mode analog voltage signals.

[0111] This invention provides a device including a processor, a memory, and a program stored in the memory and executable on the processor. When the processor executes the program, it performs at least the following steps:

[0112] Step S101: Control each of the second switches to close and the first switch to open, so that the first input terminal and the second input terminal receive analog voltage signals;

[0113] Step S102: Control each of the second switches to close and the first switch to open, so that the first output terminal and the second output terminal output common-mode analog voltage signals.

[0114] This application also provides a computer program product, which, when executed on a data processing device, is suitable for executing an initialization program having at least the following method steps:

[0115] Step S101: Control each of the second switches to close and the first switch to open, so that the first input terminal and the second input terminal receive analog voltage signals;

[0116] Step S102: Control each of the second switches to close and the first switch to open, so that the first output terminal and the second output terminal output common-mode analog voltage signals.

[0117] It is obvious to those skilled in the art that the modules or steps of the present invention described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those described herein, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, the present invention is not limited to any particular combination of hardware and software.

[0118] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0119] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1A device that provides the functions specified in one or more boxes.

[0120] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0121] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0122] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0123] Memory may include non-persistent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0124] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0125] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0126] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0127] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0128] In the analog-to-digital converter of this application, when multiple second switches are closed and the first switch is open, analog voltages are input to the first and second input terminals, making the voltage of the second capacitor equal to the input analog voltage. When multiple second switches are open and the first switch is closed, the second capacitor is short-circuited, and charge transfer occurs between the first and third capacitors, making the outputs of the first and second input terminals symmetrical with respect to the reference voltage. This ensures that the first and second output terminals output common-mode analog voltage signals, solving the problem of low accuracy in analog-to-digital converters due to the lack of common-mode voltage in existing technologies.

[0129] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. An analog-to-digital converter, characterized in that, The analog-to-digital converter includes a voltage scaling module, which comprises: A common-mode circuit includes a first switch, multiple second switches, a first capacitor, a second capacitor, and a third capacitor. The first switch is located on the connection line between the two ends of the second capacitor. One second switch is located on the connection line between the first reference voltage input terminal and one end of the first capacitor. One second switch is located on the connection line between the other end of the first capacitor and the first input terminal. One second switch is located on the connection line between one end of the third capacitor and the second input terminal. One second switch is located on the connection line between the second reference voltage input terminal and the other end of the third capacitor. One end of the first capacitor is connected to the first output terminal, and the other end of the third capacitor is connected to the second output terminal. The capacitances of the first capacitor and the third capacitor are equal.

2. The analog-to-digital converter according to claim 1, characterized in that, The analog-to-digital converter also includes: The calibration circuit includes multiple third switches and multiple fourth switches. One third switch is located on the connection line between the third reference voltage input terminal and one end of the first capacitor; one third switch is located on the connection line between one end of the third capacitor and the ground terminal; one third switch is located on the connection line between the other end of the first capacitor and the first output terminal; one third switch is located on the connection line between the fourth reference voltage input terminal and the second output terminal; one fourth switch is located on the connection line between the fifth reference voltage input terminal and the other end of the third capacitor; one fourth switch is located on the connection line between the other end of the first capacitor and the ground terminal; one fourth switch is located on the connection line between one end of the third capacitor and the second output terminal; and one fourth switch is located on the connection line between the sixth reference voltage input terminal and the first output terminal.

3. The analog-to-digital converter according to claim 1, characterized in that, The analog-to-digital converter also includes multiple calibration switches, one first switch connected in series with one calibration switch, one second switch connected in series with one calibration switch, one calibration switch located on the connection line between the first output terminal and one end of the first capacitor, and one calibration switch located on the connection line between the second output terminal and the other end of the third capacitor.

4. A control method for an analog-to-digital converter, applicable to the analog-to-digital converter according to any one of claims 1 to 3, characterized in that, The method includes: Control each of the second switches to close and the first switch to open, so that the first input terminal and the second input terminal receive analog voltage signals; Controlling each of the second switches to close and the first switch to open causes the first output terminal and the second output terminal to output common-mode analog voltage signals.

5. The method according to claim 4, characterized in that, The analog-to-digital converter further includes a calibration circuit, which comprises multiple third switches and multiple fourth switches. One third switch is located on the connection line between a third reference voltage input terminal and one end of a first capacitor; one third switch is located on the connection line between one end of a third capacitor and a ground terminal; one third switch is located on the connection line between the other end of the first capacitor and a first output terminal; one third switch is located on the connection line between a fourth reference voltage input terminal and a second output terminal; one fourth switch is located on the connection line between a fifth reference voltage input terminal and the other end of the third capacitor; one fourth switch is located on the connection line between the other end of the first capacitor and a ground terminal; one fourth switch is located on the connection line between one end of the third capacitor and the second output terminal; and one fourth switch is located on the connection line between a sixth reference voltage input terminal and the first output terminal. Before controlling each second switch to close and the first switch to open, the method further includes: Control each of the third switches to close and each of the fourth switches to open, and calculate the mismatch coefficient of the common-mode analog voltage signal output from the first output terminal to obtain the first mismatch coefficient; The third switches are controlled to open and the fourth switches are controlled to close, and the mismatch coefficient of the common-mode analog voltage signal output from the second output terminal is calculated to obtain the second mismatch coefficient.

6. The method according to claim 5, characterized in that, The method further includes: The common-mode analog voltage signal output from the first output terminal is calibrated using the first mismatch coefficient to obtain a first calibrated common-mode analog voltage signal; The common-mode analog voltage signal output from the second output terminal is calibrated using the second mismatch coefficient to obtain a second calibrated common-mode analog voltage signal.

7. The method according to claim 5, characterized in that, Calculate the mismatch coefficient of the common-mode analog voltage signal output from the first output terminal to obtain the first mismatch coefficient, including: The voltage value output by the analog-to-digital converter when each of the third switches is closed and each of the fourth switches is open is obtained to obtain the first actual voltage value; Obtain the voltage value output by the analog-to-digital converter when each of the third switches is closed and each of the fourth switches is open, and obtain the first theoretical voltage value; The first mismatch coefficient is obtained by calculating the ratio of the first actual voltage value to the first theoretical voltage value.

8. The method according to claim 5, characterized in that, Calculate the mismatch coefficient of the common-mode analog voltage signal output from the second output terminal to obtain the second mismatch coefficient, including: The voltage value output by the analog-to-digital converter when each of the third switches is open and each of the fourth switches is closed is obtained to obtain the second actual voltage value; The voltage values ​​output by the analog-to-digital converter when each of the third switches is open and closed and each of the fourth switches is closed are obtained to obtain the second theoretical voltage value; The ratio of the second actual voltage value to the second theoretical voltage value is calculated to obtain the second mismatch coefficient.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a stored program, wherein, when the program is executed, it controls the device on which the computer-readable storage medium is located to perform the method according to any one of claims 4 to 8.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the method described in any one of claims 4 to 8.

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