A 7b / 8b dc-balanced encoding method and system

Abstract

The application provides a 7b / 8b direct current balance encoding method and system, and belongs to the technical field of data encoding. The scheme receives 14-bit ADC sampling data, groups the data according to high and low bits to obtain two groups of data to be encoded; initializes parameters such as accumulated polarity deviation, high and low bit continuous number and deviation number, sets a limit rule to obtain an initialization item; constructs a balance, positive and negative encoding set and divides the set into multiple non-intersecting subsets, combines the initialization item to exert constraint on the subsets to generate an encoding rule; dynamically selects a corresponding encoding set according to the accumulated polarity deviation, looks up the table to encode the data to be encoded to obtain target encoding data, sequentially splices the target encoding data to form a target encoding stream, and constructs a synchronization code and a control code according to the polarity of the last bit of the target encoding stream to generate a calibration sequence; and combines the synchronization code, the control code, the calibration sequence and the target encoding stream to output a serial bit stream. The application dynamically offsets accumulated direct current deviation by using the polarity symmetry characteristics of non-subsets, and is suitable for the scene of high-speed data serial transmission of ADC.

Description

Technical Field

[0001] This application relates to the field of data encoding technology, and in particular to a 7b / 8b DC balanced encoding method and system. Background Technology

[0002] Existing 8b / 10b encoding methods achieve DC balance through a polarity bias mechanism, limiting the maximum number of consecutive identical bits in the data stream to no more than 5, facilitating clock recovery at the receiver. By distinguishing between D data codes and K control codes with unique comma sequences, codeword alignment, transmission frame control, and link idle marking can be quickly achieved. Basic error detection can also be implemented using valid codeword verification, requiring only two levels of table lookup in hardware. It features fixed latency, low resource consumption, and compatibility with AC-coupled cables, optical fibers, backplanes, and other transmission environments. However, its drawbacks are significant: every 8 bits of effective data requires the transmission of 10 bits, resulting in an encoding efficiency of only 80% and a 20% bandwidth redundancy overhead. When higher physical transmission rates are required for the same effective throughput, it increases hardware power consumption and cost, especially in ultra-high-speed transmission scenarios with high-speed ADC sampling (exceeding 250Msps), where data is typically no more than 14 bits and transmitted in 16-bit units. Using 8b / 10b encoding would further increase bandwidth, and its internal 5-bit / 6-bit and 3-bit / 4-bit group differential encoding has high complexity.

[0003] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the Invention

[0004] The main objective of this application is to propose a 7b / 8b DC balanced encoding method and system to achieve DC balanced encoding capability in ultra-high-speed transmission scenarios with ADC sampling (exceeding 250Msps), and to achieve Gbps-level high-speed serial bus transmission without increasing bandwidth.

[0005] To achieve the above objectives, this application proposes a 7b / 8b DC balanced coding method, which includes the following steps: Initialize the parameters of cumulative motivation deviation, high-order consecutive number, low-order consecutive number and deviation number, and set the corresponding restriction rules for each parameter to obtain the initialization item; Construct multiple sets of encodings, each set containing multiple non-overlapping subsets, and generate encoding rules by constraining the subsets according to the initialization term; The data to be encoded is encoded according to the encoding rules to obtain target encoded data, and multiple sets of target encoded data are arranged in order to generate a target encoded stream; A synchronization code and a control code are constructed based on the last bit of the target encoded stream, and a PWM calibration sequence is generated based on the synchronization code and the control code. The synchronization code, the control code, the PWM calibration sequence, and the target encoded stream are combined and then output.

[0006] Preferably, the encoding set includes a negative set, a balanced set, and a positive set; the negative set includes a negative-to-negative subset, a negative-to-balanced subset, and a negative-to-positive subset; the balanced set includes a balanced-to-negative subset, a balanced subset, and a balanced-to-positive subset; and the positive set includes a positive-to-negative subset, a positive-to-balanced subset, and a positive-to-positive subset.

[0007] Preferably, the deviation of the 8-bit encoded value of any element in the negative set is only allowed to be 0, +2, or +4; the deviation of the 8-bit encoded value of any element in the balanced set is only allowed to be -2, 0, or +2; and the deviation of the 8-bit encoded value of any element in the positive set is only allowed to be -4, -2, or 0.

[0008] Preferably, the encoding rules include restriction rules and constraint rules; the restriction rules include cumulative positive deviation rules, deviation number rules, and continuous bit value rules; the constraint rules include low-bit continuous number constraints, high-bit continuous number constraints, and subset non-constraint constraints.

[0009] Preferably, the low-order consecutive number constraint includes: all subsets of the negative set, the balanced set, and the positive set have an encoding constraint that the low-order consecutive number is no greater than 3; and the negative-to-positive subset, the balanced-to-positive subset, and the positive-to-positive subset all remove the 0bxxxx1000 encoding, and the negative-to-negative subset, the balanced-to-negative subset, and the positive-to-negative subset all remove the 0bxxxx0111 encoding.

[0010] Preferably, the high-order consecutive number constraint includes: the balanced to negative subset, the balanced subset, and the balanced to positive subset all have an encoding constraint that the high-order consecutive number is no greater than 2; the positive to balanced subset and the positive to positive subset have an encoding constraint that the high-order consecutive number is no greater than 3, and 0b1110xxxx codes are removed; the negative to negative subset and the negative to balanced subset have an encoding constraint that the high-order consecutive number is no greater than 3, and 0b0001xxxx codes are removed; the positive to negative subset and the negative to positive subset have an encoding constraint that the high-order consecutive number is no greater than 4.

[0011] Preferably, the subset non-constraints include: the balanced to negative subset and the balanced to positive subset are non-constrained, the negative to balanced subset and the positive to balanced subset are non-constrained, the negative to negative subset and the positive to positive subset are non-constrained, and the positive to negative subset and the negative to positive subset are non-constrained.

[0012] Preferably, when the last bit of the target encoded stream is 1, a synchronization code is constructed using a combination of 0x0ff0 and 0xf00f, and a control code is constructed using a combination of 0x0f and Ctrl; when the last bit of the target encoded stream is 0, a synchronization code is constructed using a combination of 0xf00f and 0x0ff0, and a control code is constructed using a combination of 0xf0 and Ctrl; wherein, Ctrl adopts the encoding format of 0b101XX101 or 0b010XX010, providing 8 control codes.

[0013] To achieve the above objectives, this application also proposes a 7b / 8b DC balanced coding system, the system comprising: The data acquisition module is used to receive sampled data and group it according to the high and low bits to obtain the data to be encoded; The initialization module is used to initialize and define various parameters such as cumulative motivation deviation, high-order consecutive number, low-order consecutive number, and deviation number, and to set the constraint rules corresponding to each parameter to obtain the initialization items; The encoding rule generation module is used to construct multiple sets of encodings, each set of encodings containing multiple non-overlapping subsets, and to generate encoding rules by constraining the subsets according to the initialization terms. The encoding stream generation module is used to encode the data to be encoded based on the encoding rules to obtain target encoded data, and multiple sets of target encoded data are arranged in order to generate a target encoded stream; A special codeword construction module is used to construct a synchronization code and a control code based on the last bit value of the target encoded stream, and to generate a PWM calibration sequence based on the synchronization code and the control code; The data output module is used to combine the synchronization code, the control code, the PWM calibration sequence and the target encoded stream and then output them.

[0014] To achieve the above objectives, this application also proposes an electronic device comprising a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the above-described method.

[0015] To achieve the above objectives, this application also proposes a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method.

[0016] To achieve the above objectives, this application also proposes a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0017] This application includes at least the following beneficial effects: This application provides a 7b / 8b DC balanced encoding method and system. This scheme splits the 14-bit ADC sampling data into two independent sets of data to be encoded, namely the high 7 bits and the low 7 bits, to achieve data adaptation from 14 bits to two sets of 7 bits. Then, it initializes the cumulative positive deviation, the number of consecutive high and low bits, the number of deviations and the corresponding restriction rules, and establishes the state basis for DC offset statistics and consecutive code detection. This provides a state basis for the subsequent dynamic selection of the encoding set and the suppression of ultra-long consecutive codes, ensuring that the encoding process can operate iteratively in a closed loop.

[0018] Then, an encoding set containing a balanced set, a positive set, and a negative set is constructed, and multiple non-overlapping subsets are configured within the encoding set. Encoding rules are generated by combining initialization terms with constraints. Through the hierarchical configuration of codewords with different deviations, a code library basis is provided for dynamically offsetting accumulated DC polarity deviations. The codewords between subsets do not overlap, avoiding mapping conflicts. At the same time, built-in code pattern constraints suppress ultra-long continuous bits from the source of codewords, avoiding the risk of clock lockout at the receiving end.

[0019] Then, based on the cumulative positive deviation, the code set is dynamically selected to complete the 7b / 8b lookup table encoding. Multiple sets of codewords are concatenated in an orderly manner to obtain the target encoded stream. It can adaptively select positive, zero, and negative deviation codewords according to the real-time cumulative offset, dynamically neutralize the DC offset of the transmission link, and achieve global DC balance. Through 7-bit to 8-bit encoding, high-speed serial data adaptation is achieved, ensuring high encoding efficiency, while the controllable code type constraint reduces invalid long consecutive codes.

[0020] A matching synchronization code and control code are constructed using the polarity of the last bit of the target encoded stream. The synchronization code carries frame boundary information to achieve frame synchronization at the receiving end, while the control code carries channel configuration and frame start / stop control commands. The generated synchronization code and control code are then combined to form a PWM calibration sequence. This sequence provides sufficient bit transition edges specifically for clock phase and frequency calibration at the receiving end's CDR, maintaining clock lock even in the event of localized long code sequences. The target encoded stream, synchronization code, control code, and PWM calibration sequence are concatenated and output, achieving integrated serial output of service data, synchronization information, control commands, and clock calibration sequence. This not only fully transmits ADC sampling service data but also simultaneously meets multiple requirements for frame positioning, command interaction, and clock recovery, improving the overall reliability of high-speed serial transmission and adapting to long-distance transmission scenarios of high-speed ADC sampling data. Attached Figure Description

[0021] Figure 1 This is a schematic diagram illustrating the steps of a 7b / 8b DC balanced encoding method provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of a 7b / 8b DC balanced encoding system provided in an embodiment of this application; Figure 3This is a schematic diagram of data grouping in an embodiment of this application; Figure 4 This is a schematic diagram of the coding process in an embodiment of this application; Figure 5 This is a schematic diagram of the cumulative motivation deviation encoding according to an embodiment of this application; Figure 6 This is a schematic diagram of the encoding set of embodiments of this application; Figure 7 This is a schematic diagram of the hardware structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0023] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various concepts, but unless otherwise stated, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the words “if,” “when,” or “in response to a determination” as used herein may be interpreted as “when…” or “when…” or “in response to a determination.”

[0024] As used in this application, the terms "at least one", "multiple", "each", "any", etc., "at least one" includes one, two or more, "multiple" includes two or more, "each" refers to each of the corresponding multiples, and "any" refers to any one of the multiples.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0026] Existing 8b / 10b encoding methods suffer from low encoding efficiency and high bandwidth overhead, especially in ultra-high-speed transmission scenarios with high-speed ADC sampling (exceeding 250Msps), where they further increase bandwidth. Furthermore, their internal 5-bit / 6-bit and 3-bit / 4-bit group differential encoding is highly complex. Therefore, this application provides a 7b / 8b DC-balanced encoding method and system. For ultra-high-speed transmission scenarios with high-speed ADC sampling (exceeding 250Msps), it possesses DC-balanced encoding capability when transmitting data in 16-bit units, and achieves Gbps-level high-speed serial bus transmission without increasing bandwidth.

[0027] This application provides a 7b / 8b DC balanced encoding method and system, relating to the field of data encoding. The 7b / 8b DC balanced encoding method and system provided in this application can be applied to a terminal, a server, or software running on a terminal or server. In some embodiments, the terminal can be a smartphone, tablet, laptop, desktop computer, smart speaker, smartwatch, or vehicle terminal, but is not limited thereto; the server can be configured as an independent physical server, a server cluster composed of multiple physical servers, or a distributed system; it can also be configured as a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms; the server can also be a node server in a blockchain network; the software can be an application implementing a 7b / 8b DC balanced encoding method and system, but is not limited to the above forms.

[0028] This application can be used in a wide variety of general-purpose or special-purpose computer system environments or configurations. Examples include: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics devices, network PCs, minicomputers, mainframe computers, and distributed computing environments including any of the above systems or devices. This application can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform specific tasks or implement specific abstract data types. This application can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0029] Figure 1This is a schematic diagram illustrating an optional step of a 7b / 8b DC balanced encoding method provided in an embodiment of this application. Figure 1 The method may include, but is not limited to, steps S1 to S6: S1 receives the sampled data and groups it according to the high and low bits to obtain the data to be encoded.

[0030] This embodiment primarily encodes 14-bit ADC sampling data into 16-bit data. This is achieved by splitting the 14 bits into two unrelated 7-bit groups of data to be encoded. Each group of data is then processed according to encoding rules to obtain 8-bit target encoded data. Figure 3 As shown. N consecutive 14-bit ADC sample data points are divided into 2... N data to be encoded are encoded sequentially to form 2 N target encoded data are generated and arranged in the encoding order to form a target encoded stream. The latest target encoded data is appended to the end of the target encoded stream according to the principle of high-order bits first and low-order bits last.

[0031] S2 initializes the parameters of cumulative motivation deviation, high-order continuous number, low-order continuous number and deviation number, and sets the corresponding restriction rules for each parameter to obtain the initialization items.

[0032] The cumulative polarity deviation is defined as the sum of the deviations of all transmitted codewords from the start of the target encoded stream to the end of the current encoding. This is a dynamically changing global state, initialized to 0. It is updated in real time after each 7-bit group of data to be encoded. The cumulative polarity deviation = original polarity deviation + deviation of the current codeword.

[0033] The deviation is defined as the difference between the number of 1s and the number of 0s in a single 8-bit target encoded data. It is an inherent parameter that remains constant within the codeword itself, and each 8-bit codeword uniquely corresponds to a deviation. For example, in the data 0b11001110, the number of 1s is 5 and the number of 0s is 3, so the deviation is +2; in the data 0b00010010, the number of 1s is 2 and the number of 0s is 6, so the deviation is -4.

[0034] In 8-bit target encoded data, the number of consecutive identical bit values ​​from the most significant bit to the least significant bit is defined as the high-order consecutive count, and the number of consecutive identical bit values ​​from the least significant bit to the most significant bit is defined as the low-order consecutive count. For example, in the data 0b11001110, counting the identical bit values ​​from the most significant bit to the least significant bit (left to right), there are two 1s, so the high-order consecutive count is 2. Counting the identical bit values ​​from the least significant bit to the most significant bit (right to left), there is one 0, so the low-order consecutive count is 1. Similarly, in the data 0b00011011, the high-order consecutive count is 3, and the low-order consecutive count is 2.

[0035] In some embodiments, the limiting rules include cumulative motivation deviation rules, deviation number rules, and continuous position value rules.

[0036] Specifically, the deviation rule is: the deviation of the target encoded data at any given time is only allowed to be -4, -2, 0, +2, or +4.

[0037] The cumulative positive bias rules are as follows: at any given time, the cumulative positive bias in the target encoded stream is only allowed to be -2, 0, or +2; and when the cumulative positive bias in the target encoded stream is 0, the bias of newly added target encoded data is only allowed to be -2, 0, or +2; when the cumulative positive bias in the target encoded stream is -2, the bias of newly added target encoded data is only allowed to be 0, +2, or +4; and when the cumulative positive bias in the target encoded stream is +2, the bias of newly added target encoded data is only allowed to be -4, -2, or 0.

[0038] The rule for consecutive bit values ​​is as follows: At any given time, the number of consecutive identical bits after concatenating the high-order bits of newly added target encoded data with the low-order bits of the previous target encoded data is not allowed to exceed 6. For example, if the previous target encoded data is 0b11000111, and the newly added target encoded data is 0b11110111, the concatenation will form 0b11000111 11110111. This data contains 7 consecutive 1s, therefore, the newly added target encoded data 0b11110111 is not allowed to be appended to the target encoded stream to avoid the number of consecutive bit values ​​exceeding 6 after encoding.

[0039] S3: Construct multiple sets of encodings, each set containing multiple non-overlapping subsets. Generate encoding rules by constraining the subsets according to the initialization terms.

[0040] In some embodiments, the encoding set includes a negative set {N}, a balanced set {B}, and a positive set {P}; the negative set {N} includes negative to negative subsets {N2N}, negative to balanced subsets {N2B}, and negative to positive subsets {N2P}; the balanced set {B} includes balanced to negative subsets {B2N}, balanced subsets {B2B}, and balanced to positive subsets {B2P}; and the positive set {P} includes positive to negative subsets {P2N}, positive to balanced subsets {P2B}, and positive to positive subsets {P2P}.

[0041] The encoding set consists of 128 distinct 8-bit encoded values. A one-to-one correspondence is established between any 7-bit value of the data to be encoded and an 8-bit encoded value in the encoding set; the 8-bit encoded value is the element corresponding to that 7-bit data. This embodiment constructs three encoding sets: a negative set {N}, a balanced set {B}, and a positive set {P}. Duplicate elements are allowed in different encoding sets.

[0042] In some embodiments, the deviation of the 8-bit encoded value of any element in the negative set {N} is only allowed to be 0, +2, or +4; the deviation of the 8-bit encoded value of any element in the balanced set {B} is only allowed to be -2, 0, or +2; and the deviation of the 8-bit encoded value of any element in the positive set {P} is only allowed to be -4, -2, or 0.

[0043] Specifically, in the negative set {N}, elements with a deviation of 0 form the negative to negative subset {N2N}; elements with a deviation of +2 form the negative to balanced subset {N2B}; and elements with a deviation of +4 form the negative to positive subset {N2P}.

[0044] In the balanced set {B}, elements with a deviation of -2 form the balanced to negative subset {B2N}; elements with a deviation of 0 form the balanced subset {B2B}; and elements with a deviation of +2 form the balanced to positive subset {B2P}.

[0045] In the positive set {P}, elements with a deviation of -4 form the positive to negative subset {P2N}; elements with a deviation of -2 form the positive to balanced subset {P2B}; and elements with a deviation of 0 form the positive to positive subset {P2P}.

[0046] Based on the cumulative positive bias deviation in the current target encoding stream, a corresponding subset is selected, and this subset is used as the encoding set for the current 7 bits of data to be encoded. The encoded value corresponding to the current 7 bits of data to be encoded is determined according to this encoding set. For example, the encoding set corresponding to the previous 7 bits of data to be encoded that makes the cumulative positive bias deviation in the target encoding stream -2 can be a negative-to-negative subset {N2N}, a balanced-to-negative subset {B2N}, or a positive-to-negative subset {P2N}. The encoding set corresponding to the current data to be encoded is selected as the negative set {N} to achieve DC balance in the encoding.

[0047] In this embodiment, please refer to Figure 6 As shown, the moduli of different subsets / sets are as follows: |N2N|=61, |N2B|=48, |N2P|=19, |N|=128; |B2N|=34, |B2B|=60, |B2P|=34, |B|=128; |P2N|=19, |P2B|=48, |P2P|=61, |P|=128.

[0048] In some embodiments, the low-order consecutive number constraint includes: all subsets of the negative set {N}, the balanced set {B}, and the positive set {P} have an encoding constraint that the low-order consecutive number is no greater than 3; and the negative to positive subset {N2P}, the balanced to positive subset {B2P}, and the positive to positive subset {P2P} all remove the 0bxxxx1000 encoding, and the negative to negative subset {N2N}, the balanced to negative subset {B2N}, and the positive to negative subset {P2N} all remove the 0bxxxx0111 encoding.

[0049] In some embodiments, the high-order consecutive number constraint includes: the balanced to negative subset {B2N}, the balanced subset {B2B}, and the balanced to positive subset {B2P} all have an encoding constraint that the high-order consecutive number is no greater than 2; the positive to balanced subset {P2B} and the positive to positive subset {P2P} have an encoding constraint that the high-order consecutive number is no greater than 3, and the 0b1110xxxx code is removed; the negative to negative subset {N2N} and the negative to balanced subset {N2B} have an encoding constraint that the high-order consecutive number is no greater than 3, and the 0b0001xxxx code is removed; the positive to negative subset {P2N} and the negative to positive subset {N2P} have an encoding constraint that the high-order consecutive number is no greater than 4.

[0050] By using high-order consecutive number constraints, low-order consecutive number constraints, and prohibition templates, the probability of 6 consecutive identical bits appearing is significantly reduced, ensuring sufficient level transitions in the serial stream and making it less likely for the clock data recovery circuit at the receiving end to lose lock.

[0051] In this embodiment of the application, two sets are defined as mutually exclusive if they have the following constraint: for any element 'a' in set A, there always exists an element 'b' in set B such that 'a' is equal to or the opposite of 'b'. For example, a = 0b11011010 and b = 0b00100101 are mutually exclusive, as expressed by the formula: .

[0052] In some embodiments, the subset non-constraints include: the balanced to negative subset {B2N} and the balanced to positive subset {B2P} are non-constrained, the negative to balanced subset {N2B} and the positive to balanced subset {P2B} are non-constrained, the negative to negative subset {N2N} and the positive to positive subset {P2P} are non-constrained, and the positive to negative subset {P2N} and the negative to positive subset {N2P} are non-constrained.

[0053] The negative-to-balance subset {B2N} and the positive-to-balance subset {B2P} are mutually exclusive and belong to the same balance set. They cancel out the DC offset by pairing negative and positive subsets, specifically for use when the global cumulative positive bias RD=0. The nine subsets are completely paired mirror images; subsets in the positive set are mutually exclusive with subsets in the negative set, and subsets within the balance set are mutually exclusive, forming a complete symmetrical codebook. This application dynamically selects codewords based on the global RD (cumulative positive bias): if RD is positive, the positive set is selected to lower RD; if RD is negative, the negative set is selected to raise RD. For example, when RD=+2, the positive to balanced subset {P2B} (deviation -2) and the positive to negative subset {P2N} (deviation -4) can be used to quickly neutralize the positive cumulative offset; when RD=-2, the negative to balanced subset {N2B} (deviation +2) and the negative to positive subset {N2P} (deviation +4) can be used to neutralize the negative cumulative offset; when RD=0, the balanced to negative subset {B2N} (deviation -2) and the balanced to positive subset {B2P} (deviation +2) can be used in pairs for alternating transmission, ensuring a strict balance of the long-term average number of 0 / 1 values. This application can solve the problems of baseline drift in AC coupled transmission and DC component accumulation in optical modules. Compared with 8b / 10b encoding, only 7b / 8b is needed to achieve higher encoding efficiency and no DC drift throughout the entire process. Furthermore, only half of the non-subset encoding table needs to be stored, and the other half can be generated in real time by 8-bit bit-by-bit inversion hardware, eliminating the need for additional ROM to store the complete code table and reducing the ROM usage for registers and lookup tables. When decoding to determine the codeword's affiliation, cross-checking using a non-reciprocal relationship is employed. If the decoded codeword belongs to the balanced to positive subset {B2P}, its inverted codeword must fall within the balanced to negative subset {B2N}. This allows for rapid verification of valid codewords and simplifies error detection logic. The 14-bit data is split into two groups of 7-bit data to be encoded, one high and one low. Each group of 7-bit data to be encoded, with inputs ranging from 0 to 127, is segmented and mapped within the three sets: the negative set {N}, the balanced set {B}, and the positive set {P}. The non-reciprocal structure ensures a one-to-one monotonic mapping between the 7-bit input data and the 8-bit encoded value, eliminating mapping conflicts.

[0054] In some embodiments, the deviation numbers of the subsets are as follows: the deviation number of any element in the balanced subset {B2B}, the negative to negative subset {N2N}, and the positive to positive subset {P2P} is 0; the deviation number of any element in the positive to negative subset {P2N} is -4; the deviation number of any element in the negative to positive subset {N2P} is +4; the deviation number of any element in the balanced to negative subset {B2N} and the positive to balanced subset {P2B} is -2; and the deviation number of any element in the negative to balanced subset {N2B} and the balanced to positive subset {B2P} is +2.

[0055] Specifically, the difference between the number of 1s and 0s in a single 8-bit target encoded data is the deviation number. Assuming the number of 1s in an 8-bit codeword is *a* and the number of 0s is *b*, satisfying *a+b=8*, the deviation number *c* = *ab* = *a* - *(8-a)* = 2*a* - 8. Therefore, the deviation number must be even, with a range of [-8, -6, -4, -2, 0, +2, +4, +6, +8]. Letting the deviation number *c* = *a* - *(8-a)* = 2*a* - 8 = 0, we get *a* = 4 and *b* = 4. The 8-bit codewords containing four 1s and four 0s are then assigned to the balanced subset {B2B}, the negative-to-negative subset {N2N}, and the positive-to-positive subset {P2P}, where the deviation number is 0. Let the bias number c = a - (8 - a) = 2a - 8 = -2, then we get a = 3 and b = 5. We assign the 8-bit codewords containing 3 ones and 5 zeros to the balanced to negative subset {B2N} and the positive to balanced subset {P2B}, respectively, with a bias number of -2. We calculate the bias number in the same way, thus assigning the 8-bit codewords to the 9 subsets.

[0056] Since ±6 and ±8 represent extreme imbalances in codeword 1 / 0, leading to excessive DC components and long consecutive codes that disrupt CDR clock recovery, this application employs only three levels of deviation: 0, ±2, and ±4. Combined with dynamic codeword selection based on cumulative deviation, this continuously offsets the accumulated DC offset, achieving full-range DC balance. Furthermore, a nine-subset mutual negation design ensures that positive and negative deviation codewords are mutually exclusive, facilitating dynamic correction of the global cumulative deviation.

[0057] In some embodiments, subsets with the same deviation number are distinguished based on codeword inherent constraints, subset non-constraints, and encoding runtime adaptation. Codeword inherent constraints include high-order consecutive number constraints, low-order consecutive number constraints, and prohibited templates (such as 0bxxxx1000 / 0bxxxx0111). Encoding runtime adaptation means that the subset deviation number is adapted to the current global cumulative deviation.

[0058] There is only one positive to negative subset {P2N} with a deviation of -4 and one negative to positive subset {N2P} with a deviation of +4, so there is no need to distinguish them.

[0059] For the three subsets with a deviation of 0: the balanced subset {B2B}, the negative-to-negative subset {N2N}, and the positive-to-positive subset {P2P}, the subsets are divided according to the high-order continuous number constraint, the low-order continuous number constraint, the forbidden template, the coding runtime adaptation, and the subset non-constraint constraint. Specifically: {B2B} is a balanced subset containing 60 codewords, with no more than 2 consecutive high-order bits and no more than 3 consecutive low-order bits, and no forbidden template restrictions. It is used to construct control codes by concatenating with prefix codes and is selected when the global cumulative positive bias RD=0.

[0060] {N2N} is a negative to negative subset containing 61 codewords, with no more than 3 consecutive high-order bits and no more than 3 consecutive low-order bits, and does not contain 0bxxxx0111 or 0b0001xxxx codes. It is also NOT of the positive to positive subset {P2P} and is selected when the global cumulative positive bias RD = -2.

[0061] {P2P} is a positive to positive subset containing 61 codewords, with no more than 3 consecutive high-order bits and no more than 3 consecutive low-order bits, and does not contain 0bxxxx1000 or 0b1110xxxx codes. It is also NOT of the negative to negative subset {N2N} and is selected when the global cumulative positive bias RD = +2.

[0062] For the two subsets {B2N} (balanced to negative) and {P2B} (positive to balanced) with a deviation of -2, they are distinguished based on the forbidden template (low-order bit), high-order consecutive number constraint, subset mutual negation constraint, and encoding runtime adaptation. Specifically: {B2N} is the balanced to negative subset, containing 34 codewords, with no more than 3 consecutive low-order bits, and does not contain the 0bxxxx0111 code. It is NOT the balanced to positive subset {B2P} and is selected when the global cumulative positive bias RD=0.

[0063] {P2B} is the positive to balanced subset, containing 48 codewords, with no more than 3 consecutive low-order bits and no more than 3 consecutive high-order bits, and does not contain 0b1110xxxx encoding. It is NOT the negative to balanced subset {N2B} and is selected when the global cumulative positive bias RD = +2.

[0064] That is, if the lower 4 bits of the codeword are 0111, it must not belong to the balanced to negative subset {B2N}, and it is classified as the positive to balanced subset {P2B}; if the higher 4 bits of the codeword are 1110, it must not belong to the positive to balanced subset {P2B}, and it is classified as the balanced to negative subset {B2N}.

[0065] For the two subsets {N2B} (negative to balanced) and {B2P} (balanced to positive) with a deviation of +2, they are distinguished based on low-order consecutive number constraints, high-order consecutive number constraints, forbidden templates, subset non-constituent constraints, and encoding runtime adaptation. Specifically: {N2B} is the negative to balanced subset, containing 48 codewords, with no more than 3 consecutive low-order bits and no more than 3 consecutive high-order bits, and does not contain 0b0001xxxx encoding. It is NOT the positive to balanced subset {P2B} and is selected when the global cumulative positive bias RD = -2.

[0066] {B2P} is the balanced to positive subset, containing 34 codewords, with no more than 3 consecutive low-order bits and no more than 2 consecutive high-order bits, and does not contain 0bxxxx1000 encoding. It is NOT the balanced to negative subset {B2N} and is selected when the global cumulative positive bias RD=0.

[0067] That is, if the high 4 bits of the codeword are 0001, it must not belong to the negative to balanced subset {N2B}, and it is classified as the balanced to positive subset {B2P}; if the low 4 bits of the codeword are 1000, it must not belong to the balanced to positive subset {B2P}, and it is classified as the negative to balanced subset {N2B}.

[0068] S4: Encode the data to be encoded according to the encoding rules to obtain the target encoded data. Multiple sets of target encoded data are arranged in order to generate the target encoded stream.

[0069] DC balanced encoding is achieved by segmenting the 7 bits of data to be encoded (0-127, decimal) into different subsets within each encoding set. For example, for the balanced set {B}, input 0-59 is mapped to the balanced subset {B2B} with a deviation of 0; input 60-93 is mapped to the balanced-to-positive subset {B2P} with a deviation of +2; and input 94-127 is mapped to the balanced-to-negative subset {B2N} with a deviation of -2. For the positive set {P}, input 0-60 is mapped to the positive-to-positive subset {P2P} with a deviation of 0; input 61-108 is mapped to the positive-to-balanced subset {P2B} with a deviation of -2; and input 109-127 is mapped to the positive-to-negative subset {P2N} with a deviation of -4. For the negative set {N}, input 0-60 is mapped to the negative to negative subset {N2N} with a deviation of 0; input 61-108 is mapped to the negative to balanced subset {N2B} with a deviation of +2; input 109-127 is mapped to the negative to positive subset {N2P} with a deviation of +4.

[0070] During decoding, the number of 1 / 0 in the 8-bit target encoded data is first counted to calculate the deviation, and the encoding set is locked. Then, the number of consecutive high-bits and consecutive low-bits is calculated to match the maximum consecutive number constraint of each subset. Then, the prohibited template is verified, including the prefix 0001xxxx / 1110xxxx and the suffix 0111 / 1000. Subsets that do not meet the requirements are filtered out. Then, cross-validation is performed using the non-reciprocal relationship. Finally, combined with the codeword capacity, the 7-bit data to be encoded is segmented and mapped to the corresponding subset.

[0071] S5: Construct synchronization code and control code based on the last bit of the target encoded stream, and generate PWM calibration sequence based on synchronization code and control code.

[0072] S6 combines the synchronization code, control code, PWM calibration sequence, and target encoded stream and outputs the result.

[0073] In some embodiments, when the last bit of the target encoded stream is 1, a synchronization code is constructed using the combination of 0x0ff0 and 0xf00f, and a control code is constructed using the combination of 0x0f and Ctrl; when the last bit of the target encoded stream is 0, a synchronization code is constructed using the combination of 0xf00f and 0x0ff0, and a control code is constructed using the combination of 0xf0 and Ctrl; wherein, Ctrl adopts the encoding form of 0b101XX101 or 0b010XX010, providing 8 control codes.

[0074] Specifically, the control code is composed of an 8-bit prefix concatenated with Ctrl. If the last bit of the current target encoded stream is 1, then the prefix 0x0f is used to concatenate with Ctrl to form the complete control code; if the last bit of the current target encoded stream is 0, then the prefix 0xf0 is used to concatenate with Ctrl to form the complete control code.

[0075] The synchronization code employs a 16-bit double-prefix combination. Two sets of non-16-bit synchronization sequences are switched based on the polarity of the last bit of the target encoded stream to ensure overall DC balance within the synchronization segment. If the last bit of the current target encoded stream is 1, the synchronization code uses either 0x0ff0 or 0xf00f; if the last bit is 0, it uses either 0xf00f or 0x0ff0. The two sequences are inverted and alternately transmitted to cancel out cumulative synchronization bias within the synchronization segment. This 16-bit synchronization code has a unique alternating feature of four consecutive 0s and four consecutive 1s, and it does not overlap with any data subset codewords. The receiver can quickly identify frame boundaries and complete frame alignment.

[0076] The generated 16-bit synchronization code and 16-bit control code are used as basic code elements, and N>2 sets are continuously concatenated to form a PWM (Pulse Width Modulation) calibration sequence. After multiple sets of synchronization codes and control codes are continuously combined, the PWM calibration sequence contains dense and uniform high and low level transitions, and no excessively long continuous 0 / 1. This PWM calibration sequence is continuously sent to the serial transmission link. The receiving end CDR (Clock Data Recovery) circuit relies on frequent level transitions to lock the sampling clock phase and frequency to achieve synchronization calibration, avoiding clock lockout caused by long consecutive codes during long-term data codeword transmission.

[0077] The specific process of steps S5-S6 is as follows: First, read the last 1 bit level (0 or 1) of the target encoded stream to be transmitted to determine the polarity reference. Then, match the corresponding 8-bit prefix according to the polarity of the last bit of the target encoded stream and concatenate it with Ctrl to generate the control code. At the same time, match the corresponding 16-bit non-interchangeable combination to generate the frame synchronization code. Then, use the synchronization code and control code as the basic unit and continuously concatenate N>2 units to construct the PWM calibration sequence. Insert the synchronization code, control code, and PWM calibration sequence into the header / frame interval of the serial encoded stream for the receiver CDR to realize clock synchronization and frame positioning.

[0078] Please see Figure 2 As shown, another aspect of this application embodiment also provides a 7b / 8b DC balanced encoding system, the system comprising: The data acquisition module is used to receive sampled data and group it according to the high and low bits to obtain the data to be encoded; The initialization module is used to initialize and define various parameters such as cumulative motivation deviation, high-order continuous number, low-order continuous number, and deviation number, and to set the corresponding constraint rules for each parameter to obtain the initialization items; The encoding rule generation module is used to construct multiple sets of encodings, each set of encodings containing multiple non-overlapping subsets, and to generate encoding rules by constraining the subsets according to the initialization terms. The encoding stream generation module is used to encode the data to be encoded based on encoding rules to obtain the target encoded data. Multiple sets of target encoded data are arranged in order to generate the target encoded stream. A special codeword construction module is used to construct synchronization codes and control codes based on the last bit of the target encoded stream, and to generate a PWM calibration sequence based on the synchronization codes and control codes; The data output module is used to combine the synchronization code, control code, PWM calibration sequence and target encoded stream and output them.

[0079] The following section provides a detailed description and explanation of the solutions in the embodiments of this application, using specific application examples.

[0080] For the nine subsets, since the balanced-to-negative subset {B2N} and the balanced-to-positive subset {B2P} are mutually NOT, the negative-to-balanced subset {N2B} and the positive-to-balanced subset {P2B} are mutually NOT, the negative-to-negative subset {N2N} and the positive-to-positive subset {P2P} are mutually NOT, and the positive-to-negative subset {P2N} and the negative-to-positive subset {N2P} are mutually NOT, this embodiment only lists five encoding tables: balanced-to-negative subset {B2N}, balanced subset {B2B}, positive-to-negative subset {P2N}, positive-to-balanced subset {P2B}, and positive-to-positive subset {P2P}.

[0081] The encoding table for the balanced subset {B2B} is shown in Table 1 below.

[0082] Table 1

[0083] The encoding table for the balanced negative subset {B2N} is shown in Table 2 below.

[0084] Table 2

[0085] The encoding table for the positive-to-positive subset {P2P} is shown in Table 3 below.

[0086] Table 3

[0087] The encoding table for the positive to balanced subset {P2B} is shown in Table 4 below.

[0088] Table 4

[0089] The encoding table for the positive to negative subset {P2N} is shown in Table 5 below.

[0090] Table 5

[0091] Combination Figure 3 and Figure 4 As shown, the complete encoding process of this application is as follows: First, 14-bit raw ADC sampling data is received and grouped into two independent 7-bit groups of data to be encoded, with the high 7 bits as one group and the low 7 bits as another group. Encoding is performed independently on each of the two groups of 7-bit data, and the cumulative bias is updated independently. Each group of 7-bit data is mapped to an 8-bit target encoded data. The two groups of 8-bit target encoded data are sequentially concatenated to form a 16-bit basic transmission unit. Multiple 16-bit basic transmission units constitute the target encoded stream until the encoding of 128 14-bit data is completed.

[0092] Initialize the cumulative positive bias to 0. Select the encoding set by reading the real-time cumulative positive bias RD of the 7 bits of data to be encoded. Please refer to [link to relevant documentation]. Figure 5As shown, if the cumulative positive bias RD = 0, the balanced set {B} is selected; if the cumulative positive bias RD = +2, the positive set {P} is selected; and if the cumulative positive bias RD = -2, the negative set {N} is selected. After selecting the encoding set, the 7-bit data to be encoded is mapped to the corresponding 8-bit target encoded data within the selected encoding set through hardware lookup. The generated 8-bit target encoded data is then appended to the end of the target encoded stream in a high-order first, low-order last order manner to form a new encoded stream. The cumulative positive bias of the current new encoded stream is then read to update the real-time cumulative positive bias. That is, the real-time cumulative positive bias is the cumulative positive bias of the previous target encoded stream plus the bias number of the set corresponding to the latest target encoded data. The calculated real-time cumulative positive bias value is used as the basis for selecting the encoding set corresponding to the next set of 7-bit data to be encoded.

[0093] Next, the steps of selecting the encoding set and updating the real-time cumulative clock bias are repeated, continuously encoding the split 7-bit data to be encoded cyclically. Simultaneously, the number of encoding cycles and the number of 16-bit basic transmission units are counted. Every two cycles of 7-bit encoding (one for the high 7 bits and one for the low 7 bits) generate one complete 16-bit basic transmission unit. The encoding cycle is repeated a total of 256 times, corresponding to 128 16-bit basic transmission units, triggering the synchronization frame insertion process. After each 128 16-bit basic transmission units are collected, a synchronization code sequence is inserted. This involves reading the last bit level of the current encoded stream. If the last bit level is 1, a synchronization code is constructed using a combination of 0x0ff0 and 0xf00f, which are not 16-bit values. If the last bit level is 0, the two sets of synchronization codes are swapped. Four consecutive synchronization codes (0xf00f / 0x0ff0) are inserted to form a synchronization frame, used for frame boundary identification at the receiver and coarse clock synchronization for the CDR. While inserting the synchronization code, the control codeword is concatenated according to the control code rules. That is, the polarity of the last bit of the encoded stream is matched with the 8-bit prefix. If the last bit is 1, 0x0f is selected as the prefix and concatenated with Ctrl. If the last bit is 0, 0xf0 is selected as the prefix and concatenated with Ctrl. Ctrl uses the encoding format of 0b101XX101 or 0b010XX010, providing 8 control codes. The control code carries instruction information such as frame start / stop and channel configuration.

[0094] By concatenating N>2 consecutive sets of synchronization codes and control codes to generate a PWM calibration sequence, and inserting it into the frame header / frame interval of the target encoded stream, a dense level transition edge is provided for the receiver's CDR circuit, continuously completing clock phase and frequency synchronization calibration and suppressing the risk of clock lockout caused by long consecutive codes. Finally, the target encoded stream generated by 7b / 8b encoding, the periodically inserted synchronization frames, control codes, and PWM calibration sequence are sequentially concatenated into a complete serial bit stream for high-speed serial transmission.

[0095] In this embodiment, assuming there are N currently encoded data points and the cumulative positive bias is RD = +2, to offset the DC offset, the (N+1)th encoded data should be selected from the positive set {P}. Sequential encoding is used for the 7 bits of data to be encoded. For example, 0-60 (decimal) corresponds to the positive to positive subset {P2P}, 61-108 (decimal) corresponds to the positive to balanced subset {P2B}, and 109-127 (decimal) corresponds to the positive to negative subset {P2N}. Only 109 (decimal) corresponds to 0b00001001, 110 (decimal) corresponds to 0b00001010, and 111 (decimal) corresponds to 0b00001100, which have four consecutive 0s in the high-order bits. Therefore, the probability that the (N+1)th encoded 7-bit data has four consecutive 0s in the high-order bits is 3 / 128. Since the subsets with positive cumulative positive bias after the additional coding include three subsets: negative to positive {N2P}, balanced to positive {B2P}, and positive to positive {P2P}, the Nth code may belong to one of these three subsets. The specific analysis is as follows.

[0096] If the Nth code belongs to the balanced positive subset {B2P}, since the low-order consecutive bits in the balanced positive subset {B2P} contain at most one 0, for example, 79 (decimal) in the balanced positive subset {B2P} corresponds to 0b10101110, the bit stream corresponding to 79 (decimal) is combined with the bit stream corresponding to the N+1th code. Assuming the N+1th code is 109 (decimal) corresponding to 0b00001001, the combined bit stream is 0b10101110 00001001, which contains only 5 consecutive 0s.

[0097] Similarly, if the Nth code belongs to the negative to positive subset {N2P}, since the negative to positive subset {N2P} and the positive to negative subset {P2N} are mutually exclusive, the encoding table of the negative to positive subset {P2N} can be consulted (Table 5). In the negative to positive subset {P2N}, when the least significant bit of any code is 1, there is always one consecutive number of least significant bits. Similarly, in the negative to positive subset {N2P}, when the least significant bit of any code is 0, there is always one consecutive number of least significant bits. For example, in the negative to positive subset {P2N}, the code corresponding to 65 (decimal) is 0b01000001. Therefore, in the negative to positive subset {N2P}, there is a mutually exclusive code 0b10111110 corresponding to 65. Even if 0b10111110 is combined with 0b00001001 corresponding to the (N+1)th code, there will be at most 5 consecutive 0s.

[0098] Therefore, for a sequence of 6 consecutive zeros to occur, the Nth code must belong to the positive-to-positive subset {P2P}. For example, a sequence of 6 consecutive zeros is only possible when the Nth code is 0b00111100. There are 9 such sequences, as shown in Table 6 below. The overall probability of a sequence of 6 consecutive zeros is: ; In the formula, , , These respectively indicate that the cumulative motivation deviation is 0, and the encoding falls within the balanced to positive subset. The probability that there are two consecutive zeros in the lower bits of the set {P2P}, positive to positive subsets, and negative to positive subsets {N2P}. This indicates that when the cumulative positivity bias is 2, the encoding falls within the positive to negative subset. And the probability of having four consecutive zeros in the higher digits.

[0099] Table 6

[0100] It is understood that the content of the above method embodiments is applicable to this system embodiment. The specific functions implemented in this system embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.

[0101] This application also provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the above-described method. This electronic device can be any smart terminal, including tablet computers, in-vehicle computers, etc.

[0102] It is understood that the content of the above method embodiments is applicable to this device embodiment. The specific functions implemented by this device embodiment are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0103] Please see Figure 7 , Figure 7 The hardware structure of an electronic device according to another embodiment is illustrated. The electronic device includes: The processor 701 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application. The memory 702 can be implemented as a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 702 can store the operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 702 and is called and executed by the processor 701 using the methods described in the embodiments of this application. The input / output interface 703 is used to implement information input and output; The communication interface 704 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.). Bus 705 transmits information between various components of the device (e.g., processor 701, memory 702, input / output interface 703, and communication interface 704); The processor 701, memory 702, input / output interface 703, and communication interface 704 are connected to each other within the device via bus 705.

[0104] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method.

[0105] It is understood that the content of the above method embodiments is applicable to this storage medium embodiment. The specific functions implemented in this storage medium embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.

[0106] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0107] It is understood that the content of the above method embodiments is applicable to the embodiments of this program product. The specific functions implemented by the embodiments of this program product are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0108] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0109] This application provides a 7b / 8b DC balanced encoding method. This scheme splits the 14-bit ADC sampling data into two independent sets of data to be encoded, namely the high 7 bits and the low 7 bits, to achieve data adaptation from 14 bits to two sets of 7 bits. Then, it initializes the cumulative positive deviation, the number of consecutive high and low bits, the number of deviations and the corresponding restriction rules, and establishes the state basis for DC offset statistics and consecutive code detection. This provides a state basis for the subsequent dynamic selection of the encoding set and the suppression of ultra-long consecutive codes, ensuring that the encoding process can operate iteratively in a closed loop.

[0110] Then, an encoding set containing a balanced set, a positive set, and a negative set is constructed, and multiple non-overlapping subsets are configured within the encoding set. Encoding rules are generated by combining initialization terms with constraints. Through the hierarchical configuration of codewords with different deviations, a code library basis is provided for dynamically offsetting accumulated DC polarity deviations. The codewords between subsets do not overlap, avoiding mapping conflicts. At the same time, built-in code pattern constraints suppress ultra-long continuous bits from the source of codewords, avoiding the risk of clock lockout at the receiving end.

[0111] Then, based on the cumulative positive deviation, the code set is dynamically selected to complete the 7b / 8b lookup table encoding. Multiple sets of codewords are concatenated in an orderly manner to obtain the target encoded stream. It can adaptively select positive, zero, and negative deviation codewords according to the real-time cumulative offset, dynamically neutralize the DC offset of the transmission link, and achieve global DC balance. Through 7-bit to 8-bit encoding, high-speed serial data adaptation is achieved, ensuring high encoding efficiency, while the controllable code type constraint reduces invalid long consecutive codes.

[0112] A matching synchronization code and control code are constructed using the polarity of the last bit of the target encoded stream. The synchronization code carries frame boundary information to achieve frame synchronization at the receiving end, while the control code carries channel configuration and frame start / stop control commands. The generated synchronization code and control code are then combined to form a PWM calibration sequence. This sequence provides sufficient bit transition edges specifically for clock phase and frequency calibration at the receiving end's CDR, maintaining clock lock even in the event of localized long code sequences. The target encoded stream, synchronization code, control code, and PWM calibration sequence are concatenated and output, achieving integrated serial output of service data, synchronization information, control commands, and clock calibration sequence. This not only fully transmits ADC sampling service data but also simultaneously meets multiple requirements for frame positioning, command interaction, and clock recovery, improving the overall reliability of high-speed serial transmission and adapting to long-distance transmission scenarios of high-speed ADC sampling data.

[0113] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0114] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0115] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0116] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0117] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A 7b / 8b DC balanced encoding method, characterized in that, The method includes the following steps: The sampled data is received and grouped according to the high and low bits to obtain the data to be encoded; Initialize the parameters of cumulative motivation deviation, high-order consecutive number, low-order consecutive number and deviation number, and set the corresponding restriction rules for each parameter to obtain the initialization item; Construct multiple sets of encodings, each set containing multiple non-overlapping subsets, and generate encoding rules by constraining the subsets according to the initialization term; The data to be encoded is encoded according to the encoding rules to obtain target encoded data, and multiple sets of target encoded data are arranged in order to generate a target encoded stream; A synchronization code and a control code are constructed based on the last bit of the target encoded stream, and a PWM calibration sequence is generated based on the synchronization code and the control code. The synchronization code, the control code, the PWM calibration sequence, and the target encoded stream are combined and then output.

2. The method according to claim 1, characterized in that, The encoding set includes a negative set, a balanced set, and a positive set; the negative set includes a negative-to-negative subset, a negative-to-balanced subset, and a negative-to-positive subset; the balanced set includes a balanced-to-negative subset, a balanced subset, and a balanced-to-positive subset; and the positive set includes a positive-to-negative subset, a positive-to-balanced subset, and a positive-to-positive subset.

3. The method according to claim 2, characterized in that, The deviation of the 8-bit encoded value of any element in the negative set is only allowed to be 0, +2, or +4; the deviation of the 8-bit encoded value of any element in the balanced set is only allowed to be -2, 0, or +2; and the deviation of the 8-bit encoded value of any element in the positive set is only allowed to be -4, -2, or 0.

4. The method according to claim 2, characterized in that, The encoding rules include restriction rules and constraint rules; the restriction rules include cumulative positive deviation rules, deviation number rules, and continuous bit value rules; the constraint rules include low-bit continuous number constraints, high-bit continuous number constraints, and subset non-constraint constraints.

5. The method according to claim 4, characterized in that, The low-order consecutive number constraint includes: all subsets of the negative set, the balanced set, and the positive set have an encoding constraint that the low-order consecutive number is no greater than 3; and the negative-to-positive subset, the balanced-to-positive subset, and the positive-to-positive subset all remove the 0bxxxx1000 encoding, and the negative-to-negative subset, the balanced-to-negative subset, and the positive-to-negative subset all remove the 0bxxxx0111 encoding.

6. The method according to claim 4, characterized in that, The high-order consecutive number constraint includes: the balanced to negative subset, the balanced subset, and the balanced to positive subset all have an encoding constraint that the high-order consecutive number is no greater than 2; the positive to balanced subset and the positive to positive subset have an encoding constraint that the high-order consecutive number is no greater than 3, and the 0b1110xxxx code is removed; the negative to negative subset and the negative to balanced subset have an encoding constraint that the high-order consecutive number is no greater than 3, and the 0b0001xxxx code is removed; The positive to negative subset and the negative to positive subset have an encoding constraint that the number of consecutive high-order bits is no greater than 4.

7. The method according to claim 4, characterized in that, The subset non-constraints include: the balanced to negative subset and the balanced to positive subset are non-constrained, the negative to balanced subset and the positive to balanced subset are non-constrained, the negative to negative subset and the positive to positive subset are non-constrained, and the positive to negative subset and the negative to positive subset are non-constrained.

8. The method according to claim 1, characterized in that, When the last bit of the target encoded stream is 1, a synchronization code is constructed using the combination of 0x0ff0 and 0xf00f, and a control code is constructed using the combination of 0x0f and Ctrl; when the last bit of the target encoded stream is 0, a synchronization code is constructed using the combination of 0xf00f and 0x0ff0, and a control code is constructed using the combination of 0xf0 and Ctrl; wherein, Ctrl adopts the encoding form of 0b101XX101 or 0b010XX010, providing 8 control codes.

9. A 7b / 8b DC balanced encoding system, applied to the method described in any one of claims 1-8, characterized in that, The system includes: The data acquisition module is used to receive sampled data and group it according to the high and low bits to obtain the data to be encoded; The initialization module is used to initialize and define various parameters such as cumulative motivation deviation, high-order consecutive number, low-order consecutive number, and deviation number, and to set the constraint rules corresponding to each parameter to obtain the initialization items; The encoding rule generation module is used to construct multiple sets of encodings, each set of encodings containing multiple non-overlapping subsets, and to generate encoding rules by constraining the subsets according to the initialization terms. The encoding stream generation module is used to encode the data to be encoded based on the encoding rules to obtain target encoded data, and multiple sets of target encoded data are arranged in order to generate a target encoded stream; A special codeword construction module is used to construct a synchronization code and a control code based on the last bit value of the target encoded stream, and to generate a PWM calibration sequence based on the synchronization code and the control code; The data output module is used to combine the synchronization code, the control code, the PWM calibration sequence and the target encoded stream and then output them.

10. An electronic device, characterized in that, The electronic device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the method according to any one of claims 1 to 8.

Images