Electronic device and its multi-input amplification circuit

Abstract

The present disclosure relates to an electronic device and a multi-input amplification circuit thereof. An electronic device is disclosed, comprising a first baseband circuit, a second baseband circuit, a first transceiver circuit, a second transceiver circuit, and a switch. The first transceiver circuit is coupled to the first baseband circuit and comprises a first transmitting circuit and a multi-input amplification circuit. The first transmitting circuit is coupled to the first baseband circuit. The multi-input amplification circuit is coupled to the first transmitting circuit. The second transceiver circuit is coupled to the second baseband circuit and comprises a second transmitting circuit and a driver amplifier. The second transmitting circuit is coupled to the second baseband circuit. The switch is coupled to the second transmitting circuit, the multi-input amplification circuit, and the driver amplifier. The switch is controlled by the first baseband circuit or the second baseband circuit to connect the second transmitting circuit to the multi-input amplification circuit or the driver amplifier.

Description

Technical Field

[0001] This invention relates to amplifier circuits, and more particularly to multi-input amplifier circuits. Background Technology

[0002] Please see Figure 1 , Figure 1 This is a functional block diagram of an embodiment of a conventional electronic device. The electronic device 100 includes a baseband circuit 111, a baseband circuit 121, a transceiver circuit 110, a transceiver circuit 120, switches SW1 and SW2, an antenna 119, and an antenna 129. The baseband circuit 111 receives and transmits signals through the transceiver circuit 110 and the antenna 119. The baseband circuit 121 receives and transmits signals through the transceiver circuit 120 and the antenna 129. Switch SW1 switches the antenna 119 to either the transmitting circuit 113 or the receiving circuit 117. Switch SW2 switches the antenna 129 to either the transmitting circuit 123 or the receiving circuit 127. Switches SW1 and SW2 can be controlled by the baseband circuit 111 and the baseband circuit 121, respectively.

[0003] The transceiver circuit 110 includes a digital-to-analog converter (DAC) 112, a transmission circuit 113, a driver amplifier 114, a power amplifier (PA) 115, a low noise amplifier (LNA) 116, a receiving circuit 117, and an analog-to-digital converter (ADC) 118.

[0004] The transceiver circuit 120 includes a DAC 122, a transmission circuit 123, a driver amplifier 124, a PA 125, an LNA 126, a receiving circuit 127, and an ADC 128.

[0005] Because electronic device 100 includes two transceiver circuits, it can simultaneously transmit two independent signals of different frequencies. Therefore, electronic device 100 has a large transmission bandwidth. However, since PA 115 and PA 125 are quite power-intensive, using two transceiver circuits simultaneously to transmit signals increases the total power consumption of electronic device 100. Summary of the Invention

[0006] In view of the shortcomings of the prior art, one object of the present invention is to provide an electronic device and a multi-input amplifier circuit thereof to improve the shortcomings of the prior art.

[0007] One embodiment of the present invention provides an electronic device comprising: a first baseband circuit, a second baseband circuit, a first transceiver circuit, a second transceiver circuit, and a switch. The first transceiver circuit is coupled to the first baseband circuit and includes a first transmission circuit and a multi-input amplifier circuit. The first transmission circuit is coupled to the first baseband circuit. The multi-input amplifier circuit is coupled to the first transmission circuit. The second transceiver circuit is coupled to the second transceiver circuit and includes a second transmission circuit and a driver amplifier. The second transmission circuit is coupled to the second baseband circuit. The switch is coupled to the second transmission circuit, the multi-input amplifier circuit, and the driver amplifier. The switch is controlled by the first baseband circuit or the second baseband circuit and is used to connect the second transmission circuit to the multi-input amplifier circuit or the driver amplifier.

[0008] Another embodiment of the present invention provides a multi-input amplifier circuit having a first input terminal, a second input terminal, and a first output terminal. The first input terminal is used to receive a first signal, and the second input terminal is used to receive a second signal. The multi-input amplifier circuit includes: a power divider, a first switch, a second switch, a third switch, an amplifier, and a power combiner. The power divider has a third input terminal, a second output terminal, and a third output terminal, and is used to generate a first intermediate signal and a second intermediate signal based on the first signal. The first switch is coupled to the first input terminal and the third input terminal. The second switch is coupled to the second output terminal and the first switch. The third switch is coupled to the second input terminal and the third output terminal. The amplifier is coupled to the second switch and the third switch, and is used to amplify the first intermediate signal or the first signal to generate a third signal, and to amplify the second intermediate signal or the second signal to generate a fourth signal. The power combiner is coupled to the amplifier and the first output terminal, and is used to combine the third signal and the fourth signal to generate a fifth signal.

[0009] Another embodiment of the present invention provides a multi-input amplifier circuit having a first input terminal, a second input terminal, and an output terminal. The first input terminal is used to receive a first signal, and the second input terminal is used to receive a second signal. The multi-input amplifier circuit includes: a power divider, a first switch, a second switch, an amplifier, and a power combiner. The power divider includes a first primary-side coil, a first secondary-side coil, a second primary-side coil, and a second secondary-side coil, used to generate a first intermediate signal and a second intermediate signal, wherein the first primary-side coil is coupled to the first input terminal, and the second primary-side coil is coupled to a reference voltage. The first switch is coupled to the first primary-side coil and the second primary-side coil. The second switch is coupled to the second input terminal and the second primary-side coil. The amplifier is coupled to the first secondary-side coil and the second secondary-side coil, used to amplify the first intermediate signal and the second intermediate signal to generate a third signal and a fourth signal, respectively. The power combiner is coupled to the amplifier and the output terminal, used to combine the third signal and the fourth signal to generate a fifth signal.

[0010] Another embodiment of the present invention provides a multi-input amplifier circuit having a first input terminal, a second input terminal, and an output terminal. The first input terminal is used to receive a first signal, and the second input terminal is used to receive a second signal. The multi-input amplifier circuit includes: a power divider, an amplifier, and a power combiner. The power divider is coupled to the first input terminal and the second input terminal to generate a first intermediate signal and a second intermediate signal, and includes a first coupler, a second coupler, and a third coupler coupled to each other. The amplifier is coupled to the power divider to amplify the first intermediate signal and the second intermediate signal to generate a third signal and a fourth signal, respectively. The power combiner is coupled to the amplifier and the output terminal to combine the third signal and the fourth signal to generate a fifth signal.

[0011] The technical means embodied in the embodiments of the present invention can improve at least one of the disadvantages of the prior art, and therefore the present invention can reduce power consumption compared to the prior art.

[0012] The features, implementation, and effects of this invention are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0013] Figure 1 This is a functional block diagram of an embodiment of a conventional electronic device;

[0014] Figures 2A-2B This is a functional block diagram of one embodiment of the electronic device of the present invention;

[0015] Figures 3A-3B This is a circuit diagram of one embodiment of the multi-input amplifier circuit of the present invention;

[0016] Figures 4A-4B This is a circuit diagram of one embodiment of the multi-input amplifier circuit of the present invention; and

[0017] Figures 5A-5B This is a circuit diagram of one embodiment of the multi-input amplifier circuit of the present invention. Detailed Implementation

[0018] The technical terms used in the following description are based on the customary terms in this technical field. If this specification provides explanations or definitions for certain terms, the interpretation of those terms shall be based on the explanations or definitions in this specification.

[0019] The disclosure of this invention includes electronic devices and their multi-input amplifier circuits. Since some components of the electronic devices and their multi-input amplifier circuits of this invention may be known components individually, details of known components will be omitted in the following description without affecting the full disclosure and implementability of the invention.

[0020] Please see Figure 2A and Figure 2B , Figure 2A and Figure 2B This is a functional block diagram of one embodiment of the electronic device of the present invention. The electronic device 200 includes a baseband circuit 211, a baseband circuit 221, a transceiver circuit 210, a transceiver circuit 220, switches SW1 and SW2, an antenna 119, and an antenna 129. Figure 1 and Figures 2A-2B In this circuit, components with the same symbol have similar or identical functions. Switches SW1 and SW2 can be controlled by baseband circuit 211 and baseband circuit 221, respectively.

[0021] The transceiver circuit 210 includes a multi-input amplifier circuit 214. The multi-input amplifier circuit 214 is coupled between the transmission circuit 113 and the antenna 119, and is also coupled to the transmission circuit 123 via switch SW3. The multi-input amplifier circuit 214 is a multi-input, single-output circuit. The input terminal N1 of the multi-input amplifier circuit 214 is coupled or electrically connected to the transmission circuit 113 to receive signal S1; the input terminal N2 of the multi-input amplifier circuit 214 is coupled or electrically connected to switch SW3; and the output terminal N3 of the multi-input amplifier circuit 214 is coupled or electrically connected to switch SW1. The multi-input amplifier circuit 214 amplifies signal S1 (…). Figure 2A or essentially amplify both signal S1 and signal S2 simultaneously. Figure 2B This is used to generate the amplified signal Sout.

[0022] Details of the multi-input amplifier circuit 214 will be provided below. Figures 3A-3B , Figures 4A-4B as well as Figures 5A-5B Detailed explanation.

[0023] Transceiver circuit 220 is similar to transceiver circuit 120, except that it further includes switch SW3. Switch SW3 is a single-pole double-throw switch that can switch between the first path (between transmission circuit 123 and drive amplifier 124) and the second path (between transmission circuit 123 and multi-input amplifier circuit 214). Switch SW3 is controlled by baseband circuit 211 or baseband circuit 221 via control signal Ctrl.

[0024] When switch SW3 is switched to the first path (i.e., the transmission circuit 123 is electrically connected to the drive amplifier 124, and the transmission circuit 123 is not electrically connected to the multi-input amplifier circuit 214) (e.g.) Figure 2A As shown, electronic device 200 can simultaneously use two amplifiers (124 and 214) to amplify signal S1 and signal S2 respectively. Signal S1 and signal S2 are transmitted through antennas 119 and 129 respectively. The frequency bands of signal S1 and signal S2 are different or do not overlap.

[0025] When switch SW3 is switched to the second path (i.e., the transmission circuit 123 is electrically connected to the multi-input amplifier circuit 214, and the transmission circuit 123 is not electrically connected to the drive amplifier 124) (e.g. Figure 2B As shown, electronic device 200 uses a multi-input amplifier circuit 214 to simultaneously amplify signals S1 and S2. Signals S1 and S2 are transmitted via antenna 119. Signals S1 and S2 have different or non-overlapping frequency bands.

[0026] Compared to Figure 2A Application scenarios, Figure 2B The application scenarios are more power-efficient because the driver amplifier 124 and PA 125 can be turned off. In some cases, when the signal quality requirements are relatively low, the signal power is relatively low, and / or the signal modulation scheme is relatively simple, the electronic device 200 can operate at... Figure 2B Application scenarios to save electricity.

[0027] Electronic device 200 is a multi-input multi-carrier circuit. In some embodiments, electronic device 200 is part of a wireless transceiver and can be used with signals such as Wi-Fi or Long Term Evolution (LTE) technologies (e.g., 4G, 5G).

[0028] In some embodiments, PA 125 may be omitted if the gain of the drive amplifier 124 is high enough.

[0029] Please see Figures 3A-3B , Figures 3A-3B This is a circuit diagram of one embodiment of the multi-input amplifier circuit 214 of the present invention. Figure 3A and Figure 3B The operation states correspond to respectively Figure 2A and Figure 2B .

[0030] The multi-input amplifier circuit 214 includes amplifier 305, power divider 330, power combiner 340, PA 350, and switches SW4, SW5, and SW6. Power divider 330 has input terminal N4, output terminal N5, and output terminal N6. Amplifier 305 includes driver amplifiers 310 and 320. Switches SW4, SW5, and SW6 are all single-pole double-throw switches and are all controlled by baseband circuit 211 or baseband circuit 221.

[0031] The first terminal of switch SW4 is coupled or electrically connected to input terminal N1 (to receive signal S1); the second terminal of switch SW4 is coupled or electrically connected to input terminal N4 of power divider 330; the third terminal of switch SW4 is coupled or electrically connected to drive amplifier 310 via switch SW5.

[0032] The first terminal of switch SW5 is coupled or electrically connected to input terminal N1 via switch SW4 (to receive signal S1); the second terminal of switch SW5 is coupled or electrically connected to output terminal N5 of power divider 330; and the third terminal of switch SW5 is coupled or electrically connected to drive amplifier 310.

[0033] The first terminal of switch SW6 is coupled or electrically connected to input terminal N2 (to receive signal S2); the second terminal of switch SW6 is coupled or electrically connected to output terminal N6 of power divider 330; and the third terminal of switch SW6 is coupled or electrically connected to drive amplifier 320.

[0034] exist Figure 3A In the operating mode, the power divider 330 generates intermediate signals S1_1 and S1_2 based on signal S1. The sum of the power of intermediate signal S1_1 and the power of intermediate signal S1_2 is substantially equal to the power of signal S1. In some embodiments, the power ratio of intermediate signal S1_1 to intermediate signal S1_2 can be 1:1. The operating principle of the power divider 330 is well known to those skilled in the art and will not be described in detail here.

[0035] The driver amplifier 310 amplifies the intermediate signal S1_1 to generate signal S3. The output of the driver amplifier 310 is coupled to or electrically connected to the power combiner 340.

[0036] The driver amplifier 320 amplifies the intermediate signal S1_2 to generate signal S4. The output of the driver amplifier 320 is coupled to or electrically connected to the power combiner 340.

[0037] Power combiner 340 is coupled or electrically connected to drive amplifier 310, drive amplifier 320, and PA 350. Power combiner 340 combines signals S3 and S4 to generate signal S5. In other words, the power of signal S5 is substantially equal to the sum of the power of signal S3 and the power of signal S4.

[0038] PA 350 amplifies signal S5 to generate the amplified signal Sout.

[0039] In some embodiments, if the gains of drive amplifiers 310 and 320 are sufficiently high, PA 350 can be omitted. In this case, the amplified signal Sout is equal to the signal S5.

[0040] exist Figure 3A In the operating mode, switch SW4 connects input terminal N1 to input terminal N4 of power divider 330, enabling power divider 330 to receive signal S1. Output terminals N5 and N6 of power divider 330 are connected to driver amplifier 310 and driver amplifier 320, respectively. Therefore, driver amplifier 310 and driver amplifier 320 amplify intermediate signals S1_1 and S1_2, respectively. In other words, signal S5 is equivalent to signal S1 amplified by amplifier 305.

[0041] Please see Figure 3B .exist Figure 3B In this operating mode, switches SW4 and SW5 connect the input terminal of driver amplifier 310 to input terminal N1, while switch SW6 connects the input terminal of driver amplifier 320 to input terminal N2. Therefore, power divider 330 is inactive, and driver amplifiers 310 and 320 amplify signals S1 and S2 respectively to generate signals S3 and S4. In other words, signal S5 is a combination of amplified signal S1 (essentially signal S3) and amplified signal S2 (essentially signal S4).

[0042] Please see Figures 4A-4B , Figures 4A-4B This is a circuit diagram of another embodiment of the multi-input amplifier circuit 214 of the present invention. Figure 4A and Figure 4B The operation states correspond to respectively Figure 2A and Figure 2B .

[0043] The multi-input amplifier circuit 214 includes amplifier 405, power divider 430, power combiner 440, PA 450, switch SW7, and switch SW8. Amplifier 405 includes driver amplifier 410 and driver amplifier 420. Switch SW7 is a single-pole double-throw switch. Both switches SW7 and SW8 are controlled by baseband circuit 211 or baseband circuit 221.

[0044] The power divider 430 includes a first primary side coil 432a, a first secondary side coil 432b, a second primary side coil 434a, and a second secondary side coil 434b.

[0045] One end N7 of the first primary coil 432a is coupled or electrically connected to the input terminal N1 (to receive signal S1); the other end N8 of the first primary coil 432a is coupled or electrically connected to the switch SW7. Terminals N7 and N8 constitute the first input port of the power divider 430.

[0046] The two ends (N9 and N10, which constitute the first output port of the power divider 430) of the first and second side coils 432b are coupled or electrically connected to drive amplifier 410.

[0047] One end N11 of the second primary coil 434a is coupled to or electrically connected to switch SW8; the other end N12 of the second primary coil 434a is coupled to or electrically connected to reference voltage GND. Ends N11 and N12 constitute the second input port of power divider 430.

[0048] The two ends (N13 and N14, which constitute the second output port of the power divider 430) of the second secondary side coil 434b are coupled or electrically connected to drive amplifier 420.

[0049] The power combiner 440 is a multi-tap transformer. The power combiner 440 includes a first primary winding 442a, a first secondary winding 442b, a second primary winding 444a, and a second secondary winding 444b.

[0050] The two ends (N15 and N16, which constitute the first input port of the power combiner 440) of the first primary side coil 442a are coupled or electrically connected to the output of the driver amplifier 410 to receive the signal S3.

[0051] One end N17 of the first secondary side coil 442b (i.e., one of the outputs of the power combiner 440) is coupled or electrically connected to PA 450; the other end N18 of the first secondary side coil 442b is coupled or electrically connected to one end N21 of the second secondary side coil 444b.

[0052] The two ends (N19 and N20, which constitute the second input port of the power combiner 440) of the second primary coil 444a are coupled or electrically connected to the output of the driver amplifier 420 to receive the signal S4.

[0053] The other end N22 of the secondary side coil 444b is coupled to or electrically connected to the reference voltage GND.

[0054] Terminals N17 and N22 constitute the output ports of the power combiner 440.

[0055] The first terminal of switch SW7 is coupled or electrically connected to the reference voltage GND (e.g., ground); the second terminal of switch SW7 is coupled or electrically connected to terminal N8 of the first primary side coil 432a. The third terminal of switch SW7 is coupled or electrically connected to terminal N11 of the second primary side coil 434a.

[0056] One end of switch SW8 is coupled or electrically connected to input terminal N2 to receive signal S2; the other end of switch SW8 is coupled or electrically connected to switch SW7 and terminal N11 of the second primary coil 434a.

[0057] The first output port of the power divider 430 outputs an intermediate signal S1_1 and is coupled or electrically connected to the driver amplifier 410; the second output port of the power divider 430 outputs an intermediate signal S1_2 and is coupled or electrically connected to the driver amplifier 420.

[0058] The power combiner 440 combines signals S3 and S4 to generate signal S5. In other words, the power of signal S5 is essentially equal to the sum of the power of signal S3 and the power of signal S4.

[0059] PA 450 is coupled or electrically connected to power combiner 440 to amplify signal S5 to produce amplified signal Sout.

[0060] In some embodiments, if the gains of drive amplifiers 410 and 420 are sufficiently high, PA 450 can be omitted. In this case, the amplified signal Sout is equal to the signal S5.

[0061] exist Figure 4A In the operating mode, switch SW7 connects terminal N8 of the first primary coil 432a to terminal N11 of the second primary coil 434a, and switch SW8 does not connect terminal N11 of the second primary coil 434a to input terminal N2. Therefore, power divider 430 generates intermediate signals S1_1 and S1_2 according to signal S1. In some embodiments, the power ratio of intermediate signal S1_1 to intermediate signal S1_2 can be 1:1. Figure 4AAs shown, when the first primary winding 432a and the second primary winding 434a are connected in series through switch SW7, the power divider 430 forms a multi-tap transformer. The operating principle of the power divider 430 is well known to those skilled in the art, and therefore will not be described in detail.

[0062] Please see Figure 4B .exist Figure 4B In the operating mode, switch SW7 connects terminal N8 of the first primary coil 432a to the reference voltage GND (instead of terminal N11 of the second primary coil 434a), and switch SW8 is turned on to connect terminal N11 of the second primary coil 434a to the input terminal N2. Therefore, the first primary coil 432a and the second primary coil 434a are not connected in series, and the power divider 430 essentially contains two transformers: transformer 432 (composed of the first primary coil 432a and the first secondary coil 432b) and transformer 434 (composed of the second primary coil 434a and the second secondary coil 434b). Thus, intermediate signal S1_1 is essentially equal to signal S1, and intermediate signal S1_2 is essentially equal to signal S2. In other words, signal S5 is a combination of amplified signal S1 (essentially signal S3) and amplified signal S2 (essentially signal S4).

[0063] The adjustment of signal coupling power and / or voltage by adjusting the turns ratio of the coil is well known to those skilled in the art, and will not be described in detail here.

[0064] Please see Figures 5A-5B , Figures 5A-5B This is a circuit diagram of another embodiment of the multi-input amplifier circuit 214 of the present invention. Figure 5A and Figure 5B The operation states correspond to respectively Figure 2A and Figure 2B .

[0065] The multi-input amplifier circuit 214 includes a power divider 610, an amplifier 620, a power combiner 630, and a power amplifier (PA) 640.

[0066] The power divider 610 includes couplers 612, 614, and 616, as well as switches SW9, SW10, and SW11. Switches SW9 to SW11 are single-pole double-throw switches.

[0067] The first terminal of switch SW9 is coupled or electrically connected to input terminal N1 to receive signal S1; the second terminal of switch SW9 is coupled or electrically connected to switch SW10; the third terminal of switch SW9 is coupled or electrically connected to input terminal N23 of coupler 612.

[0068] The first terminal of switch SW10 is coupled to or electrically connected to switch SW9; the second terminal of switch SW10 is coupled to or electrically connected to the input terminal N27 of coupler 614; and the third terminal of switch SW10 is coupled to or electrically connected to the output terminal N25 of coupler 612.

[0069] The first terminal of switch SW11 is coupled or electrically connected to input terminal N2 to receive signal S2; the second terminal of switch SW11 is coupled or electrically connected to output terminal N26 of coupler 612; and the third terminal of switch SW11 is coupled or electrically connected to input terminal N31 of coupler 616.

[0070] The input terminal N23 of coupler 612 is coupled or electrically connected to switch SW9; the input terminal N24 of coupler 612 is coupled or electrically connected to reference voltage GND; the output terminal N25 of coupler 612 is coupled or electrically connected to switch SW10; the output terminal N26 of coupler 612 is coupled or electrically connected to switch SW11.

[0071] The input terminal N27 of coupler 614 is coupled or electrically connected to switch SW10; the input terminal N28 of coupler 614 is coupled or electrically connected to reference voltage GND; the output terminal N29 of coupler 614 is coupled or electrically connected to drive amplifier 622; the output terminal N30 of coupler 614 is coupled or electrically connected to drive amplifier 624.

[0072] The input terminal N31 of coupler 616 is coupled or electrically connected to switch SW11; the input terminal N32 of coupler 616 is coupled or electrically connected to reference voltage GND; the output terminal N33 of coupler 616 is coupled or electrically connected to drive amplifier 626; the output terminal N34 of coupler 616 is coupled or electrically connected to drive amplifier 628.

[0073] Coupler 614 outputs intermediate signal S1_1. Coupler 616 outputs intermediate signal S1_2.

[0074] Amplifier 620 includes driver amplifiers 622-628 and capacitors C1-C4. Capacitor C1 is coupled between the output of driver amplifier 622 and power combiner 630. Capacitor C2 is coupled between the output of driver amplifier 624 and power combiner 630. Capacitor C3 is coupled between the output of driver amplifier 626 and power combiner 630. Capacitor C4 is coupled between the output of driver amplifier 628 and power combiner 630.

[0075] Driver amplifiers 622-628 receive power supply voltages VDD1, VDD2, VDD3, and VDD4, respectively. The characteristics or output power of driver amplifiers 622-628 can be adjusted by changing the power supply voltages VDD1-VDD4. A higher power supply voltage results in higher power or gain for the corresponding driver amplifier.

[0076] Driver amplifiers 622 and 624 amplify the intermediate signal S1_1 to generate signal S3. Driver amplifiers 626 and 628 amplify the intermediate signal S1_2 to generate signal S4.

[0077] In some embodiments, capacitors C1 to C4 can be omitted to save costs.

[0078] The power combiner 630 combines signals S3 and S4 to generate signal S5. In other words, the power of signal S5 is essentially equal to the sum of the power of signal S3 and the power of signal S4.

[0079] In some embodiments, if the gain of the driver amplifiers 622-628 is sufficiently high, PA 640 can be omitted. In this case, the amplified signal Sout is equal to the signal S5.

[0080] exist Figure 5A In the operating mode, switch SW9 connects input terminal N23 of coupler 612 to input terminal N1, switch SW10 connects input terminal N27 of coupler 614 to output terminal N25 of coupler 612, and switch SW11 connects input terminal N31 of coupler 616 to output terminal N26 of coupler 612. Therefore, power divider 610 generates intermediate signals S1_1 and S1_2 based on signal S1. The sum of the power of intermediate signal S1_1 and the power of intermediate signal S1_2 is substantially equal to the power of signal S1. In other words, signal S5 is equivalent to signal S1 amplified by amplifier 620. In some embodiments, the power ratio of intermediate signal S1_1 to intermediate signal S1_2 can be 1:1.

[0081] In some embodiments, couplers 612-616 can be implemented as Lange couplers or branch-line couplers. The advantage of Lange couplers and branch-line couplers is their stable impedance. The operating principles of Lange couplers and branch-line couplers are well known to those skilled in the art and will not be described further.

[0082] exist Figure 5B In the operating mode, switches SW9 and SW10 connect input terminal N27 of coupler 614 to input terminal N1, and switch SW11 connects input terminal N31 of coupler 616 to input terminal N2. Therefore, coupler 612 is not activated, the power of intermediate signal S1_1 is substantially equal to the power of signal S1, and the power of intermediate signal S1_2 is substantially equal to the power of signal S2. In other words, signal S5 is equivalent to the result of signal S1 and signal S2 being amplified by amplifier 620.

[0083] In summary, the multi-input amplifier circuit 214 of the present invention can operate in single-input mode. Figure 2A , Figure 3A , Figure 4A and Figure 5A or multiple input modes Figure 2A , Figure 3B , Figure 4B and Figure 5B In multi-input mode, the amplifier circuit of transceiver circuit 220 (i.e., driver amplifier 124 and / or PA 125) can be turned off to save power consumption. Therefore, the electronic device 200 of the present invention can balance bandwidth and power consumption.

[0084] Please note that the shapes, sizes, and proportions of the components in the above-mentioned illustrations are merely illustrative and intended to help those skilled in the art understand the present invention, and are not intended to limit the present invention.

[0085] While the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention. Those skilled in the art can make changes to the technical features of the present invention based on the explicit or implicit content of the present invention, and all such changes may fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be determined by the scope of the patent application in this specification.

[0086] Symbol Explanation

[0087] 100, 200: Electronic devices

[0088] 110, 120, 210, 220: Transceiver circuits

[0089] 111, 121, 211, 221: Baseband circuit

[0090] 112, 122: DAC (Digital-to-Analog Converter)

[0091] 113, 123: Transmission circuit

[0092] 114, 124, 310, 320, 410, 420, 622, 624, 626, 628: Driver amplifiers

[0093] 115, 125, 350, 450, 640: PA (Power Amplifier)

[0094] 116, 126: LNA (Low Noise Amplifier)

[0095] 117, 127: Receiving circuit

[0096] 118, 128: ADC (Analog-to-Digital Converter)

[0097] 119, 129: Antenna

[0098] SW1, SW2, SW3, SW4, SW5, SW6, SW7, SW8, SW10, SW11, SW9: Switches

[0099] 214: Multi-input amplifier circuit

[0100] Ctrl: Control signal

[0101] N1, N2, N4, N23, N24, N27, N28, N31, N32: Input terminals

[0102] N3, N5, N6, N25, N26, N29, N30, N33, N34: Output terminals

[0103] S1, S2, S3, S4, S5: Signals

[0104] Sout: Amplified signal

[0105] 305, 405, 620: Amplifiers

[0106] 330, 430, 610: Power dividers

[0107] 340, 440, 630: Power Combiners

[0108] S1_1, S1_2: Intermediate signals

[0109] 432a, 442a: First primary winding

[0110] 432b, 442b: First and secondary side coils

[0111] 434a, 444a: Second primary winding

[0112] 434b, 444b: Secondary side coil

[0113] GND: Reference voltage

[0114] N7, N8, N9, N10, N11, N12, N13, N14, N15, N16, N17, N18, N19, N20, N21, N22: End

[0115] 432, 434: Transformers

[0116] 612, 614, 616: Couplers

[0117] C1, C2, C3, C4: Capacitors

[0118] VDD1, VDD2, VDD3, VDD4: Power supply voltage

Claims

1. An electronic device comprising: First baseband circuit; A second baseband circuit; A first transceiver circuit, coupled to the first baseband circuit, includes: A first transmission circuit, coupled to the first baseband circuit; and A multi-input amplifier circuit is coupled to the first transmission circuit; A second transceiver circuit, coupled to the second transceiver circuit, includes: A second transmission circuit, coupled to the second baseband circuit; and A driver amplifier; and A switch is coupled to the second transmission circuit, the multi-input amplifier circuit, and the driver amplifier; in, The switch is controlled by the first baseband circuit or the second baseband circuit and is used to connect the second transmission circuit to the multi-input amplifier circuit or the driver amplifier.

2. The electronic device as claimed in claim 1, wherein, The multi-input amplifier circuit has a first input terminal and a second input terminal. The first input terminal is coupled to the first transmission circuit, and the second input terminal is coupled to the switch. The multi-input amplifier circuit includes: A power divider is coupled to the first input terminal; An amplifier, coupled to the power divider, is used to generate a first signal and a second signal; and A power combiner, coupled to the amplifier, is used to combine the first signal and the second signal to generate a third signal.

3. The electronic device as claimed in claim 2, wherein, The first transmission circuit outputs a fourth signal. When the switch connects the second transmission circuit to the drive amplifier, the power divider generates a first intermediate signal and a second intermediate signal based on the fourth signal, and the amplifier amplifies the first intermediate signal and the second intermediate signal to generate the first signal and the second signal respectively.

4. The electronic device as claimed in claim 3, wherein, This power divider includes: A first primary winding has a first terminal and a second terminal, wherein the first terminal is coupled to the first input terminal; A primary and secondary side coil are coupled to the amplifier; A second primary winding has a third terminal and a fourth terminal, wherein the third terminal is coupled to the second terminal, and the fourth terminal is coupled to a reference voltage; and A second secondary side coil is coupled to the amplifier.

5. The electronic device as claimed in claim 3, wherein, This power divider includes: A first coupler has a third input terminal, a fourth input terminal, a first output terminal and a second output terminal, wherein the third input terminal is coupled to the first input terminal and the fourth input terminal is coupled to a reference voltage. A second coupler has a fifth input terminal, a sixth input terminal, a third output terminal, and a fourth output terminal, wherein the fifth input terminal is coupled to the first output terminal, the sixth input terminal is coupled to the reference voltage, and the third and fourth output terminals are coupled to the amplifier; and A third coupler has a seventh input, an eighth input, a fifth output, and a sixth output, wherein the seventh input is coupled to the second output, the eighth input is coupled to the reference voltage, and the fifth and sixth outputs are coupled to the amplifier.

6. The electronic device as claimed in claim 2, wherein, The first transmission circuit outputs a fourth signal, and the second transmission circuit outputs a fifth signal. When the switch connects the second transmission circuit to the multi-input amplifier circuit, the amplifier amplifies the fourth signal and the fifth signal to generate the first signal and the second signal respectively.

7. The electronic device as claimed in claim 6, wherein, This power divider includes: A first primary side coil has a first terminal and a second terminal, wherein the first terminal is coupled to the first input terminal and the second terminal is coupled to a reference voltage; A primary and secondary side coil are coupled to the amplifier; A second primary winding has a third terminal and a fourth terminal, wherein the third terminal is coupled to the second input terminal and the fourth terminal is coupled to the reference voltage; and A second secondary side coil is coupled to the amplifier.

8. The electronic device as claimed in claim 6, wherein, This power divider includes: A first coupler has a third input terminal, a fourth input terminal, a first output terminal, and a second output terminal, wherein the third input terminal is coupled to the first input terminal, the fourth input terminal is coupled to a reference voltage, and the first and second output terminals are coupled to the amplifier; and A second coupler has a fifth input terminal, a sixth input terminal, a third output terminal and a fourth output terminal, wherein the fifth input terminal is coupled to the second input terminal, the sixth input terminal is coupled to the reference voltage, and the third output terminal and the fourth output terminal are coupled to the amplifier.

9. A multi-input amplifier circuit having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is used to receive a first signal, and the second input terminal is used to receive a second signal, the multi-input amplifier circuit comprising: A power divider includes a first primary winding, a first secondary winding, a second primary winding, and a second secondary winding, used to generate a first intermediate signal and a second intermediate signal, wherein... The first primary side coil is coupled to the first input terminal, and the second primary side coil is coupled to a reference voltage; A first switch is coupled to the first primary side coil and the second primary side coil; A second switch is coupled to the second input terminal and the second primary coil; An amplifier, coupled to the first secondary winding and the second secondary winding, is used to amplify the first intermediate signal and the second intermediate signal to generate a third signal and a fourth signal, respectively; and A power combiner, coupled to the amplifier and the output, is used to combine the third signal and the fourth signal to generate a fifth signal.

10. A multi-input amplifier circuit having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is used to receive a first signal, and the second input terminal is used to receive a second signal, the multi-input amplifier circuit comprising: A power divider, coupled to the first input terminal and the second input terminal, is used to generate a first intermediate signal and a second intermediate signal, and includes a first coupler, a second coupler and a third coupler coupled to each other. An amplifier, coupled to the power divider, is used to amplify the first intermediate signal and the second intermediate signal to generate a third signal and a fourth signal, respectively; and A power combiner, coupled to the amplifier and the output, is used to combine the third signal and the fourth signal to generate a fifth signal.

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