Receiver device and method of operating a receiver device

Abstract

A receiver device and a method of operating a receiver device are provided. The receiver device includes a receiver LC resonant circuit including a receiver load capacitor and a receiver coil, and the receiver LC resonant circuit is configured to receive wireless charging power induced from a transmitter device; a rectifier circuit configured to rectify, responsive to a rectifier gate signal, a receiver AC voltage of a differential signal provided from the receiver LC resonant circuit to a rectified voltage; and an overvoltage protection circuit configured to generate and output the rectifier gate signal to the rectifier circuit. The overvoltage protection circuit is configured to generate the rectifier gate signal to cause a shift in a phase of the differential signal between the receiver AC voltages relative to a receiver coil current in the receiver coil responsive to the rectified voltage reaching or exceeding an overvoltage rise threshold.

Description

Technical Field

[0001] This disclosure relates to a receiver device and a method of operating the receiver device. Background Technology

[0002] With the development of information technology (IT), various types of electronic devices, such as smartphones and tablet PCs, have become widely available. For portability, battery modules are commonly included in such devices. Wireless charging technology for battery modules has advanced to improve user convenience, and charging power continues to increase, thus shortening charging time.

[0003] However, as charging voltages increase to boost charging power, transient overvoltages exceeding the withstand voltage of integrated circuits in electronic devices can occur. Therefore, overvoltage protection (OVP) is becoming increasingly important in wireless charging systems. Summary of the Invention

[0004] One object of this disclosure is to provide a wireless charging system with improved voltage clamping efficiency through quasi-reactive rectification operation.

[0005] Another object of this disclosure is to provide a wireless charging system that mitigates unnecessary power consumption and potential damage caused by coil current during overvoltage operation by adjusting the coil current.

[0006] The purposes of this disclosure are not limited to those described above, and other purposes not explicitly stated will be clearly understood by those skilled in the art based on the following description.

[0007] According to one aspect of this disclosure, a receiver device is provided, the receiver device comprising: a receiver LC resonant circuit including a receiver load capacitor and a receiver coil, and the receiver LC resonant circuit being configured to receive wireless charging power from a transmitter device; a rectifier circuit configured to rectify a receiver AC voltage of a differential signal provided from the receiver LC resonant circuit into a rectified voltage in response to a rectifier gate signal; and an overvoltage protection circuit configured to generate a rectifier gate signal and output the rectifier gate signal to the rectifier circuit. The overvoltage protection circuit is configured to generate a rectifier gate signal such that, in response to the rectified voltage reaching or exceeding an overvoltage rise threshold, a phase shift of the differential signal between the receiver AC voltages relative to the receiver coil current in the receiver coil is caused.

[0008] One embodiment of the receiver device is further configured such that the overvoltage protection circuit is configured to generate a rectifier gate signal to cause the rectifier circuit to perform quasi-reactive rectification, thereby achieving voltage clamping of the rectified voltage.

[0009] The receiver device is further configured such that the rectifier circuit is configured to perform quasi-reactive rectification in response to receiving a rectifier gate signal, so as to reduce the rectified voltage below an overvoltage rise threshold.

[0010] Another embodiment of the receiver device is further configured such that the overvoltage protection circuit is also configured to generate a rectifier gate signal in response to the rectified voltage dropping below an overvoltage drop threshold after voltage clamping has been enabled, to shift the phase of the differential signal between the receiver AC voltages relative to the receiver coil current, such that the phase difference is substantially zero degrees.

[0011] According to one aspect of this disclosure, a method of operating a receiver device that wirelessly receives power from a transmitter device, the method comprising: comparing a rectified voltage of the receiver device with an overvoltage rise threshold; generating coil sensing information by sensing a receiver coil current induced from the transmitter device via a receiver coil; obtaining a rising edge zero signal indicating a rising edge zero of the coil sensing information and a falling edge zero signal indicating a falling edge zero of the coil sensing information; shifting the indicated rising edge zero and falling edge zero relative to a zero in the current in a first direction by applying a first delay to the rising edge zero signal and the falling edge zero signal, the first direction corresponding to phase lag or phase lead; generating a rectifier gate signal for a rectifier circuit based on the delayed rising edge zero signal and the delayed falling edge zero signal; and adjusting the rectified voltage by applying the adjusted rectifier gate signal to the rectifier circuit to adjust the phase difference between a differential signal between the receiver AC voltage and the receiver coil current.

[0012] According to an aspect of this disclosure, a receiver device includes: a receiver LC resonant circuit including a receiver load capacitor and a receiver coil; a coil current sensor configured to generate coil sensing information by sensing a current induced from a transmitter device via the receiver coil; a rectifier circuit including a plurality of switching transistors switched in response to a rectifier gate signal, and the rectifier circuit configured to receive a receiver AC voltage generated by the receiver LC resonant circuit and rectify the receiver AC voltage into a rectified voltage; an overvoltage protection circuit configured to generate a rectifier gate signal based on a comparison between an overvoltage reference level and the rectified voltage, and output the rectifier gate signal to the rectifier circuit; and a primary low-dropout (LDO) circuit configured to output a power supply voltage from the rectified voltage after noise removal, wherein the rectifier circuit is configured to adjust the phase difference between a differential signal between the receiver AC voltages and the receiver coil current based on the rectifier gate signal received from the overvoltage protection circuit.

[0013] The receiver device is further configured such that the rectifier circuit is configured to perform quasi-reactive rectification, thereby adjusting the phase between the differential signal between the receiver AC voltage and the receiver coil current based on the rectifier gate signal received from the overvoltage protection circuit.

[0014] The receiver device is further configured such that the rectifier circuit is configured to perform quasi-reactive rectification to generate a rectified voltage at a voltage level lower than the overvoltage reference level stored in the receiver device.

[0015] The receiver device is further configured such that: the phase direction determination circuit is configured to turn on the first and second transmission transistors in response to a first logic level of the polarity test signal, thereby generating a rectified voltage having a first rectified voltage level, and to turn off the first and second transmission transistors in response to a second logic level of the polarity test signal, thereby generating a rectified voltage having a second rectified voltage level.

[0016] According to an aspect of this disclosure, a receiver device includes: a receiver LC resonant circuit including a receiver load capacitor and a receiver coil; a coil current sensor configured to generate coil sensing information by sensing a current induced from a transmitter device via the receiver coil; a rectifier circuit including a plurality of switching transistors switched in response to a rectifier gate signal, and the rectifier circuit configured to receive a receiver AC voltage generated by the receiver LC resonant circuit and rectify the receiver AC voltage into a rectified voltage; an overvoltage protection circuit configured to generate a rectifier gate signal based on a comparison between an overvoltage reference level and the rectified voltage, and output the rectifier gate signal to the rectifier circuit; and a primary low-dropout (LDO) circuit configured to output a power supply voltage from the rectified voltage after noise removal, wherein the rectifier circuit is configured to adjust the phase difference between a differential signal between the receiver AC voltages and the receiver coil current based on the rectifier gate signal received from the overvoltage protection circuit.

[0017] It should be noted that the effects of this disclosure are not limited to those described above, and other effects of this disclosure will be clear from the following description. Attached Figure Description

[0018] The above and other aspects and features of this disclosure will become clearer from the detailed description of exemplary embodiments with reference to the accompanying drawings.

[0019] Figure 1 This is a block diagram illustrating a wireless charging system according to some embodiments of the present disclosure.

[0020] Figure 2 It is shown Figure 1 Block diagram of the receiver MCU in the system.

[0021] Figure 3 It is shown Figure 1 Block diagram of the overvoltage protection (OVP) circuit.

[0022] Figure 4 It is used for explanation Figure 1 The timing diagram of the operation of the wireless charging system.

[0023] Figure 5 This is shown as a model of time-domain wireless power transmission. Figure 1 Wireless charging system.

[0024] Figure 6 Showing with Figure 5 The frequency domain wireless power transmission model corresponds to the wireless power transmission model.

[0025] Figure 7 It is shown in Figure 6 The diagram shows a simplified RX-side power transmission model using resistive rectified impedance in the wireless power transmission model. Figure 8 It is used for explanation Figure 7 A graph showing the operation of the RX-side power transmission model.

[0026] Figure 9 Shown in Figure 7 The simplified RX-side power transmission model uses quasi-reactive rectifier impedance in the wireless power transmission model. Figure 10 It is used for explanation Figure 9 A graph showing the operation of the RX-side power transmission model.

[0027] Figure 11 It is a phase-voltage graph used to explain the clamping effect on the rectified voltage in a wireless charging system using quasi-reactive rectification according to some embodiments.

[0028] Figure 12 The RX-side power transmission model shows a comparative example using clamping resistors.

[0029] Figure 13 It is a comparison Figure 12 A comparative example is shown in the graph of coil current increase relative to clamping voltage level between this disclosure and the present disclosure.

[0030] Figure 14 This is a detailed block diagram of a rectified gate signal generator according to some embodiments.

[0031] Figure 15 yes Figure 14 Block diagram of the gate signal generator.

[0032] Figure 16 It is used for explanation Figure 1Timing diagram of an embodiment of the operation of a wireless charging system.

[0033] Figure 17 It is used for explanation Figure 1 A timing diagram of another embodiment of the operation of the wireless charging system.

[0034] Figure 18 It is used for explanation Figure 1 A timing diagram of another embodiment of the operation of the wireless charging system.

[0035] Figure 19 The graphs show the rectified voltage, RX AC voltage, and coil current of a wireless charging system operating under overvoltage conditions according to some embodiments.

[0036] Figure 20 This is a block diagram illustrating a wireless charging system according to some embodiments of the present disclosure.

[0037] Figure 21 It is used to explain how to determine Figure 20 The time-voltage curve of the phase shift direction in the wireless charging system.

[0038] Figure 22 It is used for explanation Figure 20 A flowchart illustrating the operation method of a wireless charging system.

[0039] Figure 23 This shows how to determine Figure 20 The reactance component X in a wireless charging system RX The polarity of the RX-side power transmission model.

[0040] Figure 24 This is a flowchart illustrating an operation method of a wireless charging system according to some embodiments of the present disclosure. Detailed Implementation

[0041] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements and / or components, regions, these elements and / or components should not be limited by these terms. Unless the context otherwise requires, these terms are used only (e.g., as a naming convention) to distinguish one element or component from another. Therefore, without departing from the teachings of the invention, the first element or first component discussed below in a portion of the specification may be referred to as the second element or second component in other portions of the specification or in the claims. Furthermore, in certain cases, even if the terms "first," "second," etc., are not used in the specification, they may still be referred to as "first" or "second" in the claims in order to distinguish the different claimed elements from each other.

[0042] As can be seen, for example, in the accompanying drawings, items described herein in a singular form may be provided in a plural form. Therefore, unless the context otherwise requires, a description of a single item provided in a plural form should be understood to apply to the remaining multiple items.

[0043] Throughout this specification, unless the context otherwise requires, when a component is described as “comprising” a particular element or group of elements, it will be understood that the component is formed solely by that element or group of elements, or that the element or group of elements may be combined with other elements to form the component.

[0044] It will be understood that when a component is referred to as "connected" to another component, it can be directly connected to or combined with the other component, or there may be an intermediate component.

[0045] Figure 1 This is a block diagram illustrating a wireless charging system according to some embodiments of the present disclosure. Figure 2 It is shown Figure 1 Block diagram of the receiver microcontroller unit (MCU) in the system. Figure 3 It is shown Figure 1 Block diagram of the overvoltage protection (OVP) circuit. Figure 4 It is used for explanation Figure 1 The timing diagram of the operation of the wireless charging system.

[0046] Reference Figure 1 and Figure 2 The transmitter (TX) device 10 includes an input power supply 11, an inverter 12, and a TX LC resonant circuit 17 (also referred to as an LC circuit).

[0047] The input power (or input voltage) V that the input power supply 11 will send from the TX device 10 IN Provided to receiver (RX) device 20. Inverter 12 includes inverter controller 13 and TX bridge circuit 14. Inverter controller 13 generates first TX rectifier gate signal QG1. TX The second TX rectifier gate signal QG2 TX The third TX rectifier gate signal QG3 TX and the gate signal QG4 of the fourth TX rectifier TX The TX bridge circuit 14 is connected between the input power supply 11 and the ground terminal, and includes the gate signal QG1 of the first TX rectifier. TX The second TX rectifier gate signal QG2 TX The third TX rectifier gate signal QG3 TX and the gate signal QG4 of the fourth TX rectifier TXFour switching transistors QTx1, QTx2, QTx3, and QTx4 are turned on / off, and generate the TX coil current ICOIL at the output of the TX bridge circuit 14. TX .

[0048] The TX bridge circuit 14 operates according to the first TX rectifier gate signal QG1. TX The second TX rectifier gate signal QG2 TX The third TX rectifier gate signal QG3 TX and the gate signal QG4 of the fourth TX rectifier TX The four switching transistors are complementary, generating a first TX AC voltage AC1 between the opposite ends of the bridge. TX Second TX AC voltage AC2 TX The first TX AC voltage AC1 of complementary switching TX Second TX AC voltage AC2 TX AC power or an AC power signal is supplied to the TX LC resonant circuit 17, thereby transmitting wireless charging power to the RX device 20. The TX LC resonant circuit 17 includes a TX load capacitor C. P And the TX coil, the TX coil is composed of the TX inductor L P and TX parasitic resistor R P express.

[0049] RX device 20 includes an RX LC resonant circuit 21, a rectifier circuit 30, a main low-dropout (LDO) regulator circuit (or main low-dropout (LDO) circuit) 40, an RX microcontroller unit (MCU) 50 (also referred to as a microcontroller), a battery 60, and an overvoltage protection (OVP) circuit 100. The MCU may be logic circuitry forming a controller (e.g., a hardware processor (e.g., a CPU)) for the device (in this example, for RX device 20).

[0050] The RX LC resonant circuit 21 receives wireless charging power from the TX device 10. The RX LC resonant circuit 21 includes an RX load capacitor C. S And the RX coil, the RX coil is composed of the RX inductor L S and parasitic resistor R S express.

[0051] The rectifier circuit 30 is based on the first RX AC voltage AC1 generated by the RX LC resonant circuit 21. RX Second RX AC voltage AC2 RX and the RX coil current I generated by the RX LC resonant circuit 21 RL To generate rectified voltage V RECTIn some embodiments, the rectifier circuit 30 includes a plurality of RX switching transistors connected in a bridge configuration, the plurality of RX switching transistors receiving a first RX AC voltage AC1. RX Second RX AC voltage AC2 RX As input, and multiple RX switching transistors QRx1, QRx2, QRx3, and QRx4 are controlled by the first rectifier gate signal QG1. PH The second rectifier gate signal QG2 PH The third rectifier gate signal QG3 PH and the gate signal QG4 of the fourth rectifier PH Complementary switching, thereby generating rectified voltage V RECT and rectified current I RECT The multiple RX switching transistors (QRx1 to QRx4) included in the rectifier circuit 30 can be connected in the same configuration as the TX bridge circuit 14.

[0052] For example, rectifier circuit 30 includes a first path and a second path. The first path includes a first RX switching transistor QRx1 and a third RX switching transistor QRx3 connected in series, and the second path includes a second RX switching transistor QRx2 and a fourth RX switching transistor QRx4 connected in series. Unless the context otherwise requires, paths referred to herein will be understood as current paths or electrical paths. The first and second paths are connected in parallel between the output node and the ground node (PGND). The common node of the first and third RX switching transistors (QRx1 and QRx3) in the first path receives a first AC voltage AC1. RX The common node of the second RX switching transistor and the fourth RX switching transistor (QRx2 and QRx4) in the second path receives the second AC voltage AC2. RX The first RX switching transistor, the second RX switching transistor, the third RX switching transistor, and the fourth RX switching transistor (QRx1 to QRx4) are respectively powered by the gate signal QG1 of the first rectifier. PH The second rectifier gate signal QG2 PH The third rectifier gate signal QG3 PH and the gate signal QG4 of the fourth rectifier PH Switching. For example, the first RX switching transistor and the fourth RX switching transistor (QRx1 and QRx4) switch complementaryly with the second RX switching transistor and the third RX switching transistor (QRx2 and QRx3).

[0053] The main LDO circuit 40 draws from the rectified voltage V RECT Remove noise, and then change the power supply voltage V after noise removal. OUTA stable supply is provided to the battery 60. The main LDO circuit 40 includes a main LDO controller 41 and an LDO transfer transistor 42. The LDO controller 41 adjusts the power supply voltage V by providing a gate signal to the LDO transfer transistor 42 based on a reference voltage and feedback. OUT This is to minimize the voltage drop. The LDO transfer transistor 42 receives the voltage from the rectified voltage V. RECT The power supply voltage V after noise removal OUT Output to battery 60. The main LDO circuit 40 can output current I. OUT .

[0054] The RX MCU 50 is based on the setting signals (SEL_LOOP, SET_PHASE, V...) RECT_TARGET and SET_GATE_SIG[1:0]) and the rectified voltage V received from rectifier circuit 30 RECT This is used to generate various control signals. For example, the RX MCU 50 provides the gate signal control signals SET_GATE_SIG[1:0], first-type time delay information (SET_TRISE1 and SET_TFALL1), and second-type time delay information (SET_TRISE2 and SET_TFALL2) to the OVP circuit 100. Note that, depending on the context, "timing / time delay information" can refer to the information itself (e.g., data, values, or settings representing delays) and / or signals that include or convey such information.

[0055] Reference Figure 2 The RX MCU 50 can be implemented as including or used as a phase value generator 51, a set value selector 52, a first phase shift delay value generator 53, and a second phase shift delay value generator 54.

[0056] In some embodiments, the RX MCU 50 may receive a setting signal output from the firmware based on the state of the RX device 20 or user settings. The setting signal from the firmware may include, for example, a delay value selection signal SEL_LOOP, a phase setting value SET_PHASE, and a target rectified voltage V. RECT_TARGET And the gate signal control signal SET_GATE_SIG[1:0].

[0057] Phase value generator 51 will rectify voltage V RECT With the target rectified voltage V RECT_TARGET Compare and calculate the rectified voltage V RECT Achieve the target rectified voltage V RECT_TARGET The phase value is calculated and output as the target phase shift value PHASE. VRECT_TARGET .

[0058] The set value selector 52 selects either the phase set value SET_PHASE or the target phase shift value PHASE based on the delay value selection signal SEL_LOOP. VRECT_TARGET And output the selected value as the phase selection value PHASE_MUXED.

[0059] The first phase shift delay value generator 53 adjusts the phase selection value PHASE_MUXED according to the gate signal control signal SET_GATE_SIG[1:0], and outputs the adjusted value as second-type time delay information (SET_TRISE2 and SET_TFALL2) to the OVP circuit 100. The gate signal control signal SET_GATE_SIG[1:0] is a signal that selects the first path through the differentiator circuit (or differentiator) 221, the second path without a differentiator or integrator, or the third path through the integrator circuit (or integrator) 222, an example of which is shown in Figure 14 Described in the text.

[0060] For example, if the gate signal control signal SET_GATE_SIG[1:0] selects the first path, the first phase shift delay value generator 53 uses the differentiator 221 to adjust the phase selection value PHASE_MUXED, thereby generating and outputting first second-type time delay information. For example, if the gate signal control signal SET_GATE_SIG[1:0] selects the second path, the first phase shift delay value generator 53 adjusts the phase selection value PHASE_MUXED, thereby generating and outputting second second-type time delay information. For example, if the gate signal control signal SET_GATE_SIG[1:0] selects the third path, the first phase shift delay value generator 53 uses the integrator 222 to adjust the phase selection value PHASE_MUXED, thereby generating and outputting third second-type time delay information.

[0061] The first type of time delay information, the second type of time delay information, and the third type of time delay information can have different values.

[0062] The second phase shift delay value generator 54 outputs the first type of time delay information signals (SET_TRISE1 and SET_TFALL1) to the OVP circuit 100 according to the gate signal control signal SET_GATE_SIG[1:0].

[0063] For example, if the gate signal control signal SET_GATE_SIG[1:0] selects the first path, the second phase shift delay value generator 54 generates and outputs first type time delay information. If the gate signal control signal SET_GATE_SIG[1:0] selects the second path, the second phase shift delay value generator 54 generates and outputs second type time delay information by adjustment. If the gate signal control signal SET_GATE_SIG[1:0] selects the third path, the second phase shift delay value generator 54 generates and outputs third type time delay information.

[0064] The first type of time delay information, the second type of time delay information, and the third type of time delay information can have different values.

[0065] In some embodiments, the RX MCU 50 may output second type time delay information (SET_TRISE2 and SET_TFALL2) based on the phase setting value SET_PHASE output by the delay value selection signal SEL_LOOP as a first setting value, causing a phase shift of θ° to be performed, thereby allowing the rectifier gate signal generator 135 to generate a first rectifier gate signal QG1 corresponding to the first setting value. PH The second rectifier gate signal QG2 PH The third rectifier gate signal QG3 PH and the gate signal QG4 of the fourth rectifier PH In this case, due to the change in active reactance caused by phase lag or phase lead operation, the non-zero phase shift θ° can lead to a change in resonance characteristics, thereby realizing quasi-reactive rectification operation between RX device 20 and TX device 10.

[0066] In some embodiments, the RX MCU 50 may select the target phase shift value PHASE based on the delay value selection signal SEL_LOOP, which is a second setting value. VRECT_TARGET Output the second type of time delay information (SET_TRISE2 and SET_TFALL2) to make the rectified voltage V RECT Gradually or continuously change to achieve the target rectified voltage V RECT_TARGET This allows the rectifier gate signal generator 135 to generate a phase-shifted first rectifier gate signal QG1 corresponding to the second set value. PH Phase-shifted second rectifier gate signal QG2 PH Phase-shifted gate signal QG3 of the third rectifier PH and the phase-shifted fourth rectifier gate signal QG4 PH In this case, unlike the first setting value, the second setting value can be changed gradually or continuously until the rectified voltage V... RECTApproaching the target rectified voltage V RECT_TARGET until.

[0067] Reference Figure 3 The OVP circuit 100 includes a comparator 110, a coil current sensor 120, and a rectified power synchronous phase shift controller 130.

[0068] Comparator 110 converts the rectified voltage V generated by rectifier circuit 30 into voltage V. RECT Compared with the preset overvoltage reference level V REF_OVP The comparison is performed, and an overvoltage flag signal (FLAG) is generated based on the comparison result. OVP EN_PHASE_SHIFT serves as the phase shift control signal. Overvoltage reference level V REF_OVP The values ​​can be set by the RX MCU 50 or by the firmware. For example, the overvoltage reference level and other thresholds described herein can be programmed or stored (e.g., stored in non-volatile memory or registers) in the receiver device 20.

[0069] The rectified power synchronous phase shift controller 130 includes a rectified gate signal generator 135, a first multiplexer (MUX) 141, and a second multiplexer 142.

[0070] The first multiplexer 141 and the second multiplexer 142 select one of multiple time delay information (SET_TRISE1, SET_TRISE2, SET_TFALL1 and SET_FALL2) based on the phase shift control signal EN_PHASE_SHIFT, and provide the selected time delay information to the rectifier gate signal generator 135.

[0071] For example, when the phase shift control signal EN_PHASE_SHIFT is deactivated, the first multiplexer 141 selects and outputs the first rise time delay information SET_TRISE1 as the selected rise time delay information SET_TRISE_MUXED. For example, when the phase shift control signal EN_PHASE_SHIFT is activated, the first multiplexer 141 selects and outputs the second rise time delay information SET_TRISE2 as the selected rise time delay information SET_TRISE_MUXED.

[0072] For example, when the phase shift control signal EN_PHASE_SHIFT is deactivated, the second multiplexer 142 selects and outputs the first fall time delay information SET_TFALL1 as the selected fall time delay information SET_TFALL_MUXED. For example, when the phase shift control signal EN_PHASE_SHIFT is activated, the second multiplexer 142 selects and outputs the second fall time delay information SET_TFALL2 as the selected fall time delay information SET_TFALL_MUXED.

[0073] When the phase shift control signal EN_PHASE_SHIFT is deactivated (0), the rectifier gate signal generator 135 generates the first rectifier gate signal QG1 based on the selected rise time delay information SET_TRISE_MUXED and the selected fall time delay information SET_TFALL_MUXED. PH The second rectifier gate signal QG2 PH The third rectifier gate signal QG3 PH and the gate signal QG4 of the fourth rectifier PH This makes the first RX AC voltage AC1 RX With the second RX AC voltage AC2 RX The differential signal between (AC2) RX -AC1 RX ) has the same current I as the RX coil RL Same phase.

[0074] When the phase shift control signal EN_PHASE_SHIFT is activated (1), the rectifier gate signal generator 135 performs a phase shift based on the selected rise time delay information SET_TRISE_MUXED and the selected fall time delay information SET_TFALL_MUXED, and generates and outputs a first rectifier gate signal QG1 with a phase shift of θ° (i.e., not 0°). PH The second rectifier gate signal QG2 PH The third rectifier gate signal QG3 PH and the gate signal QG4 of the fourth rectifier PH .

[0075] In this specification, phase shifts can be classified as phase lag or phase lead based on their direction. For example, refer to... Figure 4 , so that the differential signal (AC2) RX -AC1 RX (relative to the RX coil current I) RL A phase shift of θ° backward is called phase lead, and it causes the differential signal (AC2) to... RX -AC1 RX (relative to the RX coil current I)RL A phase shift that is shifted forward by θ° is called phase lead.

[0076] For example, when the overvoltage flag signal FLAG OVP When deactivated (0), the rectifier gate signal generator 135 generates and outputs the first rectifier gate signal QG1 based on the rise time delay information SET_TRISE_MUXED and the fall time delay information SET_TFALL_MUXED selected in response to the deactivated phase shift control signal EN_PHASE_SHIFT. PH The second rectifier gate signal QG2 PH The third rectifier gate signal QG3 PH and the gate signal QG4 of the fourth rectifier PH This makes the differential signal (AC2) RX -AC1 RX The phase of the RX coil current IRL becomes the same as the phase of the overvoltage flag signal FLAG. Conversely, when the overvoltage flag signal FLAG... OVP When activated (1), the rectifier gate signal generator 135 generates and outputs the first rectifier gate signal QG1 based on the selected rise time delay information SET_TRISE_MUXED and fall time delay information SET_TFALL_MUXED under the activated EN_PHASE_SHIFT signal. PH The second rectifier gate signal QG2 PH The third rectifier gate signal QG3 PH and the gate signal QG4 of the fourth rectifier PH This makes the differential signal (AC2) RX -AC1 RX (relative to the RX coil current I) RL Phase lag θ°.

[0077] Reference Figure 3 and Figure 4 The rectified power synchronous phase shift controller 130 will convert the rectified voltage V RECT The overvoltage flag signal FLAG is generated by comparing it with a preset overvoltage rise threshold (OVP R). OVP Overvoltage flag signal FLAG OVP The EN_PHASE_SHIFT phase shift control signal is input to the rectifier power synchronous phase shift controller 130.

[0078] During the time period from 0 to t1, when the rectified voltage V RECT Below the overvoltage rise threshold (OVP R) and the overvoltage flag signal (FLAG) OVP Deactivated (FLAG) OVPWhen the current is low, the rectifier power synchronous phase shift controller 130 generates a phase shifter with a current I that corresponds to the RX coil current. RL Differential signals (AC2) with the same phase (i.e., 0° phase shift) RX -AC1 RX ).

[0079] At t1, with the input voltage V in the TX device 10 IN When the (TX) level rises, the rectified voltage V RECT Increase, at t2, when the rectified voltage V RECT When the preset overvoltage rise threshold 0VP R is reached, the rectifier power synchronous phase shift controller 130 activates the overvoltage flag signal FLAG. OVP (FLAG) OVP =High).

[0080] When the overvoltage flag signal FLAG OVP When activated, the rectifier power synchronous phase shift controller 130 generates the first rectifier gate signal QG1. PH The second rectifier gate signal QG2 PH The third rectifier gate signal QG3 PH and the gate signal QG4 of the fourth rectifier PH This makes the differential signal (AC2) RX -AC1 RX ) has the same current I as the RX coil RL The phase difference is θ° (i.e., the phase shift of θ°).

[0081] When the rectified voltage V RECT When the voltage drops to the preset overvoltage drop threshold 0VP F after voltage clamping, the rectifier power synchronous phase shift controller 130 sets the overvoltage flag signal FLAG. OVP Deactivate (FLAG) OVP =Low). When the overvoltage flag signal FLAG OVP When deactivated (e.g., at t6), the rectifier power synchronization phase shift controller 130 generates the first rectifier gate signal QG1. PH The second rectifier gate signal QG2 PH The third rectifier gate signal QG3 PH and the gate signal QG4 of the fourth rectifier PH This makes the differential signal (AC2) RX -AC1 RX ) and RX coil current I RL They have the same phase (i.e., a phase shift of 0°) (e.g., at t7).

[0082] In some embodiments, the overvoltage rise threshold OVP R and the overvoltage fall threshold OVP F are output from the RX MCU 50 and provided to the comparator 110 (e.g., provided as V). REF_OVP Comparator 110 outputs rectified voltage V. RECT The comparison result between the overvoltage rise threshold (OVP R) and the overvoltage fall threshold (OVP F) is used as the overvoltage flag signal FLAG. OVP .

[0083] Figure 5 This is shown as a model of time-domain wireless power transmission. Figure 1 Wireless charging system. Figure 6 Showing with Figure 5 The frequency domain wireless power transmission model corresponds to the wireless power transmission model. This is to theoretically explain... Figure 1 The operation of the wireless charging system Figure 1 The wireless charging system will be described below as a power transmission model with mutual components represented in both the time and frequency domains.

[0084] Reference Figure 5 and Figure 6 The TX coil of TX device 10T and the RX coil of RX device 20T are coupled by a coupling factor k. TX device 10T includes a TX bridge circuit 14T, which serves as a converter for input voltage V. IN Converted to the first TX AC voltage AC1 TX Second TX AC voltage AC2 TX The inverter operates, and the RX device 20T includes a rectifier circuit 30T, which draws a first RX AC voltage AC1 induced in the RX coil. RX Second RX AC voltage AC2 RX Generate rectified voltage V RECT In the TX device 10T, an issue arises related to the RX coil current ICOIL. RX (i RX The related mutual power Mdi RX / dt, and in the RX device 20T, there appears a current ICOIL in the TX coil. TX (i TX The related mutual power Mdi TX / dt.

[0085] exist Figure 5 In the middle, C P L represents the capacitance of the TX capacitor. P R represents the inductance of the TX inductor. P C represents the parasitic resistance of the TX LC resonant circuit 17. S L represents the capacitance of the RX capacitor.S R represents the inductance of the RX inductor. S C represents the parasitic resistance of the RX LC resonant circuit 21. L1 and C L2 It can represent parasitic capacitance.

[0086] In addition, AC1 TX and AC2 TX These represent the first TX AC voltage and the second TX AC voltage generated by the TX bridge circuit 14T, respectively, and V IN This indicates the input voltage of the TX device 10T. Additionally, AC1... RX and AC2 RX The first RX AC voltage and the second RX AC voltage are respectively indicated to the rectifier circuit 30T input to the RX device 20T, and V RECT This represents the rectified voltage generated and output by the rectifier circuit 30T. Additionally, R... L This indicates the load resistor.

[0087] Analyzing a wireless charging system in the time domain involves using high-order differential equations based on capacitors, inductors, and resistors via differentiation / integration, which is extremely difficult. Therefore, the wireless charging system in the time domain is transformed into the frequency domain. According to Ohm's law, the wireless charging system in the frequency domain can be analyzed using only first-order equations while still representing the corresponding impedances.

[0088] By using Fourier transform Figure 5 The time-domain wireless charging transmission model is transformed to the frequency domain to obtain Figure 6 The wireless charging transmission model.

[0089] Figure 5 The capacitors, inductors, and resistors in the equation can be represented as impedance components in the frequency domain (e.g., Z). CP Z LP Z RP Z CS Z LS Z RS Z CM and Z RLeq Each impedance component can be calculated using Equations 1, 2, and 3.

[0090] [Equation 1]

[0091] [Equation 2]

[0092] [Equation 3]

[0093] Figure 5 and Figure 6 M in this context represents mutual inductance. When the inductance L of the TX coil and the RX coil... P and L S When coupled, the mutual inductance M is as defined in Equation 3 above.

[0094] As Equation 4 indicates, Figure 6 The load resistor R on the RX side in L From frequency domain transformation to load resistance R L The resulting equivalent rectified impedance Z RLeq .

[0095] [Equation 4] Z RLeq =A RL R L

[0096] Here, we assume ideal rectifier operation, A RL It is 1, but can be changed in other ways.

[0097] Because the TX device 10F and the RX device 20F are coupled, the power on each side changes according to the induced current on the opposite side, making it difficult to calculate the operating point. For example, Figure 5 The mutual power Mdi on the TX side of the middle RX / dt is transformed in the frequency domain as , Figure 5 The mutual power Mdi on the RX side TX / dt is transformed in the frequency domain as To calculate the operating point of the wireless charging transmission model, as shown in Equation 5, the TX coil current I... TX Based on the RX device 20F.

[0098] [Equation 5]

[0099] Then, by using the TX coil current I in Equation 5 TX Substitute the cross power of the RX device 20F (i.e., The simplified RX-side power transmission model can be obtained as shown in Equation 6, where all TX-side components are eliminated and only RX-side elements are retained.

[0100] [Equation 6]

[0101] Reference Figure 6 (a1), the transmitting voltage V of TX device 10F PULSE(t) can be in the form of a square pulse with a period of 1 / f. For example... Figure 6 As shown in (a2), the transmitted voltage V in the frequency domain PULSE (ω) can be represented as a short pulse that appears at frequencies ω of 2πf and 6πf.

[0102] Similarly, in the RX device 20F, such as Figure 6 As shown in (b1), the RX AC voltage V AC21_RX (ω) can be represented as short pulses occurring at frequencies ω of 2πf and 6πf. For example... Figure 6 As shown in (b2), when the RX AC voltage V AC21_RX When (ω) is transformed to the time domain, the resulting RX AC voltage V AC21_RX (t) can be expressed as having a period of 1 / f and a sum equal to the rectified voltage V. RECT A square pulse of a certain amplitude.

[0103] Figure 7 It is shown in Figure 6 A diagram illustrating a simplified RX-side power transmission model using resistive rectified impedance in a wireless power transmission model. Figure 8 It is used for explanation Figure 7 A graph showing the operation of the RX-side power transmission model.

[0104] Figure 7 The simplified model shown is a circuit transformed from a bidirectional circuit to a unidirectional circuit (e.g., from the perspective of the RX device) to calculate the operating point. In the bidirectional circuit, TX device 10F and RX device 20F influence each other. For convenience, in this simplified RX-side power transmission model, the mutual influence of TX device 10F in Equation 6 is described by replacing the TX-side components with RX-side components. .

[0105] Specifically, such as Figure 7 As shown in (a), By reflecting the RX side component, the reflected power supply V P_REFL and reflection impedance Z P_REFL To indicate. Here, as... Figure 6 and Figure 7 As shown in (a) and Equation 7, Figure 5 The load resistor R at the rear end of the rectifier circuit 30T L The rectified impedance Z between the first RX AC node and the second RX AC node is represented as Z. RLeq .

[0106] [Equation 7] Z RLeq =A RL R L

[0107] Applied to the rectifier impedance Z RLeq The voltage V across the RX AC terminals AC21_RX (ω) can be expressed as follows: Figure 7 As shown in (b), similar to Figure 6 (b1), and as Figure 7 As shown in (c), similar to Figure 6 (b2) can be represented as a square pulse in the time domain.

[0108] As indicated by Equation 8, the voltage V between the first RX AC node and the second RX AC node of the RX LC resonant circuit 21 can be increased by... AC21_RX Divide by the RX coil current I RL To obtain the rectified impedance Z between the first RX AC node and the second RX AC node. RLeq .

[0109] [Equation 8]

[0110] Reference Figure 8 (a) Assuming ideal rectifier operation, the voltage V between the first RX AC node and the second RX AC node of the RX LC resonant circuit 21 is... AC21_RX It can be considered as a period of 1 / f at the rectified voltage V RECT With reverse rectified voltage -V RECT A square wave that switches between [variables]. This switching operation is based on the RX coil current I. RL The zero point, therefore the RX coil current I RL The voltage between the first RX AC node and the second RX AC node of the RXLC resonant circuit 21 The phase difference between them converges to approximately 0°.

[0111] Therefore, under ideal conditions, the rectified impedance Z RLeq This can be considered as resistive rectified impedance. (Refer to...) Figure 7 As indicated by Equation 8, the voltage V between the first RX AC node and the second RX AC node of the RX LC resonant circuit 21 is (b). AC21_RX It can be approximated by extracting only the single-tone operating frequency component.

[0112] [Equation 9]

[0113] As coil sensing information (e.g., V) ISEN and I ISEN The RX coil current I RL It typically exhibits a sine wave, but its amplitude is unknown. RX coil current I RL amplitude I M This can be derived from Equation 10.

[0114] [Equation 10]

[0115] As indicated by Equation 11 Figure 7 The resistive rectified impedance Z shown in (a) RLeq It can be calculated from equations 9 and 10.

[0116] [Equation 11]

[0117] In the resistive rectification method, as shown in Equation 12, it can be based on the reflected power supply V. P_REFL The rectified voltage V is obtained by dividing the voltage by each impedance in the circuit model. RECT .

[0118] [Equation 12]

[0119] As shown in Equation 13, the RX coil current I RL By converting the reflected power source V P_REFL It is obtained by dividing by the sum of the total impedances.

[0120] [Equation 13]

[0121] Furthermore, in resistive rectification, the rectified voltage V RECT Size and RX coil current I RL Size (i.e., and ) can be obtained as shown in Equations 14 and 15, respectively.

[0122] [Equation 14]

[0123] [Equation 15]

[0124] Figure 9 (a) shows in Figure 7 The simplified RX-side power transmission model using quasi-reactive rectifier impedance is used in (a) of the wireless power transmission model. Figure 10 In (a) and (b) including the explanation Figure 9 The graph of the operation of the RX-side power transmission model in (a).

[0125] Reference Figure 9 (a) to Figure 9 (c) and Figure 10 (a) and Figure 10 (b) represents the mutual influence of the TX device 10F in Equation 6 in the simplified unidirectional RX-side power transmission model. Reflected using the RX-side component (as previously referenced). Figure 8 (as described in (a)), and using a reflected power source V P_REFL and reflection impedance Z P_REFL Let V be the voltage V between the first RX AC node and the second RX AC node in quasi-reactive rectification operation. AC21_RX The phase relative to the RX coil current I RL The phase shift θ°.

[0126] like Figure 9 As shown in "A" in (a), due to the reflection impedance Z P_REFL The impedance Z of the RX coil S When connected in series, they can be represented as a combined impedance Z. RX As shown in Equation 16, the combined impedance Z RX This can be expressed as a resistance component R related to power consumption. RX and inductive reactance component X RX .

[0127] [Equation 16]

[0128] The voltage V between the first RX AC node and the second RX AC node of the RX LC resonant circuit 21 AC21_RX This is achieved by a phase shift of θ° relative to the RX coil current IRL. Therefore, with... Figure 7 Compared to the resistive impedance of (a), such as Figure 10 As shown in (a) and (b), the voltage V AC21_RX The phase can be relative to the RX coil current I RL Shift by θ°. In this case, the voltage V between the first RX AC node and the second RX AC node... AC21_RX It is represented as shown in Equation 17.

[0129] [Equation 17]

[0130] When the voltage V between the first RX AC node and the second RX AC node AC21_RX Relative to the RX coil current I RL When the phase shifts upward, the RX coil current I RL amplitude I M It also changes. Due to the voltage V AC21_RX The phase is not always with the RX coil current I RL In-phase operation, therefore the rectified current I supplied to the main LDO circuit 40 RECT Part of V RECT Instead of contributing, it leaks. As shown in Equation 18, this is reflected in the RX coil current I. RL amplitude I M middle.

[0131] [Equation 18]

[0132] Based on equations 17 and 18, the inductive rectified impedance Z caused by phase-shifted active reactance control can be obtained as shown in equation 19. RLeq .

[0133] [Equation 19]

[0134] Referring to Equation 19, it can be seen that, similar to an inductor, the inductive rectified impedance Z Rleq Both the numerator and denominator include a reactance component (i.e., a complex number).

[0135] As shown in Equation 20, a reflected power source V can be used. P_REFL The rectified voltage V is obtained by dividing the voltage by each impedance. RECT And as shown in Equation 21, this can be achieved by converting the reflected power source V... P_REFL Divide by the total impedance to obtain the coil current I RL .

[0136] [Equation 20] =

[0137] [Equation 21]

[0138] Rectified voltage V under quasi-reactive rectification RECT The amplitude and RX coil current I RL The magnitude (i.e., and It can be calculated as shown in Equations 22 and 23.

[0139] [Equation 22]

[0140] [Equation 23]

[0141] Figure 11 It is a phase-voltage graph used to explain the clamping effect on the rectified voltage in a wireless charging system using quasi-reactive rectification according to some embodiments.

[0142] Referring to equations 12 and 13 above, in the resistive rectification method, only the rectified voltage V is considered. RECT and coil current I RL The real parts of both. That is, the rectified voltage V RECT Phase and coil current I RL They are in the same phase.

[0143] On the other hand, referring to Equations 20 and 21 above, the quasi-reactive rectification method adds cosine and sine terms due to phase shift, thereby generating an imaginary (j) component in addition to the real component.

[0144] Reference Figure 11 The rectified voltage V with 0° phase RECT In comparison, the larger the phase shift, the greater the rectified impedance Z due to the cosine term in Equation 19. RLeq The smaller it becomes, and the smaller the rectified voltage V. RECT The amplitude becomes lower and lower.

[0145] Using this principle, the quasi-reactive rectification method can control the rectified voltage V through clamping. RECT .

[0146] Figure 12 (a) shows a power transmission model on the RX side using a comparative example with clamping resistors. Figure 13 It is a comparison Figure 12 A comparative example is shown in the graph of coil current increase relative to clamping voltage level between this disclosure and the present disclosure.

[0147] Reference Figure 12 (a) to (c), with Figure 6 Compared to the RX-side power transmission model in the previous example, the RX-side power transmission model in the comparative example has a clamping resistor R added in parallel between the first RX AC node and the second RX AC node. PCLAMP .

[0148] Clamping resistor R PCLAMP impedance ZRLpclamp The rectified load impedance Z between the first RX AC node and the second RX AC node RLeq They appear in parallel and can be represented as shown in Equation 24.

[0149] [Equation 24] Z RLpclamp =A RL R PCLAMP

[0150] In the comparative example model, due to the clamping resistor R PCLAMP The impedance between the first RX AC node and the second RX AC node decreases, which reduces the AC gain and thus affects the rectified voltage V. RECT Clamping was performed.

[0151] Reference Figure 12 (a) to (c) and Figure 13 With the clamping rectified voltage V RECT As the overvoltage increases, the coil current in the quasi-reactive rectification method of this disclosure increases more slowly than the coil current in the comparative example ("PRIOR"). Therefore, for the same coil current, the overvoltage period in the quasi-reactive rectification method of this disclosure results in a slower increase in the rectified voltage V. RECT The clamping performance is more advantageous than in the comparison example.

[0152] Furthermore, since no additional clamping resistors are used in the quasi-reactive rectification method, no unnecessary power consumption due to resistive elements occurs.

[0153] Figure 14 This is a detailed block diagram of a rectified gate signal generator according to some embodiments. Figure 15 yes Figure 14 A block diagram of the gate signal generator. According to some embodiments, Figure 3 The rectifier gate signal generator 135 and the coil current sensor 120 can be implemented as follows: Figure 14 The (rectifier gate) signal generator 200 and the coil current sensor 210 are included.

[0154] Reference Figure 14 The rectified gate signal generator 200 can be implemented as including a differentiator circuit 221, an integrator circuit 222, multiple zero-edge detectors or zero-edge detector circuits 231, 232 and 233, multiple timing controllers 241, 242 and 243, and a (gate) signal generator 260.

[0155] In one embodiment, zero-edge detectors 231, 232, and 233 can generate short pulse signals at the points where the signal in each path reaches 0V due to a rising or falling edge. The rising-edge zero and falling-edge zero can optionally be represented by other types of signals that can indicate such zero-edge detection.

[0156] For example, the zero-edge detector 231 can detect the coil sensing information V output from the coil current sensor 210, which is output from the differentiator circuit 221. ISEN The differential signal d / dt (V) ISEN The zero-edge detector 232 detects the rising edge zero (RISING EDGE_DIFF) and falling edge zero (FALLING EDGE_DIFF). For example, the zero-edge detector 232 can detect the coil sensing information V output from the coil current sensor 210. ISEN The rising edge zero (RISING EDGE_NORM) and falling edge zero (FALLING EDGE_NORM) are specified. For example, the zero-edge detector 233 can detect the coil sensing information V output from the integrator circuit 222. ISEN The integral signal Integ (V ISEN The rising edge zero is RISING EDGE_INTEG and the falling edge zero is FALLING EDGE_INTEG. Note that, as the context indicates, the term “coil sensing information” can refer to the information itself or the form in which it is represented (such as a voltage or current signal derived from the receiver coil representing the current of the receiver coil, and / or one or more signals carrying or indicating such information).

[0157] In some embodiments, timing controllers 241, 242, and 243 may delay the signals output from zero-edge detectors 231, 232, and 233 by an amount corresponding to the selected rise time delay information SET_TRISE_MUXED, and output the delayed signal. Optionally, timing controllers 241, 242, and 243 may delay the signals output from zero-edge detectors 231, 232, and 233 by an amount corresponding to the selected fall time delay information SET_TFALL_MUXED, and output the delayed signal.

[0158] Reference Figure 15 The gate signal generator 260 includes a first (gate) signal generator 260A and a second (gate) signal generator 260B.

[0159] The first gate signal generator 260A includes a third multiplexer (MUX3) 261 and a first gate signal generator 262. The second gate signal generator 260B includes a fourth multiplexer (MUX4) 263 and a second gate signal generator 264. When the falling edge delayed signals FALLING EDGE_DIFF_DELAY, FALLING EDGE_NORM_DELAY, and FALLING EDGE_INTEG_DELAY, and the rising edge delayed signals RISING EDGE_DIFF_DELAY, RISING EDGE_NORM_DELAY, and RISING EDGE_INTEG_DELAY, output from timing controllers 241, 242, and 243 are received, the third multiplexer 261 and the fourth multiplexer 263 output the falling edge delayed signal and the rising edge delayed signal selected according to the gate signal control signal SET_GATE_SIG[1:0] as gate on signals GATE_ON1 and GATE_ON3 and gate off signals GATE_OFF2 and GATE_OFF4, respectively. The gate signal generator 262 generates the first rectifier gate signal QG1 based on the gate on signal GATE_ON1 and the gate off signal GATE_OFF2. PH and the gate signal QG4 of the fourth rectifier PH The gate signal generator 264 generates the second rectifier gate signal QG2 based on the gate on signal GATE_ON3 and the gate off signal GATE_OFF4. PH and the third rectifier gate signal QG3 PH .

[0160] Please refer to later Figures 15 to 17 A more detailed description Figure 14 and Figure 15 Configuration and operation of the rectifier gate signal generator 200.

[0161] Figure 16 It is used for explanation Figure 1 Timing diagram of an embodiment of the operation of a wireless charging system.

[0162] Reference Figure 14 , Figure 15 and Figure 16 Coil sensing information V ISEN The signal is converted into a differential signal d / dt (V) by differentiator 221. ISEN Differential signal d / dt (V) ISEN The zero-edge detector 231 outputs a rising edge differential signal RISING EDGE_DIFF and a falling edge differential signal FALLING EDGE_DIFF.

[0163] Timing controller 241 delays the rising edge differential signal RISING EDGE_DIFF and the falling edge differential signal FALLING EDGE_DIFF by preset delay settings SET_TRISE_MUXED and SET_TFALL_MUXED, respectively, to achieve differential signal (AC2) RX -AC1 RX ) and RX coil current I RL The phase difference between them is calculated, and the rising edge delayed differential signal RISING EDGE_DIFF_DELAY and the falling edge delayed differential signal FALLING EDGE_DIFF_DELAY are output.

[0164] During the time period from 0 to t1, when the overvoltage flag signal FLAG OVP When low, RX device 20 sets the delay between the rising edge differential signal RISING EDGE_DIFF and the rising edge delayed differential signal RISING EDGE_DIFF_DELAY (e.g., during the period from t41 to t51) to T. RISE1 And set the delay between the falling edge differential signal FALLING EDGE_DIFF and the falling edge delayed differential signal FALLING EDGE_DIFF_DELAY (e.g., during the periods t61 to t71 and t62 to t72) to T. FALL1 This makes the differential signal (AC2) RX -AC1 RX ) and RX coil current I RL The phase difference between them becomes zero (0°). The fourth multiplexer 263 selects the gate on signal GATE_ON3 as the rising edge delayed differential signal RISING EDGE_DIFF_DELAY, and selects the gate off signal GATE_OFF4 as the falling edge delayed differential signal FALLING EDGE_DIFF_DELAY.

[0165] In some embodiments, when the gate on signal GATE_ON3 is high, the gate signal generator 264 generates the second rectifier gate signal QG2. PH The output is high, and when the gate cutoff signal GATE_OFF4 goes high, the gate signal generator 264 outputs the second rectifier gate signal QG2. PH The output is low, thus generating the switching second rectifier gate signal QG2. PH In this way, during the first time interval up to t1, the differential signal (AC2) RX -AC1 RX ) and RX coil current I RL It operates with a phase difference of 0°.

[0166] Other rectifier gate signals (i.e., the first rectifier gate signal QG1) PH The third rectifier gate signal QG3 PH and the gate signal QG4 of the fourth rectifier PH It can also be used with the second rectifier gate signal QG2. PH The same operating scheme is generated. For example, the first rectifier gate signal QG1 PH It can be used with the fourth rectifier gate signal QG4 PH The same phase is generated, and the second rectifier gate signal QG2 PH It can be used with the third rectifier gate signal QG3 PH The same phase is generated.

[0167] During the time period from t1 to t3, when the overvoltage flag signal FLAG OVP When high, the timing controller 241, based on the first multiplexer 141, reduces the time between the rising edge differential signal RISING EDGE_DIFF and the rising edge delayed differential signal RISING EDGE_DIFF_DELAY (e.g., during the period from t43 to t53) from T. RISE1 Change to T RISE2 At this time, due to T RISE2 At t21, the second rectifier gate signal QG2 is applied. PH The timing controller 241, based on the second multiplexer 142, determines the time interval following the rising edge of the signal, and therefore, the timing controller 241, according to the second multiplexer 142, the delay between the falling edge differential signal FALLING EDGE_DIFF and the falling edge delayed differential signal FALLING EDGE_DIFF_DELAY (e.g., during the time interval t64 to t74) from T. FALL1 Change to T FALL2 In this case, the second rectifier gate signal QG2 PH The gate turn-on / gate turn-off timing is changed, causing the differential signal (AC2) to... RX -AC1 RX (relative to the RX coil current I) RL By lagging the phase by a specific amount of degrees (θ°), the rectified voltage V is achieved as a quasi-reactive rectification operation. RECT Voltage clamping operation. When differential signals are used, even with a small phase delay, the probability of a change in the operating point is minimized, reducing the likelihood of error relative to the expected phase shift operation, without maintaining periodic operation during the delay time.

[0168] When the voltage clamping operation causes the rectified voltage V RECTWhen the voltage level decreases to reach the preset overvoltage drop level OVP F (e.g., at t3), the overvoltage flag signal FLAG... OVP The signal transitions to a low level, and the delay between the rising edge differential signal RISING EDGE_DIFF and the rising edge delayed differential signal RISING EDGE_DIFF_DELAY (e.g., during the period from t44 to t54) from T RISE2 Restore to T RISE1 Similarly, the delay between the falling edge differential signal FALLING EDGE_DIFF and the falling edge delayed differential signal FALLING EDGE_DIFF_DELAY (e.g., during the period from t65 to t75) from T FALL2 Restore to T FALL1 Therefore, the differential signal (AC2) RX -AC1 RX ) and RX coil current I RL The phase difference is restored to 0°, thus ending the voltage clamping operation and enabling normal rectification operation.

[0169] In some embodiments, the delay setting T RISE1 and T RISE2 And T FALL1 and T FALL2 The same principle applies to the gate signal QG1 of the first rectifier. PH The second rectifier gate signal QG2 PH The third rectifier gate signal QG3 PH and the gate signal QG4 of the fourth rectifier PH All of them. Optionally, in some embodiments, only the differential signal (AC2) is required. RX -AC1 RX (relative to the RX coil current I) RL Operating with a phase shift of θ°, and a delay setting T RISE1 and T RISE2 And T FALL1 and T FALL2 This can be applied differently to the gate signal QG1 of the first rectifier. PH The second rectifier gate signal QG2 PH The third rectifier gate signal QG3 PH and the gate signal QG4 of the fourth rectifier PH Each of them.

[0170] Figure 17 It is used for explanation Figure 1 A timing diagram of another embodiment of the operation of a wireless charging system. Further reference will be made below to a system without... Figure 13 The paths of the differentiator 221 and the integrator 222 are described. Figure 17The timing diagram.

[0171] Reference Figure 14 , Figure 15 and Figure 17 First, during the time period from t0 to t1, the zero-edge detector 232 of the RX device 20 will sense the RX coil current I from the RX LC resonant circuit 21. RL The output is a rising edge normal signal RISING EDGE_NORM and a falling edge normal signal FALLING EDGE_NORM.

[0172] The timing controller 242 delays the rising edge normal signal RISING EDGE_NORM and the falling edge normal signal FALLINGEDGE_NORM by preset delay settings SET_TRISE_MUXED and SET_TFALL_MUXED, respectively, to achieve differential signal (AC2) RX -AC1 RX ) and RX coil current I RL The phase difference between them is calculated, and the rising edge delay normal signal RISING EDGE_NORM_DELAY and the falling edge delay normal signal FALLING EDGE_NORM_DELAY are output.

[0173] During the time period from 0 to t1, when the overvoltage flag signal FLAG OVP When low, RX device 20 sets the delay between the rising edge normal signal RISING EDGE_NORM and the rising edge delayed normal signal RISING EDGE_NORM_DELAY (e.g., at t41) to T. RISE1 And set the delay between the falling edge normal signal FALLING EDGE_NORM and the falling edge delayed normal signal FALLING EDGE_NORM_DELAY (e.g., in t61) to T. FALL1 This makes the differential signal (AC2) RX -AC1 RX ) and RX coil current I RL The phase difference between them becomes approximately or essentially 0°. In this case, T RISE1 and T FALL1 It can be zero. The fourth multiplexer 263 selects the gate on signal GATE_ON3 as the rising edge delay normal signal RISING EDGE_NORM_DELAY, and selects the gate off signal GATE_OFF4 as the falling edge delay normal signal FALLING EDGE_NORM_DELAY.

[0174] In some embodiments, when the gate on signal GATE_ON3 is high, the gate signal generator 264 generates the second rectifier gate signal QG2. PH The output is high, and when the gate cutoff signal GATE_OFF4 goes high, the gate signal generator 264 outputs the second rectifier gate signal QG2. PH The output is low, thus generating the switching second rectifier gate signal QG2. PH In this way, when the second rectifier gate signal QG2 is generated... PH At that time, the differential signal (AC2) RX -AC1 RX ) and RX coil current I RL During the first time interval up to t1, the operation is performed with a phase difference close to 0°. At this time, when using coil sensing information (V... ISEN and I ISEN When T is at the zero edge of ) RISE1 and T FALL1 It became very small.

[0175] Other rectifier gate signals (i.e., the first rectifier gate signal QG1) PH The third rectifier gate signal QG3 PH and the gate signal QG4 of the fourth rectifier PH It can also be used with the second rectifier gate signal QG2. PH The same operating scheme is generated. For example, the first rectifier gate signal QG1 PH It can be used with the fourth rectifier gate signal QG4 PH The same phase is generated, and the second rectifier gate signal QG2 PH It can be used with the third rectifier gate signal QG3 PH The same phase is generated.

[0176] During the period from t1 to t41, when the overvoltage flag signal FLAG... OVP When high, the timing controller 242 delays the rising edge normal delay signal RISING EDGE_NORM_DELAY to t43 instead of t42 according to the first multiplexer 141, thereby changing the delay of the rising edge normal delay signal RISING EDGE_NORM_DELAY relative to the rising edge normal signal RISING EDGE_NORM to T. RISE2(For example, during the time period t42 to t43). Similarly, timing controller 242 delays the falling edge normal delay signal FALLING EDGE_NORM_DELAY to t64 instead of t63 according to the second multiplexer 142, thereby reducing the delay of the falling edge normal delay signal FALLING EDGE_NORM_DELAY relative to the falling edge normal signal FALLING EDGE_NORM from T FALL1 Change to T FALL2 (For example, during the period from t63 to t64). At this time, from Figure 17 As can be seen from this, because it is based on the RX coil current I RL The zero point of the differential signal (AC2) RX -AC1 RX It cannot be shifted (or advanced) by θ° immediately in phase, so T RISE2 and T FALL2 It has a long delay corresponding to approximately (360°-θ°) × period. Therefore, instead of directly performing θ° phase lead, the falling edge normal delay signal FALLING EDGE_NORM_DELAY can achieve an effect equivalent to phase lead by delaying the phase by (360°-θ°) in phase, taking into account the subsequent periodic operation.

[0177] In this case, the second rectifier gate signal QG2 PH The gate turn-on / gate turn-off timing is changed, causing the differential signal (AC2) to... RX -AC1 RX (relative to the RX coil current I) RL Phase shift (or lag) θ°, thereby achieving voltage clamping operation based on quasi-reactive rectification operation.

[0178] When voltage clamping operation causes the rectified voltage V RECT When the voltage drops to the preset overvoltage drop level OVP F (e.g., at t41), the delay between the rising edge normal signal RISING EDGE_NORM and the rising edge normal delay signal RISING EDGE_NORM_DELAY changes from T... RISE2 Restore to T RISE1 (For example, in t44), the delay between the falling edge normal signal FALLING EDGE_NORM and the falling edge normal delayed signal FALLING EDGE_NORM_DELAY is from T FALL2 Restore to T FALL1 (For example, at t65). Thus, the differential signal (AC2) RX -AC1 RX ) and RX coil current I RLThe phase difference is restored to 0°, thus ending the voltage clamping operation and enabling normal rectification operation.

[0179] In some embodiments, the delay setting T RISE1 and T RISE2 And T FALL1 and T FALL2 The same principle applies to the gate signal QG1 of the first rectifier. PH The second rectifier gate signal QG2 PH The third rectifier gate signal QG3 PH and the gate signal QG4 of the fourth rectifier PH Optionally, in some embodiments, as long as the differential signal (AC2) is used... RX -AC1 RX (relative to the RX coil current I) RL Operating with a phase lag of θ°, delay setting T RISE1 and T RISE2 And T FALL1 and T FALL2 This can be applied differently to the gate signal QG1 of the first rectifier. PH The second rectifier gate signal QG2 PH The third rectifier gate signal QG3 PH and the gate signal QG4 of the fourth rectifier PH Each of them.

[0180] Figure 18 It is used for explanation Figure 1 A timing diagram of another embodiment of the operation of the wireless charging system.

[0181] Reference Figure 14 , Figure 15 and Figure 18 First, the coil sensing information (V) is processed by integrator 222. ISEN and I ISEN ) is converted into an integral signal Integ(V) ISEN Integral signal Integ(V) ISEN The rising edge integration signal RISING EDGE_INTEG and the falling edge integration signal FALLING EDGE_INTEG are output from the zero edge detector 233.

[0182] The timing controller 243 delays the rising edge integral signal RISING EDGE_INTEG and the falling edge integral signal FALLING EDGE_INTEG by preset delay settings SET_TRISE_MUXED and SET_TFALL_MUXED, respectively, to achieve differential signal (AC2) RX -AC1 RX) and RX coil current I RL The phase difference between them is calculated, and the rising edge delayed integration signal RISING EDGE_INTEG_DELAY and the falling edge delayed integration signal FALLING EDGE_INTEG_DELAY are output.

[0183] During the time period from 0 to t1, when the overvoltage flag signal FLAG OVP When low, RX device 20 sets the delay between the rising edge integral signal RISING EDGE_INTEG and the rising edge delayed integral signal RISING EDGE_INTEG_DELAY (e.g., during the period from t41 to t51) to T. RISE1 And set the delay between the falling edge integral signal FALLING EDGE_INTEG and the falling edge delayed integral signal FALLING EDGE_INTEG_DELAY (e.g., during the period from t61 to t71) to T. FALL1 This makes the differential signal (AC2) RX -AC1 RX ) and RX coil current I RL The phase difference between them becomes 0°. The fourth multiplexer 263 selects the gate on signal GATE_ON3 as the falling edge delayed integration signal FALLING EDGE_INTEG_DELAY, and selects the gate off signal GATE_OFF4 as the rising edge delayed integration signal RISING EDGE_INTEG_DELAY.

[0184] In some embodiments, when the gate on signal GATE_ON3 is high, the gate signal generator 264 generates the second rectifier gate signal QG2. PH The output is high, and when the gate cutoff signal GATE_OFF4 goes high, the gate signal generator 264 outputs the second rectifier gate signal QG2. PH The output is low, thus generating the switching second rectifier gate signal QG2. PH In this way, when the second rectifier gate signal QG2 is generated... PH At that time, the differential signal (AC2) RX -AC1 RX ) and RX coil current I RL The operation is performed with a phase difference of 0° during the first time interval up to t1 ("shift 0°").

[0185] Other rectifier gate signals (i.e., the first rectifier gate signal QG1) PH The third rectifier gate signal QG3 PH and the gate signal QG4 of the fourth rectifier PHIt can also be used with the second rectifier gate signal QG2. PH The same operating scheme is generated. For example, the first rectifier gate signal QG1 PH It can be used with the fourth rectifier gate signal QG4 PH The same phase is generated, and the second rectifier gate signal QG2 PH It can be used with the third rectifier gate signal QG3 PH The same phase is generated.

[0186] During the time period from t1 to t3, when the overvoltage flag signal FLAG OVP When high, the timing controller 243, based on the first multiplexer 141, reduces the time between the rising edge integral signal RISING EDGE_INTEG and the rising edge delayed integral signal RISING EDGE_INTEG_DELAY (e.g., during the period from t43 to t53) from T. RISE1 Change to T RISE2 Furthermore, the timing controller 243, based on the second multiplexer 142, reduces the time delay between the falling edge integrated signal FALLING EDGE_INTEG and the falling edge delayed integrated signal FALLING EDGE_INTEG_DELAY (e.g., during the period from t63 to t73) from T FALL1 Change to T FALL2 In this case, the second rectifier gate signal QG2 PH The gate turn-on / gate turn-off timing is changed, causing the differential signal (AC2) to... RX -AC1 RX The phase of ) relative to the RX coil current I RL Shifting by θ°, thereby achieving the rectified voltage V as a quasi-reactive rectification operation. RECT Voltage clamping operation. In this embodiment, the gate on signal GATE_ON3 is selected as the falling edge delayed integration signal FALLING EDGE_INTEG_DELAY, and the gate off signal GATE_OFF4 is selected as the rising edge delayed integration signal RISING EDGE_INTEG_DELAY, thereby achieving a voltage clamping operation with minimum delay T. RISE2 and T FALL2 Phase shift operation.

[0187] When the voltage clamping operation will rectify the voltage V RECT When the voltage level drops to the preset overvoltage drop level OVP F (e.g., at t3), the delay between the rising edge integral signal RISING EDGE_INTEG and the rising edge delayed integral signal RISING EDGE_INTEG_DELAY decreases from T RISE2 Restore to T RISE1(For example, during the period from t45 to t55). Furthermore, the delay between the falling edge integral signal FALLING EDGE_INTEG and the falling edge delayed integral signal FALLING EDGE_INTEG_DELAY is from T... FALL2 Restore to T FALL1 (For example, during the interval from t64 to t74). Thus, the differential signal (AC2) RX -AC1 RX ) and RX coil current I RL The phase difference between them is restored to 0°, thus ending the voltage clamping operation and enabling normal rectification operation.

[0188] In some embodiments, the delay setting T RISE1 and T RISE2 And T FALL1 and T FALL2 The same principle applies to the gate signal QG1 of the first rectifier. PH The second rectifier gate signal QG2 PH The third rectifier gate signal QG3 PH and the gate signal QG4 of the fourth rectifier PH Optionally, in some embodiments, as long as the differential signal (AC2) is used... RX- AC1 RX (relative to the RX coil current I) RL Operating with a phase lag of θ°, delay setting T RISE1 and T RISE2 And T FALL1 and T FALL2 This can be applied differently to the gate signal QG1 of the first rectifier. PH The second rectifier gate signal QG2 PH The third rectifier gate signal QG3 PH and the gate signal QG4 of the fourth rectifier PH Each of them.

[0189] Figure 19 The graphs show the rectified voltage, RX AC voltage, and coil current of the wireless charging system under overvoltage conditions according to some embodiments.

[0190] The case of reference and execution phase shift corresponding to Figure 19 From (b), it can be seen that, corresponding to the non-RX coil current I RL Phase shift is performed at the zero-crossing point. Figure 19 Compared to (a), the differential signal (AC2) RX -AC1 RX The rectified voltage V is shifted forward by 45° due to the voltage clamping operation. RECTWhen a 45° phase lead shift occurs (such as...) Figure 19 (as shown in (b)) is in a state compared to when no phase shift is performed (such as...) Figure 19 (as shown in (a)) a lower level.

[0191] Figure 20 This is a block diagram illustrating a wireless charging system according to some embodiments of the present disclosure. Figure 21 It is used to explain how to determine Figure 20 The time-voltage curve of the phase shift direction in the wireless charging system. Figure 22 It is used for explanation Figure 20 A flowchart illustrating the operation method of a wireless charging system. Figure 23 This shows how to determine Figure 20 The reactance component X in a wireless charging system RX The polarity of the RX-side power transmission model.

[0192] Reference Figures 20 to 23 The RX device 320 includes a phase direction determination circuit (or phase direction determination unit) 400, an RX LC resonant circuit 325, a rectifier circuit 330, a main LDO circuit 340, an RX MCU 350, an OVP circuit 100, and a battery 360. The RX LC resonant circuit 325, rectifier circuit 330, main LDO circuit 340, RX MCU 350, OVP circuit 100, and battery 360 correspond to... Figure 1 Their corresponding counterparts are omitted here, hence their redundant descriptions will be omitted. For example, the RX LC resonant circuit 325 is configured to receive wireless charging power from the transmitter device 310.

[0193] The phase direction determination circuit 400 performs a test to determine the phase shift direction. The phase direction determination circuit 400 includes a transfer transistor circuit 410 (which may include a first transfer transistor and a second transfer transistor), an imaginary polarity tester circuit 420, an imaginary polarity determiner circuit 430, and a phase direction selector circuit (or phase direction selector) 440. In some embodiments, the phase direction determination circuit 400 includes: a first communication capacitor C. CM1 Connected in series to generate the first RX AC voltage AC1 RX The first AC node; the second communication capacitor C CM2 Connected in series to generate the second RX AC voltage AC2 RX The second AC node; the first transmission transistor, connected to the first communication capacitor C CM1 The polarity test signal G is between the second end and the ground node. CM A first transmission transistor connected to its gate; and a second transmission transistor connected to the second communication capacitor C. CM2The polarity test signal G is between the second end and the ground node. CM The first and second transmission transistors are connected to the gate of the second transmission transistor. The first and second transmission transistors can selectively adjust the first communication capacitor C according to a gate signal (e.g., selectively). CM1 Second communication capacitor C CM2 Connect to the ground node, or the first communication capacitor C may not (e.g., selectively) be connected according to the gate signal. CM1 Second communication capacitor C CM2 Connect to the ground node. When the communication capacitor C... CM1 and C CM2 When connected to the output of the RX LC resonant circuit 325, they are related to the RX load capacitor C. S They operate together as a combined capacitor. Therefore, the rectified voltage V RECT According to the first communication capacitor C CM1 Second communication capacitor C CM2 Whether it is connected or not changes.

[0194] When it is necessary to determine in advance whether to perform quasi-reactive rectification operation by phase lead or phase lag under non-overvoltage conditions, the RX MCU 50 activates the test enable signal TEST_EN (and outputs the test enable signal TEST_EN to the phase direction determination circuit 400) and determines the direction of phase shift (S10).

[0195] Therefore, the imaginary polarity tester circuit 420, based on the test enable signal TEST_EN, switches the polarity test signal G from low to high to low. CM The output is sent to the transmission transistor circuit 410 (S20). When the polarity test signal G... CM When the signal is high, the transmission transistor circuit 410 connects the first CM path and the second CM path to the ground node, thereby connecting AC1. RX The first communication capacitor C between the node and the ground node CM1 And connect AC2 RX The second communication capacitor C between the node and the ground node CM2 When the polarity test signal G CM When the voltage is low, the transmission transistor circuit 410 disconnects the first CM path and the second CM path from the ground node, thereby disconnecting the first communication capacitor C. CM1 Second communication capacitor C CM2 Disconnect from the ground node.

[0196] The imaginary polarity determiner circuit 430 converts the rectified voltage V RECT The current level and the rectified voltage V RECT The rectified voltage V is compared with the previous level. RECTThe current level is determined by the transmission transistor circuit 410 in response to the polarity test signal G. CM The operation changes accordingly. For example, the imaginary part polarity determiner circuit 430 determines the polarity when the polarity test signal G... CM The rectified voltage level V when it is high RECT_CM Is it higher or lower than the polarity of the test signal G? CM The rectified voltage level V when it is low RECT1 And output the determined result as the result signal RESULT (S30).

[0197] The phase direction selector circuit 440 determines the direction of the phase shift to be performed (S40 and S50) based on the resulting signal RESULT. If the rectified voltage level V... RECT_CM Higher than the rectified voltage level V RECT1 If "Yes" is selected in S30, then the phase direction selector 440 determines that phase lead will be executed (S40). If the rectified voltage level V RECT_CM Below the rectified voltage level V RECT1 If "No" is selected in S30, then the phase direction selector 440 determines that phase lag will be executed (S50).

[0198] The phase direction selector circuit 440 outputs the determination result (i.e., the determination signal SEL_LEAD) from step S40 or step S50 to the RX MCU 350 (S60).

[0199] The RX MCU 50 sets the time delay information based on the determined signal SEL_LEAD. For example, when SEL_LEAD=1, the RX MCU 50 sets the second type of time delay information (SET_TRISE2, SET_TFALL2) with the first set value to a phase lead value. When SEL_LEAD=0, the RX MCU 50 sets the second type of time delay information (SET_TRISE2, SET_TFALL2) with the second set value to a phase lag value.

[0200] Reference Figure 23 The impedance Z of the phase direction determination unit 400 in the frequency domain CM rectified voltage V RECT It can be expressed as indicated by Equation 25.

[0201] [Equation 25]

[0202] When the phase direction is determined, the resistive impedance Z of unit 400 RX Represented as When, if reactance X RX If it is negative, then the resistive impedance ZRX phase It becomes negative. By applying Euler's formula, equation 25 can be rearranged into equation 26.

[0203] [Equation 26]

[0204] According to Equation 26, in reactance X RX When the phase is negative, make the phase The rectified voltage V is negative. RECT Decrease. Furthermore, when reactance X RX When positive, make the phase Positive, rectified voltage V RECT This increases. Therefore, the phase direction determining circuit 400 can determine the reactance X. RX At the rectified voltage V RECT It is negative when decreasing, and in the rectified voltage V RECT It is positive when it increases.

[0205] Figure 24 This is a flowchart illustrating an operation method of a wireless charging system according to some embodiments of the present disclosure. Figure 22 The implementation methods are different. Figure 24 The embodiment can determine the direction of phase shift without using the phase direction determination circuit 400.

[0206] When it is necessary to pre-determine whether to perform quasi-reactive rectification operation under non-overvoltage conditions via phase lead or phase lag, the RX MCU 50 activates the test enable signal TEST_EN and determines the direction of phase shift (S110). For testing, phase lead is first performed for a predetermined period (S120). Then, if the rectified voltage V... RECT If the voltage is reduced ("Yes" in S130), the RX MCU50 will set the determination signal SEL_LEAD to 1 to perform phase lead in the event of overvoltage (S140) and terminate the test (S160). If the rectified voltage V RECT If the phase lead performed in S120 is increased ("No" in S130), then the RX MCU50 will set the determination signal SEL_LEAD to 0 to perform phase hysteresis in the event of overvoltage (S150) and terminate the test (S160).

[0207] Although embodiments of the invention have been described above with reference to the accompanying drawings, the invention is not limited to the above embodiments and can be made in various different forms. Those skilled in the art will understand that the invention can be implemented in other specific forms without changing the technical spirit or essential characteristics of the invention. Therefore, the above embodiments should be understood in all respects as illustrative and not restrictive.

Claims

1. A receiver device, comprising: The receiver LC resonant circuit includes a receiver load capacitor and a receiver coil, and is configured to receive wireless charging power from the transmitter device; The rectifier circuit is configured to rectify the receiver AC voltage, which is a differential signal provided by the receiver LC resonant circuit, into a rectified voltage in response to a rectifier gate signal. as well as The overvoltage protection circuit is configured to generate a rectifier gate signal and output the rectifier gate signal to the rectifier circuit. The overvoltage protection circuit is configured to generate a rectifier gate signal, thereby causing a phase shift of the differential signal between the receiver AC voltages relative to the receiver coil current in the receiver coil in response to the rectified voltage reaching or exceeding the overvoltage reference level.

2. The receiver device as claimed in claim 1, further comprising: The receiver microcontroller unit (MCU) is configured to output gate signal control signals, first-type timing delay information, and second-type timing delay information to the overvoltage protection circuit based on the rectified voltage. The overvoltage protection circuit is configured to generate a rectifier gate signal based on a gate signal control signal, a first type of timing delay information, and / or a second type of timing delay information.

3. The receiver device as claimed in claim 2, wherein, The receiver MCU is configured as follows: Obtain the first setting value corresponding to the preset phase setting; The second type of timing delay information is generated based on the first setting value; and The second type of timing delay information is output to the overvoltage protection circuit, so that the overvoltage protection circuit adjusts the phase of the differential signal between the receiver AC voltages relative to the receiver coil current based on the second type of timing delay information.

4. The receiver device as claimed in claim 2, wherein, The receiver MCU is configured as follows: Obtain the second setting value; Generate a second type of timing delay information based on the second setting value; and The second type of timing delay information is output to the overvoltage protection circuit, enabling the overvoltage protection circuit to adjust the phase of the differential signal between the receiver AC voltages relative to the receiver coil current based on the second type of timing delay information. The second setting value is gradually changed until the rectified voltage reaches the target rectified voltage.

5. The receiver device as claimed in claim 1, wherein, The overvoltage protection circuit includes: The comparator is configured to compare the rectified voltage with an overvoltage reference level and output an overvoltage flag signal; A coil current sensor is configured to sense the receiver coil current in the receiver coil, thereby outputting coil sensing information; and The controller is configured to generate a rectifier gate signal based on an overvoltage flag signal and coil sensing information, and output the rectifier gate signal to the rectifier circuit.

6. The receiver device as claimed in claim 5, wherein, The controller includes: The first multiplexer is configured to select and output either a first rise time delay information or a second rise time delay information as the selected rise time delay information based on the overvoltage flag signal. The second multiplexer is configured to select and output either a first fall time delay information or a second fall time delay information as the selected fall time delay information based on an overvoltage flag signal; and The rectifier gate signal generator is configured to generate a rectifier gate signal corresponding to selected rise time delay information and selected fall time delay information, and output the rectifier gate signal to the rectifier circuit.

7. The receiver device as claimed in claim 6, wherein, The rectified gate signal generator is also configured to: A rising edge delay signal is generated by shifting the rising edge zero of the differential signal of the coil sensing information to select the rising time delay information. A falling edge delay signal is generated by shifting the falling edge zero of the differential signal of the coil sensing information to select the falling time delay information; and The rectifier gate signal is generated based on the rising edge delay signal and the falling edge delay signal, and then output to the rectifier circuit.

8. The receiver device as claimed in claim 6, wherein, The rectified gate signal generator is also configured to: A rising edge delay signal is generated by shifting the rising edge zero of the integral signal of the coil sensing information to select the rising time delay information. A falling edge delay signal is generated by shifting the falling edge zero point of the integrated signal of the coil sensing information to select the falling time delay information; and The rectifier gate signal is generated based on the rising edge delay signal and the falling edge delay signal, and then output to the rectifier circuit.

9. The receiver device as claimed in claim 1, further comprising: The phase direction determination circuit is configured to perform a test to determine the phase shift direction. The phase direction determination circuit is configured as follows: Connect or disconnect the communication capacitor between the AC node and the ground node based on the switched polarity test signal; The first level of the rectified voltage in response to connecting the communication capacitor is compared with the second level of the rectified voltage in response to disconnecting the communication capacitor; and The phase shift direction is determined based on the comparison results. The overvoltage protection circuit is configured to generate a rectifier gate signal to shift the phase of the differential signal relative to the receiver coil current according to the phase shift direction.

10. The receiver device as claimed in claim 1, wherein, The overvoltage protection circuit is also configured as follows: Based on the test enable signal, the differential signal between the receiver AC voltages is phase-shifted relative to the receiver coil current along a first direction; In response to the rectified voltage being lower after the phase shift than before the phase shift, the differential signal between the receiver AC voltages continues to be phase-shifted along the first direction; and In response to the rectified voltage becoming higher after a phase shift along the first direction, the differential signal between the receiver AC voltages is phase-shifted along a second direction different from the first direction.

11. A method of operating a receiver device, the receiver device wirelessly receiving power from a transmitter device, the method comprising: The rectified voltage of the receiver device is compared with the overvoltage reference level, and an overvoltage flag signal is generated; Coil sensing information is generated by sensing the receiver coil current sensed from the transmitter device via the receiver coil; Obtain the rising edge zero signal of the rising edge zero point of the indicator coil sensing information and the falling edge zero signal of the falling edge zero point of the indicator coil sensing information; In response to the activation of the overvoltage flag signal, the rising edge zero signal is shifted along a first direction and the falling edge zero signal is shifted along a first direction by applying a first delay to the rising edge zero signal and the falling edge zero signal, the first direction corresponding to phase lag or phase lead. The rectifier gate signal for the rectifier circuit is generated based on the shifted rising edge zero signal and the shifted falling edge zero signal. as well as The rectified voltage is adjusted by applying the adjusted rectifier gate signal to the rectifier circuit, thereby adjusting the phase difference between the differential signal between the receiver AC voltage and the receiver coil current.

12. The method of claim 11, wherein, The steps of shifting the zero signal at the rising edge and the zero signal at the falling edge also include: In response to the rectified voltage level being lower than the rectified voltage level before the shift began, the shift continues along the first direction; and In response to the voltage level of the rectified voltage becoming higher compared to the voltage level of the rectified voltage after the shift begins, the rising edge zero signal is shifted relative to the rising edge zero signal along a second direction different from the first direction by applying a second delay to the rising edge zero signal and the falling edge zero signal.

13. The method of claim 11, wherein, The rising edge zero of the coil sensing information is the rising edge zero of the differential signal of the coil sensing information, and The falling edge zero of the coil sensing information is the falling edge zero of the differential signal of the coil sensing information.

14. The method of claim 11, wherein, The rising edge zero of the coil sensing information is the rising edge zero of the integrated signal of the coil sensing information, and The falling edge zero of the coil sensing information is the falling edge zero of the integrated signal of the coil sensing information.

15. A receiver device, comprising: The receiver LC resonant circuit includes a receiver load capacitor and a receiver coil; A coil current sensor is configured to generate coil sensing information by sensing the current induced from a transmitter device via a receiver coil; A rectifier circuit includes a plurality of switching transistors that are switched in response to a rectifier gate signal and are configured to receive a receiver AC voltage generated by a receiver LC resonant circuit and rectify the receiver AC voltage into a rectified voltage. The overvoltage protection circuit is configured to generate a rectifier gate signal based on a comparison between an overvoltage reference level and the rectified voltage, and to output the rectifier gate signal to the rectifier circuit. as well as The main low-dropout circuit is configured to output a power supply voltage from which noise has been removed by rectified voltage. The rectifier circuit is configured to adjust the phase difference between the differential signal between the receiver AC voltage and the receiver coil current based on the rectifier gate signal received from the overvoltage protection circuit.

16. The receiver device as claimed in claim 15, wherein, The overvoltage protection circuit is also configured to generate a rectifier gate signal, thereby responding to the rectified voltage reaching an overvoltage reference level, causing the rectifier circuit to adjust the phase difference between the differential signal between the receiver AC voltage and the receiver coil current to reduce the rectified voltage.

17. The receiver device of claim 16, further comprising: Phase direction determination circuit The phase direction determination circuit includes: A first communication capacitor, the first end of which is connected to a first AC node that generates the AC voltage of the first receiver; The second communication capacitor has its first end connected to the second AC node that generates the AC voltage for the second receiver. A first transmission transistor is connected between the second terminal of the first communication capacitor and a ground node, and the first transmission transistor is configured to receive a polarity test signal at its gate; and The second transmission transistor is connected between the second terminal of the second communication capacitor and the ground node, and is configured to receive a polarity test signal connected to its gate.

18. The receiver device as claimed in claim 17, wherein, The phase direction determination circuit is configured as follows: The first rectified voltage level is compared with the second rectified voltage level. The first rectified voltage level corresponds to the operation of the first and second transmission transistors in response to the polarity test signal at the first logic level. The second rectified voltage level corresponds to the operation of the first and second transmission transistors in response to the polarity test signal at the second logic level. and Based on the comparison between the first rectified voltage level and the second rectified voltage level, the phase shift direction between the differential signal between the receiver AC voltage and the receiver coil current is determined.

19. The receiver device as claimed in claim 15, wherein, The overvoltage protection circuit includes: The comparator is configured to compare the overvoltage reference level with the rectified voltage and output an overvoltage flag signal; The first multiplexer is configured to select and output one of multiple first rise time delay messages as the selected rise time delay message based on the overvoltage flag signal; The second multiplexer is configured to select and output one of multiple first fall time delay messages as the selected fall time delay message based on the overvoltage flag signal; and The controller is configured to generate a rectifier gate signal based on an overvoltage flag signal, coil sensing information, selected rise time delay information, and selected fall time delay information.

20. The receiver device as claimed in claim 19, wherein, The controller includes: The zero-edge detector circuit is configured to detect the zero point of the signal based on coil sensing information; The timing controller is configured to generate a rising edge delay signal and a falling edge delay signal by respectively taking the detected rising time delay information and the selected falling time delay information from the zero-point shift selection; and The signal generator is configured to use rising edge delayed signals and falling edge delayed signals as gate turn-on signals or gate turn-off signals to generate rectifier gate signals.

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