Satellite integrated electronic system 1553B bus communication fault diagnosis and processing method

Abstract

The application relates to a satellite integrated electronic system 1553B bus communication fault diagnosis and processing method, which is based on the 1553B bus communication protocol format, and is designed to take the message block state word as the center to judge the 1553B bus RT communication fault, and proposes a two-stage fault processing strategy of A / B channel switching and RT device switching for the RT communication fault, and proposes a two-stage fault processing strategy of BC chip initialization and satellite computer switching for the BC communication fault, so that the problem of 1553B bus communication failure is solved, and the reliability of the 1553B bus communication of the satellite integrated electronic system is improved.

Description

Technical Field

[0001] This invention relates to a method for diagnosing and handling faults in the 1553B bus communication of a satellite integrated electronic system. It is mainly used for the reliability design and implementation of the 1553B bus communication in a satellite integrated electronic system and belongs to the field of spacecraft embedded software design. Background Technology

[0002] The 1553B bus is a centralized, time-division multiplexed serial bus. Due to its high reliability, good real-time performance, and strong scalability, it has been widely used in spacecraft. A spacecraft bus typically consists of one bus controller (BC), multiple remote terminals (RTs), and dual bus cables. Currently, most integrated electronic systems on spacecraft use the 1553B bus for critical data transmission between various subsystems, such as telemetry data acquisition and remote control command distribution. BC-side devices, such as the Central Management Unit (CMU), often use a combination of a CPU and a bus chip (such as the B61580) to complete the BC-side bus control.

[0003] When the satellite integrated electronic system uses 1553B bus communication, whether the 1553B communication controller of the BC or RT end device fails due to space environment or other reasons, or the BC or RT end device itself fails, data transmission between devices will fail, which may lead to the spacecraft not working properly. Summary of the Invention

[0004] The technical problem solved by this invention is to overcome the shortcomings of the prior art and provide a method for diagnosing and handling faults in the 1553B bus communication of a satellite integrated electronic system. For the fault conditions of BC and RT equipment, a graded fault discrimination condition and handling strategy are designed to solve the reliability problem of the 1553B bus communication of the satellite integrated electronic system.

[0005] The technical solution adopted in this invention is as follows: A method for diagnosing and handling communication faults in a satellite integrated electronic system 1553B bus, comprising: Set the initialization state of the BC-side chip; Extract RT communication fault conditions based on the 1553B bus communication protocol and determine RT communication faults. Design a fault diagnosis and handling strategy for level 0 RT faults on the 1553B bus, and perform level 0 RT fault handling. Design a fault diagnosis and handling strategy for Level 1 RT on the 1553B bus, and perform Level 1 RT fault handling. Design a fault diagnosis and handling strategy for Level 0 BC faults on the 1553B bus, and perform Level 0 BC fault handling. Design a fault diagnosis and handling strategy for Level 1 BC faults on the 1553B bus, and perform Level 1 BC fault handling.

[0006] Furthermore, the specific process of setting the initialization state of the BC terminal chip is as follows: software initializes and sets the registers and storage areas of the BC terminal chip, including the working mode and A / B stack area; selects the RT address for communication according to the RT on-duty status in the device status table; each terminal device initializes and uses the primary RT address and A channel for communication.

[0007] Furthermore, the specific process for determining RT communication faults is as follows: (21) The CPU software polls the messages in the 1553B bus message stack and parses the block status word, RT address, sub-address, and transmit / receive T / R data of each message according to the 1553B bus communication protocol; (22) If the 11th bit of the block status word of the message is 1, increment the status setting error count by 1 and proceed to step (25); otherwise, proceed to step (23). (23) If the 10th bit of the block status word of the message is 1, the message format error count is incremented by 1 and proceed to step (25); otherwise, proceed to step (24). (24) If the 9th bit of the block status word of the message is 1, increment the response timeout error count by 1 and proceed to step (25); otherwise, proceed to step (25). (25) Determine the values ​​of the status setting error count, message format error count, and response timeout error count. If any one of the count values ​​is greater than the preset threshold M, proceed to step (26); otherwise, proceed to step (27). M is the communication failure number threshold. (26) Set the RT communication flag to abnormal; (27) Set the RT communication flag to normal.

[0008] Furthermore, the specific process for handling Level 0 RT faults is as follows: (31) The CPU checks the communication flags of all RTs in each control cycle. For each RT communication flag, if the RT communication flag is abnormal, the RT communication abnormal count corresponding to the RT communication flag is incremented by 1 and the process proceeds to step (32); otherwise, the RT communication abnormal count corresponding to the RT communication flag is cleared to zero and the process proceeds to step (32). (32) Determine the value of the RT communication anomaly count. If the count value is greater than the preset threshold N, a level 0 RT fault occurs and proceed to step (33); otherwise, proceed to step (35); N is the threshold for the number of communication faults. (33) Determine whether the communication bus with the current RT device is channel A. If it is, proceed to step (34); otherwise, proceed to step (35). (34) Determine whether the current RT switching A / B channel function is enabled. If it is, switch the communication channel of the RT, switch from channel A to channel B, and clear the RT communication error count to zero, then proceed to step (35). Otherwise, proceed to step (35). (35) The communication failure handling is now complete.

[0009] Furthermore, the specific process for handling Level 1 RT faults is as follows: (41) The CPU software retrieves data from the message data receiving area and parses the data content according to the 1553B bus communication protocol; (42) If the frame count is unchanged relative to the previous received frame count, the data update count is incremented by 1, the data update flag is set to no update, and the process proceeds to step (43). Otherwise, the data update count is cleared to zero, the data update flag is set to update, and the process proceeds to step (46). (43) Determine the current RT shift status. If it is on duty, proceed to step (44); otherwise, proceed to step (49). (44) Determine a certain RT communication flag other than the current RT shift flag. If it is normal, proceed to step (45); otherwise, proceed to step (49). (45) Determine the current RT communication flag. If it is abnormal, increment the RT communication fault count by 1 and proceed to step (47); otherwise, proceed to step (46). (46) Determine the current RT data update flag. If it is not updated, increment the RT communication fault count by 1 and proceed to step (47); otherwise, proceed to step (49). (47) Determine the RT communication fault count value. If the count value is greater than the preset threshold K, a level 1 RT fault occurs and proceed to step (48); otherwise, proceed to step (49); K is the communication fault count threshold. (48) Determine whether the Level 1 1553B bus communication fault handling function of the current RT is enabled. If yes, switch the current device communication RT address, switch from the current RT to the backup RT, modify the device status table, set the current RT to be off duty and the backup RT to be on duty, and proceed to step (49). Otherwise, proceed to step (49). (49) This communication failure handling is now complete.

[0010] Furthermore, the specific process for handling level 0 BC faults is as follows: (51) The CPU software checks the working mode, idle state, and communication flags with all RTs of the BC terminal 1553B bus communication controller every cycle. (52) If the working mode of the BC terminal 1553B bus controller is different from the initial state, the fault count of the BC chip working mode is incremented by 1 and the process proceeds to step (53); otherwise, the fault count of the BC chip working mode is cleared and the process proceeds to step (53). (53) If the BC terminal 1553B bus controller is in a non-idle state, the non-idle fault count of the BC chip is incremented by 1 and the process proceeds to step (54); otherwise, the non-idle fault count of the BC chip is cleared and the process proceeds to step (54). (54) If all RT device communication flags are abnormal, the BC chip and all RT communication fault counts are incremented by 1, and the process proceeds to step (55); otherwise, the BC chip and all RT communication fault counts are cleared to zero, and the process proceeds to step (55). (55) Determine the BC chip working mode fault count, BC chip non-idle fault count, and BC chip communication fault count with all RTs. If any of the counts is greater than the preset threshold I, a level 0 BC fault occurs and proceed to step (56); otherwise, proceed to step (57); I is the communication fault count threshold. (56) Determine whether the BC end level 0 1553B bus communication fault handling function is enabled. If it is, initialize the BC end 1553B bus chip, increment the BC end chip initialization count by 1, and clear all fault counts to zero, and proceed to step (57). Otherwise, proceed to step (57). (57) The communication failure handling is now complete.

[0011] Furthermore, the specific process for handling Level 1 BC faults is as follows: (61) Determine whether the communication flags of the three designated RTs are all abnormal. If they are all abnormal, increment the 1553B bus communication fault count by 1 and proceed to step (62). Otherwise, clear the 1553B bus communication fault count and proceed to step (64). (62) Determine the 1553B bus communication fault count value. If the count value is greater than the preset threshold J, a level 1 BC fault occurs and proceed to step (63); otherwise, proceed to step (64); J is the communication fault count threshold. (63) Switch the onboard computer and use the backup onboard computer for control, then proceed to step (64). (64) This communication failure handling is now complete.

[0012] Furthermore, the three designated RTs refer to any three RTs selected from all 1553B bus communication RTs. Examples include the platform integrated service unit, the load integrated service unit, and the power controller.

[0013] In a second aspect, the present invention also proposes a non-volatile storage medium comprising: a computer program product, wherein the method is executed when the computer program product is executed.

[0014] Thirdly, the present invention also proposes a computer program product, which includes a computer program that, when executed by a processor, implements the method described.

[0015] The advantages of this invention compared to the prior art are: (1) Based on the 1553B bus communication protocol format, this invention extracts the status settings, message format, and judgment conditions for response timeout errors, and realizes the judgment method of 1553B bus RT communication layer fault.

[0016] (2) This invention designs a fault condition and handling strategy for a fault in the RT terminal communication controller of the 1553B bus at level 0. Based on the RT communication flag, a judgment condition for a fault in the RT terminal communication controller at level 0 is designed. When a communication fault occurs, the problem of 1553B bus communication failure caused by a fault inside the RT terminal communication controller component is solved by switching the A / B channel of the RT communication, thereby improving the reliability of 1553B bus communication.

[0017] (3) This invention designs a fault condition and handling strategy for a Level 1 RT terminal communication controller failure on the 1553B bus. Based on the RT communication flag, data update flag, shift flag, and other RT communication flags, a fault judgment condition for the Level 1 RT terminal communication controller is designed. When a communication failure occurs, the lower-level 1553B communication controller is switched by switching the lower-level RT address, which solves the problem of 1553B bus communication failure caused by abnormality of the RT terminal communication controller or the RT device itself, and improves the reliability of 1553B bus communication.

[0018] (4) This invention designs a fault condition and handling strategy for a fault in the BC terminal communication controller at level 0 of the 1553B bus. It periodically detects the working mode, idle state, and communication status with all RTs of the BC terminal chip, and designs a judgment condition for a fault in the BC terminal communication controller at level 0. When a communication fault occurs, the BC terminal 1553B communication controller is reset by initializing the BC terminal chip, which solves the problem of 1553B bus communication failure caused by a single fault in the BC terminal communication controller component and improves the reliability of 1553B bus communication.

[0019] (5) This invention designs a fault condition and handling strategy for a fault in the Level 1 BC communication controller of the 1553B bus. The communication status of three designated RTs is periodically detected, and a fault judgment condition for the Level 1 BC communication controller is designed. When a communication failure occurs, the BC 1553B communication controller is switched by switching the onboard computer, which solves the problem of 1553B bus communication failure caused by abnormality of the BC communication controller or the onboard computer itself, and improves the reliability of 1553B bus communication. Attached Figure Description

[0020] Figure 1 Flowchart for RT-side communication fault diagnosis; Figure 2 Flowchart for Level 0 RT fault diagnosis and handling; Figure 3 Flowchart for Level 1 RT fault diagnosis and handling; Figure 4 Flowchart for Level 0 BC fault diagnosis and handling; Figure 5 This is a flowchart for diagnosing and handling Level 1 BC faults. Detailed Implementation

[0021] In satellite integrated electronic systems, the Central Management Unit (CMU), acting as the BC controller, interacts with other RT devices via the 1553B bus. Regarding the 1553B bus communication method, if a fault occurs within the BC chip or RT chip due to space environment or other factors, communication errors may result. To address this issue, this invention proposes a 1553B bus fault diagnosis and handling method for satellite integrated electronic systems. Based on the 1553B bus communication protocol, RT communication fault discrimination conditions are designed, and a reliable and reasonable hierarchical fault diagnosis and handling strategy is proposed, improving the reliability of 1553B bus communication in satellite integrated electronic systems. The specific embodiments of this invention will be further described in detail below with reference to the accompanying drawings.

[0022] This invention proposes a method for diagnosing and handling communication faults in the 1553B bus of a satellite integrated electronic system, comprising the following steps: Step 1: Set the initialization state of the BC terminal chip; The specific process is as follows: the software initializes and sets the registers and storage areas of the BC terminal chip, including the working mode and A / B stack area; the RT address for communication is selected according to the RT on-duty status in the device status table; each terminal device initializes using the primary RT address and A channel communication.

[0023] Step 2: Extract the RT communication fault conditions according to the 1553B bus communication protocol and perform RT communication fault judgment. like Figure 1As shown, the specific process is as follows: (21) The CPU software polls the messages in the 1553B bus message stack and parses the block status word, RT address, sub-address, and transmit / receive T / R data of each message according to the 1553B bus communication protocol; (22) If the 11th bit of the block status word of the message is 1, increment the status setting error count by 1 and proceed to step (25); otherwise, proceed to step (23). (23) If the 10th bit of the block status word of the message is 1, the message format error count is incremented by 1 and proceed to step (25); otherwise, proceed to step (24). (24) If the 9th bit of the block status word of the message is 1, increment the response timeout error count by 1 and proceed to step (25); otherwise, proceed to step (25). (25) Determine the values ​​of the status setting error count, message format error count, and response timeout error count. If any one of the count values ​​is greater than the preset threshold M, proceed to step (26); otherwise, proceed to step (27). M is the communication failure number threshold. (26) Set the RT communication flag to abnormal; (27) Set the RT communication flag to normal.

[0024] Step 3: Design a fault diagnosis and handling strategy for Level 0 RT faults on the 1553B bus, and perform Level 0 RT fault handling. like Figure 2 As shown, the specific process is as follows: (31) The CPU checks the communication flags of all RTs in each control cycle. For each RT communication flag, if the RT communication flag is abnormal, the RT communication abnormal count corresponding to the RT communication flag is incremented by 1 and the process proceeds to step (32); otherwise, the RT communication abnormal count corresponding to the RT communication flag is cleared to zero and the process proceeds to step (32). (32) Determine the value of the RT communication anomaly count. If the count value is greater than the preset threshold N, a level 0 RT fault occurs and proceed to step (33); otherwise, proceed to step (35); N is the threshold for the number of communication faults. (33) Determine whether the communication bus with the current RT device is channel A. If it is, proceed to step (34); otherwise, proceed to step (35). (34) Determine whether the current RT switching A / B channel function is enabled. If it is, switch the communication channel of the RT, switch from channel A to channel B, and clear the RT communication error count to zero, then proceed to step (35). Otherwise, proceed to step (35). (35) The communication failure handling is now complete.

[0025] Step 4: Design a fault diagnosis and handling strategy for Level 1 RT of the 1553B bus, and perform Level 1 RT fault handling. like Figure 3 As shown, the specific process for handling Level 1 RT faults is as follows: (41) The CPU software retrieves data from the message data receiving area and parses the data content according to the 1553B bus communication protocol; (42) If the frame count is unchanged relative to the previous received frame count, the data update count is incremented by 1, the data update flag is set to no update, and the process proceeds to step (43). Otherwise, the data update count is cleared to zero, the data update flag is set to update, and the process proceeds to step (46). (43) Determine the current RT shift status. If it is on duty, proceed to step (44); otherwise, proceed to step (49). (44) Determine a certain RT communication flag other than the current RT shift flag. If it is normal, proceed to step (45); otherwise, proceed to step (49). (45) Determine the current RT communication flag. If it is abnormal, increment the RT communication fault count by 1 and proceed to step (47); otherwise, proceed to step (46). (46) Determine the current RT data update flag. If it is not updated, increment the RT communication fault count by 1 and proceed to step (47); otherwise, proceed to step (49). (47) Determine the RT communication fault count value. If the count value is greater than the preset threshold K, a level 1 RT fault occurs and proceed to step (48); otherwise, proceed to step (49); K is the communication fault count threshold. (48) Determine whether the Level 1 1553B bus communication fault handling function of the current RT is enabled. If yes, switch the current device communication RT address, switch from the current RT to the backup RT, modify the device status table, set the current RT to be off duty and the backup RT to be on duty, and proceed to step (49). Otherwise, proceed to step (49). (49) This communication failure handling is now complete.

[0026] Step 5: Design a fault diagnosis and handling strategy for Level 0 BC faults on the 1553B bus, and perform Level 0 BC fault handling. like Figure 4 As shown, the specific process for handling a level 0 BC fault is as follows: (51) The CPU software checks the working mode, idle state, and communication flags with all RTs of the BC terminal 1553B bus communication controller every cycle. (52) If the working mode of the BC terminal 1553B bus controller is different from the initial state, the fault count of the BC chip working mode is incremented by 1 and the process proceeds to step (53); otherwise, the fault count of the BC chip working mode is cleared and the process proceeds to step (53). (53) If the BC terminal 1553B bus controller is in a non-idle state, the non-idle fault count of the BC chip is incremented by 1 and the process proceeds to step (54); otherwise, the non-idle fault count of the BC chip is cleared and the process proceeds to step (54). (54) If all RT device communication flags are abnormal, the BC chip and all RT communication fault counts are incremented by 1, and the process proceeds to step (55); otherwise, the BC chip and all RT communication fault counts are cleared to zero, and the process proceeds to step (55). (55) Determine the BC chip working mode fault count, BC chip non-idle fault count, and BC chip communication fault count with all RTs. If any of the counts is greater than the preset threshold I, a level 0 BC fault occurs and proceed to step (56); otherwise, proceed to step (57); I is the communication fault count threshold. (56) Determine whether the BC end level 0 1553B bus communication fault handling function is enabled. If it is, initialize the BC end 1553B bus chip, increment the BC end chip initialization count by 1, and clear all fault counts to zero, and proceed to step (57). Otherwise, proceed to step (57). (57) The communication failure handling is now complete.

[0027] Step 6: Design a fault diagnosis and handling strategy for Level 1 BC faults on the 1553B bus, and perform Level 1 BC fault handling.

[0028] like Figure 5 As shown, the specific process for handling a Level 1 BC fault is as follows: (61) Determine whether the communication flags of the three designated RTs are all abnormal. If they are all abnormal, increment the 1553B bus communication fault count by 1 and proceed to step (62). Otherwise, clear the 1553B bus communication fault count and proceed to step (64). (62) Determine the 1553B bus communication fault count value. If the count value is greater than the preset threshold J, a level 1 BC fault occurs and proceed to step (63); otherwise, proceed to step (64); J is the communication fault count threshold. (63) Switch the onboard computer and use the backup onboard computer for control, then proceed to step (64). (64) This communication failure handling is now complete.

[0029] In this invention, "three designated RTs" refers to any three RTs selected from all 1553B bus communication RTs. Examples include the platform integrated service unit, the payload integrated service unit, and the power controller.

[0030] Example: This embodiment provides a method for fault diagnosis and handling of the 1553B bus in a satellite integrated electronic system. The specific steps are as follows: Step 1: Initialize the B / C chip status: The software initializes the registers and memory areas of the BC-side chip, including the working mode, A / B stack area, etc.; selects the RT address for communication based on the RT on-duty status in the device status table; each device initializes using the primary RT address and A channel communication.

[0031] Step 2, RT communication fault diagnosis: The CPU software polls the messages in the 1553B bus message stack and parses the block status word, RT address, sub-address, transmit / receive T / R, and other data of each message according to the communication protocol. For example... Figure 1 As shown, during unpacking, the message block data words should be strictly checked. If the 11th bit of the message block status word is 1, the status setting error count is incremented by 1; if the 10th bit of the message block status word is 1, the message format error count is incremented by 1; if the 9th bit of the message block status word is 1, the response timeout error count is incremented by 1. If any of the status setting error count, message format error count, or response timeout error count is greater than 0, it indicates that the message communication was unsuccessful. In each communication cycle, the software checks the error count value. If any count value is greater than M (M is set according to actual needs), the RT communication flag is set to abnormal; otherwise, the RT communication flag is set to normal.

[0032] Step 3: Design of fault diagnosis and handling strategy for 1553B bus level 0 RT faults: like Figure 2 The diagram shows the RT fault diagnosis and handling flowchart for level 0 of the 1553B bus. Each control cycle, the CPU checks all RT communication flags. If an error is detected, the RT communication error count is incremented by 1; otherwise, it is reset to zero. If the RT communication error count is not zero, it indicates an internal fault in the RT communication controller component causing a data transmission error. The software determines the magnitude of the RT communication error count. If the count is greater than N (where N is set according to actual requirements), the communication channel for that RT is switched from channel A to channel B, and the RT communication error count is reset to zero. In other words, BC uses channel B to communicate with that RT.

[0033] Step 4: Design of Level 1 RT Fault Diagnosis and Handling Strategy: The CPU software retrieves data from the message data receiving area and parses the data content according to the pre-agreed communication protocol. If the frame count remains unchanged compared to the previously received frame count, the data is not updated, the count is incremented by 1, and the data update flag is set to not update. If the current RT is on duty, other RTs are communicating normally, the current RT is malfunctioning, or the current RT is not updating data, the RT communication fault count is incremented by 1; otherwise, the RT communication fault count is reset to zero. If the RT communication fault count is not zero, it indicates that the RT communication controller has not received correct data, or the RT device itself has malfunctioned. The software checks the RT communication fault count value each communication cycle. If the count value is greater than K (K is set according to actual needs), it switches the communication RT address of the device, switching from the current RT to the backup RT, and modifies the device status table, setting the current RT to off-duty and the backup RT to on-duty. Communication is then performed using the backup RT. Figure 3 The diagram shown is a flowchart for fault diagnosis and handling of Level 1 RT faults on the 1553B bus.

[0034] Step 5: Design of 1553B bus level 0 BC fault diagnosis and handling strategy: The CPU software checks the operating mode, idle state, and communication flags of all RTs of the BC-side 1553B bus communication controller every cycle. If the operating mode of the BC-side 1553B bus controller differs from its initial state, the BC chip's operating mode fault count is incremented by 1; otherwise, the BC chip's operating mode fault count is reset to zero. If the BC-side 1553B bus controller's idle state is not idle, the BC chip's non-idle fault count is incremented by 1; otherwise, the BC chip's non-idle fault count is reset to zero. If all RT device communication flags are abnormal, the BC chip's communication fault count with all RTs is incremented by 1; otherwise, the BC chip's communication fault count with all RTs is reset to zero. If any of the BC chip's operating mode fault count, BC chip's non-idle fault count, or BC chip's communication fault count with all RTs is not zero, it indicates a malfunction in the BC-side communication controller. The software judges the fault count value in each control cycle. If any count value is greater than I (the value of I is set according to actual needs), the BC-side 1553B bus communication fault handling function is enabled, the BC-side 1553B bus chip is initialized, the BC-side chip initialization count is incremented by 1, and all fault counts are reset to zero. Figure 4 The diagram shown is a flowchart for troubleshooting and handling level 0 BC faults on the 1553B bus.

[0035] Step 6: Design of Fault Diagnosis and Handling Strategy for Level 1 BC Faults on the 1553B Bus: The CPU software checks the communication flags of the three designated RTs each communication cycle. If all flags are abnormal, the 1553B bus communication fault count is incremented by 1; otherwise, the count is reset to zero. If the 1553B bus communication fault count is greater than J (the value of J is set according to actual needs), the onboard computer is switched to a backup onboard computer for control, specifically using the BC communication controller of the backup computer. Figure 5 The diagram shown is a flowchart for troubleshooting and handling Level 1 BC faults on the 1553B bus.

[0036] This invention solves the problem of 1553B bus communication failure and improves the reliability of 1553B bus communication in satellite integrated electronic systems.

[0037] The contents not described in detail in this specification are common knowledge to those skilled in the art.

Claims

1. A method for diagnosing and handling communication faults in a satellite integrated electronic system using the 1553B bus, characterized in that, include: Set the initialization state of the BC-side chip; Extract RT communication fault conditions based on the 1553B bus communication protocol and determine RT communication faults. Design a fault diagnosis and handling strategy for level 0 RT faults on the 1553B bus, and perform level 0 RT fault handling. Design a fault diagnosis and handling strategy for Level 1 RT on the 1553B bus, and perform Level 1 RT fault handling. Design a fault diagnosis and handling strategy for Level 0 BC faults on the 1553B bus, and perform Level 0 BC fault handling. Design a fault diagnosis and handling strategy for Level 1 BC faults on the 1553B bus, and perform Level 1 BC fault handling.

2. The method for diagnosing and handling communication faults in a satellite integrated electronic system 1553B bus according to claim 1, characterized in that: The specific process for setting the initialization state of the BC terminal chip is as follows: software initialization sets the registers and storage areas of the BC terminal chip, including the working mode and A / B stack area; according to the RT on-duty status in the device status table, the RT address for communication is selected; each terminal device initializes using the primary RT address and A channel communication.

3. The method for diagnosing and handling communication faults in a satellite integrated electronic system 1553B bus according to claim 1, characterized in that: The specific process for RT communication fault diagnosis is as follows: (21) The CPU software polls the messages in the 1553B bus message stack and parses the block status word, RT address, sub-address, and transmit / receive T / R data of each message according to the 1553B bus communication protocol; (22) If the 11th bit of the block status word of the message is 1, increment the status setting error count by 1 and proceed to step (25); otherwise, proceed to step (23). (23) If the 10th bit of the block status word of the message is 1, the message format error count is incremented by 1 and proceed to step (25); otherwise, proceed to step (24). (24) If the 9th bit of the block status word of the message is 1, increment the response timeout error count by 1 and proceed to step (25); otherwise, proceed to step (25). (25) Determine the values ​​of the status setting error count, message format error count, and response timeout error count. If any one of the count values ​​is greater than the preset threshold M, proceed to step (26); otherwise, proceed to step (27). M is the communication failure number threshold. (26) Set the RT communication flag to abnormal; (27) Set the RT communication flag to normal.

4. The method for diagnosing and handling communication faults in a satellite integrated electronic system 1553B bus according to claim 3, characterized in that: The specific process for handling Level 0 RT faults is as follows: (31) The CPU checks the communication flags of all RTs in each control cycle. For each RT communication flag, if the RT communication flag is abnormal, the RT communication abnormal count corresponding to the RT communication flag is incremented by 1 and the process proceeds to step (32); otherwise, the RT communication abnormal count corresponding to the RT communication flag is cleared to zero and the process proceeds to step (32). (32) Determine the value of the RT communication anomaly count. If the count value is greater than the preset threshold N, a level 0 RT fault occurs and proceed to step (33); otherwise, proceed to step (35); N is the threshold for the number of communication faults. (33) Determine whether the communication bus with the current RT device is channel A. If it is, proceed to step (34); otherwise, proceed to step (35). (34) Determine whether the current RT switching A / B channel function is enabled. If it is, switch the communication channel of the RT, switch from channel A to channel B, and clear the RT communication error count to zero, then proceed to step (35). Otherwise, proceed to step (35). (35) The communication failure handling is now complete.

5. The method for diagnosing and handling communication faults in a satellite integrated electronic system 1553B bus according to claim 3, characterized in that: The specific process for handling Level 1 RT faults is as follows: (41) The CPU software retrieves data from the message data receiving area and parses the data content according to the 1553B bus communication protocol; (42) If the frame count is unchanged relative to the previous received frame count, the data update count is incremented by 1, the data update flag is set to no update, and the process proceeds to step (43). Otherwise, the data update count is cleared to zero, the data update flag is set to update, and the process proceeds to step (46). (43) Determine the current RT shift status. If it is on duty, proceed to step (44); otherwise, proceed to step (49). (44) Determine a certain RT communication flag other than the current RT shift flag. If it is normal, proceed to step (45); otherwise, proceed to step (49). (45) Determine the current RT communication flag. If it is abnormal, increment the RT communication fault count by 1 and proceed to step (47); otherwise, proceed to step (46). (46) Determine the current RT data update flag. If it is not updated, increment the RT communication fault count by 1 and proceed to step (47); otherwise, proceed to step (49). (47) Determine the RT communication fault count value. If the count value is greater than the preset threshold K, a level 1 RT fault occurs and proceed to step (48); otherwise, proceed to step (49); K is the communication fault count threshold. (48) Determine whether the Level 1 1553B bus communication fault handling function of the current RT is enabled. If yes, switch the current device communication RT address, switch from the current RT to the backup RT, modify the device status table, set the current RT to be off duty and the backup RT to be on duty, and proceed to step (49). Otherwise, proceed to step (49). (49) This communication failure handling is now complete.

6. The method for diagnosing and handling communication faults in a satellite integrated electronic system 1553B bus according to claim 1, characterized in that: The specific process for handling a Level 0 BC fault is as follows: (51) The CPU software checks the working mode, idle state, and communication flags with all RTs of the BC terminal 1553B bus communication controller every cycle. (52) If the working mode of the BC terminal 1553B bus controller is different from the initial state, the fault count of the BC chip working mode is incremented by 1 and the process proceeds to step (53); otherwise, the fault count of the BC chip working mode is cleared and the process proceeds to step (53). (53) If the BC terminal 1553B bus controller is in a non-idle state, the non-idle fault count of the BC chip is incremented by 1 and the process proceeds to step (54); otherwise, the non-idle fault count of the BC chip is cleared and the process proceeds to step (54). (54) If all RT device communication flags are abnormal, the BC chip and all RT communication fault counts are incremented by 1, and the process proceeds to step (55); otherwise, the BC chip and all RT communication fault counts are cleared to zero, and the process proceeds to step (55). (55) Determine the BC chip working mode fault count, BC chip non-idle fault count, and BC chip communication fault count with all RTs. If any of the counts is greater than the preset threshold I, a level 0 BC fault occurs and proceed to step (56); otherwise, proceed to step (57); I is the communication fault count threshold. (56) Determine whether the BC end level 0 1553B bus communication fault handling function is enabled. If it is, initialize the BC end 1553B bus chip, increment the BC end chip initialization count by 1, and clear all fault counts to zero, and proceed to step (57). Otherwise, proceed to step (57). (57) The communication failure handling is now complete.

7. The method for diagnosing and handling communication faults in a satellite integrated electronic system 1553B bus according to claim 1, characterized in that: The specific process for handling a Level 1 BC fault is as follows: (61) Determine whether the communication flags of the three designated RTs are all abnormal. If they are all abnormal, increment the 1553B bus communication fault count by 1 and proceed to step (62). Otherwise, clear the 1553B bus communication fault count and proceed to step (64). (62) Determine the 1553B bus communication fault count value. If the count value is greater than the preset threshold J, a level 1 BC fault occurs and proceed to step (63); otherwise, proceed to step (64); J is the communication fault count threshold. (63) Switch the onboard computer and use the backup onboard computer for control, then proceed to step (64). (64) This communication failure handling is now complete.

8. The method for diagnosing and handling communication faults in a satellite integrated electronic system 1553B bus according to claim 7, characterized in that: The three designated RTs refer to any three RTs that can be selected from all 1553B bus communication RTs.

9. A non-volatile storage medium, characterized in that, include: A computer program product that, when executed, performs the method described in any one of claims 1 to 8.

10. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the steps of the method according to any one of claims 1 to 8.

Images