A clock synchronization method and related device

Abstract

Embodiments of the present application provide a clock synchronization method and related equipment, which are used to improve the reliability of clock synchronization, and in the case of a fault in a synchronization network, the clock source of the fault node is degraded, thereby reducing the impact of the node fault on the synchronization network. The clock synchronization method provided by the embodiments of the present application is a physical layer clock reliability enhanced synchronization method, which is applied to a first device, and the method comprises: the first device receives a first signal from a second device, and the second device is a selected clock source of the first device. If the frequency offset of the first signal is abnormal, the first device sends a first clock level signal, the first clock level signal indicates that the quality of the clock source of the first device changes, and the quality level of the first clock level signal is lower than the quality level of the clock source of the second device.

Description

Technical Field

[0001] This application relates to the field of optical communication, and in particular to a clock synchronization method and related equipment. Background Technology

[0002] In optical communication networks, clock synchronization technology is typically used to ensure the accuracy and stability of signal transmission. Specifically, clock synchronization technology involves devices in the optical communication network selecting a clock source from upstream or peer devices, thereby constructing a top-down synchronization network.

[0003] However, if a node in the synchronization network experiences a clock synchronization signal anomaly or a hardware failure, the clock synchronization signal it sends to downstream devices will also be abnormal. This abnormal clock synchronization signal will propagate downstream from that node, affecting downstream synchronization services. Furthermore, since clock synchronization is a network-level issue, a failure will significantly increase maintenance and troubleshooting costs, making the time required to resolve the fault unpredictable. Summary of the Invention

[0004] This application provides a clock synchronization method and related equipment for degrading the clock source of a faulty node in the event of a synchronization network failure, thereby reducing the impact of the node failure on the synchronization network.

[0005] In a first aspect, embodiments of this application provide a clock synchronization method. The method is applied to a first device and includes: the first device receiving a first signal from a second device, where the second device is a clock source selected by the first device. If the frequency offset of the first signal is abnormal, the first device sends a first clock level signal, which indicates a change in the quality of the clock source of the first device, and the quality level of the first clock level signal is lower than the quality level of the clock source of the second device.

[0006] In this embodiment, the first device, the second device (and subsequently the third device, etc.) are network elements, routers, etc., in an optical communication network. The first signal is a physical signal sent by the second device to the first device. The first device can quantize the first signal (e.g., perform frequency offset quantization) and then perform corresponding operations (e.g., degradation operations). The frequency offset of the first signal can indicate the jitter of the first signal. The first clock level signal is the message content carried on the physical signal sent by the first device, specifically the message content carried in the message overhead area. The first clock level signal is used to indicate the quality of the synchronization signal upstream of the first device and is the basis for the clock synchronization source selection of devices connected to the first device.

[0007] In this embodiment, when the first device detects an abnormal frequency offset in the signal (first signal) between itself and the clock source, it considers the communication link between the first device and the clock source (second device) to be abnormal and thus sends a first clock level signal. This abnormality can be considered to have originated from the second device. Since the quality level of the first clock level signal is lower than that of the clock source (second device) selected by the first device, devices connected to the first device, upon receiving the first clock level signal, can determine that the clock source quality of the first device has deteriorated and thus reselect a clock source, achieving clock source switching for downstream devices of the first device. This prevents the abnormality at the second device from propagating downstream from the first device, reducing the impact of the abnormality at the second device on the synchronization network.

[0008] In one alternative implementation, after the first device receives the first signal from the second device, the method further includes: if the frequency offset of the first signal is abnormal, the first device sends an alarm message indicating a communication link failure between the second device and the first device.

[0009] Optionally, alarm information can be sent to a network management device, which may be a network management system, network element management system, routing management system, etc., that communicates with the first device; alarm information can also be sent to the display interface of the first device to convey alarm information to the user through the display interface, and this application does not limit this.

[0010] In this embodiment, when the first device detects an abnormal frequency offset in the signal (first signal) between itself and the clock source, it considers the communication link between the first device and the clock source (second device) to be abnormal and sends an alarm message. Based on this alarm message, the location of the abnormality can be quickly located (i.e., upstream of the first device, specifically the second device upstream of the first device, or the communication link between the first device and the second device), thereby accelerating the fault resolution process.

[0011] In one optional implementation, the clock source quality level of the second device is higher than the device clock level QL-SEC. The step of the first device sending a first clock level signal if the frequency offset of the first signal is abnormal may specifically include: if the frequency offset jitter of the first signal is greater than a first threshold, then sending a first clock level signal to a device other than the second device, where the first threshold is the maximum frequency offset jitter threshold that the first device can tolerate, the quality level of the first clock level signal is QL-SEC, and the first clock level signal indicates that the clock source of the first device is switched to the first device.

[0012] In this embodiment, when the frequency offset jitter of the first signal exceeds the maximum tolerable threshold range of the first device, the first device can continue to communicate with the second device. However, the clock source quality level of the synchronization signal provided by the first device downstream is lower than that of the second device. In this case, the first device switches the clock source to itself, thereby avoiding using the clock source of the abnormal second device as a backup clock source for downstream devices. This prevents the anomaly at the second device from spreading downstream from the first device, reducing the impact of the anomaly at the second device on the synchronization network.

[0013] In one optional implementation, the step of the first device sending a first clock level signal if the frequency offset of the first signal is abnormal may specifically include: if the frequency offset of the first signal is greater than a second threshold, or if the first signal is lost, the first device sends a first clock level signal to a device other than the second device, where the second threshold is the maximum frequency offset threshold that the first device can tolerate, the quality of the first clock level signal is registered as device clock level QL-SEC, and the first clock level signal indicates that the clock source of the first device is switched to the first device.

[0014] In this embodiment, when the frequency offset of the first signal exceeds the maximum tolerable frequency offset threshold of the first device or the first signal is lost, the first device cannot continue communicating with the second device, and the clock source quality level of the synchronization signal provided by the first device downstream is lower than that of the second device. In this case, the first device switches its clock source back to itself, thereby avoiding using the clock source of the abnormal second device as a backup clock source for downstream devices. This prevents the anomaly at the second device from spreading downstream from the first device, reducing the impact of the anomaly at the second device on the synchronization network.

[0015] In one alternative implementation, the clock source quality of the second device is of the reference master clock level QL-PRC, the transfer station level QL-SSU-A, or the local station level QL-SSU-B.

[0016] In one optional implementation, the step of the first device sending a second clock level signal if the frequency offset of the first signal is abnormal may specifically include: if the frequency offset of the first signal is greater than a second threshold, or if the first signal is lost, the first device sends a first clock level signal to a third device and sends a second clock level signal to devices other than the third device. The second threshold is the maximum frequency offset threshold that the first device can tolerate. The quality level of the first clock level signal is QL-DNU, which should not be used as a synchronization source. The first clock level signal indicates that the clock source of the first device is switched to the third device. The second clock level signal indicates the clock source quality level of the third device. The clock source quality level of the third device is higher than that of the first device.

[0017] In this embodiment, when the frequency offset of the first signal exceeds the maximum tolerable frequency offset threshold of the first device or the first signal is lost, the first device cannot continue communicating with the second device. Furthermore, the clock source quality level of the third device connected to the first device is higher than that of the first device. In this situation, the first device switches its clock source to the third device, thereby avoiding using the abnormal clock source of the second device as a backup clock source for downstream devices. This prevents the anomaly at the second device from spreading downstream from the first device, reducing the impact of the anomaly at the second device on the synchronization network.

[0018] In one alternative implementation, the second clock level signal indicates that the clock source quality level of the third device is the reference master clock level QL-PRC, the transfer station level QL-SSU-A, or the local station level QL-SSU-B.

[0019] In one alternative implementation, before the first device sends the second clock level signal to a device other than the third device, the method further includes: the first device switching its clock source to the third device.

[0020] In one alternative implementation, the first device switches its clock source to the third device, including: the first device adjusts the clock source quality level of the second device to "synchronization source unavailable", performs synchronization clock selection based on the adjusted clock source quality level of the second device, and determines the third device as the new clock source for the first device.

[0021] In one alternative implementation, the first device and the second device are routers, microwave devices, base station devices, or network elements, and the first device and the second device are connected by optical fiber.

[0022] Secondly, embodiments of this application provide an optical communication device, which includes one or more modules for implementing the clock synchronization method described in the first aspect.

[0023] Thirdly, embodiments of this application provide an optical communication device, which includes: a processor and a memory, the processor being coupled to the memory; the memory being used to store a program; and the processor being used to execute the program in the memory, causing the optical communication device to perform the method described in the first aspect.

[0024] Fourthly, this application provides a computer-readable storage medium storing a computer program that, when executed, implements the method described in the first aspect above.

[0025] Fifthly, a computer program product is provided, which, when executed on a computer, causes the computer to perform the method described in the first aspect.

[0026] The beneficial effects of aspects two through five are described in aspect one, and will not be repeated here. Attached Figure Description

[0027] Figure 1a A schematic diagram of the architecture of the clock synchronization network provided in this application;

[0028] Figure 1b A schematic diagram illustrating a clock synchronization network failure provided in this application;

[0029] Figure 2 A schematic diagram of the synchronization network relationship for the clock synchronization network provided in this application;

[0030] Figure 3 A flowchart illustrating the clock synchronization method provided in this application;

[0031] Figure 4 A schematic diagram of a clock synchronization method for a small frequency offset scenario provided in an embodiment of this application;

[0032] Figure 5 A flowchart illustrating a clock synchronization method for a small frequency offset scenario provided in this application embodiment;

[0033] Figure 6 A flowchart illustrating a clock synchronization method for a large frequency offset scenario provided in an embodiment of this application;

[0034] Figure 7 A schematic diagram of a clock synchronization method for a small frequency offset scenario provided in an embodiment of this application;

[0035] Figure 8 Another flowchart illustrating the clock synchronization method for a large frequency offset scenario provided in the embodiments of this application;

[0036] Figure 9 This is another schematic diagram of a clock synchronization method for small frequency offset scenarios provided in the embodiments of this application;

[0037] Figure 10 A schematic diagram of the optical communication device provided in this application;

[0038] Figure 11 Another structural schematic diagram of the optical communication device provided in this application. Detailed Implementation

[0039] The embodiments of this application will now be described with reference to the accompanying drawings. Those skilled in the art will recognize that, with technological advancements and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are equally applicable to similar technical problems.

[0040] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms are interchangeable where appropriate; this is merely a way of distinguishing objects with the same attributes in the embodiments of this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, so that a process, method, system, product, or apparatus that comprises a series of units is not necessarily limited to those units, but may include other units not explicitly listed or inherent to those processes, methods, products, or apparatuses. Additionally, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or multiple items. For example, at least one of a, b, or c can be expressed as: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0041] In optical communication networks, clock synchronization technology is typically used to ensure the accuracy and stability of signal transmission. The role of clock synchronization in optical communication networks is mainly reflected in the following aspects:

[0042] 1. Ensure the accuracy and stability of signal transmission: In optical communication networks, the clocks of all nodes need to be highly synchronized to ensure the accuracy and stability of signal transmission. If the clocks of the nodes are not synchronized, it may cause delays, jitter, or even loss of signal transmission, affecting the performance and reliability of the network.

[0043] 2. Reduce network latency and jitter: Clock synchronization can reduce latency and jitter in the network, ensuring consistent data packet transmission time and thus improving overall network performance. In a network, each node needs a unified time base to ensure the correct order and timing of data packets.

[0044] 3. Support for distributed systems and cloud computing platforms: In distributed systems and cloud computing platforms, all servers and computing nodes need to maintain time synchronization to ensure log recording, task scheduling, and data consistency. Clock synchronization is crucial for ensuring the efficient operation of these systems.

[0045] 4. Improve communication quality: In communication networks, especially 5G base stations and fiber optic communication networks, clock synchronization can ensure the smoothness and stability of signal transmission and avoid lag and network outages when switching mobile phone signals.

[0046] The International Telecommunication Union (ITU)-T G.803 specifies the synchronization network architecture, where synchronization information is transmitted through synchronization network connections. These synchronization network connections can transmit different synchronization levels. Each synchronization network connection is provided by one or more synchronization link connections, each supported by a plesiochronous digital hierarchy (PDH) path, a synchronous digital hierarchy (SDH) multiplexed section path, an optical transport network (OTN) optical transform unit (OTU) path, an optical supervisory channel (OSC) path, or an IEEE 802.3 physical medium path. Figure 1a As shown, a complete clock synchronization network consists of three parts: clock source, bearer network, and base station. The embodiments of this application are mainly applied to bearer network equipment.

[0047] like Figure 1b As shown, SDH networks and base stations require strict time synchronization, and WDM / OTN networks are needed to achieve clock synchronization in mobile backhaul networks.

[0048] Clock synchronization technology specifically involves devices in an optical communication network selecting a clock source from upstream or peer devices to construct a top-down synchronization network. However, if a node in the synchronization network experiences an abnormal clock synchronization signal or hardware failure, the clock synchronization signal it sends to downstream devices will also be abnormal. This abnormal clock synchronization signal will propagate downstream from that node, thus affecting downstream synchronization services. For example... Figure 1b As shown, if the main building-integrated timing supply (BITS) source fails, an anomaly in the synchronization signal will occur between devices in the backbone OTN that use the main BITS source as their clock source. This anomaly (or fault) will propagate downwards along the synchronization network, thereby affecting the clock synchronization of downstream OTN, SDH, base stations, etc.

[0049] Furthermore, since clock synchronization is at the network level, a failure will greatly increase the cost of operation and maintenance, making the time to resolve the failure unpredictable.

[0050] To address the aforementioned issues, embodiments of this application provide a clock synchronization method and related equipment, which degrades the clock source of a faulty node in the event of a synchronization network failure, thereby reducing the impact of the node failure on the synchronization network.

[0051] The clock synchronization method provided in this application is a physical layer clock reliability enhancement synchronization method, which can be implemented based on the Synchronous Status Message (SSM) source selection algorithm. The SSM source selection algorithm is a physical layer clock source selection algorithm used to establish tracking relationships between networks. Two important parameters of the SSM source selection algorithm are node priority and clock source quality.

[0052] The priority is determined based on the network topology, for example... Figure 1a In the context of backbone layer devices, the primary BITS source and the backup BITS source are upstream devices of the device and have higher priority in the device's clock source priority list; other devices in the backbone layer are peer devices of the device and are also in the device's clock source priority list.

[0053] The clock source quality of the SSM source selection algorithm is shown in Table 1. When clock source quality is the same, the source is selected according to the order of the clock source priority list. Therefore, the clock source with the best quality is selected first during clock source selection. Clock source quality includes quality levels such as Primary Reference Clock (PRC), Synchronization Supply Unit (SSU), Equipment Clock (SEC), and Do Not Use for Synchronization (DNU). Specifically, the order of clock source quality levels is: QL-PRC (Primary Master Clock) > QL-SSU-A (Transfer Center Clock) > QL-SSU-B (Local Center Clock) > QL-SEC (Equipment Clock) > QL-DNU (Do Not Use for Synchronization).

[0054] Table 1 SSM Quality Grade Information

[0055] Quality grade SSM value Clock source quality QL-PRC 0x2 G.811 clock signal, reference master clock, primary clock. QL-SSU-A 0x4 G.812 converter clock signal, secondary clock QL-SSU-B 0x8 G.812 local clock signal, level three clock QL-SEC 0xb Synchronization device timing source (SETS) clock signal QL-DNU 0xf Synchronization source unavailable

[0056] like Figure 2 As shown, based on Figure 2The physical network topology shown in the left-middle diagram, combined with the priority and clock source quality of each net element (NE), allows for SSM source selection by each net element, resulting in... Figure 2 The clock synchronization network shown in the middle right figure is as follows. NE1 selects the primary clock on the left as its synchronization source, NE3 and NE2 both select NE1 as their synchronization source, NE5 selects NE3 as its synchronization source, NE7 and base station 1 select NE5 as their synchronization source, and so on, thus constructing a clock synchronization network from the primary clock to each base station.

[0057] Figure 3 A flowchart illustrating the clock synchronization method provided in this application embodiment is shown below. Figure 3 As shown, the method includes:

[0058] 301. The first device receives a first signal from the second device, whereby the second device is the clock source selected by the first device.

[0059] In the embodiments of this application, the first device, the second device (and the third device that appears later, etc.) are network elements, routers, microwave equipment or base station equipment in optical communication networks.

[0060] Assumption Figure 4 NE2 is the first device. Based on SSM source selection, NE1 can select the left-side primary clock as the clock source, and NE2 (the first device) can select NE1 (the second device) as the clock source. Similarly, NE4 selects NE2 as the clock source, NE6 selects NE4 as the clock source, and base station 4 selects NE6 as the clock source; thus realizing the transmission of synchronization signals from the left-side primary clock, NE1, NE2, NE4, NE6 to base station 4. This line is also called a synchronization network.

[0061] Then, synchronization signals can be transmitted in the synchronization network. Specifically, the first device NE2 can receive a first signal from the second device NE1. The first signal is a physical signal sent by the second device NE1 to the first device NE2, which is not limited in this application. Since the first device and the second device are in the same clock synchronization network, the first signal is also a synchronization signal between the second device and the first device.

[0062] In this embodiment, the first signal is a physical signal sent from the second device to the first device. The first device can quantize the first signal (e.g., perform frequency offset quantization) and then perform corresponding operations (e.g., degradation operations). It is worth noting that in this embodiment, the clock source quality level of the second device is not limited. The clock source quality level of the second device can be a reference clock level QL-PRC, a switching office level QL-SSU-A, or a local office level QL-SSU-B, etc.

[0063] 302. If the frequency offset of the first signal is abnormal, the first device sends a first clock level signal. The first clock level signal indicates a change in the clock source quality of the first device. The quality level of the first clock level signal is lower than the clock source quality level of the second device.

[0064] In this embodiment, a first threshold is set as a threshold for determining whether a signal is abnormal. When the frequency offset jitter of the synchronization signal is greater than the first threshold, the synchronization signal is considered abnormal. For example, if the frequency offset jitter value of the synchronization signal exceeds a certain threshold (e.g., 3ppm, 1ppm) within a certain time period (e.g., within 1 second), the frequency offset jitter can be considered to exceed the first threshold. The first threshold can be the aforementioned 3ppm or 1ppm (corresponding to a time window of 1 second), or it can be a threshold corresponding to other time windows. This application does not limit this.

[0065] In the event of a failure in the second device NE1 or a failure in the communication link between the second device NE1 and the first device NE2, the synchronization signal (first signal) received by NE2 from NE1 will be abnormal, causing the frequency offset jitter of the first signal to exceed the aforementioned first threshold.

[0066] After the first device NE2 confirms that the upstream synchronization signal (first signal) is abnormal, it actively degrades the clock quality level of the signal sent to the downstream device. For example Figure 4 In this process, the first device NE2 sends a first clock level signal to NE4, indicating that the clock source quality of the first device NE2 is reduced, specifically lower than the clock source quality of the second device NE1. For example, the quality level of the first clock level signal can be the device clock level QL-SEC in Table 1, meaning that the clock source of the first device NE2 is NE2 itself.

[0067] In this embodiment, the first clock level signal is the message content carried on the physical signal sent by the first device, specifically the message content carried within the message overhead area. The first clock level signal is used to indicate the quality of the synchronization signal upstream of the first device and is the basis for devices connected to the first device to select a clock synchronization source.

[0068] The NE4 network element downstream of the first device NE2 can receive synchronization signals from its peers or superior devices. For example... Figure 4 As shown, the upstream or peer network elements of NE4 include NE2 (the first device) and NE3 (…). Figure 4 In the middle, the same row indicates the same level, and the network element located above the node is the superior network element of that node.

[0069] The clock source for NE3 is NE1, and the clock source for NE1 is the first-level clock on the left. Therefore, the clock source quality level of both NE1 and NE3 is the reference master clock level QL-PRC, that is, the clock source quality is the reference master clock (first-level clock) in Table 1.

[0070] The synchronization signal from NE2 (the first device) is the aforementioned first clock level signal. Since NE2 (the first device) has switched its clock source to itself, the clock source quality level of the first device NE2 is the device clock QL-SEC in Table 1.

[0071] NE4 uses the SSM source selection algorithm to compare the clock source quality levels of NE2 (the first device) and NE3. If it determines that the clock source quality level of NE3 is better than that of NE2 (the first device), NE4 will switch to tracking NE3 to achieve fault isolation of NE1.

[0072] In this embodiment, when the first device detects an abnormal frequency offset in the signal (first signal) between itself and the clock source, it considers the communication link between the first device and the clock source (second device) to be abnormal and thus sends a first clock level signal. This abnormality can be considered to have originated from the second device. Since the clock source quality level of the first clock level signal is lower than that of the clock source (second device) selected by the first device, downstream devices connected to the first device, upon receiving the first clock level signal, can determine that the clock source quality of the first device has deteriorated and thus reselect a clock source, achieving clock source switching for downstream devices of the first device. This prevents the abnormality at the second device from propagating downstream from the first device, reducing the impact of the abnormality at the second device on the synchronization network.

[0073] 303. If the frequency offset of the first signal is abnormal, the first device will send an alarm message indicating that the communication link between the second device and the first device is faulty.

[0074] Optionally, the first device can also communicate with network management equipment (such as a network management system, network element management system, routing management system, etc.). Upon determining that the frequency offset of the first signal from the second device NE1 is abnormal, it determines that the communication link between the first device NE2 and the second device NE1 is faulty, and thus sends an alarm message to the network management equipment. This alarm message indicates a communication link failure between the second device and the first device.

[0075] Optionally, the first device may also send alarm information to the display interface of the first device to convey the alarm information to the user through the display interface; this application does not limit this.

[0076] In this embodiment, when the first device detects an abnormal frequency offset in the signal (first signal) between itself and the clock source, it considers the communication link between the first device and the clock source (second device) to be abnormal and sends an alarm message. Based on this alarm message, the location of the abnormality can be quickly located (i.e., upstream of the first device, specifically the second device upstream of the first device, or the communication link between the first device and the second device), thereby accelerating the fault resolution process.

[0077] In this embodiment, the abnormal frequency offset of the first signal can be categorized into two types of communication failures between the first and second devices. One type is the frequency offset jitter scenario, where communication between the first and second devices is still possible; the other type is the large frequency offset scenario, where communication between the first and second devices is impossible. The clock synchronization methods for each of these different scenarios will be described below.

[0078] 1. In the frequency offset jitter scenario, the clock source of the first device is degraded to the first device itself.

[0079] like Figure 5 As shown, in the case of frequency offset jitter, the clock synchronization method provided in this application embodiment includes:

[0080] 501. The first device receives a first signal from the second device, whereby the second device is the clock source selected by the first device.

[0081] See step 501. Figure 2 Step 201 of the illustrated embodiment will not be repeated here.

[0082] 502. If the frequency offset jitter of the first signal is greater than the first threshold, the first device sends a first clock level signal to the device other than the second device. The quality level of the first clock level signal is the device clock level QL-SEC.

[0083] In this embodiment, the maximum frequency offset jitter threshold that the first device can tolerate is defined as the first threshold. When the frequency offset jitter of the first signal exceeds the first threshold, clock synchronization between the second device and the first device becomes unreliable, and clock synchronization is lost.

[0084] For example, if the frequency offset jitter value of the synchronization signal exceeds a certain threshold (e.g., 3ppm, 1ppm) within a certain time period (e.g., within 1 second), it can be considered that the frequency offset jitter exceeds the first threshold. The first threshold can be the aforementioned 3ppm or 1ppm (corresponding to a time window of 1 second), or it can be the threshold corresponding to other time windows. This application does not limit this.

[0085] Or with Figure 4For example, when the frequency offset jitter of the first signal is greater than the first threshold, the first device NE2 can continue to communicate with the second device NE1. However, due to a communication link failure between the first device NE2 and the second device NE1 (the frequency offset jitter of the first signal is greater than the first threshold), the quality level of the synchronization signal provided by the first device NE2 to the downstream device is lower than the quality level of the synchronization source of the second device NE1. Therefore, the first device NE2 can adjust the synchronization source to itself.

[0086] Therefore, the quality level of the first clock level signal transmitted by the first device is the device clock level QL-SEC. The first clock level signal can be used to instruct the clock source of the first device NE2 to switch to the first device NE2 itself.

[0087] 503. The downstream device of the first device adjusts the clock source level of the first device to QL-SEC according to the first clock level signal.

[0088] The downstream device of the first device NE2 includes NE4. If the clock source quality level of NE2 changes, NE4 must also adjust the clock source quality level of NE2 to QL-SEC accordingly.

[0089] 504. The downstream devices of the first device select a new clock source.

[0090] For NE4, the upstream or peer devices include NE2 and NE3. NE4 can select a new clock source based on the adjusted clock source level of the first device NE2 and the clock source level of NE3. For example... Figure 4 In the right figure, NE4 selects NE3, which has a higher clock source level, as its clock source.

[0091] In this embodiment, when the frequency offset jitter of the first signal exceeds the maximum tolerable threshold range of the first device, the first device can continue to communicate with the second device. However, the clock source quality level of the synchronization signal provided by the first device downstream is lower than that of the second device. In this case, the first device switches the clock source to itself, thereby avoiding using the clock source of the abnormal second device as a backup clock source for downstream devices. This prevents the anomaly at the second device from spreading downstream from the first device, reducing the impact of the anomaly at the second device on the synchronization network.

[0092] Second, in scenarios with large frequency offset, the clock source of the first device is degraded to the first device itself.

[0093] like Figure 6 As shown, in scenarios with large frequency offset, the clock synchronization method provided in this application embodiment includes:

[0094] 601. The first device receives a first signal from the second device, whereby the second device is the clock source selected by the first device.

[0095] See step 601. Figure 2 Step 201 of the illustrated embodiment will not be repeated here.

[0096] 602. If the frequency deviation of the first signal is greater than the second threshold, or if the first signal is lost, the first device will invalidate the current synchronization source, the second device.

[0097] If the frequency deviation of the first signal is greater than the second threshold, the second device and the first device cannot communicate. Alternatively, if the first signal is lost, since the first signal is the synchronization signal between the second and first devices, the loss of the first signal indicates that the first device cannot receive the synchronization signal from the second device, and therefore, the second device and the first device also cannot communicate. For example, the second threshold can be 7.5ppm, 9.2ppm, etc., and can be adjusted based on the tolerance capabilities of the OTN or SDH equipment; this application does not limit this adjustment.

[0098] by Figure 7 For example, the first device is NE2, and the second device is NE1. When the frequency deviation of the first signal is greater than the second threshold, or when the first signal is lost, the first device NE2 cannot continue to communicate with the second device NE1. Therefore, the first device NE2 invalidates the currently selected synchronization source NE1. That is, it adjusts the clock source quality of the second device NE1 to make the synchronization source unavailable.

[0099] Specifically, the first device NE2 includes a transmit port TX and a receive port RX. The current synchronization source selected by the first device NE2 is the second device NE1. Therefore, the receive port RX of the first device NE2, which connects to the second device NE1, is used to receive information from NE1. After determining that the second device and the first device cannot communicate, the first device NE2 can invalidate the receive port RX connecting to the second device NE1. This is equivalent to locally reducing the quality level of the (faulty) NE1 to DNU (unable to serve as a synchronization source) on NE2, thus facilitating NE2's switching of synchronization sources.

[0100] Furthermore, the first device NE2 can also report the alarm message SYN_BAD to the network management device, indicating a communication link failure between the second device NE1 and the first device NE2.

[0101] 603. The first device sends a first clock level signal to a device other than the second device. The quality level of the first clock level signal is the device clock level QL-SEC.

[0102] like Figure 7As shown, the first device NE2's superior or peer device only includes NE1, and NE1 and NE2 cannot communicate with each other. Therefore, the highest clock source that NE2 can access is NE2 itself. Thus, the first device NE2 adjusts its synchronization source to itself.

[0103] Optionally, if the upstream or peer devices of NE2 include not only NE1, but the synchronization source quality level of all upstream or peer devices of NE2 is not higher than that of the first device NE2, then the first device NE2 can adjust the synchronization source to itself.

[0104] Therefore, the quality level of the first clock level signal transmitted by the first device is the device clock level QL-SEC. The first clock level signal can be used to instruct the clock source of the first device NE2 to switch to the first device NE2 itself.

[0105] 604. The downstream device of the first device adjusts the clock source level of the first device to QL-SEC according to the first clock level signal.

[0106] 605. The downstream devices of the first device select a new clock source.

[0107] See steps 604-605. Figure 5 Steps 503-504 of the illustrated embodiment will not be repeated here.

[0108] In this embodiment, when the frequency offset of the first signal exceeds the maximum tolerable frequency offset threshold of the first device or the first signal is lost, the first device cannot continue communicating with the second device, and the clock source quality level of the synchronization signal provided by the first device downstream is lower than that of the second device. In this case, the first device switches its clock source back to itself, thereby avoiding using the clock source of the abnormal second device as a backup clock source for downstream devices. This prevents the anomaly at the second device from spreading downstream from the first device, reducing the impact of the anomaly at the second device on the synchronization network.

[0109] 3. In scenarios with large frequency deviation, the clock source of the first device is adjusted to the clock source that the first device has reselected.

[0110] like Figure 8 As shown, in scenarios with large frequency offset, the clock synchronization method provided in this application embodiment includes:

[0111] 801. The first device receives a first signal from the second device, whereby the second device is the clock source selected by the first device.

[0112] 802. If the frequency deviation of the first signal is greater than the second threshold, or if the first signal is lost, the first device will invalidate the current synchronization source, the second device.

[0113] See steps 801-802. Figure 6 Steps 601-602 of the illustrated embodiment will not be repeated here.

[0114] 803. The first device determines the third device as the new synchronization source and sends a first clock level signal to the third device. The quality level of the first clock level signal is QL-DNU, which should not be used as a synchronization source.

[0115] by Figure 9 For example, the first device is NE2, and the second device is NE1. In step 802, the first device NE2 adjusts the clock source quality of the second device to a state where the synchronization source is unavailable. Then, the first device NE2 can select a synchronization clock source based on the adjusted clock source quality of the second device. At this time, the peer or superior devices of NE2 include NE1 and NE0, and the clock source quality level of NE0 (the third device) is the reference master clock QL-PRC. Therefore, the first device determines the third device NE0 as the new clock source for the first device NE2. The clock source quality level of the new clock source of the first device NE2 (the third device NE0) is higher than the clock source quality level of the first device NE2 itself.

[0116] Optionally, the synchronization source quality level of the third device NE0 can also be either the transfer office level QL-SSU-A or the local office level QL-SSU-B. As long as the synchronization source quality level of the third device NE0 is higher than that of the first device NE2, the first device NE2 can adjust its synchronization source to the third device NE0.

[0117] Therefore, the first device NE2 can send a first clock level signal to the third device NE0. The quality level of the first clock level signal is QL-DNU, which should not be used as a synchronization source, and is used to indicate that the clock source of the first device is switched to the third device.

[0118] 804. The first device sends a second clock level signal to a device other than the third device. The second clock level signal indicates the clock source quality level of the third device.

[0119] After selecting the third device NE0 as the clock source for the first device NE2, the clock source quality level of the first device NE2 becomes the clock source quality level of the third device NE0. Therefore, the first device NE2 can send a second clock level signal to devices other than the third device. The second clock level signal indicates the current clock source quality level of the first device NE2 (which is equal to the clock source quality level of the third device).

[0120] For example, Figure 9If the clock source quality level of NE0 is the reference master clock QL-PRC, then the quality level of the second clock level signal sent by the first device NE2 to the device other than the third device is QL-PRC, indicating that the current clock source quality level of the first device NE2 is QL-PRC.

[0121] 805. The downstream devices of the first device select a new clock source based on the second clock level signal.

[0122] The downstream device of the first device NE2 includes NE4. NE4 can determine the latest clock source quality level of NE2 as QL-PRC based on the second clock level signal in step 804.

[0123] For NE4, the upstream or peer devices include NE2 and NE3. NE4 can select a new clock source based on the latest clock source level of the first device NE2 and the clock source level of NE3. For example... Figure 4 In the right figure, NE4 selects NE2, which has a higher clock source level, as its clock source.

[0124] In this embodiment, when the frequency offset of the first signal exceeds the maximum tolerable frequency offset threshold of the first device or the first signal is lost, the first device cannot continue communicating with the second device. Furthermore, the clock source quality level of the third device connected to the first device is higher than that of the QL-DNU. In this case, the first device switches its clock source to the third device, thereby avoiding using the abnormal clock source of the second device as a backup clock source for downstream devices. This prevents the anomaly at the second device from propagating downstream from the first device, reducing the impact of the anomaly at the second device on the synchronization network.

[0125] Please see Figure 10 , Figure 10 This is a schematic diagram of the structure of an optical communication device provided in an embodiment of this application. The optical communication device can be as described above. Figures 3 to 9 The first device in the illustrated embodiment. (As shown) Figure 10 As shown, the optical communication device 1000 includes a receiving module 1001 and a transmitting module 1002.

[0126] The receiving module 1001 is used to: receive a first signal from a second device, wherein the second device is a clock source selected by the first device;

[0127] The transmitting module 1002 is configured to: if the frequency offset of the first signal is abnormal, transmit a first clock level signal, wherein the first clock level signal indicates a change in the clock source quality of the first device, and the quality level of the first clock level signal is lower than the clock source quality level of the second device.

[0128] The receiving module 1001 is used to perform Figure 3Step 301 of the illustrated embodiment Figure 5 Step 501 of the illustrated embodiment Figure 6 Step 601 of the illustrated embodiment Figure 8 Step 801 of the illustrated embodiment; the sending module 1002 is used to perform Figure 3 Steps 302 and 303 of the illustrated embodiment Figure 5 Step 502 of the illustrated embodiment Figure 6 Step 603 of the illustrated embodiment Figure 8 Steps 803 and 804 of the illustrated embodiment.

[0129] Optical communication equipment 1000 is used to achieve the aforementioned Figures 3 to 9 The clock synchronization method shown.

[0130] In an optional implementation, the sending module 1002 is further configured to: if the frequency offset of the first signal is abnormal, send an alarm message indicating a communication link failure between the second device and the first device.

[0131] In one optional implementation, the clock source quality level of the second device is higher than the device clock level QL-SEC; the transmitting module 1002 is specifically used to: if the frequency offset jitter is greater than a first threshold, send the first clock level signal to a device other than the second device, the first threshold being the maximum frequency offset jitter threshold that the first device can tolerate, the quality level of the first clock level signal being the QL-SEC, and the first clock level signal indicating that the clock source of the first device is switched to the first device.

[0132] In one optional implementation, the transmitting module 1002 is specifically configured to: if the frequency deviation of the first signal is greater than a second threshold, or if the first signal is lost, then transmit the first clock level signal to a device outside the second device, wherein the second threshold is the maximum frequency deviation threshold that the first device can tolerate, the quality level of the first clock level signal is the device clock level QL-SEC, and the first clock level signal indicates that the clock source of the first device is switched to the first device.

[0133] In one alternative implementation, the clock source quality level of the second device is a reference clock level QL-PRC, a transfer station level QL-SSU-A, or a local station level QL-SSU-B.

[0134] In an optional implementation, the transmitting module 1002 is specifically configured to: if the frequency deviation of the first signal is greater than a second threshold, or if the first signal is lost, then transmit the first clock level signal to a third device and transmit a second clock level signal to a device other than the third device. The second threshold is the maximum frequency deviation threshold that the first device can tolerate. The quality level of the first clock level signal is QL-DNU, which should not be used as a synchronization source. The first clock level signal indicates that the clock source of the first device is switched to the third device. The second clock level signal indicates the clock source quality level of the third device. The clock source quality level of the third device is higher than the clock source quality level of the first device.

[0135] In one alternative implementation, the second clock level signal indicates that the clock source quality level of the third device is a reference master clock level QL-PRC, a transfer station level QL-SSU-A, or a local station level QL-SSU-B.

[0136] In an optional implementation, the receiving module 1001 is further configured to: switch the clock source of the first device to the third device.

[0137] In one optional implementation, the receiving module 1001 is specifically configured to: adjust the clock source quality of the second device to a state where the synchronization source is unavailable, perform synchronization clock selection based on the adjusted clock source quality of the second device, and determine the third device as the new clock source for the first device.

[0138] In one alternative implementation, the first device and the second device are routers, microwave devices, or base station devices, and the first device and the second device are connected via optical fiber.

[0139] Figure 11 This is a schematic diagram of the structure of an optical communication device provided in an embodiment of this application. The optical communication device 1100 may include one or more CPUs 1101 and memory 1102, and the memory 1102 stores one or more application programs or data.

[0140] The memory 1102 can be volatile or persistent storage. The program stored in the memory 1102 can include one or more modules, each module including a series of instruction operations on the port allocation device 1100. Furthermore, the central processing unit 1101 can be configured to communicate with the memory 1102 and execute the series of instruction operations in the memory 1102 on the optical communication device 1100.

[0141] The optical communication device 1100 may also include one or more communication interfaces 1103, and / or one or more operating systems, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, etc.

[0142] The optical communication device 1100 can perform the aforementioned functions. Figures 3 to 9 The specific operations performed by the first device in the illustrated embodiment will not be described in detail here.

[0143] This application also provides a computer program product that, when run on a computer, causes the computer to perform the aforementioned actions. Figures 3 to 9 The steps performed by the first device in the illustrated embodiment.

[0144] This application embodiment also provides a computer-readable storage medium storing a program for performing signal processing, which, when run on a computer, causes the computer to perform the aforementioned actions. Figures 3 to 9 The steps performed by the first device in the illustrated embodiment.

[0145] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0146] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection between apparatuses or units through some interfaces, and may be electrical, mechanical, or other forms.

[0147] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0148] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0149] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

Claims

1. A clock synchronization method, characterized in that, Applied to a first device, the method includes: Receive a first signal from a second device, the second device being a clock source selected by the first device; If the frequency offset of the first signal is abnormal, a first clock level signal is sent. The first clock level signal indicates a change in the clock source quality of the first device. The quality level of the first clock level signal is lower than the clock source quality level of the second device.

2. The method according to claim 1, characterized in that, After receiving the first signal from the second device, the method further includes: If the frequency offset of the first signal is abnormal, an alarm message is sent, indicating a communication link failure between the second device and the first device.

3. The method according to claim 1 or 2, characterized in that, The clock source quality level of the second device is higher than the device clock quality level QL-SEC; If the frequency offset of the first signal is abnormal, then sending a first clock level signal includes: If the frequency offset jitter is greater than the first threshold, the first clock level signal is sent to a device other than the second device. The first threshold is the maximum frequency offset jitter threshold that the first device can tolerate. The quality level of the first clock level signal is QL-SEC. The first clock level signal indicates that the clock source of the first device is switched to the first device.

4. The method according to claim 1 or 2, characterized in that, If the frequency offset of the first signal is abnormal, then sending a first clock level signal includes: If the frequency deviation of the first signal is greater than the second threshold, or if the first signal is lost, the first clock level signal is sent to a device other than the second device. The second threshold is the maximum frequency deviation threshold that the first device can tolerate. The quality level of the first clock level signal is the device clock level QL-SEC. The first clock level signal indicates that the clock source of the first device is switched to the first device.

5. The method according to any one of claims 1 to 4, characterized in that, The clock source quality level of the second device is the reference clock level QL-PRC, the transfer station level QL-SSU-A, or the local station level QL-SSU-B.

6. The method according to claim 1 or 2, characterized in that, If the frequency offset of the first signal is abnormal, then sending a second clock level signal includes: If the frequency deviation of the first signal is greater than the second threshold, or if the first signal is lost, the first clock level signal is sent to the third device, and the second clock level signal is sent to devices other than the third device. The second threshold is the maximum frequency deviation threshold that the first device can tolerate. The quality level of the first clock level signal is QL-DNU, which should not be used as a synchronization source. The first clock level signal indicates that the clock source of the first device is switched to the third device. The second clock level signal indicates the clock source quality level of the third device. The clock source quality level of the third device is higher than that of the first device.

7. The method according to claim 6, characterized in that, The second clock level signal indicates that the clock source quality level of the third device is the reference master clock level QL-PRC, the transfer station level QL-SSU-A, or the local station level QL-SSU-B.

8. The method according to claim 6 or 7, characterized in that, Before sending the second clock level signal to a device other than the third device, the method further includes: Switch the clock source of the first device to the third device.

9. The method according to claim 8, characterized in that, Switching the clock source of the first device to the third device includes: The clock source quality level of the second device is adjusted to "synchronization source unavailable". Based on the adjusted clock source quality level of the second device, a synchronization clock source is selected, and the third device is determined as the new clock source for the first device.

10. The method according to any one of claims 1 to 9, characterized in that, The first device and the second device are routers, microwave devices or base station devices, and the first device and the second device are connected by optical fiber.

11. An optical communication device, characterized in that, It includes one or more modules for implementing the clock synchronization method according to any one of claims 1 to 10.

12. An optical communication device, characterized in that, It includes a processor and a memory, wherein the processor is coupled to the memory; The memory is used to store programs; The processor is configured to execute a program in the memory, causing the port allocation device to perform the method as described in any one of claims 1 to 10.

13. A computer program product, characterized in that, When it is run on a computer, it causes the computer to perform the method as described in any one of claims 1 to 10.

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