A communication method and apparatus

Abstract

A communication method and device are used to implement polarization coding of a longer code length based on a shorter reliability sequence and guarantee better communication performance. The method comprises: a first device obtaining an information bit sequence with a length of K; the first device determining a first reliability sequence number according to a first sequence with a length of N1, a code length N0 and K, the sequence number of N1 bit positions in the first sequence being arranged according to the reliability of the bit positions, and N1 being less than N0; the first device determining an information bit position set according to a second sequence with a length of N1 and the first reliability sequence number, the second sequence including N1 reliability sequence numbers, the reliability sequence numbers in the second sequence being arranged according to the sequence numbers of the bit positions, and the information bit position set including K information bit position sequence numbers; the first device performing polarization coding on the information bit sequence according to the information bit position set, to obtain a polarization coded bit sequence with a length of N0; and the first device outputting the polarization coded bit sequence.

Description

Technical Field

[0001] This application relates to the field of mobile communication technology, and in particular to a communication method and apparatus. Background Technology

[0002] Polar codes are the first coding scheme that can be rigorously proven to "achieve" the Shannon channel capacity. They have the advantages of good decoding performance and low complexity. They have been selected by the 3rd Generation Partnership Project (3GPP) as the control channel coding scheme for enhanced mobile broadband (eMBB) scenarios.

[0003] Currently, the maximum length of the reliability sequence in the New Radio (NR) standard is 1024. How to achieve polar coding with a longer code length is a technical problem that urgently needs to be solved. Summary of the Invention

[0004] This application provides a communication method and apparatus for implementing long code length polar coding based on a shorter reliability sequence, while ensuring better communication performance.

[0005] In a first aspect, embodiments of this application provide an encoding method, which can be executed by a first device. Unless otherwise specified, the "first device" in this application can refer to the first device itself (e.g., a terminal, terminal device, or network device), a component used in the first device (e.g., a functional module, communication module, processor, circuit, chip, or chip system), or a logic module or software capable of implementing all or part of the functions of the first device. The component used in the first device can be within the first device or independent of it. The first device can be a transmitting device, and correspondingly, the receiving device is a second device. Taking the first device as the executing entity as an example, the method includes: the first device acquiring an information bit sequence of length K, where K is a positive integer; the first device determining a first reliability index based on a first sequence of length N1, a code length N0, and K, wherein the first sequence includes the indexes of N1 bits, the indexes of the bits in the first sequence are sorted according to the reliability of the bits, N1 is a positive integer, N0 is a positive integer, and N1 is less than N0; the first device determining an information bit position set based on a second sequence of length N1 and the first reliability index, wherein the second sequence includes N1 reliability indexes, the reliability indexes in the second sequence are arranged according to the index of the bits, and the information bit position set includes the indexes of K information bits; the first device performing polar coding on the information bit sequence based on the information bit position set to obtain a polar-coded bit sequence of length N0; and the first device outputting the polar-coded bit sequence.

[0006] Based on the method described in the first aspect, the first device can implement polar coding of code length N0 based on a first sequence of length N1, where N1 < N0. Therefore, it can implement polar coding of a longer code length based on a shorter reliability sequence and can guarantee good communication performance. The first sequence can be a reliability sequence of length N1, i.e., a Q-sequence. It is evident that based on this implementation, polar coding can be performed based on a reliability sequence of length N1 without using a reliability sequence of length N0. Therefore, only the reliability sequence of length N1 needs to be stored, and the reliability sequence of length N0 does not need to be stored, which can reduce storage overhead. Furthermore, the second sequence can be a Z-sequence of length N1. It is evident that based on this implementation, polar coding can be performed based on a Z-sequence of length N1 without using a Z-sequence of length N0. Therefore, only the Z-sequence of length N1 needs to be stored, and the Z-sequence of length N0 does not need to be stored, which can reduce storage overhead.

[0007] Secondly, embodiments of this application provide a decoding method, which can be executed by a second device. Unless otherwise specified, the "second device" in this application can refer to the second device itself (e.g., a terminal, terminal equipment, or network device), a component within the second device (e.g., a functional module, communication module, processor, circuit, chip, or chip system), or a logic module or software capable of implementing all or part of the functions of the second device. The components used in the second device can be within the second device or independent of it. The second device can be a receiving device. Taking the execution subject as an example, the method includes:

[0008] The second device acquires information to be decoded, which corresponds to an encoded bit sequence of length N0, where N0 is a positive integer. The second device determines a first reliability index based on a first sequence of length N1, the N0, and the information bit length K. The first sequence includes the indices of N1 bits, which are ordered according to their reliability. N1 and N0 are both positive integers, and N1 is less than N0. The second device determines an information bit position set based on a second sequence of length N1 and the first reliability index. The second sequence includes N1 reliability values, which are ordered according to their bit indices. The information bit position set includes the indices of K information bits. The second device decodes the information to be decoded based on the information bit position set.

[0009] In one possible implementation of the first and / or second aspect, "determining the information bit position set based on a second sequence of length N1 and the first reliability index" can also be replaced by "determining the information bit position set based on the first sequence and the first reliability index". The second sequence can be determined based on the first sequence.

[0010] In one possible implementation of the first aspect and / or the second aspect, the first reliability index is Z. i i = 0, 1, ..., m-1 Represents rounding down; the K information bits include the Z with the highest reliability in the i-th sequence. i The i-th sequence is obtained by adding i*N1 to each index in the first sequence and then removing the index from the pre-frozen bit position set. i It can be 0 or a positive integer.

[0011] Based on this implementation, information bits can be determined flexibly and efficiently according to the first reliability index and the i-th sequence related to the first sequence, thus improving the efficiency of information bit determination. Optionally, Z, the sequence with the highest reliability in the i-th sequence...i One bit does not belong to the set of pre-frozen bit positions.

[0012] Alternatively, if the reliability indices in the second sequence are sorted in descending order of reliability, then the K information bits, including those with reliability indices less than or equal to Z in the i-th sequence... i The bits; or, if the reliability indices in the second sequence are sorted in ascending order of reliability, the K information bits include those whose reliability indices in the i-th sequence are greater than or equal to Z. i The bits. Wherein, the i-th sequence is the sequence obtained by adding i*N1 to the index of the bit corresponding to each reliability index in the second sequence, and then removing the index from the pre-frozen bit position set. Z i It can be 0 or a positive integer.

[0013] Based on this implementation, information bits can be determined flexibly and efficiently according to the first reliability index and the i-th sequence related to the second sequence, thus improving the efficiency of information bit determination. Optionally, the reliability index in the i-th sequence is less than or equal to Z. i One bit does not belong to the set of pre-frozen bit positions.

[0014] In one possible implementation of the first aspect and / or the second aspect, i = 0, 1; the first reliability index includes the number of indexes less than or equal to N1 / 2 among the K / 2 indexes with the highest reliability in the first sequence, 2*Z0 and / or the number of indexes greater than N1 / 2 among the K / 2 indexes with the highest reliability in the first sequence, 2*Z1.

[0015] Based on this implementation method, the information bit sequence can be efficiently determined according to Z0 and Z1.

[0016] In one possible implementation of the first aspect and / or the second aspect, i = 0, 1, and N1 and N0 satisfy:

[0017] N1 = N0 / 2, the first reliability index includes Z0 and Z1, and the determination of the first reliability index of the information bit position based on the first sequence of length N1, code length N0, and K includes:

[0018] Let id = N1-1, Z0 = 0, and Z1 = 0;

[0019] Perform the following steps until the sum of Z0 and Z1 equals K:

[0020] Read the id-th sequence number from the first sequence to obtain the first sequence number;

[0021] If the first sequence number is less than or equal to N1 / 2, let Z0 = Z0 + 2;

[0022] If the second sequence number is greater than N1 / 2, let Z1 = Z1 + 2;

[0023] exist In this case, let id = id - 1;

[0024] exist If K is odd, read the (id-1)th index from the first sequence to obtain the second index. If the second index is less than or equal to N1, let Z0 = Z0 + 1. If the second index is greater than N1, let Z1 = Z1 + 1.

[0025] Based on this implementation, when N1 = N0 / 2, the first device and / or the second device can execute the above process. They can read the first sequence number in the first sequence of length N1 according to the reliability from high to low, and determine the information bits when the mother code length is N0 based on the first sequence number. Since the process of allocating information bits based on the reliability sequence of length N1 is similar to that based on the reliability sequence of length N0, the above process can reasonably determine the information bits when the mother code length is N0 based on the first sequence of length N1 according to this similarity, thus ensuring communication performance when encoding with length N0 based on the information bits.

[0026] In one possible implementation of the first aspect and / or the second aspect, the K / 2 most reliable indices in the first sequence do not include indices in the pre-frozen bit position set, wherein the pre-frozen bit position set includes indices of pre-frozen bits, which are determined based on the length E of the polar-coded bit sequence after rate matching, where E is a positive integer.

[0027] Based on this implementation method, the set of information bit positions can be accurately determined according to the pre-frozen bit position set, improving the accuracy of the construction and ensuring communication performance.

[0028] In one possible implementation of the first aspect and / or the second aspect, the K information bits include k bits in the i-th sequence. i N bits, where i = 0, 1; N1 = N0 / 2, the determination of the first reliability index based on the first sequence of length N1, code length N0, and K includes:

[0029] Let id = N1-1, idx = id, M = 0, Z0 = 0, and Z1 = 0, where M is the number of information bit positions in the information bit position set;

[0030] When the rate matching mode is punched, perform the following steps until M equals K:

[0031] Read the id-th sequence number from the first sequence to obtain the first sequence number;

[0032] If the first sequence number is less than or equal to T, read the idx-th sequence number from the first sequence to obtain the second sequence number. Let M = M + d0, where d0 = 0 if the second sequence number belongs to the pre-frozen bit position set, or d0 = 1 if the second sequence number does not belong to the pre-frozen bit position set; read the idx-1-th sequence number from the first sequence to obtain the third sequence number. Let M = M + d0', where d0' = 0 if the third sequence number belongs to the pre-frozen bit position set, or d0' = 1 if the third sequence number does not belong to the pre-frozen bit position set, where T is a positive integer; let idx = idx-2; or...

[0033] If the first sequence number is greater than T, let M = M + 2;

[0034] In the case where M < K, let id = id-1 and Z0 = Z0+2;

[0035] If M > K, and the third sequence number is less than or equal to T, then let Z0 = Z0-1; if the third sequence number is greater than T, then let Z1 = Z1-1.

[0036] or,

[0037] When the rate matching mode is shortened, perform the following steps until M equals K:

[0038] Read the id-th sequence number from the first sequence to obtain the first sequence number;

[0039] If the first sequence number is less than or equal to T, let M = M + 2;

[0040] If the first sequence number is greater than T, read the idx-th sequence number in the first sequence to obtain the fourth sequence number. Let M = M + d1. If the sum of the fourth sequence number and N1 belongs to the pre-frozen bit position set, d1 = 0; or if the sum of the fourth sequence number and N1 does not belong to the pre-frozen bit position set, d1 = 1. Read the idx-1-th sequence number in the first sequence to obtain the fifth sequence number. Let M = M + d1'. If the sum of the fifth sequence number and N1 belongs to the pre-frozen bit position set, d1' = 0; or if the sum of the fifth sequence number and N1 does not belong to the pre-frozen bit position set, d1' = 1. Let idx = idx-2.

[0041] In the case where M < K, let id = id-1 and let Z1 = Z1 + 2x1;

[0042] If M > K, and the fifth sequence number is less than or equal to T, then let Z0 = Z0-1; if the fifth sequence number is greater than T, then let Z1 = Z1-1.

[0043] Based on this implementation, when N1 = N0 / 2, the first device and / or the second device can execute the above process, reading the first sequence number in the first sequence of length N1 according to the reliability from high to low, and determining the information bits when the mother code length is N0 based on the first sequence number. Since the process of allocating information bits based on the reliability sequence of length N1 is similar to the process of allocating information bits based on the reliability sequence of length N0, the above process can reasonably determine the information bits when the mother code length is N0 based on the first sequence of length N1 according to this similarity, so as to ensure the communication performance when encoding with length N0 based on information bits. Optionally, the above implementation conforms to the similarity between the process of allocating information bits based on the reliability sequence of length N1 and the process of allocating information bits based on the reliability sequence of length N0 when using natural order rate matching. Therefore, this implementation can be applied to the case of using natural order rate matching, and can guarantee the communication performance when communicating based on the above information bits when using natural order rate matching.

[0044] In one possible implementation of the first aspect and / or the second aspect, the K information bits include k bits in the i-th sequence. i 1 bit, where i = 0, 1;

[0045] N1 = N0 / 2, wherein determining the first reliability index based on the first sequence of length N1, the code length N0, and K includes:

[0046] Let id = N1-1, id0 = id, id1 = id, M = 0, Z0 = 0, and Z1 = 0, where M is the number of information bit positions in the information bit position set;

[0047] Perform the following steps until M equals K:

[0048] Read the id-th sequence number from the first sequence to obtain the first sequence number;

[0049] If the first sequence number is less than or equal to T (x0 = 1, x1 = 0), perform the following steps, where T is a positive integer:

[0050] Read the id0th index from the first sequence to obtain the second index, and let M = M + d0, where d0 = 0 if the second index belongs to the pre-frozen bit position set, or d0 = 1 if the second index does not belong to the pre-frozen bit position set; read the id0-1th index from the first sequence to obtain the third index, and let M = M + d0', where d0' = 0 if the third index belongs to the pre-frozen bit position set, or d0' = 1 if the third index does not belong to the pre-frozen bit position set;

[0051] In the case of M < K, let id = id-1, where Z0 = Z0+2 and id0 = id0-2;

[0052] When M > K, let Z0 = Z0-1;

[0053] or,

[0054] If the first index is greater than T (x0 = 0, x1 = 1), perform the following steps, where T is a positive integer:

[0055] Read the id1-th index from the first sequence to obtain the fourth index. Let M = M + d1. If the sum of the fourth index and N1 belongs to the pre-frozen bit position set, d1 = 0; or if the sum of the fourth index and N1 does not belong to the pre-frozen bit position set, d1 = 1. Read the (id1-1)-th index from the first sequence to obtain the fifth index. Let M = M + d1'. If the fifth index belongs to the pre-frozen bit position set, d1' = 0; or if the fifth index does not belong to the pre-frozen bit position set, d1' = 1.

[0056] In the case of M < K, let id = id-1, then Z1 = Z1+2, and id1 = id1-2;

[0057] If M > K, let Z1 = Z1-1.

[0058] Based on this implementation, when N1 = N0 / 2, the first device and / or the second device can execute the above process, reading the first sequence number in the first sequence of length N1 according to the reliability from high to low, and determining the information bits when the mother code length is N0 based on the first sequence number. Since the process of allocating information bits based on the reliability sequence of length N1 is similar to that based on the reliability sequence of length N0, the above process can reasonably determine the information bits when the mother code length is N0 based on the first sequence of length N1 according to this similarity, thus ensuring communication performance when encoding with length N0 based on the information bits. Optionally, the above implementation conforms to the similarity between the process of allocating information bits based on the reliability sequence of length N1 and the process of allocating information bits based on the reliability sequence of length N0 when using NR rate matching. Therefore, this implementation can be applied to the case of using NR rate matching, ensuring communication performance when communicating based on the above information bits under NR rate matching.

[0059] In one possible implementation of the first aspect and / or the second aspect, T is equal to N1 / 4.

[0060] Based on this implementation method, the value of T can be reasonably determined to improve the accuracy of information bit determination.

[0061] In one possible implementation of the first aspect and / or the second aspect, when E is less than or equal to N0 and K / E is less than or equal to the first threshold, the pre-frozen bit position set corresponds to the indices of the first (N0-E) bits of the first bit sequence; when E is less than or equal to N0 and K / E is greater than the first threshold, the pre-frozen bit position set corresponds to the indices of the last (N0-E) bits of the first bit sequence; wherein the first bit sequence is a bit sequence of length N0, wherein the indices in the bit sequence of length N0 are 0, 1, ..., N0-1, and the bit sequence of length N0 is sorted in ascending order of bit indices; or, the first bit sequence is a sequence obtained by interleaving the bit sequence of length N0 with sub-blocks.

[0062] Based on this implementation, the pre-frozen bit position set is determined according to the rate-matched code length E and code rate K / E, or in other words, the pre-frozen bit position set is determined according to the rate-matched code length E and K. Specifically, when E is less than or equal to N0 and K / E is less than or equal to a first threshold, the rate matching method is puncturing; when E is less than or equal to N0 and K / E is greater than the first threshold, the rate matching method is shortening. The first bit sequence can be a natural sequence of length N0, or a sequence obtained by interleaving a natural sequence of length N0 with sub-blocks.

[0063] In one possible implementation of the first aspect and / or the second aspect, the pre-frozen bit position set is determined based on N0 and a first bit sequence set, the first bit sequence set being determined based on N1; wherein, when E*N1 / N0 is less than or equal to N1 and K / E is less than or equal to a first threshold, the first bit sequence set corresponds to the first (N1-E*N1 / N0) bits of the second bit sequence; or, when E*N1 / N0 is less than or equal to N1 and K / E is greater than the first threshold, the first bit sequence set corresponds to the last (N1-E*N1 / N0) bits of the second bit sequence; wherein, the second bit sequence is a bit sequence of length N1, wherein the indices in the bit sequence of length N1 are 0, 1, ..., N1-1, and the bit sequence of length N1 is sorted in ascending order of bit indices; or, the second bit sequence is a sequence obtained by interleaving the bit sequence of length N1 with sub-blocks.

[0064] Based on this implementation, the set of pre-frozen bit positions is determined according to the first bit sequence number set corresponding to N1 and N0. The first bit sequence number set can be considered to include the pre-frozen bits determined based on the mother code length N1 and the code length E*N1 / N0 after rate matching. Therefore, based on this implementation, the set of pre-frozen bits corresponding to N0 can be determined according to the set of pre-frozen bits corresponding to N1, supporting the determination of pre-frozen bit positions for longer code lengths based on shorter reliability sequences. It is evident that based on this implementation, the pre-frozen bit positions can be determined based on a reliability sequence of length N1, without needing to determine them based on a reliability sequence of length N0. Therefore, only the reliability sequence of length N1 needs to be stored, and the reliability sequence of length N0 does not need to be stored, reducing storage overhead. The second bit sequence number can be a natural sequence of length N1, or a sequence obtained by interleaving a natural sequence of length N1 with sub-blocks.

[0065] In one possible implementation of the first aspect and / or the second aspect, determining the first reliability index based on the first sequence of length N1, the code length N0, and K includes: determining the first reliability index based on a first correspondence, wherein the first correspondence includes the correspondence between N1, N0, K, and the first reliability index.

[0066] Based on this implementation method, the first correspondence can also be predefined by standards, preconfigured by the network, or indicated by signaling, so that the first device and / or the second device can flexibly and efficiently determine the first reliability sequence number according to the first correspondence.

[0067] In one possible implementation of the first aspect and / or the second aspect, N1 = N0 / 2, and determining the information bit position set based on the second sequence of length N1 and the first reliability index includes: determining the index of the information bit in the second sequence whose reliability index is less than Z0; and determining the index of the information bit by the sum of the index of the second sequence whose reliability index is less than Z1 and N1.

[0068] Based on this implementation, the first device and / or the second device can flexibly and efficiently determine the set of information bit positions according to the second sequence number and the first reliability sequence number.

[0069] In one possible implementation of the first aspect and / or the second aspect, N1 is equal to N0 / 2. p p is a positive integer.

[0070] Based on this implementation, N0 is an integer power of 2 of N1. That is, when this condition is met, the method of this application is adopted to reduce the processing complexity.

[0071] Thirdly, a communication device is provided. The device can implement the methods described in any one of the first to second aspects and any possible implementation thereof. The device possesses the functions of the first or second device described above. The device is, for example, a terminal device, a functional module within a terminal device, or a network device or a functional module within a network device, etc.

[0072] In one optional implementation, the device may include modules corresponding one-to-one with the methods / operations / steps / actions described in any of the first to second aspects and any possible implementations thereof. These modules may be hardware circuits, software, or a combination of hardware circuits and software. In another optional implementation, the device includes a processing unit (sometimes also called a processing module) and a communication unit (sometimes also called a transceiver module, communication module, etc.). The transceiver unit is capable of both sending and receiving functions. When the transceiver unit performs the sending function, it may be called a sending unit (sometimes also called a sending module); when it performs the receiving function, it may be called a receiving unit (sometimes also called a receiving module). The sending unit and the receiving unit may be the same functional module, referred to as the transceiver unit, which performs both sending and receiving functions; or, the sending unit and the receiving unit may be different functional modules, with the transceiver unit being a collective term for these functional modules.

[0073] For example, when the apparatus is used to perform the method described in any one of the first to second aspects, the apparatus may include a communication unit and a processing unit.

[0074] Fourthly, embodiments of this application also provide a communication device, including a processor for executing a computer program (or computer-executable instructions) stored in a memory, which, when executed, causes the device to perform the method as described in any one of the first to second aspects and any possible implementation thereof.

[0075] In one possible implementation, the processor and memory are integrated together;

[0076] In another possible implementation, the memory is located outside the communication device.

[0077] The communication device also includes a communication interface for communicating with other devices, such as sending or receiving data and / or signals. Exemplarily, the communication interface may be a transceiver, circuit, bus, module, or other type of communication interface.

[0078] Fifthly, a computer-readable storage medium is provided for storing a computer program or instructions that, when executed, cause the methods described in any of the first to second aspects and any possible implementations thereof, and the methods shown in any possible implementations thereof, to be implemented.

[0079] A sixth aspect provides a computer program product containing instructions that, when run on a computer, enables the method described in any of the first to second aspects and any possible implementation thereof to be implemented.

[0080] In a seventh aspect, embodiments of this application also provide a communication device for performing the method described in any one of the first to second aspects and any possible implementation thereof.

[0081] Eighthly, a chip system is provided, comprising logic circuitry (or, as understood, a processor, which may include logic circuitry, etc.), and further comprising input / output interfaces. The input / output interfaces can be used to input messages or to output messages. The input / output interfaces can be the same interface, i.e., the same interface can implement both sending and receiving functions; or, the input / output interface includes an input interface and an output interface, the input interface being used to implement the receiving function, i.e., to receive messages; and the output interface being used to implement the sending function, i.e., to send messages. The logic circuitry can be used to perform operations other than the sending and receiving functions in the methods described in any of the first to second aspects and any possible implementations thereof; the logic circuitry can also be used to transmit messages to the input / output interfaces or to receive messages from other communication devices from the input / output interfaces. The chip system can be used to implement the methods described in any of the first to second aspects and any possible implementations thereof. The chip system can be composed of chips or can include chips and other discrete devices.

[0082] Optionally, the chip system may also include a memory, which can be used to store instructions, and the logic circuits can call the instructions stored in the memory to implement the corresponding functions.

[0083] Ninth aspect, a communication method is provided, which may include the method implemented by a first device as shown in the first aspect and any possible implementation thereof, and the method implemented by a second device as shown in the second aspect and any possible implementation thereof.

[0084] In a tenth aspect, a communication system is provided, which may include a first device and a second device. The first device may be used to implement the method shown in the first aspect and any possible implementation thereof, and the second device may be used to implement the method shown in the second aspect and any possible implementation thereof.

[0085] The technical effects brought about by the third to tenth aspects above can be found in the descriptions of the beneficial effects of the corresponding solutions in the first and second aspects above, and will not be repeated here. Attached Figure Description

[0086] Figure 1 This application provides a schematic diagram of the architecture of a wireless communication system.

[0087] Figure 2 A schematic diagram illustrating an encoding and decoding process provided for an embodiment of this application;

[0088] Figure 3(a) is a schematic diagram of a polarization coding provided in an embodiment of this application;

[0089] Figure 3(b) is a schematic diagram of a serial cancellation decoding method provided in an embodiment of this application;

[0090] Figure 3(c) is a schematic diagram of a serial cancellation list decoding method provided in an embodiment of this application;

[0091] Figure 4 and Figure 8 These are schematic flowcharts illustrating a communication method provided in an embodiment of this application;

[0092] Figure 5 , Figure 6 and Figure 7 These are schematic diagrams illustrating a method for determining information bits when N1 = 1024 and N1 = N0 / 2, as provided in an embodiment of this application.

[0093] Figure 9 and Figure 10 These are schematic diagrams of a communication device provided in the embodiments of this application. Detailed Implementation

[0094] In the embodiments of this application, words such as "exemplarily" and "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design scheme described as an "example" in this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of the term "example" is intended to present concepts in a concrete manner. In the embodiments of this application, "of," "relevant," and "corresponding" may sometimes be used interchangeably, and it should be noted that their intended meanings are consistent unless their distinction is emphasized.

[0095] The technical solutions of this application can be applied to various wireless communication systems, such as Universal Mobile Telecommunications System (UMTS), Wireless Local Area Network (WLAN), short-range wireless communication systems (such as sidelink, Wireless Fidelity (Wi-Fi), Bluetooth, etc.), wired networks, vehicle-to-everything (V2X) communication systems, device-to-device (D2D) communication systems, vehicle-to-everything (V2X) communication systems, 4th generation (4G) mobile communication systems (such as Long Term Evolution (LTE) systems), LTE Frequency Division Duplex (FDD) systems, LTE Time Division Duplex (TDD) systems, 5G mobile communication systems (such as NR systems), Future Communication Systems, or other similar communication systems, and are not limited thereto. The embodiments of this application use... Figure 1 The communication system shown is used as an example for description. When the technical solutions of the embodiments of this application are applied to other communication systems, the devices, components, modules, etc. in the embodiments can be replaced with corresponding devices, components, modules in other communication systems without limitation.

[0096] Figure 1 This is a schematic diagram of the architecture of the communication system used in the embodiments of this application. Figure 1 As shown, the communication system includes an access network 100. Optionally, the communication system may also include a core network 200 and an Internet 300. The access network 100 may include at least one network device, such as... Figure 1 110a and 110b may also include at least one terminal device, such as Figure 1 The series consists of 120a-120j. Specifically, 110a is a base station, 110b is a micro-station, 120a, 120e, 120f, and 120j are mobile phones, 120b is a car, 120c is a fuel dispenser, 120d is a home access point (HAP) deployed indoors or outdoors, 120g is a laptop, 120h is a printer, and 120i is a drone. The same terminal device or network device can provide different functions in different application scenarios. For example... Figure 1The mobile phones included are 120a, 120e, 120f, and 120j. Mobile phone 120a can access base station 110a, connect to car 120b, communicate directly with mobile phone 120e, and access HAP. Car 120b can access HAP and communicate directly with mobile phone 120a. Mobile phone 120f can connect to micro-station 110b, connect to laptop 120g, and connect to printer 120h. Mobile phone 120j can control drone 120i.

[0097] The communication system provided in this application may also include AI network elements for implementing some or all AI-related operations. AI network elements can also be referred to as AI nodes, AI devices, AI entities, AI modules, AI models, or AI units, etc. The AI ​​network elements may be built into the network elements of the communication system. For example, an AI network element may be an AI module built into: access network equipment, core network equipment, cloud server, or operation, administration, and maintenance (OAM) to implement AI-related functions. The OAM may act as the network management system for core network equipment and / or access network equipment. Alternatively, the AI ​​network element may also be an independently configured network element in the communication system. Optionally, the terminal or its built-in chip may also include AI entities for implementing AI-related functions.

[0098] (1) Network equipment

[0099] A network device is a network-side device with wireless transceiver capabilities. A network device can be a device in a radio access network (RAN) that provides wireless communication capabilities to terminal devices; this is called RAN equipment. The RAN can be an access network within the 3rd Generation Partnership Project (3GPP), such as 4G, 5G, or future networks. The RAN can also be an open RAN (O-RAN or ORAN), a cloud radio access network (CRAN), or a communication network combining two or more of these.

[0100] RAN equipment can also be a base station, an evolved NodeB (eNodeB), a transmission reception point (TRP), a next-generation NodeB (gNB) in a 5G mobile communication system, a base station in a future mobile communication system, or an access node in a WiFi system, etc.

[0101] RAN equipment can also be modules or units that perform some of the functions of a base station. For example, it can be a central unit (CU), a distributed unit (DU), or a radio unit (RU). The CU performs the functions of the radio resource control (RRC) and packet data convergence protocol (PDCP) of the base station, and can also perform the functions of the service data adaptation protocol (SDAP). The CU can be further divided into a CU control plane (CP) (i.e., CU-CP) and a CU user plane (UP) (i.e., CU-UP). The DU performs the functions of the radio link control (RLC) layer and medium access control (MAC) layer of the base station, and can also perform some or all of the physical layer functions. For specific descriptions of the above protocol layers, please refer to the relevant 3GPP technical specifications. The CU and DU can be set up separately, or they can be included in the same network element, such as in the baseband unit (BBU). The RU can be included in radio frequency equipment or radio frequency units, such as in a remote radio unit (RRU), an active antenna unit (AAU), or a remote radio head (RRH). In different systems, CU, DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an ORAN system, CU can also be called O-CU (open CU), DU can also be called O-DU, and RU can also be called O-RU. Any of the units among CU (or CU-CP, CU-UP), DU, and RU in this application can be implemented through software modules, hardware modules, or a combination of software and hardware modules. RAN equipment can be a macro base station (such as...) Figure 1 110a in the text), can also be a micro base station or an indoor station (such as... Figure 1 In 110b), it can also be a relay node or a donor node, etc. The embodiments of this application do not limit the specific technology or device form used in the network equipment.

[0102] In the embodiments of this application, the functions of the network device can be executed by modules (such as chips) within the network device, or by a control subsystem that includes the functions of the network device. This control subsystem, which includes the functions of the network device, can be a control center in the aforementioned application scenarios such as smart grids, industrial control, intelligent transportation, and smart cities.

[0103] (2) Terminal equipment

[0104] A terminal device is a user-side device with wireless transceiver capabilities. Terminal devices can also be called terminals, user equipment (UE), mobile stations, mobile terminals, etc. Terminal devices can be widely used in various scenarios, such as D2D communication, V2X communication, machine-type communication (MTC), the Internet of Things (IoT), virtual reality, augmented reality, industrial control, autonomous driving, telemedicine, smart grids, smart furniture, smart offices, smart wearables, intelligent transportation, and smart cities. Terminal devices can be mobile phones, tablets, computers with wireless transceiver capabilities, wearable devices, vehicle devices (such as vehicle units, in-vehicle modules, in-vehicle chips, onboard units (OBUs) or telematics boxes (T-BOXs)), drones, helicopters, airplanes, ships, robots, robotic arms, smart home devices, satellite terminals, Internet of Things (IoT) terminals, virtual reality (VR) devices, augmented reality (AR) devices, smart point-of-sale (POS) machines, customer-premises equipment (CPE), light user equipment (UE), reduced capability UE (REDCAP UE), etc. In the embodiments of this application, the device used to implement the functions of the terminal device can be the terminal device itself, or a device capable of supporting the terminal device in implementing that function, such as a chip system or a combination of devices or components capable of implementing the functions of the terminal device. This device can be installed in the terminal device. The embodiments of this application do not limit the specific technology or specific device form used in the terminal device.

[0105] In this embodiment of the application, the functions of the terminal device can also be performed by modules (such as chips or modems) in the terminal device, or by a device that includes the functions of the terminal device.

[0106] Network devices and terminal devices can be fixed in location or mobile. They can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; they can also be deployed on water; and they can also be deployed in the air on airplanes, balloons, and artificial satellites. The embodiments of this application do not limit the application scenarios of the network devices and terminal devices.

[0107] The roles of network devices and terminal devices can be relative, for example, Figure 1 The helicopter or drone 120i can be configured as a mobile network device. For terminal devices 120j that access the wireless access network 100 via 120i, terminal device 120i is a network device; however, for network device 110a, 120i is a terminal device, meaning that 110a and 120i communicate via a wireless air interface protocol. Of course, 110a and 120i can also communicate via a network device-to-network device interface protocol; in this case, 120i is also a network device relative to 110a. Therefore, both network devices and terminal devices can be collectively referred to as communication devices. Figure 1 110a and 110b can be referred to as communication devices with network equipment functions. Figure 1 The 120a-120j in the text can be referred to as communication devices with terminal equipment functions.

[0108] Network devices and terminal devices, network devices and network devices, and terminal devices can communicate through licensed spectrum, unlicensed spectrum, or both simultaneously, without limitation.

[0109] The network architecture and business scenarios described in this application are intended to more clearly illustrate the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0110] The following is an explanation of the relevant terms used in the embodiments of this application. Unless otherwise specified, these explanations are provided to support the meaning of the relevant terms and to make the embodiments of this application easier to understand, and should not be regarded as a strict limitation of the relevant terms within the scope of protection claimed by this application.

[0111] (1) Channel coding and channel decoding

[0112] Figure 2 This is a schematic diagram illustrating a processing flow between the information source and the information sink. For example... Figure 2As shown, the transmitting end (i.e., the source) obtains the bit sequence to be encoded (i.e., the information bit sequence) through source coding, and then performs channel coding on the bit sequence to obtain the encoded bit sequence. Correspondingly, after the receiving end (i.e., the sink) obtains the information to be decoded, it performs channel decoding on the information to be decoded to obtain the information bit sequence, and then performs source recovery on the information bit sequence to obtain useful information.

[0113] Since source coding does not consider interference resistance, if the bit sequence output from source coding is directly transmitted through the channel, noise interference in the channel will cause bit errors, reducing communication reliability. Therefore, channel coding, which encodes the bit sequence output from source coding again, can improve communication reliability. Channel decoding is the inverse process of channel coding.

[0114] There are various channel coding methods, such as polar coding or low-density parity-check (LDPC) coding. Polar codes were selected as the control channel coding method in the 5G standard. Polar codes are a coding scheme that can be rigorously proven to "achieve" the Shannon channel capacity, and have the advantages of good decoding performance and low complexity. LDPC codes were selected as the data channel coding method in the 5G standard. LDPC codes are linear block codes with a sparse parity-check matrix, which not only have good performance approaching the Shannon limit, but also have low decoding complexity and flexible structure.

[0115] (2) Modulation and demodulation

[0116] See Figure 2 As shown, the transmitting end can also map the encoded bit sequence to the modulation symbol sequence, and then transmit the modulation symbol sequence; correspondingly, the receiving end can receive the modulation symbol sequence and obtain the information to be decoded by demodulation.

[0117] Modulation refers to the process by which the transmitting end maps the encoded bit sequence to a constellation based on a constellation diagram to obtain a modulated symbol sequence. Demodulation is the inverse process of modulation. Common modulation methods include quadrature amplitude modulation (QAM) and amplitude shift keying (ASK) modulation.

[0118] (3) Information bit sequence

[0119] An information bit sequence refers to a sequence of bits to be transmitted. For example, if the bits to be transmitted are 1, 0, 1, 0, 1, 1, 0, 0, 1, 0, 1, then the resulting information bit sequence is 10101100101. In this application, K represents the length of the information bit sequence. The information bits may include payload bits. Optionally, the information bits may also include check bits, such as cyclic redundancy check (CRC) bits.

[0120] (4) Code length

[0121] Code length refers to the length of the bit sequence to be transmitted obtained by encoding the information bit sequence. The code length is greater than or equal to the length of the information bit sequence. In this application, N represents the code length.

[0122] (5) Bitrate

[0123] The code rate is the ratio of the length of the information bit sequence to the code length. In this application, R represents the code rate. For example, R = K / E. Where rate matching is required, E represents the code length after rate matching, in which case E is greater than the mother code length N, or E is less than N. Where rate matching is not required, E = N.

[0124] The length, code length, and code rate of the information bit sequence can be pre-configured by higher-layer signaling, MAC layer signaling, or downlink physical layer signals, and can also be obtained or calculated by the transmitting and receiving devices. For example, the transmitting and receiving devices can determine the code length based on the coding method, the frame structure used to transmit the information bits, the number of layers, and the modulation scheme. For example, the transmitting and receiving devices can obtain the code rate based on higher-layer signaling, MAC layer signaling, or downlink physical layer signals, or determine the code rate based on the modulation and coding scheme (MCS).

[0125] (6) Rate matching

[0126] Rate matching refers to removing some bits from the encoded bit sequence without transmitting them, or repeating some bits.

[0127] The rate matching method will be further explained in three categories below.

[0128] Punching: Punching refers to directly creating holes in certain bit positions within the encoded bit sequence without transmitting them, thus generating bit sequences of arbitrary length. On the decoding side, since there is no information at the corresponding punctured positions, the log-likelihood ratio (LLR) of the corresponding bit is set to 0.

[0129] Shortening: Shortening involves fixing certain bit positions in the encoded bit sequence so that they do not need to be transmitted. On the decoding side, since the corresponding "shortened" positions are known at the receiver (usually 0), the LLR of the corresponding bit is set to infinity.

[0130] Repetition: "Repetition" refers to obtaining a longer bit sequence by repeatedly sending a portion of the encoded bit sequence.

[0131] Taking polar codes as an example, when using a regular polar kernel, the encoding length (i.e., the mother code length) of a polar code is an integer power of 2. In practical applications, the required length may be a non-encoded length. In this case, it is necessary to remove some bits from the encoded bit sequence without transmitting them, or to repeatedly transmit some bits.

[0132] NR rate matching and natural order rate matching are common rate matching types.

[0133] (6.1) NR rate matching refers to the rate matching type used in 5G NR.

[0134] In 5G NR, the process of determining the rate matching method is as follows: when E is greater than N, the rate matching method is repetition; when E ≤ N and K / E ≤ 7 / 16, the rate matching method is puncturing; when E is less than or equal to N and K / E is greater than 7 / 16, the rate matching method is shortening. Here, N is the mother code length, K is the number of bits in the information bit sequence to be encoded, and E is the code length after rate matching, also known as the code length after rate matching. The code length E after rate matching is determined by factors such as the available resource size and / or the number of bits K in the information bit sequence to be encoded. The ratio of K to E (i.e., K / E) is called the code rate R; that is, considering rate matching, the code rate R = K / E.

[0135] For example, in NR rate matching, the process of determining the rate matching position set Q is as follows: the reliability sequence of length N is divided into 32 sub-blocks, and then the sub-blocks are interleaved to obtain the bit sequence after interleaving. This application does not limit the specific implementation method of sub-block interleaving. Taking N=64 as an example, the bit sequence after interleaving is [0, 1, 2, 3, 4, 5, 8, 9, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 32, 33, 18, 19, 34, 35, 20, 21, 36, 37, 22, 23, 38, 39, 24, 25, 40, 41, 26, 27, 42, 43, 28, 29, 44, 45, 30, 31, 46, 47, 48, 49, 50, 51, 52, 53, 56, 57, 54, 55, 58, 59, 60, 61, 62, 63]. When the rate matching method is shortening, NE positions can be selected from the bit sequence before encoding as the pre-freeze position set Q. After encoding, sub-block interleaving is also required. When the rate matching method is puncturing, NE positions can be selected from the bit sequence before encoding as the pre-freeze position set Q. After encoding, sub-block interleaving is also required.

[0136] In this application, pre-frozen positions are not used as information bits. The pre-frozen positions include a first pre-frozen position, and optionally a second pre-frozen position. The first pre-frozen position corresponds to the encoded rate matching position, or in other words, the sequence number of the first pre-frozen position includes the sequence number of the rate matching position. The second pre-frozen position includes one or more bits that are not used as information bits, other than the first pre-frozen position. For example, the second pre-frozen position can be predefined by a standard or pre-configured by the network.

[0137] The second pre-frozen bit position can be determined based on E. For example, when E is greater than or equal to 3 / 4N, the second pre-frozen position includes bits 0 through 1 in the bit sequence before encoding. For example, when E is less than 3 / 4N, the second pre-freeze position includes the 0th bit to the 1st bit in the bit sequence before encoding. 1 bit.

[0138] It can also be said that the first pre-frozen position corresponds to the rate matching position after encoding.

[0139] (6.2) Natural order (NAT) rate matching

[0140] Unlike NR rate matching, NAT rate matching does not require sub-block interleaving to shuffle the encoding order.

[0141] Specifically, when the rate matching method is shortening, NE positions in the bit sequence before encoding can be selected as the pre-freeze position set Q in reverse order from back to front; that is, the last NE positions can be selected from the bit sequence before encoding as the rate matching position set Q. When the rate matching method is puncturing, NE positions in the bit sequence before encoding can be selected as the pre-freeze position set Q in reverse order from front to back; that is, the first NE positions can be selected from the bit sequence before encoding as the pre-freeze position set Q. Furthermore, rate matching types may also include BIV, etc., which are not specifically limited in this application embodiment.

[0142] (7) Polar codes

[0143] (7.1) Polar coding

[0144] Polar codes have been selected as the control channel coding scheme in 5G communication standards. Polar codes are a coding scheme that can be rigorously proven to "achieve" the Shannon channel capacity and have the advantages of good decoding performance and low complexity.

[0145] Polar codes employ encoding strategies that utilize noiseless channels to transmit useful user information, or utilize noisy channels to transmit agreed-upon information or no information at all. The generator matrix of a polar code is G. N Its encoding process is as follows It is a binary row vector with a length of N. With the generating matrix G N After multiplication, we get the encoded bit sequence; the multiplication process is the encoding process.

[0146] During the encoding process of polar codes, A portion of the bits are used to carry information, called the information bit position set, and the set of indices of these bits is denoted as A; the other portion of the bits are set to fixed values ​​agreed upon in advance by the receiver and the transmitter, called the fixed bit set or frozen bit set. The set of indices of the bits in the frozen bit set is denoted by the complement of A, A''. c These freeze bits are typically set to 0, but they can be set arbitrarily as long as the receiver and sender agree in advance.

[0147] In NR, the frozen bits and information bits of the polar code are determined based on the reliability sequence corresponding to the mother code length N. The reliability sequence corresponding to the mother code length can be calculated offline to reduce the encoding complexity. For example, the reliability sequence can be obtained by sorting the indices of N sub-channels in ascending order of their reliability, where each element is an index of the sub-channel. The mother code length is a power of 2, which is the length of the bit sequence after polar code encoding; the mother code length can also be called the encoding length. During the encoding process, the indices of the K most reliable sub-channels can be read from the reliability sequence according to their reliability, forming the set of information bit positions. Subchannels can be considered to correspond one-to-one with bits. In some scenarios, subchannels and bits can be interchanged. Taking a master code length of 8 as an example, assuming a reliability sequence of [0 1 2 4 3 5 6 7], the reliability of the bits from highest to lowest is as follows: the bit corresponding to bit number 7, the bit corresponding to bit number 6, the bit corresponding to bit number 5, the bit corresponding to bit number 3, the bit corresponding to bit number 4, the bit corresponding to bit number 2, the bit corresponding to bit number 1, and the bit corresponding to bit number 0. Here, a bit can be understood as a subchannel. Subchannels can also be called polarization channels or bit subchannels, etc. The bit number can be understood as an index or identifier of the bit. For example, when constructing a polar code with a mother code length of 8 and an information bit sequence length of 4, the bits corresponding to bit number 7, bit number 6, bit number 5, and bit number 3 are selected from the back to the front as information bits, while the bits corresponding to bit number 4, bit number 2, bit number 1, and bit number 0 are selected as frozen bits.

[0148] In one possible implementation, the reliability of a subchannel can be represented by its log-likelihood ratio (LLR). A larger LLR indicates higher reliability, while a smaller LLR indicates lower reliability.

[0149] Figure 3(a) shows an 8×8 polarization transformation matrix, where the left side can be understood as the side to be encoded, and the bits on the left are represented by u. The right side can be understood as the encoding side (or codeword side), and the bits on the right are represented by x. The process from left to right is the process of the transmitter encoding the bit sequence to be encoded. The information bits to be encoded are represented by the sequence u(0, 0, 0, 0, 0, 0, 1, 1). After the polarization transformation matrix, the encoded bits are represented by the sequence x(0, ​​1, 0, 1, 0, 1, 0, 1). Then, x is mapped to a modulation symbol for transmission in channel W. The bits corresponding to high channel reliability are used to map information bits, and the bits corresponding to low channel reliability are used to map frozen bits. As shown in Figure 3(a), {u0, u1, u2, u4} are frozen bits, i.e., the positions of frozen bits, and {u3, u5, u6, u7} are information bits, i.e., the positions of information bits. In this embodiment, information bits are also called information bits, and frozen bits are also called frozen bits.

[0150] It is understandable that the value of the frozen bit can be 0 or 1. Figure 3(a) is used as an example where all the frozen bits are 0, that is, in Figure 3(a), u0 = 0, u1 = 0, u2 = 0, u4 = 0.

[0151] Referring to Figure 3(a), in the encoding process, two adjacent columns constitute a coding layer. The left column of bits represents the input bits of the coding layer, and the right column represents the output bits. For example, in the leftmost coding layer, the input bit sequence is (0, 0, 0, 0, 0, 0, 1, 1), and the output bit sequence is (0, 0, 0, 0, 0, 0, 0, 1). The operation symbols in the middle of the coding layer... This represents the XOR operation, specifically... express The bits in the current row and A single XOR operation between the bits in the row. The bits on the right represent the result of the operation. For example, in the leftmost coding layer, the first input bit (value 0) and the second input bit (value 0) are processed... The operation yields the first output bit (with a value of 0).

[0152] (7.2) Polarization Decoding

[0153] There are several methods for decoding polar codes, such as successive cancellation (SC) decoding and successive cancellation list (SCL) decoding.

[0154] The SC decoding method refers to calculating the LLR of each decoded bit sequentially based on the LLR sequence corresponding to the bit sequence to be decoded, and making a bit-by-bit decision. When the decoded bit is an information bit, if the LLR of the decoded bit is greater than 0, then the decoded bit is 0; if the LLR of the decoded bit is less than 0, then the decoded bit is 1. When the decoded bit is a fixed bit, the decoding result is set to 0 regardless of the LLR value. Figure 3(b) is a schematic diagram of the SC decoding calculation process. Taking 4 decoded bits as an example, there are 8 calculation nodes in Figure 3(b), including 4 f nodes and 4 g nodes. The f nodes and g nodes correspond to the f operation and the g operation, respectively. The operation of the f node requires the two LLR inputs on its right side, and the operation of the g node requires the two LLR inputs on its right side and the output of the previous stage as inputs. Only after the input items are calculated can the output be calculated. According to the above calculation rules, the decoded bits obtained by calculating sequentially from the right side in Figure 3(b) are ①→②→③→④, and the decoding is completed.

[0155] The SCL decoding method refers to using the LLR sequence corresponding to the bit sequence to be decoded. When decoding each information bit, the decoding results corresponding to 0 and 1 are saved as two branches of decoding paths in the decoding path tree (referred to as path splitting). Figure 3(c) is a schematic diagram of the decoding path in the SCL decoding method. As shown in Figure 3(c), each level represents one decoded bit. If the decoding result is 0, the path is developed along the left subtree; if the decoding result is 1, the path is developed along the right subtree. When the total number of decoding paths exceeds the preset path width L (generally L = 2, 4, 8, 16, or 32), the L paths with the best path metric (PM) value are selected, saved, and the path is developed to decode subsequent bits. The PM value is used to judge the quality of the path, and the PM value is calculated through LLR. For each level of decoded bits, the PM values ​​of the L paths are sorted in ascending order, and the correct path is selected by the PM value. This process is repeated until the last bit is decoded.

[0156] Currently, the maximum length of the reliability sequence supported by 5G NR systems is 1024. How to implement polar coding with a code length greater than 1024 is a technical problem that urgently needs to be solved.

[0157] To address the aforementioned issues, this application provides corresponding solutions.

[0158] The methods provided in the embodiments of this application will be described in detail below. Figure 4This is a flowchart illustrating a communication method provided in an embodiment of this application. The method can be executed by a first device. Unless otherwise specified, the "first device" in this application can refer to a first equipment (e.g., a terminal or access network node), a component (e.g., a communication module, processor, circuit, chip, or chip system), or a logic module or software capable of implementing all or part of the functions of the first equipment. A component can also be replaced by a device or function. The component can be located within the first equipment. Similarly, the "second device" in this embodiment can refer to a second equipment (e.g., a terminal or access network node), a component (e.g., a communication module, processor, circuit, chip, or chip system), or a logic module or software capable of implementing all or part of the functions of the second equipment. A component can also be replaced by a device or function. The component can be located within the second equipment.

[0159] In this application, the first device can act as a transmitting side or an encoding side, and the second device can act as a receiving side or a decoding side. For example, the first device or the first equipment can send information or data to the second device or the second equipment. Specifically, during uplink communication, the first equipment can be a terminal, and the second equipment can be an access network device; during downlink communication, the first equipment can be an access network device, and the second equipment can be a terminal. Furthermore, this application does not exclude applications in terminal-to-terminal communication scenarios, in which case the transmitting device and the receiving device can each be a terminal.

[0160] like Figure 4 As shown, with the first device as the executing entity, the method may include the following steps:

[0161] S101: The first device acquires the information bit sequence.

[0162] In this application, the information bit sequence can be a sequence comprising multiple information bits, each of which can have a value of 0 or 1. An information bit can refer to the payload itself, or to the payload and parity bits. The length of the information bit sequence is K.

[0163] The payload can be a sequence of bits to be transmitted. For example, if the bits to be transmitted are 1, 0, 1, 0, 1, 1, 0, 0, 1, 0, 1, then the resulting information bit sequence could be 10101100101. Similarly, in Figure 3(a), if the information bits are u3 = 0, u5 = 0, u6 = 1, and u7 = 1, then the information bit sequence could be 0011.

[0164] The check bits can be obtained from the payload. For example, the check bits are CRC bits, parity bits, or check bits corresponding to other check methods. That is, the information bits can be a sequence of payload and one or more CRC bits.

[0165] In this application, the length K of the information bit sequence can refer to the number of bits contained in the information bit sequence. For example, if the information bit sequence includes a payload but does not include a parity bit, the length K of the information bit sequence can be the payload length. As another example, if the information bit sequence includes both a payload and a parity bit, the length K of the information bit sequence can be the sum of the payload length and the parity bit length.

[0166] S102: The first device determines the first reliability number based on the first sequence of length N1, the code length N0, and K.

[0167] The first sequence includes the sequence numbers of N1 sub-channels. The sequence numbers of the sub-channels in the first sequence are sorted according to the reliability of the sub-channels. N1 is a positive integer, N0 is a positive integer, and N1 is less than N0.

[0168] The first sequence is described below.

[0169] In this application, the first sequence includes the indices of N1 sub-channels. For example, the indices of these N1 sub-channels are 0, 1, 2...N1-1. The indices of the sub-channels in the first sequence are ordered according to their reliability. Alternatively, the first sequence can be described as a reliability sequence of length N1. N1 can be a positive integer power of 2. For example, N1 equals N0 / 2. p p is a positive integer, meaning N0 is an integer power of 2 of N1, which can reduce the processing complexity.

[0170] Taking N1 = 1024 as an example, the first sequence could be [0 1 2 4 8 16 32 3 5 64 9 6 17 10 18 128 12 33 65 20 256 34 24 36 71 29 66 512 11 40 68 130 19 13 48 14 72 257 21 13 235 258 26 513 80 37 25 22 136 260 264 38 514 96 67 41 144 28 69 42 516 49 74 272 160 520 288 528 192 544 70 44 131 81] 50 73 15 320 133 52 23 134 384 76 137 82 56 27 97 39 259 84 138 145 261 29 43 98 515 88 140 30 146 71 262 265 161 576 45 100 640 51 148 46 75 266 273 517 104 162 53 193 152 77 164 768 268 274 518 54 83 57 521 112 135 78 289 194 85 276 522 58 168 139 99 86 60 280 89290 529 524 196 141 101 147 176 142 530 321 31 200 90 545 292 322 532 263 149102 105 304 296 163 92 47 267 385 546 324 208 386 150 153 165 106 55 328 536 577 548 113 154 79 269 108 578 224 166 519 552 195 270 641 523 275 580 291 59169 560 114 277 156 87 197 116 170 61 531 525 642 281 278 526 177 293 388 91584 769 198 172 120 201 336 62 282 143 103 178 294 93 644 202 592 323 392 297770 107 180 151 209 284 648 94 204 298 400 608 352 325 533 155 210 305 547300 109 184 534 537 115 167 225326 306 772 157 656 329 110 117 212 171 776330 226 549 538 387 308 216 416 271 279 158 337 550 672 118 332 579 540 389173 121 553 199 784 179 228 338 312 704 390 174 554 581 393 283 122 448 353561 203 63 340 394 527 582 556 181 295 285 232 124 205 182 643 562 286 585299 354 211 401 185 396 344 586 645 593 535 240 206 95 327 564 800 402 356307 301 417 213 568 832 588 186 646 404 227 896 594 418 302 649 771 360 539111 331 214 309 188 449 217 408 609 596 551 650 229 159 420 310 541 773 610657 333 119 600 339 218 368 652 230 391 313 450 542 334 233 555 774 175 123658 612 341 777 220 314 424 395 673 583 355 287 183 234 125 557 660 616 342316 241 778 563 345 452 397 403 207 674 558 785 432 357 187 236 664 624 587780 705 126 242 565 398 346 456 358 405 303 569 244 595 189 566 676 361 706589 215 786 647 348 419 406 464 680 801 362 590 409 570 788 597 572 219 311708 598 601 651 421 792 802 611 602 410 231 688 653 248 369 190 364 654 659335 480 315 221 370 613 422 425 451 614 543 235 412 343 372775 317 222 426453 237 559 833 804 712 834 661 808 779 617 604 433 720 816 836 347 897 243662 454 318 675 618 898 781 376 428 665 736 567 840 625 238 359 457 399 787591 678 434 677 349 245 458 666 620 363 127 191 782 407 436 626 571 465 681246 707 350 599 668 790 460 249 682 573 411 803 789 709 365 440 628 689 374423 466 793 250 371 481 574 413 603 366 468 655 900 805 615 684 710 429 794252 373 605 848 690 713 632 482 806 427 904 414 223 663 692 835 619 472 455796 809 714 721 837 716 864 810 606 912 722 696 377 435 817 319 621 812 484430 838 667 488 239 378 459 622 627 437 380 818 461 496 669 679 724 841 629351 467 438 737 251 462 442 441 469 247 683 842 738 899 670 783 849 820 728928 791 367 901 630 685 844 633 711 253 691 824 902 686 740 850 375 444 470483 415 485 905 795 473 634 744 852 960 865 693 797 906 715 807 474 636 694254 717 575 913 798 811 379 697 431 607 489 866 723 486 908 718 813 476 856839 725 698 914 752 868 819 814 439 929 490 623 671 739 916 463 843 381 497930 821726 961 872 492 631 729 700 443 741 845 920 382 822 851 730 498 880742 445 471 635 932 687 903 825 500 846 745 826 732 446 962 936 475 853 867637 907 487 695 746 828 753 854 857 504 799 255 964 909 719 477 915 638 748944 869 491 699 754 858 478 968 383 910 815 976 870 917 727 493 873 701 931756 860 499 731 823 922 874 918 502 933 743 760 881 494 702 921 501 876 847992 447 733 827 934 882 937 963 747 505 855 924 734 829 965 938 884 506 749945 966 755 859 940 830 911 871 639 888 479 946 750 969 508 861 757 970 919875 862 758 948 977 923 972 761 877 952 495 703 935 978 883 762 503 925 878735 993 885 939 994 980 926 764 941 967 886 831 947 507 889 984 751 942 996971 890 509 949 973 1000 892 950 863 759 1008 510 979 953 763 974 954 879 981982 927 995 765 956 887 985 997 986 943 891 998 766 511 988 1001 951 1002 893975 894 1009 955 1004 1010 957 983 958 987 1012 999 1016 767 989 1003990 1005959 1011 1013 895 1006 1014 1017 1018 991 1020 1007 1015 1019 1021 10221023]。

[0171] The above sequence can also be called the NR reliability sequence.

[0172] The first sequence can be called the Q sequence.

[0173] The following explains the first reliability index.

[0174] In this embodiment, the first reliability index can be used to determine the set of information bit positions when performing polar coding of a mother code length of N0 based on a first sequence of length N1. Specifically, when performing polar coding of a mother code length of N0, the first reliability index can be used to determine the bit index corresponding to the set of information bit positions in the first sequence of length N1, so as to determine the bit index in the set of information bit positions based on the first reliability index and the second sequence. The second sequence can be found in the description in S103. In addition, since the second sequence can be determined based on the first sequence, "determining the bit index in the set of information bit positions based on the first reliability index and the second sequence" can also be replaced with "determining the bit index in the set of information bit positions based on the first reliability index and the first sequence".

[0175] In one possible example, the reliability index can represent the order in which the reliability of the sub-channels is sorted from smallest to largest or largest to smallest. Taking the reliability index sorted from largest to smallest as an example, a bit with a reliability index of 0 indicates that the reliability of that bit is the maximum among the multiple bits. Conversely, taking the reliability index sorted from smallest to largest as an example, a bit with a reliability index of 0 indicates that the reliability of that bit is the minimum among the multiple bits.

[0176] As an example, when the reliability numbers are sorted in descending order of reliability, the first reliability number can be used to indicate the largest reliability number corresponding to an information bit in the first sequence. Alternatively, bits with reliability numbers less than or equal to the first reliability number correspond to information bits.

[0177] As an example, the first reliability index can be represented as Z. i Z i It can include m reliability ranking values, i = 0, 1, ..., m-1. Represents rounding down. Taking the reliability index sorted in descending order of reliability as an example, Z... iZ can represent the highest reliability ranking corresponding to the information bits in the i-th sequence. Correspondingly, the reliability ranking in the i-th sequence can be less than or equal to Z. i The bit sequence number is used as the sequence number of the information bit.

[0178] The i-th sequence is obtained by adding i*N1 to each index in the first sequence and then removing the index from the pre-frozen bit position set. In other words, the set of information bit positions can also be determined based on the pre-frozen set of bit positions. Therefore, the set of information bits can be determined based on the first reliability index and the first sequence.

[0179] For example, when N1 = N0 / 2, m = 2, i.e., i = 0, 1, meaning the first reliability index includes Z0 and Z1. Similarly, when N1 = N0 / 4, m = 4, i.e., i = 0, 1, 2, 3, meaning the first reliability index includes Z0, Z1, Z2, and Z3.

[0180] In one possible embodiment, the pre-frozen bit position set and / or rate matching position set can be a set of indices of bits that are not considered information bits, determined based on rate matching, such as first pre-frozen bit positions. Optionally, the pre-frozen bit position set and / or rate matching position set may also include bits that are not considered information bits, determined by other means, such as second pre-frozen bit positions.

[0181] In one possible example, the set of pre-frozen bit positions includes a first pre-frozen position, and optionally, a second pre-frozen position. The first pre-frozen position may correspond to a rate matching bit; for example, the sequence number of the first pre-frozen position may be considered to be the same as the sequence number of the rate matching position. The rate matching bit may include, for example, a punched bit or a shortened bit. The second pre-frozen position may be standard predefined or network preconfigured, as detailed in section (6.1), and will not be repeated here.

[0182] In other words, the index of the bit in the pre-frozen bit position set can include the index of the bit in the rate matching bit position set. The number of the first pre-frozen bits is 0 or a positive integer. If the number of the first pre-frozen bits is 0, rate matching is not required, or the rate matching method performed is other than shortening and puncturing, for example, repetition. If the number of the first pre-frozen bits is a positive integer, it means that the rate matching method is shortening or puncturing.

[0183] Optionally, the reliability indices can be sorted in descending order of reliability, and the reliability in the i-th sequence can be less than or equal to Z. iThe bit index is used as the index of the information bit, where the reliability ranking in the i-th sequence is less than or equal to Z. i The bit position number does not belong to the pre-frozen bit position set.

[0184] For example, when N1 = N0 / 2, m = 2. The K information bits in the information bit position set include the bits with a reliability index less than or equal to Z0 in the i = 0th sequence, and the bits with an index less than or equal to Z1 in the i = 1st sequence. The 0th sequence can be the sequence obtained by removing the index from the pre-frozen bit position set from the first sequence, and the 1st sequence can be the sequence obtained by removing the index from the pre-frozen bit position set from each index plus N1 in the first sequence. Z0 is a positive integer, Z1 is a positive integer, and Z0 + Z1 = K.

[0185] For example, when N1 = N0 / 4, m = 4, the K information bits in the information bit position set include the indices of the i = 0th sequence whose reliability index is less than or equal to Z0, the indices of the i = 1st sequence whose reliability index is less than or equal to Z1, the indices of the i = 2nd sequence whose reliability index is less than or equal to Z2, and the indices of the i = 0th sequence whose reliability index is less than or equal to Z3. Wherein, the 0th sequence can be the sequence obtained by removing the index of the pre-frozen bit position set from the first sequence, the 1st sequence can be the sequence obtained by removing the index of the pre-frozen bit position set from the sequence obtained by adding N1 to each index in the first sequence, the 2nd sequence can be the sequence obtained by removing the index of the pre-frozen bit position set from the sequence obtained by adding 2N1 to each index in the first sequence, and the 3rd sequence can be the sequence obtained by removing the index of the pre-frozen bit position set from the sequence obtained by adding 3N1 to each index in the first sequence. Z0, Z1, Z2 and Z3 are all positive integers greater than or equal to 0, and Z0+Z1+Z2+Z3=K.

[0186] Optionally, taking N1 = N0 / 2 as an example, in the case of mother code length encoding, or in other words, when the number of sequence numbers in the pre-frozen bit position set is 0, the first reliability sequence number includes the number of sequence numbers less than or equal to N1 / 2 among the K / 2 sequence numbers with the highest reliability in the first sequence, 2*Z0, and / or the number of sequence numbers greater than N1 / 2 among the K / 2 sequence numbers with the highest reliability in the first sequence, 2*Z1.

[0187] In addition, when the number of indices in the pre-frozen bit position set is a positive integer, the K / 2 indices with the highest reliability in the first sequence do not include the indices in the pre-frozen bit position set, where the pre-frozen bit position set includes the indices of the pre-frozen bits.

[0188] As another example, in the scheme of determining the information bit position set based on the second sequence, the i-th sequence can be considered as the sequence obtained by adding i*N1 to each index of the bit corresponding to each reliability index in the second sequence and then removing the index from the pre-frozen bit position set. That is, the first reliability index can also be determined based on the pre-frozen bit position set. Correspondingly, when the reliability indices in the second sequence are sorted in descending order of reliability, the indices of bits in the i-th sequence whose reliability index is less than or equal to the first reliability index can be used as the indices of the information bits. Therefore, the information bit set can be determined based on the first reliability index and the second sequence.

[0189] The method for determining the first reliability index is explained below.

[0190] In this application, the first reliability number is determined based on the first sequence, N0, and K.

[0191] Method 1, as a possible implementation of determining the first reliability index based on the first sequence, N0, and K, involves the first device determining the set of pre-frozen bit positions based on N0, and then determining the first reliability index based on the first sequence, K, and the set of pre-frozen bit positions. Alternatively, in Method 1, the first device can determine the first reliability index based on the set of pre-frozen bit positions corresponding to N0, the first sequence, and K.

[0192] The following section, combining methods 1-1 and 1-2, explains how the set of pre-frozen bit positions is determined. In method 1-1, the set of pre-frozen bit positions can be determined based on the code length E after rate matching. Specifically, the first pre-frozen bit position and / or the second pre-frozen bit position can be determined based on the code length E after rate matching.

[0193] The first pre-frozen bit position can be related to E, and at least one of N0, K, or the code rate R = K / E. Alternatively, the rate matching position or set of rate matching positions can be determined based on E, and at least one of N0, K, or the code rate R = K / E. Furthermore, see the explanation in section (6.1), the first pre-frozen bit position can be determined based on E.

[0194] Alternatively, the position of the first pre-frozen bit can be determined using a rate-matching method. This rate-matching method involves either puncturing or shortening. The rate-matching method is related to E, and at least one of N0, K, or the bit rate R = K / E. For example, if E is less than or equal to N0 and the bit rate K / E is less than or equal to a first threshold, the rate-matching method is puncturing; if E is less than or equal to N0 and the bit rate K / E is greater than the first threshold, the rate-matching method is shortening.

[0195] The first threshold is, for example, 7 / 16.

[0196] Specifically, if the rate matching method is puncturing, the pre-frozen bit position set corresponds to the first (N0-E) bits of the N0-length bit sequence before polar coding. That is, when E is less than or equal to N0 and K / E is less than or equal to the first threshold, the pre-frozen bit position set corresponds to the first (N0-E) bits of the first bit sequence. If the rate matching method is shortening, the pre-frozen bit position set corresponds to the last (N0-E) bits of the N0-length bit sequence before polar coding. That is, when E is less than or equal to N0 and K / E is greater than the first threshold, the pre-frozen bit position set corresponds to the last (N0-E) bits of the first bit sequence.

[0197] The first bit sequence is a sequence of length N0, where the indices are 0, 1, ..., N0-1. For natural order rate matching, the first bit sequence can be a natural order sequence. For example, the indices in the natural order sequence are sorted in ascending order of bit indices; for instance, the first bit sequence could be [0, 1, 2, ..., N0-1]. For NR rate matching, the first bit sequence can be a sequence obtained by interleaving the natural order sequence with sub-blocks.

[0198] As another example, it can be assumed that there is a correspondence between at least one of E, N0, K, or the code rate and the pre-frozen bit position set and / or the rate matching position set. Therefore, based on this correspondence, the corresponding pre-frozen bit position set and / or rate matching position set can be determined according to at least one of E, N0, K, or the code rate. Alternatively, it can be said that the pre-frozen bit position set and / or rate matching position set is determined by at least one of E, N0, K, or the code rate. The aforementioned correspondence can be predefined by a standard, pre-configured by the network, or determined by signaling between the first and second devices. The signaling can be RRC messages, MAC control elements (CE), or downlink control information (DCI) sent between the first and second devices.

[0199] In method 1-2, the set of pre-frozen bit positions can be determined according to a rate matching method, which is related to at least one of E*N1 / N0, N1, K*N1 / N0 or R*N1 / N0.

[0200] In methods 1-2, the first bit sequence number set corresponding to N1 can be determined first, and then the pre-frozen bit position set corresponding to N0 can be determined based on N0 and the first bit sequence number set. The first bit sequence number set is the pre-frozen bit set determined according to the mother code length N1.

[0201] The first bit sequence set may include a third pre-freeze position, and optionally, a fourth pre-freeze position. The third pre-freeze position may be a pre-freeze position determined based on the mother code length N1 and the code length E*N1 / N0 after rate matching. For example, based on rate matching, if E*N1 / N0 is less than or equal to N1 and K / E is less than or equal to a first threshold, then the rate matching method is puncturing, and the third pre-freeze position corresponds to the first (N1-E*N1 / N0) bits of the second bit sequence. Alternatively, if E*N1 / N0 is less than or equal to N1 and K / E is greater than the first threshold, then the rate matching method is shortening, and the third pre-freeze position corresponds to the last (N1-E*N1 / N0) bits of the second bit sequence.

[0202] The second bit sequence is a sequence of length N1, where the indices are 0, 1, ..., N1-1. For natural order rate matching, the second bit sequence can be a natural order sequence. For example, the indices in the natural order sequence are sorted in ascending order of bit indices; for instance, the first bit sequence could be [0, 1, 2, ..., N1-1]. For NR rate matching, the second bit sequence can be a sequence obtained by interleaving the natural order sequence with sub-blocks.

[0203] The fourth pre-freeze position may include one or more bits that are not information bits, other than the third pre-freeze position. For example, the fourth pre-freeze position is determined based on the mother code length N1 and the code length E*N1 / N0 after rate matching. The fourth pre-freeze position can be found in the description of the second pre-freeze position in section (6.1), and will not be repeated here.

[0204] Taking the first set of bit numbers as including the first (N1-E*N1 / N0) bits of the second bit number sequence as an example, the second pre-frozen bit position set can also be considered to correspond to the first (N0-E) bits of the first bit number sequence. Similarly, taking the first set of bit numbers as including the last (N1-E*N1 / N0) bits of the second bit number sequence as an example, the second pre-frozen bit position set corresponds to the last (N0-E) bits of the first bit number sequence. The first bit number sequence is a sequence of length N0, as explained above, and will not be repeated here.

[0205] Optionally, in methods 1-2, the relationship between the first bit sequence set and the pre-frozen bit position set corresponding to N0 can also be represented by a formula. Therefore, based on the first bit sequence set and N0, the pre-frozen bit position set corresponding to N0 can be determined using the formula. For example, the first bit sequence set can be represented by P1, which is a sequence of N1 elements ordered by bit position. The value of any element in the P1 sequence is a, b, or c. Here, a represents a non-rate-matched bit (e.g., a = 0); b represents a punched bit (e.g., b = 1); and c represents a shortened bit (e.g., c = 2). The sequence of indices in the second pre-frozen bit position set can be denoted as P, which is a sequence of N0 elements ordered by bit position. The value of any element in the P sequence is a, b, or c, as described in the explanation of the elements in the P1 sequence.

[0206] For example, taking N1 = N0 / 2 as an example, P and P1 satisfy:

[0207] P = kron(P1, [1 1]);

[0208] Here, kron() represents the Kronecker product operation.

[0209] For example, P1 being [1,1,0,0] indicates that bits 0 to 1 are punctured bits, and bits 2 to 3 are non-rate-matched bits. Correspondingly, P being [1,1,1,1,0,0,0,0] indicates that bits 0 to 3 are punctured bits, and bits 4 to 7 are non-rate-matched bits. Optionally, the non-rate-matched bits can be used as information bits.

[0210] Alternatively, the sequence number in the second pre-frozen bit position set can be determined based on the sequence number in the first pre-frozen bit position set through table lookup or other operations.

[0211] The following describes how the first reliability index is determined based on the first sequence, K, and the set of pre-frozen bit positions.

[0212] The first device can read the serial numbers in the first sequence in order of reliability from highest to lowest or in order of serial numbers from back to front, and determine the first reliability serial number based on the serial numbers read in the first sequence.

[0213] Specifically, the first device can read one or more numbers in the first sequence in descending order of reliability or in reverse order of the sequence numbers, and determine the first reliability number based on these numbers. If the sum of the determined first reliability numbers is less than K, the device can further read one or more numbers in the first sequence again, starting from the position after the last read first number, in descending order of reliability or in reverse order of the sequence numbers, and determine the first reliability number based on these numbers. Optionally, the above process can be repeated until the sum of the first reliability numbers equals K.

[0214] As described above, the first reliability index can be denoted as Z. i Z i It can be the reliability sorting of the information bits with the lowest reliability in the i-th sequence, where i = 0, 1, ..., m-1. Z represents floor function. The i-th sequence is obtained by adding i*N1 to each index in the first sequence and then removing the index from the pre-frozen bit position set. i It is a positive integer greater than or equal to 0, Z0 + Z1 + ... + Z m-1 =K.

[0215] Taking N1 = N0 / 2 as an example, the following process 1 illustrates how Z0 and Z1 are determined based on the first sequence, the pre-frozen bit position set, and K. For example, in process 1, N1 = 1024 and N0 = 2048. In this exemplary process, the number of sequence numbers in the pre-frozen bit position set is 0, meaning that when determining Z... i The pre-frozen bit positions can be disregarded at this time.

[0216] Process 1 may include the following steps:

[0217] (1) The first device initializes Z0 and Z1, i.e., Z0 = 0 and Z1 = 0. And, let id = N1-1.

[0218] (2) The first device may perform the following steps until outputting Z0 and Z1.

[0219] (3) Read the id-th index in the first sequence to obtain the first index;

[0220] (4) If the value of the first serial number is less than or equal to N1 / 2, let Z0 = Z0 + 2;

[0221] (5) If the value of the first serial number is greater than N1 / 2, let Z1 = Z1 + 2;

[0222] Optionally, there is no restriction on the execution order between steps (4) and (5). They can be executed in parallel or sequentially. In sequential execution, step (4) can be executed first or step (5) can be executed first.

[0223] (6) In In the case of , let id = id-1, and then repeat step (3);

[0224] (7) In If K is odd, read the (id-1)th index from the first sequence to obtain the second index. If the second index is less than or equal to N1, let Z0 = Z0 + 1. If the second index is greater than N1, let Z1 = Z1 + 1. Then Z0 and Z1 can be output, which gives us Z0 and Z1.

[0225] (8) In In this case, Z0 and Z1 can be output, that is, Z0 and Z1 can be obtained.

[0226] In process 1 above, the first device reads a sequence number from the first sequence as the first sequence number each time, and performs subsequent steps based on the relationship between the first sequence number and N1 / 2 to update the values ​​of Z0 and / or Z1. Furthermore, after the values ​​of Z0 and / or Z1 change, it can be determined that Z0+Z1 is equal to... The size relationship is used to determine whether to output Z0 and Z1.

[0227] Optionally, step 1 above can also be performed via... Figure 5 The flowchart shown is illustrated. Here, the Q sequence represents the first sequence; that is, when reading the first sequence number for the first time, 1023 can be read as the first sequence number, and subsequent steps can be executed.

[0228] As can be seen, in process 1 above, each time a sequence number is read from the id-th sequence number in the first sequence as the first sequence number, and subsequent judgments are performed based on the first sequence number. Optionally, some steps in process 1 above can be adaptively replaced to support reading multiple sequence numbers from the first sequence each time and performing subsequent judgments based on the read multiple sequence numbers. That is, it can be understood that multiple sequence numbers in the first sequence can be read in parallel to determine Z0 and Z1, thereby speeding up the determination of Z0 and Z1.

[0229] As an example of an implementation method for reading multiple serial numbers from the first sequence, step (3) above can also be replaced by: step (3'), reading X serial numbers starting from the id-th serial number of the first sequence in descending order of reliability, where X is an integer greater than 1. The number of values ​​greater than or equal to N1 / 2 among these X serial numbers is denoted as x0, and the number of values ​​less than N1 / 2 among these X serial numbers is denoted as x1. Correspondingly, step (4) can be replaced by: step (4'), letting Z0 = Z0 + 2x0. Step (5) can be replaced by: step (5'), letting Z1 = Z1 + 2x1. Optionally, there is no restriction on the execution order between steps (4') and (5'), and they can be executed in parallel or serially. In serial execution, step (4') can be executed first or step (5') can be executed first. Step (6) can be replaced by: step (6'), in In the case of , let id = id - X, and then repeat step (3). Step (7) can be replaced with: step (7'), in If K is odd, read the id-X-1th index from the first sequence to obtain the second index. If the second index is less than or equal to N1, let Z0 = Z0 + 1. If the second index is greater than N1, let Z1 = Z1 + 1. Then Z0 and Z1 can be output, which means we get Z0 and Z1.

[0230] Optionally, if Z0+Z1+2*X>K has been satisfied before step (3'), then in step (3'), That is, starting from the id-th index of the first sequence. A sequence number is used to ensure that no more than K information bits are selected.

[0231] Understandably, as the value of X increases, the first reliability index can be determined more quickly. X can be a positive integer power of 2. For example, X = 2. x x is a natural number.

[0232] The following describes how to determine the first reliability index when the number of indexes in the pre-frozen bit location set is a positive integer. Specifically, when the number of indexes in the pre-frozen bit location set is a positive integer, the first reliability index can also be determined based on the indexes in the pre-frozen bit location set, as explained in Method 1.

[0233] If NAT rate matching is used, the first reliability sequence number can be determined through the following procedure 2; if NR rate matching is used, the first reliability sequence number can be determined through the following procedure 3. Alternatively, if BIV rate matching or other rate matching types are used, procedure 2 or procedure 3 can be followed.

[0234] Step 2: Determine the first reliability index based on the NAT rate matching method. The NAT rate matching method includes puncturing or shortening. That is, in the case of puncturing or shortening, the pre-frozen bit position set includes the index of at least one frozen bit.

[0235] Taking N1 = N0 / 2 as an example, process 2 may include the following steps:

[0236] (1) The first device initializes M, Z0 and Z1, i.e., M = 0, Z0 = 0 and Z1 = 0. Also, let id = N1-1 and idx = id.

[0237] (2) The first device may perform the following steps until the number of information bits M equals K:

[0238] (3) Read the id-th sequence number in the first sequence to obtain the first sequence number.

[0239] Subsequently, the next steps are determined based on the rate matching method. Specifically, if the rate matching method is punching, steps (4-1) to (5-1) or step (6-1) are executed. If the rate matching method is shortening, steps (4-2) or steps (5-2) to (6-2) are executed, as well as steps (7-2) to (8-2).

[0240] (4-1) If the first sequence number is less than or equal to T, read the idx-th sequence number in the first sequence to obtain the second sequence number. Let M = M + d0, where d0 = 0 if the second sequence number belongs to the set of pre-frozen bit positions, or d0 = 1 if the second sequence number does not belong to the set of pre-frozen bit positions.

[0241] (5-1) Read the (idx-1)th index in the first sequence to obtain the third index. Let M = M + d0'. If the third index belongs to the pre-frozen bit position set, d0' = 0; otherwise, if the third index does not belong to the pre-frozen bit position set, d0' = 1. T is a positive integer. Let idx = idx-2. Then execute steps (7-1), (8-1), or (9-1).

[0242] (6-1) If the first sequence number is greater than T, let M = M + 2. Then execute steps (7-1), (8-1), or (9-1).

[0243] (7-1) When M < K, let id = id-1 and Z0 = Z0+2, and then repeat step (3);

[0244] (8-1) When M > K, let Z0 = Z0-1.

[0245] Optionally, after executing Z0 = Z0 - 1 in step (8-1), M = M - 1 can be executed to update M. Then, it can be determined again whether the updated M satisfies M > K. If it still satisfies M > K, then Z0 = Z0 - 1 can be set again. Alternatively, if it is determined that the updated M based on step (8-1) satisfies M = K, then Z0 and Z1 can be output.

[0246] (9-1) When M=K, output Z0 and Z1.

[0247] (4-2) If the first sequence number is less than or equal to T, let M = M + 2. Then execute steps (7-2), (8-2), or (9-2).

[0248] (5-2) If the first sequence number is greater than T, read the idx-th sequence number in the first sequence to obtain the fourth sequence number. Let M = M + d1. If the sum of the fourth sequence number and N1 belongs to the set of pre-frozen bit positions, d1 = 0. Or, if the sum of the fourth sequence number and N1 does not belong to the set of pre-frozen bit positions, d1 = 1.

[0249] (6-2) Read the (idx-1)th index in the first sequence to obtain the fifth index. Let M = M + d1'. If the sum of the fifth index and N1 belongs to the pre-frozen bit position set, d1' = 0; otherwise, if the sum of the fifth index and N1 does not belong to the pre-frozen bit position set, d1' = 1. Let idx = idx-2. Then execute steps (7-2), (8-2), or (9-2).

[0250] (7-2) When M < K, let id = id-1, let Z1 = Z1+2, and then repeat step (3);

[0251] (8-2) When M > K, let Z0 = Z0-1.

[0252] Optionally, after executing Z1 = Z1 - 1 in step (8-2), M = M - 1 can be executed to update M. Then, it can be checked again whether the updated M satisfies M > K. If it still satisfies M > K, then Z1 = Z1 - 1 is set again, and M can be updated again. Alternatively, if it is determined that the updated M based on step (8-2) satisfies M = K, then Z0 and Z1 can be output.

[0253] (9-2) When M=K, output Z0 and Z1.

[0254] Optionally, the steps shown in process 2 above can also be performed by... Figure 6The flowchart shown is illustrated. Here, the Q sequence represents the first sequence, meaning that in step (3), when reading the first sequence number for the first time, 1023 can be read as the first sequence number, and subsequent steps can be executed.

[0255] The above steps (4-1) and (5-1) can be replaced by: reading two sequences starting from the idxth sequence number of the first sequence number in descending order of reliability, and letting M = M + d0”, where d0” is the number of sequences that do not belong to the pre-frozen bit position set among the two sequences read starting from the idxth sequence number of the first sequence number.

[0256] The above steps (5-2) and (6-2) can be replaced by: reading two sequences starting from the idxth sequence number of the first sequence number in descending order of reliability, and letting M = M + d1", where d1" is the number of sequences that do not belong to the pre-frozen bit position set among the two sequences read starting from the idxth sequence number of the first sequence number.

[0257] As can be seen, in process 2 above, each time a sequence number is read from the id-th index in the first sequence as the first index, and subsequent judgments are performed based on the first index. Optionally, some steps in process 2 above can be adaptively replaced to support reading multiple indexes from the first sequence each time and performing subsequent judgments based on the read multiple indexes. That is, it can be understood that multiple indexes can be read from the id-th index in the first sequence to determine Z0 and Z1 in parallel, thereby speeding up the determination of Z0 and Z1.

[0258] As an example of how to read multiple serial numbers from the first sequence, step (3) in process 2 can also be replaced with: Step (3'), reading X serial numbers starting from the id-th serial number of the first sequence in descending order of reliability, where X is an integer greater than 1. The number of values ​​greater than or equal to N1 / 2 among these X serial numbers is recorded as x0, and the number of values ​​less than N1 / 2 among these X serial numbers is recorded as x1. It is understandable that as the value of X increases, the first reliability serial number can be determined more quickly.

[0259] In addition, steps (4-1) to (6-1) can be replaced by: step (4-3), reading 2x0 numbers starting from the idx-th number of the first sequence in descending order of reliability, and letting M = M + d0” + 2x1, where d0” represents the number of numbers in the 2x0 numbers read that do not belong to the pre-frozen bit position set, and then letting idx = idx - 2x0.

[0260] In addition, steps (4-2) to (6-2) can be replaced by: step (4-4), reading 2x1 sequence numbers starting from the idx-th sequence number of the first sequence in descending order of reliability, and letting M = M + d1” + 2x1, where d1” represents the number of sequence numbers in the 2x1 sequence numbers that do not belong to the pre-frozen bit position set, and then letting idx = idx - 2x1.

[0261] After step (4-3) or step (4-4), the first device can execute step (7-3), step (8-3), or step (9-3) according to the relationship between M and K:

[0262] Step (7-3): When M < K, let id = id - X, Z0 = Z0 + 2x0, and Z1 = Z1 + 2x1. Then step (3') can be executed again.

[0263] Step (8-3): When M > K, let M = M - d0" - d1", and let X = 1. Then, read the idx-th sequence number of the first sequence according to X = 1. This can be understood as the first terminal rereading a sequence number from the idx-th sequence number in the first sequence when M > K. This can be done by referring to the steps of reading the first sequence number one by one and judging it. For example, after reading the idx-th sequence number of the first sequence number according to X = 1, this sequence number can be used as the first sequence number. The subsequent steps can be executed according to steps (4-1) to (9-1) or steps (4-2) to (9-2) in process 2.

[0264] Step (9-3): When M=K, output Z0 and Z1.

[0265] The above process 2 can be applied to scenarios using NAT rate matching. Specifically, it determines the first reliability sequence number and then determines the information bits based on that number. This is because the above implementation method is similar to the process of allocating information bits based on a reliability sequence of length N1 and a reliability sequence of length N0 when using natural order rate matching. Therefore, this implementation method can be applied to the case of natural order rate matching, ensuring the corresponding communication performance of the information bits determined under this method.

[0266] Step 3: Determine the first reliability index based on the NR rate matching method. The NR rate matching method includes puncturing or shortening. That is, in the case of puncturing or shortening, the pre-frozen bit position set includes the index of at least one frozen bit. Additionally, when using NR rate matching, sub-block interleaving needs to be performed after encoding.

[0267] Taking N1 = N0 / 2 as an example, process 3 may include the following steps:

[0268] (1) The first device initializes M, Z0 and Z1, i.e., M = 0, Z0 = 0 and Z1 = 0. Also, let id = N1-1, id0 = id and id1 = id.

[0269] (2) The first device may perform the following steps until the number of information bits M equals K:

[0270] (3) Read the id-th sequence number in the first sequence to obtain the first sequence number.

[0271] If the first index is less than or equal to T (x0 = 1, x1 = 0), perform the following steps, where T is a positive integer:

[0272] (4-1) Read the id0th index in the first sequence to obtain the second index. Let M = M + d0, where d0 = 0 if the second index belongs to the pre-frozen bit position set, or d0 = 1 if the second index does not belong to the pre-frozen bit position set.

[0273] (5-1) Read the id0-1th sequence number in the first sequence to obtain the third sequence number. Let M = M + d0', where d0' = 0 if the third sequence number belongs to the pre-frozen bit position set, or d0' = 1 if the third sequence number does not belong to the pre-frozen bit position set.

[0274] (6-1) When M < K, let id = id-1, Z0 = Z0+2, and id0 = id0-2, then repeat step (3);

[0275] (7-1) When M > K, let Z0 = Z0-1, and then repeat step (3);

[0276] (8-1) When M=K, output Z0 and Z1.

[0277] If the first index is less than or equal to T (x0 = 0, x1 = 1), perform the following steps, where T is a positive integer:

[0278] (4-2) Read the id1th index in the first sequence to obtain the fourth index. Let M = M + d1. If the sum of the fourth index and N1 belongs to the set of pre-frozen bit positions, d1 = 0. Or, if the sum of the fourth index and N1 does not belong to the set of pre-frozen bit positions, d1 = 1.

[0279] (5-2) Read the id1-1th sequence number in the first sequence to obtain the fifth sequence number. Let M = M + d1'. If the fifth sequence number belongs to the pre-frozen bit position set, d1' = 0, or if the fifth sequence number does not belong to the pre-frozen bit position set, d1' = 1.

[0280] (6-2) When M < K, let id = id-1, Z1 = Z1+2, and id1 = id1-2, then repeat step (3);

[0281] (7-2) When M > K, let Z1 = Z1-1, and then repeat step (3);

[0282] (8-2) When M=K, output Z0 and Z1.

[0283] Optionally, the steps shown in process 3 above can also be performed by... Figure 7 The flowchart shown is illustrated. Here, the Q sequence represents the first sequence, meaning that in step (3), when reading the first sequence number for the first time, 1023 can be read as the first sequence number, and subsequent steps can be executed.

[0284] The above steps (4-1) and (5-1) can be replaced by: reading two sequences starting from the id0th sequence number of the first sequence number in descending order of reliability, and letting M = M + d0", where d0" is the number of sequences that do not belong to the pre-frozen bit position set among the two sequences read starting from the id0th sequence number of the first sequence number.

[0285] The above steps (5-2) and (6-2) can be replaced by: reading two sequences starting from the id1th sequence number of the first sequence number in descending order of reliability, and letting M = M + d1", where d1" is the number of sequences that do not belong to the pre-frozen bit position set among the two sequences read starting from the id1th sequence number of the first sequence number.

[0286] As can be seen, in process 3 above, each time a sequence number is read from the id-th index in the first sequence as the first index, and subsequent judgments are performed based on the first index. Optionally, some steps in process 3 above can be adaptively replaced to support reading multiple indexes from the first sequence each time and performing subsequent judgments based on the read multiple indexes. That is, it can be understood that multiple indexes can be read from the id-th index in the first sequence to determine Z0 and Z1 in parallel, thereby speeding up the determination of Z0 and Z1.

[0287] As an example of an implementation method for reading multiple serial numbers from the first sequence, step (3) in process 3 can also be replaced by: step (3'), reading X serial numbers starting from the id-th serial number of the first sequence in descending order of reliability, where X is an integer greater than 1. The number of values ​​greater than or equal to N1 / 2 among these X serial numbers is recorded as x0, and the number of values ​​less than N1 / 2 among these X serial numbers is recorded as x1. It is understandable that as the value of X increases, the first reliability serial number can be determined more quickly. After step (3'), steps (4-3) and (4-4) can be executed.

[0288] Step (4-3): Read 2x0 sequences starting from the id0th sequence number in the first sequence, in descending order of reliability. Let M = M + d0” + 2x1, where d0” represents the number of sequences among the 2x0 sequences that do not belong to the pre-frozen bit position set. M remains unchanged when x0 = 0.

[0289] Step (4-4): Starting from the idx-th index of the first sequence, read 2x1 indexes in descending order of reliability. Let M = M + d1" + 2x1, where d1" represents the number of indexes among the 2x1 read indexes that do not belong to the pre-frozen bit position set. M remains unchanged when x1 = 1.

[0290] After step (4-3) or step (4-4), the first device can execute step (7-3), step (8-3), or step (9-3) according to the relationship between M and K:

[0291] Step (7-3): When M < K, let id = id - X, id0 = id0 - 2x0, id1 = id1 - 2x1, Z0 = Z0 + 2x0, and Z1 = Z1 + 2x1. Then step (3') can be executed again.

[0292] Step (8-3): When M > K, let M = M - d0" - d1", and let X = 1. Then, read the idx-th sequence number of the first sequence according to X = 1. This can be understood as the first terminal rereading a sequence number from the idx-th sequence number in the first sequence when M > K. This can be done by referring to the steps of reading the first sequence number one by one and judging it. For example, after reading the idx-th sequence number of the first sequence number according to X = 1, this sequence number can be used as the first sequence number. The subsequent steps can be executed according to steps (4-1) to (8-1) or steps (4-2) to (8-2) in process 3.

[0293] Step (9-3): When M=K, output Z0 and Z1.

[0294] The above process 3 can be applied to scenarios using NR rate matching. Specifically, it determines the first reliability sequence number in NR rate matching scenarios, and then determines the information bits based on the first reliability sequence number. This is because the above implementation method is similar to the process of allocating information bits based on an N1-length reliability sequence and an N0-length reliability sequence when using NR rate matching. Therefore, this implementation method can be applied to NR rate matching scenarios, ensuring the corresponding communication performance of the information bits determined under NR rate matching.

[0295] The above processes 1, 2, and 3 are exemplary processes for determining the first reliability sequence number and should not be construed as representing all possible implementations.

[0296] As another example, it can be considered that there is a correspondence between at least one of the first sequence, N0, and / or K and the first reliability index. Therefore, the corresponding first reliability index can be determined based on this correspondence, according to at least one of the first sequence, N0, and / or K. In other words, the first reliability index is determined by at least one of the first sequence, N0, and / or K. The aforementioned correspondence can be predefined by a standard, preconfigured by the network, or determined by signaling between the first device and the second device.

[0297] S103: The first device determines the set of information bit positions based on the second sequence of length N1 and the first reliability number.

[0298] The second sequence includes N1 reliability indices, which are arranged by bit position. For example, the reliability indices in the second sequence can be sorted in ascending or descending order of bit reliability. Taking the reliability indices sorted by bit reliability from highest to lowest as an example, assuming the reliability of the four bit indices 0, 1, 2, and 3 are 0.9, 0.7, 0.3, and 0.5 respectively, the second sequence could be [0, 1, 3, 2]. This means that the reliability corresponding to bit indices 0 is the highest, the reliability corresponding to bit indices 1 is higher than that corresponding to bit indices 3, and the reliability corresponding to bit indices 3 is higher than that corresponding to bit indices 2.

[0299] Optionally, the second sequence can be called the Z sequence.

[0300] Optionally, the second sequence can be a sequence pre-stored offline or a sequence obtained from the first sequence; no limitation is made here. Since the second sequence is obtained from the first sequence, S103 can also be replaced by: the first device determining the information bit position set based on the first sequence and the first reliability number.

[0301] In step S103, the first device can determine the sequence number of the bit corresponding to the sequence number in the information bit position set based on the first reliability sequence number and the second sequence, and use it as the sequence number of the information bit. Specifically, the first device can determine the sequence number of one or more bits from the sequence number in the second sequence based on the first reliability sequence number and the second sequence, and determine the sequence number in the information bit position set based on the sequence number of the one or more bits.

[0302] As one possible implementation, if the reliability indices in the second sequence are sorted in descending order of reliability, then the K information bits include those with a reliability index less than or equal to Z in the i-th sequence. i The bits; or, if the reliability indices in the second sequence are sorted in ascending order of reliability, the K information bits include those whose reliability indices in the i-th sequence are greater than or equal to Z. i The bits. Wherein, the i-th sequence is the sequence obtained by adding i*N1 to the index of the bit corresponding to each reliability index in the second sequence, and then removing the index from the pre-frozen bit position set. Z i It can be 0 or a positive integer.

[0303] For example, assuming the reliability of the four bit numbers 0, 1, 2, and 3 are 0.9, 0.7, 0.3, and 0.5 respectively, the second sequence could be [0, 1, 3, 2]. Correspondingly, the first sequence obtained from the second sequence is [0, 1, 3, 2], representing the reliability order of bit numbers 4, 5, 6, and 7 as [0, 1, 3, 2]. The second sequence obtained from the second sequence is [0, 1, 3, 2], representing the reliability order of bit numbers 8, 9, 10, and 11 as [0, 1, 3, 2], and so on.

[0304] Taking process 1 above as an example, when N1 = N0 / 2 and the number of sequence numbers in the pre-frozen bit position set is 0, the first device can perform the following steps after determining Z0 and Z1:

[0305] (1) Based on the second sequence of length N1, read the Y reliability indices and the corresponding bit indices in the second sequence in reverse order of parallelism Y. The reverse order can also be replaced with a forward order. Repeat the above process N0 / 2 / Y times, traversing each element in the second sequence. Y is a positive integer.

[0306] (2) Determine the information bits and freeze bits according to the Y reliability numbers in the following manner:

[0307] (2-1) Compare the Y reliability indices with Z0, determine the reliability indices less than Z0, and use the indices of the bits corresponding to the reliability indices less than Z0 as the indices of the information bits in the information bit position set. Furthermore, determine the reliability indices greater than or equal to Z0 among the Y reliability indices, and use the indices of the bits corresponding to the reliability indices greater than or equal to Z0 as the indices of the frozen bits.

[0308] (2-2) Compare the Y reliability indices with Z1, determine the indices less than Z1, and use the sum of the indices of the bits corresponding to the reliability indices less than Z1 and N1 as the indices of the information bits in the information bit position set. Furthermore, determine the reliability indices greater than or equal to Z1 among the Y reliability indices, and use the sum of the indices of the bits corresponding to the reliability indices greater than or equal to Z1 and N1 as the indices of the frozen bits.

[0309] Steps (2-1) and (2-2) above can be executed synchronously or asynchronously, and there is no restriction here.

[0310] Taking process 2 or process 3 above as an example, when N1 = N0 / 2 and the number of sequence numbers in the pre-frozen bit position set is a positive integer, the first device can perform the following steps after determining Z0 and Z1:

[0311] (1) Based on the second sequence of length N1, read the Y reliability indices and the corresponding bit indices in the second sequence in reverse order of parallelism Y. The reverse order can also be replaced by the forward order. Repeat the above process N0 / 2 / Y times to traverse each element in the second sequence.

[0312] (2) Determine the information bits and freeze bits according to the Y reliability numbers in the following manner:

[0313] (2-1) Compare the bit indices corresponding to the Y reliability indices with the pre-frozen bit position set to determine whether the bit indices corresponding to the Y reliability indices can be used as indices in the information bit position set. Specifically, if the bit indices do not belong to the pre-frozen bits, they can be used as indices in the information bit position set; if the bit indices belong to the pre-frozen bits, they are not used as indices in the information bit position set. Further, remove the reliability indices from the Y reliability indices that are not used as indices in the information bit position set, and determine the reliability indices less than Z0 among the remaining reliability indices. Use the bit indices corresponding to these reliability indices as indices in the information bit position set. The remaining reliability indices greater than or equal to Z0 can be used as frozen bits.

[0314] (2-2) Compare the bit indices corresponding to the Y reliability indices with the sum of N1 and the pre-frozen bit position set to determine whether the sum of the corresponding bit indices and N1 can be used as the indices of information bits in the information bit position set. Further, remove the reliability indices from the Y reliability indices whose sum of the corresponding bit indices and N1 is not used as the reliability indices in the information bit position set, and determine the remaining reliability indices that are less than Z1. Use the sum of the bit indices corresponding to these reliability indices and N1 as the indices of information bits in the information bit position set. The sum of the bit indices corresponding to the remaining reliability indices that are greater than or equal to Z1 and N1 can be used as frozen bits.

[0315] Steps (2-1) and (2-2) above can be executed synchronously or asynchronously, and there is no restriction here.

[0316] As a possible implementation of the first device determining the set of information bit positions based on the first sequence and the first reliability index, the K information bits may include the Z bits with the highest reliability in the i-th sequence. i The first sequence consists of 10 bits. The i-th sequence is obtained by adding i*N1 to each index in the first sequence and then removing the index from the pre-frozen bit position set. The i-th sequence can be found in the explanation in S102, and will not be repeated here.

[0317] S104: The first device performs polar coding on the information bit sequence according to the information bit position set to obtain a polar-coded bit sequence of length N0.

[0318] Specifically, the information bit sequence in S101 can be sequentially filled into the information bit positions corresponding to the K sequence numbers in the information bit position set, and then polar coding can be performed. One possible implementation is that the first device can place information bits in the information bit position set and freeze bits in the remaining positions to obtain the bit sequence before encoding (e.g., in the relevant description of Figure 3(a)). Then, the bit sequence before encoding is polarized to obtain the bit sequence after encoding.

[0319] S105: The first device outputs the polarized encoded bit sequence.

[0320] In S105, the first device can output the polarized encoded bit sequence after operations such as rate matching and / or modulation.

[0321] In S105, "output" can refer to output via an air interface or output to other devices or modules via an internal interface of the device.

[0322] based on Figure 4 The method shown can implement polar coding of code length N0 based on a first sequence of length N1, where N1 < N0. Therefore, it can achieve polar coding of a longer code length based on a shorter reliability sequence while ensuring good communication performance. The first sequence can be a reliability sequence of length N1. It is evident that polar coding based on this implementation does not require storing a reliability sequence of length N0; only a reliability sequence of length N1, i.e., the first sequence, needs to be stored, thus reducing storage overhead.

[0323] It is understandable that the second device can determine the information bit set in the same manner as S102 to S102, and perform polarization decoding on the first sequence of information to be decoded based on the information bit set. For example... Figure 8 As shown, the second device can perform polarization decoding through the following steps:

[0324] S201: The second device acquires the information to be decoded.

[0325] The information to be decoded can also be called the sequence of symbols to be decoded. It can be understood that the information to be decoded in S201 corresponds to an encoded bit sequence of length N0, that is, the information to be decoded corresponds to the polar-coded bit sequence in S103. For example, the second device can determine that the length of the corresponding polar-coded bit sequence is N0 based on the length of the information to be decoded.

[0326] In one implementation method, the second device acquires the information to be decoded by receiving a physical signal over an air interface and obtaining the information by parsing the physical signal. Alternatively, the second device can acquire the information to be decoded locally through an internal interface, which can be obtained by parsing the physical signal from other local devices, apparatuses, or modules. The physical signal can carry the polar-coded bit sequence sent by the first device. The generation process of the polar-coded bit sequence can be referred to... Figure 4 The operation of the first device in the process is that the first device can generate a polar-coded bit sequence based on the information bit sequence.

[0327] In other words, as an example, the first device can send a physical signal to the second device, which carries the polar-coded bit sequence obtained in step S103. The second device receives the physical signal generated based on the polar-coded bit sequence, parses the physical signal, and obtains the information to be decoded. That is, the information to be decoded corresponds to the encoded bit sequence sent by the first device.

[0328] S202: The second device determines the first reliability number based on the first sequence of length N1, N0, and the information bit length K.

[0329] The method by which the second device determines the first reliability number in S202 can be found in the description of the method by which the first device determines the first reliability number in S102, and will not be repeated here.

[0330] Optionally, the first device and / or the second device may also determine the set of information bit positions based on signaling from the first device. This signaling may be an RRC message, MAC CE, or DCI sent between the first and second devices. For example, after determining the first reliability number in S102, the first device may send this signaling to the second device to indicate the first reliability number. Similarly, after determining the first reliability number in S202, the second device may send this signaling to the first device to indicate the first reliability number.

[0331] One example is that the indication information may include a first reliability sequence number. Another example is that the indication information may be an index of a set of information bits, which can be used to indicate the set of information bits from multiple sets of information bits. The correspondence between the multiple sets of information bits and the index may be predefined by a standard, preconfigured by the network, or determined by signaling between the first device and the second device.

[0332] S203: The second device determines the set of information bit positions based on the second sequence of length N1 and the first reliability number.

[0333] S203 can also be replaced by: The second device determines the set of information bit positions based on the first sequence and the first reliability number.

[0334] The method by which the second device determines the set of information bit positions can be found in the description in S103, and will not be repeated here.

[0335] Optionally, the first device and / or the second device may also determine the information bit location set based on signaling from the first device. This signaling may be an RRC message, MAC CE, or DCI sent between the first and second devices. For example, the first device may send the signaling to the second device after determining the information bit location set in S102 to indicate the information bit location set. Similarly, the second device may send the signaling to the first device after determining the information bit location set in S202 to indicate the information bit location set. One example is that the indication information may include the sequence number of the information bit. Another example is that the indication information may be an index of the information bit set, which can be used to indicate the information bit set from multiple information bit sets. The correspondence between the multiple information bit sets and the index may be predefined by a standard, preconfigured by the network, or determined by signaling between the first and second devices.

[0336] S204: The second device decodes the information to be decoded according to the set of information bit positions.

[0337] The second device can perform polar decoding on the information to be decoded based on the reliability sequence to obtain the decoding result. If the decoding is correct, the decoding result can be the information bit sequence in S101. This application does not limit the specific method of polar decoding performed by the second device. The decoded bit sequence obtained by polar decoding can be the information bit sequence in S101. Here, the reliability sequence can be the same as the reliability sequence used by the first device for polar encoding.

[0338] For example, the second device can determine the information bits and frozen bits based on the set of information bit positions. Further, decoding can be performed using methods such as SC, SCL, or belief propagation (BP) on the information to be decoded, estimating the value of each information bit based on the matching information to be decoded, to determine the decoding result. The decoding result can be a sequence of information bits.

[0339] Specifically, taking SCL decoding as an example, there are multiple decoding paths in the decoding path tree. The same input information corresponds to different symbol sequences in different decoding paths. For example, a symbol sequence can be understood as the information to be decoded corresponding to the input information in one path. The second device can compare the multiple symbol sequences of multiple input information in multiple decoding paths with the information to be decoded in S201 to determine the symbol sequence with the highest similarity. The input information corresponding to the symbol sequence with the highest similarity can be used as the decoding result, that is, as the information bit sequence obtained by decoding.

[0340] In this embodiment, the reliability sequence contains N indices starting from 0 and ending at N-1, as an example. These N indices represent the indices of N sub-channels. In practice, the indices of the N sub-channels can also start from 1 and end at N; simply add 1 to each indices in the above sequence. This is also the indices format used in the calculation methods described above. Of course, other methods can also be used to represent the indices or identifiers of the sub-channels; this specific representation does not affect the specific position of the sub-channels represented in the sequence.

[0341] It should be noted that the sequences or methods of determining sequences shown in this application are merely examples, and their application in the Polar encoding process can help improve the encoding and decoding performance of Polar codes, such as supporting longer Polar codes. In any of the example sequences, adjustments or equivalent substitutions can be made, including but not limited to the following, without affecting the overall effect:

[0342] 1. The positions of a few numbers in the sequence can be interchanged. For example, the position of the number can be adjusted within a set range. For instance, if the set range is 5, the position of the number 10 can be adjusted within 5 positions to the left or right.

[0343] 2. Some sequence number values ​​in the sequence are adjusted, but the set of channels selected based on the sequence for transmitting information bit sequences is consistent or similar.

[0344] 3. The sequence contains N indices starting from 0 and ending at N-1, representing the indices of N sub-channels. In practice, the indices of the N sub-channels can also start from 1 and end at N; simply add 1 to each indice in the above sequence, which is the indices format used in the calculation methods described above. Of course, other methods can also be used to represent the indices or identifiers of the sub-channels; this specific representation does not affect the specific positions of the sub-channels represented in the sequence. The indices of the sub-channels can be the position numbers or position indices of the bits to be encoded.

[0345] 4. The N sub-channel numbers in the above sequence are arranged in ascending order of reliability. Selecting K sub-channels from high to low reliability is equivalent to selecting the sub-channels corresponding to the last K numbers in any of the above sequences. In fact, the N sub-channel numbers can also be arranged in descending order of reliability by reversing or reversing the order of the numbers in the above sequence. In this case, selecting K sub-channels from high to low reliability is equivalent to selecting the sub-channels corresponding to the first K numbers.

[0346] 5. The above sequence can also be characterized using the normalized reliability or equivalent reliability sequence of each channel. For example, if a channel is in the order n of the above sequence (the leftmost one is denoted as 1), then the reliability of the channel can be expressed as n or normalized n / N, where N is the length of the sequence.

[0347] In the embodiments of this application, "transmission" includes "output" and / or "input". "Output" and "input" represent the direction of signal transmission. For example, "outputting information to XX" can be understood as the destination of the information being XX, which may include directly sending information via an air interface or other interface, or indirectly sending information from other units or modules. "Inputting information from YY" can be understood as the source of the information being YY, which may include directly receiving information from YY via an air interface or other interface, or indirectly inputting information from YY from other units or modules. "Output" can also be understood as "sending" through a chip interface, and "input" can also be understood as "receiving" through a chip interface. In other words, output and input can occur between devices, for example, between an access network node and a terminal. Output and input can also occur within a device, for example, sending or receiving information between components, modules, chips, software modules, or hardware modules within the device via a bus, wiring, or interface.

[0348] It is understood that the first device mentioned above can be a terminal, a chip (or other component) in the terminal, and the second device can be a base station or a chip (or other component (such as CU, DU, or RU) in the base station). Alternatively, the second device can be a terminal, a chip (or other component) in the terminal, and the first device can be a base station or a chip (or other component (such as CU, DU, or RU) in the base station).

[0349] It is understood that, in order to achieve the functions in the above embodiments, the terminal device or network device includes hardware structures and / or software modules corresponding to perform each function. Those skilled in the art should readily recognize that, based on the units and method steps of the various examples described in conjunction with the embodiments disclosed in this application, this application can be implemented in the form of hardware, computer software, or a combination of hardware and computer software. Whether a function is executed by hardware or by computer software driving hardware depends on the specific application scenario and design constraints of the technical solution.

[0350] Figure 9 and Figure 10 The diagram illustrates the possible structures of communication devices provided in the embodiments of this application. These communication devices can be used to implement the functions of the first or second device in the above method embodiments, and thus can also achieve the beneficial effects of the above method embodiments. In the embodiments of this application, the communication device can be a terminal device or a network device, or it can be a module (such as a chip) applied to a terminal device or a network device.

[0351] Figure 9 The communication device 900 shown includes a processing unit 910 and a transceiver unit 920. The communication device 900 is used to implement the functions of the first or second device in the above method embodiments. For example, the functions of the first device can be found in [reference needed]. Figure 4 For a description of the relevant content, please refer to the description of the function of the second device. Figure 8 Description of the relevant content.

[0352] When the communication device 900 is used to implement the function of the first device in the above method embodiment, the processing unit 910 and / or the transceiver unit 920 can be used to acquire the information bit sequence. The processing unit 910 and / or the transceiver unit 920 can also be used to determine a first reliability index based on the first sequence code length N0 of length N1 and the information bit sequence length K, determine the information bit position set based on the second sequence of length N1 and the first reliability index, and perform polar coding on the information bit sequence based on the information bit position set to obtain the polar-coded bit sequence. The transceiver unit 920 can also be used to output the polar-coded bit sequence.

[0353] When the communication device 900 is used to implement the function of the second device in the above method embodiment, the processing unit 910 and / or the transceiver unit 920 can be used to obtain the information to be decoded. The processing unit 910 and / or the transceiver unit 920 can also be used to determine the first reliability index according to the first sequence code length N0 of length N1 and the information bit sequence length K, determine the information bit position set according to the second sequence of length N1 and the first reliability index, and decode the information to be decoded according to the information bit position set to obtain the decoded bit sequence.

[0354] For a more detailed description of the processing unit 910 and the transceiver unit 920, please refer directly to the relevant descriptions in the above method embodiments, which will not be repeated here.

[0355] Figure 10 The communication device 1000 shown includes a processor 1010 and an interface circuit 1020. The processor 1010 and the interface circuit 1020 are coupled to each other. It is understood that the interface circuit 1020 can be a transceiver or an input / output interface. Optionally, the communication device 1000 may also include a memory 1030 for storing instructions executed by the processor 1010, or storing input data required by the processor 1010 to execute instructions, or storing data generated after the processor 1010 executes instructions.

[0356] When the communication device 1000 is used to implement the above method embodiment, the processor 1010 is used to implement the function of the processing unit 910, and the interface circuit 1020 is used to implement the function of the transceiver unit 920.

[0357] It is understood that the processor in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), microprocessors without interlocked piped stages architecture (MIPS), advanced instruction set computers (RISC) machines (ARM), network processors (NPs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor or any conventional processor.

[0358] The method steps in the embodiments of this application can be implemented in hardware or by a processor executing software instructions. The software instructions can consist of corresponding software modules, which can be stored in random access memory, flash memory, read-only memory, programmable read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, hard disks, portable hard disks, compact disc read-only memory (CD-ROM), or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and storage medium can reside in an ASIC. Furthermore, the ASIC can reside in a first device or a second device. Alternatively, the processor and storage medium can exist as discrete components in the first device or the second device.

[0359] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer programs or instructions. A computer program is a set of instructions that instruct an electronic computer or other device having a first or second device to perform any step of its operation. It is typically written in a programming language and runs on a target architecture. When the computer program or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of this application are performed, in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer program or instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, the computer program or instructions can be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a digital video optical disc; or it can be a semiconductor medium, such as a solid-state drive. The computer-readable storage medium can be volatile or non-volatile, or it can include both types of storage media.

[0360] Based on the same technical concept, embodiments of this application also provide a computer-readable storage medium, including a program or instructions, which, when run on a computer, cause the methods in the above method embodiments to be executed.

[0361] Based on the same technical concept, embodiments of this application also provide a computer program product, including instructions that, when run on a computer, cause the methods in the above method embodiments to be executed.

[0362] Based on the same technical concept, embodiments of this application also provide a communication system, which may include a first device and a second device. In this communication system, the first device and the second device may be respectively used to implement… Figure 4 and Figure 8 The method flow is described in the text. As an example, the first device can be a terminal, and the second device can be a network device (such as a base station). As another example, the first device can be a network device, and the second device can be a terminal.

[0363] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0364] In the various embodiments of this application, unless otherwise specified or in case of logical conflict, the terminology and / or descriptions of different embodiments are consistent and can be referenced by each other. The technical features of different embodiments can be combined to form new embodiments according to their inherent logical relationship.

[0365] In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. In the textual description of this application, the character " / " generally indicates an "or" relationship between the preceding and following related objects; in the formulas of this application, the character " / " indicates a "division" relationship between the preceding and following related objects.

[0366] It is understood that the various numerical designations used in the embodiments of this application are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application. The order of the process numbers described above does not imply the order of execution; the execution order of each process should be determined by its function and internal logic.

Claims

1. A communication method, characterized in that, include: Obtain a bit sequence of length K, where K is a positive integer; The first reliability index is determined based on the first sequence of length N1, the code length N0, and K. The first sequence includes the indexes of N1 bits. The indexes of the bits in the first sequence are sorted according to the reliability of the bits. N1 is a positive integer, N0 is a positive integer, and N1 is less than N0. The information bit position set is determined based on a second sequence of length N1 and the first reliability index. The second sequence includes N1 reliability indices, which are arranged according to the bit position. The information bit position set includes the indices of K information bits. The information bit sequence is polar-coded according to the information bit position set to obtain a polar-coded bit sequence of length N0; Output the polarized encoded bit sequence.

2. A communication method, characterized in that, include: Obtain the information to be decoded, which corresponds to an encoded bit sequence of length N0, where N0 is a positive integer; A first reliability index is determined based on a first sequence of length N1, N0, and information bit length K. The first sequence includes the indexes of N1 bits, and the indexes of the bits in the first sequence are sorted according to the reliability of the bits. N1 is a positive integer, N0 is a positive integer, and N1 is less than N0. The information bit position set is determined based on a second sequence of length N1 and the first reliability index. The second sequence includes N1 reliability indices, which are arranged according to the bit index. The information bit position set includes K information bit indices. The information to be decoded is decoded based on the set of information bit positions.

3. The method as described in claim 1 or 2, characterized in that, The first reliability number is Z i i = 0, 1, ..., m-1 Represents rounding down; The K information bits include the Z bits with the highest reliability in the i-th sequence. i The i-th sequence is obtained by adding i*N1 to each index in the first sequence and then removing the index from the pre-frozen bit position set.

4. The method as described in claim 3, characterized in that, The i = 0, 1; The first reliability index includes the number of indexes less than or equal to N1 / 2 among the K / 2 indexes with the highest reliability in the first sequence, which is 2*Z0, and / or the number of indexes greater than N1 / 2 among the K / 2 indexes with the highest reliability in the first sequence, which is 2*Z1.

5. The method as described in claim 3 or 4, characterized in that, Where i = 0, 1, N1 and N0 satisfy: N1 = N0 / 2, the first reliability index includes Z0 and Z1, and the step of determining the first reliability index of the information bit position based on the first sequence of length N1, code length N0 and K includes: Let id = N1-1, Z0 = 0, and Z1 = 0; Perform the following steps until the sum of Z0 and Z1 equals K: Read the id-th sequence number from the first sequence to obtain the first sequence number; If the first sequence number is less than or equal to N1 / 2, let Z0 = Z0 + 2; If the second sequence number is greater than N1 / 2, let Z1 = Z1 + 2; exist In this case, let id = id - 1; exist If K is odd, read the (id-1)th index from the first sequence to obtain the second index. If the second index is less than or equal to N1, let Z0 = Z0 + 1. If the second index is greater than N1, let Z1 = Z1 + 1.

6. The method as described in claim 3 or 4, characterized in that, The K / 2 most reliable sequence numbers in the first sequence do not include the sequence numbers in the pre-frozen bit position set, wherein the pre-frozen bit position set includes the sequence numbers of the pre-frozen bits, and the pre-frozen bits are determined according to the length E of the polar-coded bit sequence after rate matching, wherein E is a positive integer.

7. The method as described in any one of claims 3, 4, and 6, characterized in that, The K information bits include k from the i-th sequence. i 1 bit, where i = 0, 1; N1 = N0 / 2, wherein determining the first reliability index based on the first sequence of length N1, the code length N0, and K includes: Let id = N1-1, idx = id, M = 0, Z0 = 0, and Z1 = 0, where M is the number of information bit positions in the information bit position set; When the rate matching mode is punched, perform the following steps until M equals K: Read the id-th sequence number from the first sequence to obtain the first sequence number; If the first sequence number is less than or equal to T, read the idx-th sequence number from the first sequence to obtain the second sequence number. Let M = M + d0, where d0 = 0 if the second sequence number belongs to the pre-frozen bit position set, or d0 = 1 if the second sequence number does not belong to the pre-frozen bit position set; read the idx-1-th sequence number from the first sequence to obtain the third sequence number. Let M = M + d0', where d0' = 0 if the third sequence number belongs to the pre-frozen bit position set, or d0' = 1 if the third sequence number does not belong to the pre-frozen bit position set, where T is a positive integer; let idx = idx-2; or... If the first sequence number is greater than T, let M = M + 2; In the case where M < K, let id = id-1 and Z0 = Z0+2; If M > K, and the third sequence number is less than or equal to T, then let Z0 = Z0-1; if the third sequence number is greater than T, then let Z1 = Z1-1. or, When the rate matching mode is shortened, perform the following steps until M equals K: Read the id-th sequence number from the first sequence to obtain the first sequence number; If the first sequence number is less than or equal to T, let M = M + 2; If the first sequence number is greater than T, read the idx-th sequence number in the first sequence to obtain the fourth sequence number. Let M = M + d1. If the sum of the fourth sequence number and N1 belongs to the pre-frozen bit position set, d1 = 0; or if the sum of the fourth sequence number and N1 does not belong to the pre-frozen bit position set, d1 = 1. Read the idx-1-th sequence number in the first sequence to obtain the fifth sequence number. Let M = M + d1'. If the sum of the fifth sequence number and N1 belongs to the pre-frozen bit position set, d1' = 0; or if the sum of the fifth sequence number and N1 does not belong to the pre-frozen bit position set, d1' = 1. Let idx = idx-2. In the case where M < K, let id = id-1 and let Z1 = Z1 + 2x1; If M > K, and the fifth sequence number is less than or equal to T, then let Z0 = Z0-1; if the fifth sequence number is greater than T, then let Z1 = Z1-1.

8. The method according to any one of claims 3, 4, and 6, characterized in that, The K information bits include k from the i-th sequence. i 1 bit, where i = 0, 1; N1 = N0 / 2, wherein determining the first reliability index based on the first sequence of length N1, the code length N0, and K includes: Let id = N1-1, id0 = id, id1 = id, M = 0, Z0 = 0, and Z1 = 0, where M is the number of information bit positions in the information bit position set; Perform the following steps until M equals K: Read the id-th sequence number from the first sequence to obtain the first sequence number; If the first sequence number is less than or equal to T (x0 = 1, x1 = 0), perform the following steps, where T is a positive integer: Read the id0th index from the first sequence to obtain the second index, and let M = M + d0, where d0 = 0 if the second index belongs to the pre-frozen bit position set, or d0 = 1 if the second index does not belong to the pre-frozen bit position set; read the id0-1th index from the first sequence to obtain the third index, and let M = M + d0', where d0' = 0 if the third index belongs to the pre-frozen bit position set, or d0' = 1 if the third index does not belong to the pre-frozen bit position set; In the case of M < K, let id = id-1, where Z0 = Z0+2 and id0 = id0-2; When M > K, let Z0 = Z0-1; or, If the first index is greater than T (x0 = 0, x1 = 1), perform the following steps, where T is a positive integer: Read the id1-th index from the first sequence to obtain the fourth index. Let M = M + d1. If the sum of the fourth index and N1 belongs to the pre-frozen bit position set, d1 = 0; or if the sum of the fourth index and N1 does not belong to the pre-frozen bit position set, d1 = 1. Read the (id1-1)-th index from the first sequence to obtain the fifth index. Let M = M + d1'. If the fifth index belongs to the pre-frozen bit position set, d1' = 0; or if the fifth index does not belong to the pre-frozen bit position set, d1' = 1. In the case of M < K, let id = id-1, then Z1 = Z1 + 2, and id1 = id1 - 2; If M > K, let Z1 = Z1-1.

9. The method as described in claim 7 or 8, characterized in that, The value of T is equal to N1 / 4.

10. The method according to any one of claims 3-9, characterized in that, When E is less than or equal to N0 and K / E is less than or equal to the first threshold, the pre-frozen bit position set corresponds to the index of the first (N0-E) bits of the first bit sequence. When E is less than or equal to N0 and K / E is greater than the first threshold, the pre-frozen bit position set corresponds to the index of the last (N0-E) bits of the first bit sequence. Wherein, the first bit sequence is a bit sequence of length N0, wherein the indices in the bit sequence of length N0 are 0, 1, ..., N0-1, and the bit sequence of length N0 is sorted in ascending order of bit indices; or, The first bit sequence is a sequence obtained by interleaving the bit sequence of length N0 with sub-blocks.

11. The method according to any one of claims 3-9, characterized in that, The pre-frozen bit position set is determined based on N0 and the first bit sequence number set, which is determined based on N1. Where E*N1 / N0 is less than or equal to N1 and K / E is less than or equal to the first threshold, the first bit sequence number set corresponds to the first (N1-E*N1 / N0) bits of the second bit sequence number; or, When E*N1 / N0 is less than or equal to N1 and K / E is greater than the first threshold, the first bit sequence number set corresponds to the last (N1-E*N1 / N0) bits of the second bit sequence number. Wherein, the second bit sequence is a bit sequence of length N1, wherein the indices in the bit sequence of length N1 are 0, 1, ..., N1-1, and the bit sequence of length N1 is sorted in ascending order of bit indices; or, The second bit sequence is a sequence obtained by interleaving the bit sequence of length N1 with sub-blocks.

12. The method according to any one of claims 1-6, characterized in that, The step of determining the first reliability index based on the first sequence of length N1, the code length N0, and K includes: The first reliability index is determined according to the first correspondence relationship, which includes the correspondence between N1, N0, K and the first reliability index.

13. The method according to any one of claims 1-12, characterized in that, The step of determining the information bit position set based on the second sequence of length N1 and the first reliability index includes: The information bit number is determined as the number of the information bit in the second sequence whose reliability index is less than Z0. The information bit number is determined by the sum of the reliability index of the second sequence and the index of Z1, which is less than that of N1.

14. The method according to any one of claims 1-13, characterized in that, The N1 is equal to N0 / 2 p p is a positive integer.

15. A communication device, characterized in that, Includes units or modules for performing the method as described in any one of claims 1-14.

16. A communication device, characterized in that, Includes a processor for executing computer programs or instructions to implement the method as described in any one of claims 1-14.

17. A computer-readable storage medium, characterized in that, The storage medium stores a computer program or instructions, and when the computer program or instructions are executed by a communication device, the method as described in any one of claims 1-14 is implemented.

18. A computer program product, characterized in that, When the computer program product is executed by a computer, the computer performs the method as described in any one of claims 1-14.

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