A data processing method, apparatus and system

Abstract

The embodiment of the application discloses a data processing method, device and system. The scheme has good error correction performance and strong burst resistance, and has low baud rate, low device bandwidth, simple realization, low power consumption, low cost, and can be applied to short distance transmission DCI or DCN transmission scene with low power consumption and cost. Specifically, the sending end performs FEC encoding on the RS encoded first data stream to obtain m second data streams. Wherein, m is a positive integer multiple of 4, the code word after FEC encoding includes 127 bits, and the 127 bits of the code word are obtained by performing FEC encoding on 120 information bits. Further, the sending end performs DP-16QAM symbol mapping and framing on the m second data streams to obtain a DP-16QAM symbol stream. Wherein, the 127 DP-16QAM symbols in the DP-16QAM symbol stream are obtained by performing DP-16QAM symbol mapping on 8 code words in the m second data streams.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a data processing method, apparatus and system. Background Technology

[0002] Driven by technologies such as 5G, cloud computing, big data, and artificial intelligence, high-speed optical transmission networks are developing towards higher capacity, packetization, and intelligence. Optical communication systems utilize the amplitude, phase, polarization, or frequency of light waves to carry information. Forward error correction (FEC) coding is used to correct transmission errors, allowing the receiver to recover the original data sent by the transmitter from the received data. A cascaded FEC transmission scheme is proposed, where the transmitting device and the transmitting processing module are connected via a connection unit interface. The transmitting device performs a first FEC encoding on the data to be transmitted and sends the first FEC-encoded data to the transmitting processing module. The transmitting processing module then performs a second FEC encoding on the first FEC-encoded data, performs symbol mapping on the bit sequence resulting from the second FEC encoding to generate a corresponding modulation symbol sequence, and finally generates an optical signal based on the modulation symbol sequence and transmits it to the receiver via optical fiber. For example, in the 800LR (a coherent optical communication standard for 10-kilometer transmission distance and 800 gigabits per second (Gbps) Ethernet services) defined by the Optical Internetworking Forum (OIF), the first FEC encoding uses Reed-Solomon (RS) encoding, i.e., RS(544,514), and the second FEC encoding uses Bose-Chaudhuri-Hocquenghem (BCH) encoding, i.e., BCH(126,110). The symbol mapping uses dual-polarization (DP) hexadecimal quadrature amplitude modulation (QAM), i.e., DP-16QAM.

[0003] In addition, coherent optical communication systems typically frame the modulation symbol sequence, adding multiple pre-designed symbols to enable the receiver to better recover the symbols transmitted by the transmitter. For example, in 800LR, the dual-polarization symbol stream to be transmitted contains multiple data frames, each containing 6144 DP-16QAM symbols, of which 6048 are payload symbols and 96 are pilot symbols. Within each data frame, 64 consecutive DP-16QAM symbols contain one pilot symbol and 63 payload symbols. The first symbol in each data frame is the pilot symbol. Here, the pilot symbol is used not only for carrier phase recovery but also for link training and frame boundary acquisition (also known as frame synchronization or frame alignment). The baud rate (Bd) corresponding to the coding, interleaving, mapping, and framing scheme defined by 800LR is approximately 850 × (126 / 110) × (64 / 63) / 8 ≈ 123.6 Gbps.

[0004] For next-generation, higher-speed coherent transmission scenarios, such as 1.6 terabits per second (Tbps), using the existing 800LR encoding, interleaving, mapping, and framing scheme results in a baud rate of approximately 247.2 Gbps, which is very high. This requires high-bandwidth devices, leading to high costs and power consumption, and is not conducive to shorter-distance transmissions such as 10 km or 2 km. Existing FEC encoding and interleaving schemes for coherent transmission are mainly applied to 800 Gbps scenarios and do not consider the need for compatibility with next-generation rates (such as 1.6 Tbps, 3.2 Tbps, etc.), which is an urgent problem to be solved in the future. Summary of the Invention

[0005] This application provides a data processing method, apparatus, and system. The solution exhibits good error correction performance and strong burst resistance. Its low baud rate results in lower required device bandwidth, making it simple to implement, power-efficient, and cost-effective. It can be applied to short-distance data center interconnect (DCI) or data center network (DCN) transmission scenarios requiring low power consumption and cost.

[0006] Firstly, this application provides a data processing method applied at a transmitting end. Specifically, the transmitting end performs forward error correction (FEC) encoding on multiple first data streams encoded with Reed-Solomon (RS) to obtain m second data streams. Here, m is a positive integer multiple of 4, and the codeword encoded by the FEC comprises 127 bits, which are obtained by encoding 120 information bits using the FEC. Furthermore, the transmitting end performs dual-polarization 16quadrature amplitude modulation (DP-16QAM) symbol mapping and framing on the m second data streams to obtain one DP-16QAM symbol stream. As one possible implementation, the 127 DP-16QAM symbols in the DP-16QAM symbol stream are obtained by mapping the 8 codewords in the m second data streams through DP-16QAM symbols. In other words, any one of the 127 DP-16QAM symbols is obtained by mapping 8 bits out of the 1016 bits of the 8 codewords through DP-16QAM symbols.

[0007] In this implementation, for next-generation coherent transmission scenarios with higher rates such as 1.6 terabits per second (Tbps), the inner code encoding of the concatenated FEC coding can adopt Hamming (127,120) codes. Assuming the existing 800LR data frame uses a scheme where 64 consecutive DP-16QAM symbols contain one pilot symbol and 63 payload symbols, the corresponding baud rate is 1700×(127 / 120)×(64 / 63) / 8≈228.5 Gbd, which is lower than the baud rate (247.2 Gbd) of directly multiplexing the existing 800LR coding and framing scheme. This allows for the use of lower bandwidth devices, resulting in lower cost and power consumption. Furthermore, the 1016 bits of the mapped 127 DP-16QAM symbols are exactly 8 codewords from m second data streams, making the hardware implementation cost lower. Of course, other implementations exist. For example, these 1016 bits may also come from 9 or more codewords in m second data streams, meaning that some bits in some codewords do not belong to these 1016 bits. Compared with other implementations, the "1016 bits of the 127 DP-16QAM symbols mapped to exactly 8 codewords in m second data streams" proposed in this application is simpler to implement and consumes less power, which is beneficial for application in power-sensitive DCI or DCN transmission scenarios.

[0008] In some possible implementations, the DP-16QAM symbol stream includes at least one data frame. Each of these data frames contains 128 consecutive DP-16QAM symbols, including one pilot symbol and 127 payload symbols. These 127 payload symbols are obtained by mapping 8 codewords from the m second data streams using DP-16QAM symbols. In other words, the 127 DP-16QAM symbols obtained by mapping 8 codewords from the m second data streams using DP-16QAM symbols can be used as the 127 payload symbols from the 128 consecutive DP-16QAM symbols in the data frame. Only one pilot symbol needs to be added for transmission. This eliminates the need for additional buffering to store the payload symbols during framing, resulting in a simple implementation and low power consumption. It should be understood that both the pilot symbol and the payload symbol refer to dual-polarization symbols, containing symbols in two polarization directions.

[0009] In some possible implementations, each data frame includes 96 pilot symbols and 12,192 payload symbols. The 96 pilot symbols of the existing 800LR can be reused for compatibility with 800LR implementations.

[0010] In some possible implementations, the eight codewords include two codewords from each of the four second data streams, providing stronger resistance to burst attacks.

[0011] In some possible implementations, 2 bits from 2 codewords in each of the 4 second data streams, totaling 8 bits, are mapped using DP-16QAM symbols to obtain 1 DP-16QAM symbol. This ensures that the 8 bits of the mapped DP-16QAM symbol can be more evenly distributed from the 2 codewords in each of the 4 second data streams, which helps to reduce hardware implementation costs.

[0012] In some possible implementations, the z-th bit and the (z+1)-th bit (a total of 8 bits) from the two codewords in each of the four second data streams are mapped using DP-16QAM symbols to obtain one DP-16QAM symbol, where 0 ≤ z ≤ 252, and z is an even number. In this application, 0 is also an even number; for example, z = 0, 2, 4, ..., 252. This is equivalent to sequentially selecting two consecutive bits from the two codewords in each of the four second data streams for DP-16QAM symbol mapping, which facilitates hardware implementation.

[0013] In some possible implementations, the two codewords in each of the m second data streams constitute a bit set. The m bit sets from the m second data streams are mapped using DP-16QAM symbols to obtain M DP-16QAM symbols, where M = 254 × m / 8. The mapping represents the 8 bits of the i-th DP-16QAM symbol among the M DP-16QAM symbols. 0≤i≤M-1, the m second data streams include second data stream 0 to second data stream m-1.

[0014] It should be understood that the m second data streams are counted starting from 0. Second data stream 0 is the 0th second data stream in the m second data streams, second data stream 1 is the 1st second data stream in the m second data streams, and so on. The m bit sets of the m second data streams are also counted starting from 0. Bit set 0 is the bit set of the 0th second data stream in the m second data streams (also called the 0th bit set), bit set 1 is the bit set of the 1st second data stream in the m second data streams (also called the 1st bit set), and so on. 8 bits It also starts counting from 0, bits. It is the 0th bit out of 8 bits. It is the first bit out of 8 bits, and so on.

[0015] The following conditions must be met:

[0016] From the second data stream The 2nd × (i % 127) + i % 2nd bit in the bit set;

[0017] From the second data stream The 2nd × (i % 127) + (i + 1) % 2nd bit in the bit set;

[0018] From the second data stream The 2nd × (i % 127) + i % 2nd bit in the bit set;

[0019] From the second data stream The 2nd × (i % 127) + (i + 1) % 2nd bit in the bit set;

[0020] From the second data stream The 2nd × (i % 127) + i % 2nd bit in the bit set;

[0021] From the second data stream The 2nd × (i % 127) + (i + 1) % 2nd bit in the bit set;

[0022] From the second data stream The 2nd × (i % 127) + i % 2nd bit in the bit set;

[0023] From the second data stream The 2nd (i%127)+(i+1)%2th bit in the bit set.

[0024] In some possible implementations, the eight codewords include one codeword from each of the eight second data streams, where m is a positive integer multiple of 8, resulting in lower latency.

[0025] In some possible implementations, 504 bits from four of the eight codewords are mapped using DP-16QAM symbols to obtain 63 DP-16QAM symbols. This means that exactly 504 bits out of the 508 bits in these four codewords can be mapped using DP-16QAM symbols to obtain 63 DP-16QAM symbols. Similarly, 504 bits from the other four codewords are mapped using DP-16QAM symbols to obtain 63 DP-16QAM symbols. The remaining 4 bits from 4 out of the 8 codewords, along with the remaining 4 bits from the other 4 out of the 8 codewords (a total of 8 bits), are mapped using DP-16QAM symbols to obtain one DP-16QAM symbol. This is equivalent to mapping the remaining 4 bits from the 508 bits of the 4 codewords and the remaining 4 bits from the 508 bits of the other 4 codewords together to obtain one DP-16QAM symbol. In other words, except for the 8 bits used to map one DP-16QAM symbol which come from each of the 8 second data streams, the 8 bits used to map the other DP-16QAM symbols can be distributed relatively evenly from one codeword in each of the 4 second data streams, which helps reduce hardware implementation costs.

[0026] In some possible implementations, the c-th bit and the (c+1)-th bit (a total of 8 bits) of each of four of the eight codewords are mapped using DP-16QAM symbols to obtain one DP-16QAM symbol, where 0 ≤ c ≤ 124, and c is an even number. In this application, 0 is also an even number; for example, c = 0, 2, 4, ..., 124. The 126-th bit of each of the four of the eight codewords and the 0-th bit of each of the other four codewords (a total of 8 bits) are mapped using DP-16QAM symbols to obtain one DP-16QAM symbol. The t-th bit and the (t+1)-th bit (a total of 8 bits) of each of the other four codewords are mapped using DP-16QAM symbols to obtain one DP-16QAM symbol, where 1 ≤ t ≤ 125, and t is an odd number. This is equivalent to first selecting two consecutive bits from one codeword in each of the four of the eight second data streams for DP-16QAM symbol mapping, then performing DP-16QAM symbol mapping on the remaining bit (the 126th bit) of one codeword from each of the four of the eight second data streams, combined with the first bit (the 0th bit) of one codeword from each of the other four of the eight second data streams, for a total of eight bits. Then, performing DP-16QAM symbol mapping on these eight bits, and finally selecting two consecutive bits from one codeword in each of the other four of the eight second data streams for DP-16QAM symbol mapping. This facilitates hardware implementation.

[0027] In some possible implementations, the m second data streams comprise m / 2 bit sets, each bit set comprising 2 codewords, the m codewords in the m / 2 bit sets originating from the m second data streams, and the m / 2 bit sets are mapped using DP-16QAM symbols to obtain M DP-16QAM symbols, where M = 127 × m / 8. The mapping represents the 8 bits of the i-th DP-16QAM symbol among the M DP-16QAM symbols. 0≤i≤M-1.

[0028] It should be understood that the m second data streams are counted starting from 0. Second data stream 0 is the 0th second data stream out of the m second data streams, second data stream 1 is the 1st second data stream out of the m second data streams, and so on. The m / 2 bit set is also counted starting from 0. Bit set 0 is the 0th bit set out of the m / 2 bit set, bit set 1 is the 1st bit set out of the m / 2 bit set, and so on. 8 bits It also starts counting from 0, bits. It is the 0th bit out of 8 bits. It is the first bit out of 8 bits, and so on.

[0029] The following conditions must be met:

[0030] From the The 2nd (i%127)+i%2th bit in the set of bits;

[0031] From the The 2nd × (i % 127) + (i + 1) % 2nd bit in the set of bits;

[0032] From the The 2nd (i%127)+i%2th bit in the set of bits;

[0033] From the The 2nd × (i % 127) + (i + 1) % 2nd bit in the set of bits;

[0034] From the The 2nd (i%127)+i%2th bit in the set of bits;

[0035] From the The 2nd × (i % 127) + (i + 1) % 2nd bit in the set of bits;

[0036] From the The 2nd (i%127)+i%2th bit in the set of bits;

[0037] From the The 2nd (i%127)+(i+1)%2th bit in the set of bits.

[0038] In some possible implementations, the m second data streams include second data stream 0 to second data stream m-1, and the bit set k in the m / 2 bit set includes two codewords that each come from a second data stream. Second data stream

[0039] In some possible implementations, the m second data streams include second data stream 0 to second data stream m-1, and the bit set k in the m / 2 bit set includes two codewords that each come from a second data stream. Second data stream

[0040] In some possible implementations, the 120 information bits are cyclically shifted before or after the FEC encoding, which helps to improve the burst resistance of the overall cascaded FEC.

[0041] In some possible implementations, before the FEC encoding, the multiple first data streams undergo convolutional interleaving, and the 120 information bits correspond to 12 RS symbols, which are derived from 12 RS codewords, thus improving the overall encoding performance.

[0042] In some possible implementations, the multiple first data streams are first convolutionally interleaved, then FEC encoded, and then cyclically shifted. Alternatively, the multiple first data streams are first convolutionally interleaved, then cyclically shifted, and then FEC encoded.

[0043] In some possible implementations, m is a positive integer multiple of 8, such as 8, 16, 32, or 64. Alternatively, m is a positive integer multiple of 4, such as 12 or 20.

[0044] Secondly, this application provides a data processing method applied at a receiving end. Specifically, the receiving end receives one DP-16QAM symbol stream. The one DP-16QAM symbol stream is obtained by mapping and framing m second data streams using DP-16QAM symbols. The m second data streams are obtained by FEC encoding multiple first data streams encoded using RS, where m is a positive integer multiple of 4. The codewords encoded using FEC consist of 127 bits, which are obtained by encoding 120 information bits using FEC. As a possible implementation, the 127 DP-16QAM symbols in the DP-16QAM symbol stream are obtained by mapping 8 codewords from the m second data streams using DP-16QAM symbols. That is, any one of the 127 DP-16QAM symbols is obtained by mapping 8 bits out of the 1016 bits of the 8 codewords using DP-16QAM symbols.

[0045] In some possible implementations, the DP-16QAM symbol stream includes at least one data frame. Each of these data frames contains 128 consecutive DP-16QAM symbols, including one pilot symbol and 127 payload symbols. These 127 payload symbols are obtained by mapping 8 codewords from the m second data streams using DP-16QAM symbols. In other words, the 127 DP-16QAM symbols obtained by mapping 8 codewords from the m second data streams using DP-16QAM symbols can be used as the 127 payload symbols from the 128 consecutive DP-16QAM symbols in the data frame. Only one pilot symbol needs to be added for transmission. This eliminates the need for additional buffering to store the payload symbols during framing, resulting in a simple implementation and low power consumption. It should be understood that both the pilot symbol and the payload symbol refer to dual-polarization symbols, containing symbols in two polarization directions.

[0046] In some possible implementations, each data frame includes 96 pilot symbols and 12,192 payload symbols. The 96 pilot symbols of the existing 800LR can be reused for compatibility with 800LR implementations.

[0047] In some possible implementations, the eight codewords include two codewords from each of the four second data streams, providing stronger resistance to burst attacks.

[0048] In some possible implementations, 2 bits from 2 codewords in each of the 4 second data streams, totaling 8 bits, are mapped using DP-16QAM symbols to obtain 1 DP-16QAM symbol. This ensures that the 8 bits of the mapped DP-16QAM symbol can be more evenly distributed from the 2 codewords in each of the 4 second data streams, which helps to reduce hardware implementation costs.

[0049] In some possible implementations, the z-th bit and the (z+1)-th bit (a total of 8 bits) from the two codewords in each of the four second data streams are mapped using DP-16QAM symbols to obtain one DP-16QAM symbol, where 0 ≤ z ≤ 252, and z is an even number. In this application, 0 is also an even number; for example, z = 0, 2, 4, ..., 252. This is equivalent to sequentially selecting two consecutive bits from the two codewords in each of the four second data streams for DP-16QAM symbol mapping, which facilitates hardware implementation.

[0050] In some possible implementations, the two codewords in each of the m second data streams constitute a bit set. The m bit sets from the m second data streams are mapped using DP-16QAM symbols to obtain M DP-16QAM symbols, where M = 254 × m / 8. The mapping represents the 8 bits of the i-th DP-16QAM symbol among the M DP-16QAM symbols. 0≤i≤M-1, the m second data streams include second data stream 0 to second data stream m-1.

[0051] It should be understood that the m second data streams are counted starting from 0. Second data stream 0 is the 0th second data stream in the m second data streams, second data stream 1 is the 1st second data stream in the m second data streams, and so on. The m bit sets of the m second data streams are also counted starting from 0. Bit set 0 is the bit set of the 0th second data stream in the m second data streams (also called the 0th bit set), bit set 1 is the bit set of the 1st second data stream in the m second data streams (also called the 1st bit set), and so on. 8 bits It also starts counting from 0, bits. It is the 0th bit out of 8 bits. It is the first bit out of 8 bits, and so on.

[0052] The following conditions must be met:

[0053] From the second data stream The 2nd × (i % 127) + i % 2nd bit in the bit set;

[0054] From the second data stream The 2nd × (i % 127) + (i + 1) % 2nd bit in the bit set;

[0055] From the second data stream The 2nd × (i % 127) + i % 2nd bit in the bit set;

[0056] From the second data stream The 2nd × (i % 127) + (i + 1) % 2nd bit in the bit set;

[0057] From the second data stream The 2nd × (i % 127) + i % 2nd bit in the bit set;

[0058] From the second data stream The 2nd × (i % 127) + (i + 1) % 2nd bit in the bit set;

[0059] From the second data stream The 2nd × (i % 127) + i % 2nd bit in the bit set;

[0060] From the second data stream The 2nd (i%127)+(i+1)%2th bit in the bit set.

[0061] In some possible implementations, the eight codewords include one codeword from each of the eight second data streams, where m is a positive integer multiple of 8, resulting in lower latency.

[0062] In some possible implementations, 504 bits from four of the eight codewords are mapped using DP-16QAM symbols to obtain 63 DP-16QAM symbols. This means that exactly 504 bits out of the 508 bits in these four codewords can be mapped using DP-16QAM symbols to obtain 63 DP-16QAM symbols. Similarly, 504 bits from the other four codewords are mapped using DP-16QAM symbols to obtain 63 DP-16QAM symbols. The remaining 4 bits from 4 out of the 8 codewords, along with the remaining 4 bits from the other 4 out of the 8 codewords (a total of 8 bits), are mapped using DP-16QAM symbols to obtain one DP-16QAM symbol. This is equivalent to mapping the remaining 4 bits from the 508 bits of the 4 codewords and the remaining 4 bits from the 508 bits of the other 4 codewords together to obtain one DP-16QAM symbol. In other words, except for the 8 bits used to map one DP-16QAM symbol which come from each of the 8 second data streams, the 8 bits used to map the other DP-16QAM symbols can be distributed relatively evenly from one codeword in each of the 4 second data streams, which helps reduce hardware implementation costs.

[0063] In some possible implementations, the c-th bit and the (c+1)-th bit (a total of 8 bits) of each of four of the eight codewords are mapped using DP-16QAM symbols to obtain one DP-16QAM symbol, where 0 ≤ c ≤ 124, and c is an even number. In this application, 0 is also an even number; for example, c = 0, 2, 4, ..., 124. The 126-th bit of each of the four of the eight codewords and the 0-th bit of each of the other four codewords (a total of 8 bits) are mapped using DP-16QAM symbols to obtain one DP-16QAM symbol. The t-th bit and the (t+1)-th bit (a total of 8 bits) of each of the other four codewords are mapped using DP-16QAM symbols to obtain one DP-16QAM symbol, where 1 ≤ t ≤ 125, and t is an odd number. This is equivalent to first selecting two consecutive bits from one codeword in each of the four of the eight second data streams for DP-16QAM symbol mapping, then performing DP-16QAM symbol mapping on the remaining bit (the 126th bit) of one codeword from each of the four of the eight second data streams, combined with the first bit (the 0th bit) of one codeword from each of the other four of the eight second data streams, for a total of eight bits. Then, performing DP-16QAM symbol mapping on these eight bits, and finally selecting two consecutive bits from one codeword in each of the other four of the eight second data streams for DP-16QAM symbol mapping. This facilitates hardware implementation.

[0064] In some possible implementations, the m second data streams comprise m / 2 bit sets, each bit set comprising 2 codewords, the m codewords in the m / 2 bit sets originating from the m second data streams, and the m / 2 bit sets are mapped using DP-16QAM symbols to obtain M DP-16QAM symbols, where M = 127 × m / 8. The mapping represents the 8 bits of the i-th DP-16QAM symbol among the M DP-16QAM symbols. 0≤i≤M-1.

[0065] It should be understood that the m second data streams are counted starting from 0. Second data stream 0 is the 0th second data stream out of the m second data streams, second data stream 1 is the 1st second data stream out of the m second data streams, and so on. The m / 2 bit set is also counted starting from 0. Bit set 0 is the 0th bit set out of the m / 2 bit set, bit set 1 is the 1st bit set out of the m / 2 bit set, and so on. 8 bits It also starts counting from 0, bits. It is the 0th bit out of 8 bits. It is the first bit out of 8 bits, and so on.

[0066] The following conditions must be met:

[0067] From the The 2nd (i%127)+i%2th bit in the set of bits;

[0068] From the The 2nd × (i % 127) + (i + 1) % 2nd bit in the set of bits;

[0069] From the The 2nd (i%127)+i%2th bit in the set of bits;

[0070] From the The 2nd × (i % 127) + (i + 1) % 2nd bit in the set of bits;

[0071] From the The 2nd (i%127)+i%2th bit in the set of bits;

[0072] From the The 2nd × (i % 127) + (i + 1) % 2nd bit in the set of bits;

[0073] From the The 2nd (i%127)+i%2th bit in the set of bits;

[0074] From the The 2nd (i%127)+(i+1)%2th bit in the set of bits.

[0075] In some possible implementations, the m second data streams include second data stream 0 to second data stream m-1, and the bit set k in the m / 2 bit set includes two codewords that each come from a second data stream. Second data stream

[0076] In some possible implementations, the m second data streams include second data stream 0 to second data stream m-1, and the bit set k in the m / 2 bit set includes two codewords that each come from a second data stream. Second data stream

[0077] In some possible implementations, the 120 information bits are cyclically shifted before or after the FEC encoding, which helps to improve the burst resistance of the overall cascaded FEC.

[0078] In some possible implementations, before the FEC encoding, the multiple first data streams undergo convolutional interleaving, and the 120 information bits correspond to 12 RS symbols, which are derived from 12 RS codewords, thus improving the overall encoding performance.

[0079] In some possible implementations, the multiple first data streams are first convolutionally interleaved, then FEC encoded, and then cyclically shifted. Alternatively, the multiple first data streams are first convolutionally interleaved, then cyclically shifted, and then FEC encoded.

[0080] In some possible implementations, m is a positive integer multiple of 8, such as 8, 16, 32, or 64. Alternatively, m is a positive integer multiple of 4, such as 12 or 20.

[0081] Thirdly, this application provides a data processing apparatus, which includes a first processing unit and a second processing unit. The first processing unit is configured to: perform FEC encoding on multiple first data streams encoded by RS to obtain m second data streams, where m is a positive integer multiple of 4, and the codewords after FEC encoding include 127 bits, wherein the 127 bits of the codeword are obtained by encoding 120 information bits through FEC. The second processing unit is configured to: perform DP-16QAM symbol mapping and framing on the m second data streams to obtain one DP-16QAM symbol stream. As a possible implementation, the 127 DP-16QAM symbols in the DP-16QAM symbol stream are obtained by mapping 8 codewords from the m second data streams through DP-16QAM symbol mapping. That is, any one of the 127 DP-16QAM symbols is obtained by mapping 8 bits out of the 1016 bits of the 8 codewords through DP-16QAM symbol mapping.

[0082] In some possible implementations, the DP-16QAM symbol stream includes at least one data frame. Each of these data frames contains 128 consecutive DP-16QAM symbols, including one pilot symbol and 127 payload symbols. These 127 payload symbols are obtained by mapping 8 codewords from the m second data streams using DP-16QAM symbols. In other words, the 127 DP-16QAM symbols obtained by mapping 8 codewords from the m second data streams using DP-16QAM symbols can be used as the 127 payload symbols from the 128 consecutive DP-16QAM symbols in the data frame. Only one pilot symbol needs to be added for transmission. This eliminates the need for additional buffering to store the payload symbols during framing, resulting in a simple implementation and low power consumption. It should be understood that both the pilot symbol and the payload symbol refer to dual-polarization symbols, containing symbols in two polarization directions.

[0083] In some possible implementations, each data frame includes 96 pilot symbols and 12,192 payload symbols. The 96 pilot symbols of the existing 800LR can be reused for compatibility with 800LR implementations.

[0084] In some possible implementations, the eight codewords include two codewords from each of the four second data streams, providing stronger resistance to burst attacks.

[0085] In some possible implementations, 2 bits from 2 codewords in each of the 4 second data streams, totaling 8 bits, are mapped using DP-16QAM symbols to obtain 1 DP-16QAM symbol. This ensures that the 8 bits of the mapped DP-16QAM symbol can be more evenly distributed from the 2 codewords in each of the 4 second data streams, which helps to reduce hardware implementation costs.

[0086] In some possible implementations, the z-th bit and the (z+1)-th bit (a total of 8 bits) from the two codewords in each of the four second data streams are mapped using DP-16QAM symbols to obtain one DP-16QAM symbol, where 0 ≤ z ≤ 252, and z is an even number. In this application, 0 is also an even number; for example, z = 0, 2, 4, ..., 252. This is equivalent to sequentially selecting two consecutive bits from the two codewords in each of the four second data streams for DP-16QAM symbol mapping, which facilitates hardware implementation.

[0087] In some possible implementations, the two codewords in each of the m second data streams constitute a bit set. The m bit sets from the m second data streams are mapped using DP-16QAM symbols to obtain M DP-16QAM symbols, where M = 254 × m / 8. The mapping represents the 8 bits of the i-th DP-16QAM symbol among the M DP-16QAM symbols. 0≤i≤M-1, the m second data streams include second data stream 0 to second data stream m-1.

[0088] It should be understood that the m second data streams are counted starting from 0. Second data stream 0 is the 0th second data stream in the m second data streams, second data stream 1 is the 1st second data stream in the m second data streams, and so on. The m bit sets of the m second data streams are also counted starting from 0. Bit set 0 is the bit set of the 0th second data stream in the m second data streams (also called the 0th bit set), bit set 1 is the bit set of the 1st second data stream in the m second data streams (also called the 1st bit set), and so on. 8 bits It also starts counting from 0, bits. It is the 0th bit out of 8 bits. It is the first bit out of 8 bits, and so on.

[0089] The following conditions must be met:

[0090] From the second data stream The 2nd × (i % 127) + i % 2nd bit in the bit set;

[0091] From the second data stream The 2nd × (i % 127) + (i + 1) % 2nd bit in the bit set;

[0092] From the second data stream The 2nd × (i % 127) + i % 2nd bit in the bit set;

[0093] From the second data stream The 2nd × (i % 127) + (i + 1) % 2nd bit in the bit set;

[0094] From the second data stream The 2nd × (i % 127) + i % 2nd bit in the bit set;

[0095] From the second data stream The 2nd × (i % 127) + (i + 1) % 2nd bit in the bit set;

[0096] From the second data stream The 2nd × (i % 127) + i % 2nd bit in the bit set;

[0097] From the second data stream The 2nd (i%127)+(i+1)%2th bit in the bit set.

[0098] In some possible implementations, the eight codewords include one codeword from each of the eight second data streams, where m is a positive integer multiple of 8, resulting in lower latency.

[0099] In some possible implementations, 504 bits from four of the eight codewords are mapped using DP-16QAM symbols to obtain 63 DP-16QAM symbols. This means that exactly 504 bits out of the 508 bits in these four codewords can be mapped using DP-16QAM symbols to obtain 63 DP-16QAM symbols. Similarly, 504 bits from the other four codewords are mapped using DP-16QAM symbols to obtain 63 DP-16QAM symbols. The remaining 4 bits from 4 out of the 8 codewords, along with the remaining 4 bits from the other 4 out of the 8 codewords (a total of 8 bits), are mapped using DP-16QAM symbols to obtain one DP-16QAM symbol. This is equivalent to mapping the remaining 4 bits from the 508 bits of the 4 codewords and the remaining 4 bits from the 508 bits of the other 4 codewords together to obtain one DP-16QAM symbol. In other words, except for the 8 bits used to map one DP-16QAM symbol which come from each of the 8 second data streams, the 8 bits used to map the other DP-16QAM symbols can be distributed relatively evenly from one codeword in each of the 4 second data streams, which helps reduce hardware implementation costs.

[0100] In some possible implementations, the c-th bit and the (c+1)-th bit (a total of 8 bits) of each of four of the eight codewords are mapped using DP-16QAM symbols to obtain one DP-16QAM symbol, where 0 ≤ c ≤ 124, and c is an even number. In this application, 0 is also an even number; for example, c = 0, 2, 4, ..., 124. The 126-th bit of each of the four of the eight codewords and the 0-th bit of each of the other four codewords (a total of 8 bits) are mapped using DP-16QAM symbols to obtain one DP-16QAM symbol. The t-th bit and the (t+1)-th bit (a total of 8 bits) of each of the other four codewords are mapped using DP-16QAM symbols to obtain one DP-16QAM symbol, where 1 ≤ t ≤ 125, and t is an odd number. This is equivalent to first selecting two consecutive bits from one codeword in each of the four of the eight second data streams for DP-16QAM symbol mapping, then performing DP-16QAM symbol mapping on the remaining bit (the 126th bit) of one codeword from each of the four of the eight second data streams, combined with the first bit (the 0th bit) of one codeword from each of the other four of the eight second data streams, for a total of eight bits. Then, performing DP-16QAM symbol mapping on these eight bits, and finally selecting two consecutive bits from one codeword in each of the other four of the eight second data streams for DP-16QAM symbol mapping. This facilitates hardware implementation.

[0101] In some possible implementations, the m second data streams comprise m / 2 bit sets, each bit set comprising 2 codewords, the m codewords in the m / 2 bit sets originating from the m second data streams, and the m / 2 bit sets are mapped using DP-16QAM symbols to obtain M DP-16QAM symbols, where M = 127 × m / 8. The mapping represents the 8 bits of the i-th DP-16QAM symbol among the M DP-16QAM symbols. 0≤i≤M-1.

[0102] It should be understood that the m second data streams are counted starting from 0. Second data stream 0 is the 0th second data stream out of the m second data streams, second data stream 1 is the 1st second data stream out of the m second data streams, and so on. The m / 2 bit set is also counted starting from 0. Bit set 0 is the 0th bit set out of the m / 2 bit set, bit set 1 is the 1st bit set out of the m / 2 bit set, and so on. 8 bits It also starts counting from 0, bits. It is the 0th bit out of 8 bits. It is the first bit out of 8 bits, and so on.

[0103] The following conditions must be met:

[0104] From the The 2nd (i%127)+i%2th bit in the set of bits;

[0105] From the The 2nd × (i % 127) + (i + 1) % 2nd bit in the set of bits;

[0106] From the The 2nd (i%127)+i%2th bit in the set of bits;

[0107] From the The 2nd × (i % 127) + (i + 1) % 2nd bit in the set of bits;

[0108] From the The 2nd (i%127)+i%2th bit in the set of bits;

[0109] From the The 2nd × (i % 127) + (i + 1) % 2nd bit in the set of bits;

[0110] From the The 2nd (i%127)+i%2th bit in the set of bits;

[0111] From the The 2nd (i%127)+(i+1)%2th bit in the set of bits.

[0112] In some possible implementations, the m second data streams include second data stream 0 to second data stream m-1, and the bit set k in the m / 2 bit set includes two codewords that each come from a second data stream. Second data stream

[0113] In some possible implementations, the m second data streams include second data stream 0 to second data stream m-1, and the bit set k in the m / 2 bit set includes two codewords that each come from a second data stream. Second data stream

[0114] In some possible implementations, the 120 information bits are cyclically shifted before or after the FEC encoding, which helps to improve the burst resistance of the overall cascaded FEC.

[0115] In some possible implementations, before the FEC encoding, the multiple first data streams undergo convolutional interleaving, and the 120 information bits correspond to 12 RS symbols, which are derived from 12 RS codewords, thus improving the overall encoding performance.

[0116] In some possible implementations, the multiple first data streams are first convolutionally interleaved, then FEC encoded, and then cyclically shifted. Alternatively, the multiple first data streams are first convolutionally interleaved, then cyclically shifted, and then FEC encoded.

[0117] In some possible implementations, m is a positive integer multiple of 8, such as 8, 16, 32, or 64. Alternatively, m is a positive integer multiple of 4, such as 12 or 20.

[0118] Fourthly, this application provides a data processing apparatus, which includes a receiving unit. The receiving unit is configured to: receive one DP-16QAM symbol stream, wherein the one DP-16QAM symbol stream is obtained by DP-16QAM symbol mapping and framing of m second data streams, the m second data streams are obtained by forward error correction (FEC) encoding of multiple first data streams encoded by Reed-Solomon (RS), m is a positive integer multiple of 4, and the codeword encoded by the FEC includes 127 bits, the 127 bits of which are obtained by FEC encoding 120 information bits. As one possible implementation, the 127 DP-16QAM symbols in the DP-16QAM symbol stream are obtained by mapping the 8 codewords in the m second data streams through DP-16QAM symbols. In other words, any one of the 127 DP-16QAM symbols is obtained by mapping 8 bits out of the 1016 bits of the 8 codewords through DP-16QAM symbols.

[0119] In some possible implementations, the DP-16QAM symbol stream includes at least one data frame. Each of these data frames contains 128 consecutive DP-16QAM symbols, including one pilot symbol and 127 payload symbols. These 127 payload symbols are obtained by mapping 8 codewords from the m second data streams using DP-16QAM symbols. In other words, the 127 DP-16QAM symbols obtained by mapping 8 codewords from the m second data streams using DP-16QAM symbols can be used as the 127 payload symbols from the 128 consecutive DP-16QAM symbols in the data frame. Only one pilot symbol needs to be added for transmission. This eliminates the need for additional buffering to store the payload symbols during framing, resulting in a simple implementation and low power consumption. It should be understood that both the pilot symbol and the payload symbol refer to dual-polarization symbols, containing symbols in two polarization directions.

[0120] In some possible implementations, each data frame includes 96 pilot symbols and 12,192 payload symbols. The 96 pilot symbols of the existing 800LR can be reused for compatibility with 800LR implementations.

[0121] In some possible implementations, the eight codewords include two codewords from each of the four second data streams, providing stronger resistance to burst attacks.

[0122] In some possible implementations, 2 bits from 2 codewords in each of the 4 second data streams, totaling 8 bits, are mapped using DP-16QAM symbols to obtain 1 DP-16QAM symbol. This ensures that the 8 bits of the mapped DP-16QAM symbol can be more evenly distributed from the 2 codewords in each of the 4 second data streams, which helps to reduce hardware implementation costs.

[0123] In some possible implementations, the z-th bit and the (z+1)-th bit (a total of 8 bits) from the two codewords in each of the four second data streams are mapped using DP-16QAM symbols to obtain one DP-16QAM symbol, where 0 ≤ z ≤ 252, and z is an even number. In this application, 0 is also an even number; for example, z = 0, 2, 4, ..., 252. This is equivalent to sequentially selecting two consecutive bits from the two codewords in each of the four second data streams for DP-16QAM symbol mapping, which facilitates hardware implementation.

[0124] In some possible implementations, the two codewords in each of the m second data streams constitute a bit set. The m bit sets from the m second data streams are mapped using DP-16QAM symbols to obtain M DP-16QAM symbols, where M = 254 × m / 8. The mapping represents the 8 bits of the i-th DP-16QAM symbol among the M DP-16QAM symbols. 0≤i≤M-1, the m second data streams include second data stream 0 to second data stream m-1.

[0125] It should be understood that the m second data streams are counted starting from 0. Second data stream 0 is the 0th second data stream in the m second data streams, second data stream 1 is the 1st second data stream in the m second data streams, and so on. The m bit sets of the m second data streams are also counted starting from 0. Bit set 0 is the bit set of the 0th second data stream in the m second data streams (also called the 0th bit set), bit set 1 is the bit set of the 1st second data stream in the m second data streams (also called the 1st bit set), and so on. 8 bits It also starts counting from 0, bits. It is the 0th bit out of 8 bits. It is the first bit out of 8 bits, and so on.

[0126] The following conditions must be met:

[0127] From the second data stream The 2nd × (i % 127) + i % 2nd bit in the bit set;

[0128] From the second data stream The 2nd × (i % 127) + (i + 1) % 2nd bit in the bit set;

[0129] From the second data stream The 2nd × (i % 127) + i % 2nd bit in the bit set;

[0130] From the second data stream The 2nd × (i % 127) + (i + 1) % 2nd bit in the bit set;

[0131] From the second data stream The 2nd × (i % 127) + i % 2nd bit in the bit set;

[0132] From the second data stream The 2nd × (i % 127) + (i + 1) % 2nd bit in the bit set;

[0133] From the second data stream The 2nd × (i % 127) + i % 2nd bit in the bit set;

[0134] From the second data stream The 2nd (i%127)+(i+1)%2th bit in the bit set.

[0135] In some possible implementations, the eight codewords include one codeword from each of the eight second data streams, where m is a positive integer multiple of 8, resulting in lower latency.

[0136] In some possible implementations, 504 bits from four of the eight codewords are mapped using DP-16QAM symbols to obtain 63 DP-16QAM symbols. This means that exactly 504 bits out of the 508 bits in these four codewords can be mapped using DP-16QAM symbols to obtain 63 DP-16QAM symbols. Similarly, 504 bits from the other four codewords are mapped using DP-16QAM symbols to obtain 63 DP-16QAM symbols. The remaining 4 bits from 4 out of the 8 codewords, along with the remaining 4 bits from the other 4 out of the 8 codewords (a total of 8 bits), are mapped using DP-16QAM symbols to obtain one DP-16QAM symbol. This is equivalent to mapping the remaining 4 bits from the 508 bits of the 4 codewords and the remaining 4 bits from the 508 bits of the other 4 codewords together to obtain one DP-16QAM symbol. In other words, except for the 8 bits used to map one DP-16QAM symbol which come from each of the 8 second data streams, the 8 bits used to map the other DP-16QAM symbols can be distributed relatively evenly from one codeword in each of the 4 second data streams, which helps reduce hardware implementation costs.

[0137] In some possible implementations, the c-th bit and the (c+1)-th bit (a total of 8 bits) of each of four of the eight codewords are mapped using DP-16QAM symbols to obtain one DP-16QAM symbol, where 0 ≤ c ≤ 124, and c is an even number. In this application, 0 is also an even number; for example, c = 0, 2, 4, ..., 124. The 126-th bit of each of the four of the eight codewords and the 0-th bit of each of the other four codewords (a total of 8 bits) are mapped using DP-16QAM symbols to obtain one DP-16QAM symbol. The t-th bit and the (t+1)-th bit (a total of 8 bits) of each of the other four codewords are mapped using DP-16QAM symbols to obtain one DP-16QAM symbol, where 1 ≤ t ≤ 125, and t is an odd number. This is equivalent to first selecting two consecutive bits from one codeword in each of the four of the eight second data streams for DP-16QAM symbol mapping, then performing DP-16QAM symbol mapping on the remaining bit (the 126th bit) of one codeword from each of the four of the eight second data streams, combined with the first bit (the 0th bit) of one codeword from each of the other four of the eight second data streams, for a total of eight bits. Then, performing DP-16QAM symbol mapping on these eight bits, and finally selecting two consecutive bits from one codeword in each of the other four of the eight second data streams for DP-16QAM symbol mapping. This facilitates hardware implementation.

[0138] In some possible implementations, the m second data streams comprise m / 2 bit sets, each bit set comprising 2 codewords, the m codewords in the m / 2 bit sets originating from the m second data streams, and the m / 2 bit sets are mapped using DP-16QAM symbols to obtain M DP-16QAM symbols, where M = 127 × m / 8. The mapping represents the 8 bits of the i-th DP-16QAM symbol among the M DP-16QAM symbols. 0≤i≤M-1.

[0139] It should be understood that the m second data streams are counted starting from 0. Second data stream 0 is the 0th second data stream out of the m second data streams, second data stream 1 is the 1st second data stream out of the m second data streams, and so on. The m / 2 bit set is also counted starting from 0. Bit set 0 is the 0th bit set out of the m / 2 bit set, bit set 1 is the 1st bit set out of the m / 2 bit set, and so on. 8 bits It also starts counting from 0, bits. It is the 0th bit out of 8 bits. It is the first bit out of 8 bits, and so on.

[0140] The following conditions must be met:

[0141] From the The 2nd (i%127)+i%2th bit in the set of bits;

[0142] From the The 2nd × (i % 127) + (i + 1) % 2nd bit in the set of bits;

[0143] From the The 2nd (i%127)+i%2th bit in the set of bits;

[0144] From the The 2nd × (i % 127) + (i + 1) % 2nd bit in the set of bits;

[0145] From the The 2nd (i%127)+i%2th bit in the set of bits;

[0146] From the The 2nd × (i % 127) + (i + 1) % 2nd bit in the set of bits;

[0147] From the The 2nd (i%127)+i%2th bit in the set of bits;

[0148] From the The 2nd (i%127)+(i+1)%2th bit in the set of bits.

[0149] In some possible implementations, the m second data streams include second data stream 0 to second data stream m-1, and the bit set k in the m / 2 bit set includes two codewords that each come from a second data stream. Second data stream

[0150] In some possible implementations, the m second data streams include second data stream 0 to second data stream m-1, and the bit set k in the m / 2 bit set includes two codewords that each come from a second data stream. Second data stream

[0151] In some possible implementations, the 120 information bits are cyclically shifted before or after the FEC encoding, which helps to improve the burst resistance of the overall cascaded FEC.

[0152] In some possible implementations, before the FEC encoding, the multiple first data streams undergo convolutional interleaving, and the 120 information bits correspond to 12 RS symbols, which are derived from 12 RS codewords, thus improving the overall encoding performance.

[0153] In some possible implementations, the multiple first data streams are first convolutionally interleaved, then FEC encoded, and then cyclically shifted. Alternatively, the multiple first data streams are first convolutionally interleaved, then cyclically shifted, and then FEC encoded.

[0154] In some possible implementations, m is a positive integer multiple of 8, such as 8, 16, 32, or 64. Alternatively, m is a positive integer multiple of 4, such as 12 or 20.

[0155] Fifthly, embodiments of this application provide a chip for performing the methods described in any of the first or second aspects.

[0156] Sixthly, embodiments of this application provide an optical module, which includes a processor and an interface. The interface is used to transmit and receive signals, and the processor is used to execute the methods described in either the first or second aspect. For example, the interface is used to transmit signals from the processor or to transmit received signals to the processor.

[0157] In a seventh aspect, embodiments of this application provide a network device. The transmitting device includes a host-side device and an optical module as described in the sixth aspect. For example, the optical module is used to convert electrical signals from the host-side device into optical signals and transmit the optical signals. As another example, the optical module is used to convert received optical signals into electrical signals and transmit the electrical signals to the host-side device.

[0158] Eighthly, embodiments of this application provide a communication system that includes multiple network devices as described in the seventh aspect, wherein the multiple network devices are used to send optical signals to each other.

[0159] Ninthly, this application provides a computer-readable storage medium storing instructions that, when executed by a computer, cause the method described in any of the embodiments of the first or second aspect to be implemented.

[0160] In a tenth aspect, this application provides a computer program product including program instructions that, when executed, implement the method described in any of the embodiments of the first or second aspect. Attached Figure Description

[0161] Figure 1 This is a schematic diagram of a communication system used in an embodiment of this application;

[0162] Figure 2 for Figure 1 A schematic diagram of a data transmission process in the communication system shown.

[0163] Figure 3 This is a schematic diagram of another communication system used in an embodiment of this application;

[0164] Figure 4 A schematic flowchart of a data processing method provided in an embodiment of this application;

[0165] Figure 5(a) is a schematic diagram of the first structure of convolutional interleaving in an embodiment of this application;

[0166] Figure 5(b) is a schematic diagram of the second structure of convolutional interleaving in an embodiment of this application;

[0167] Figure 6(a) is a schematic diagram of one embodiment of dual polarization symbol mapping and DSP framing in this application;

[0168] Figure 6(b) is a schematic diagram of another implementation of dual polarization symbol mapping and DSP framing in the embodiments of this application;

[0169] Figure 6(c) is a schematic diagram of another implementation of dual polarization symbol mapping and DSP framing in the embodiments of this application;

[0170] Figure 6(d) is a schematic diagram of another implementation of dual polarization symbol mapping and DSP framing in the embodiments of this application;

[0171] Figure 7 This is a schematic diagram of one implementation of the present application in which 127 DP-16QAM symbols are mapped.

[0172] Figure 8 This is a schematic diagram illustrating another implementation method in which 127 DP-16QAM symbols are mapped in the embodiments of this application;

[0173] Figure 9 This is a schematic diagram of one implementation method in this application for obtaining a DP-16QAM symbol stream through data processing.

[0174] Figure 10This is a schematic diagram of an application scenario for mapping DP-16QAM symbols in an embodiment of this application;

[0175] Figure 11 This is a schematic diagram of the structure of a DSP frame;

[0176] Figure 12 This is a schematic diagram illustrating another implementation method for obtaining a DP-16QAM symbol stream through data processing in this application embodiment;

[0177] Figure 13 This is a schematic diagram illustrating another application scenario of the DP-16QAM symbol mapped in the embodiments of this application;

[0178] Figure 14 This is a schematic diagram illustrating another application scenario of the DP-16QAM symbol mapped in the embodiments of this application;

[0179] Figure 15 This is a schematic diagram of the structure of a data processing device in an embodiment of this application;

[0180] Figure 16 This is a schematic diagram of another structure of the data processing device in the embodiments of this application;

[0181] Figure 17 This is a schematic diagram of the structure of an optical module in one embodiment of this application;

[0182] Figure 18 This is a schematic diagram of the structure of a network device in an embodiment of this application. Detailed Implementation

[0183] This application provides a data processing method, apparatus, and system. The solution exhibits good error correction performance and strong burst resistance. Its low baud rate results in lower required device bandwidth, making it simple to implement, power-efficient, and cost-effective. It can be applied to short-distance data center interconnect (DCI) or data center network (DCN) transmission scenarios with low power consumption and cost requirements.

[0184] To facilitate understanding of the embodiments of this application, the following points are made:

[0185] First, unless otherwise specified or there is a logical conflict, the terms and / or descriptions between different embodiments are consistent and can be referenced by each other. Technical features in different embodiments can be combined to form new embodiments based on their inherent logical relationships.

[0186] Second, "at least one" means one or more, and "more than one" means two or more (including two). "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. In the textual description of this application, the character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, and c can mean: a, or, b, or, c, or, a and b, or, a and c, or, b and c, or, a, b, and c. Here, a, b, and c can be single or multiple.

[0187] Third, the terms "first," "second," and various numerical designations (e.g., #1, #2) are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application. For example, they can be used to distinguish different indication information.

[0188] Fourth, the terms “comprising” and “having” and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product or device.

[0189] Fifth, for the tables marked with serial numbers in this application, the serial numbers are only used to distinguish the different combinations of parameters provided in the table, and do not limit the content of the table. For example, if there are 10 serial numbers in the table, it means that the table provides 10 possible combinations of parameters.

[0190] Sixth, corresponding mathematical operations This indicates rounding down the real number a; c%d indicates performing a modulo d operation on c, where c and d are positive integers.

[0191] Figure 1 This is a schematic diagram of a communication system used in an embodiment of this application. Figure 1As shown, the communication system includes a transmitting device 01, a transmitting processing module 02, a channel transmission medium 03, a receiving processing module 04, and a receiving device 05. Taking a data center network as an example, the transmitting device 01 and the receiving device 05 can be devices such as switches, routers, or servers. The transmitting device 01 is also called a client device at the transmitting end, and the receiving device 05 is also called a client device at the receiving end. The channel transmission medium 03 can be optical fiber. The client device is sometimes also called a host device. The client device includes a client chip and an interface. The client chip is also called a host chip. The connection interface between the transmitting device 01 and the transmitting processing module 02 can be connected through an attachment unit interface (AUI), and the connection interface between the receiving device 05 and the receiving processing module 04 can also be connected through an AUI. The transmitting processing module 02 and the receiving processing module 04 can be optical modules, electrical modules, connectors, or other modules that process data during data transmission. For example, the processing module can be an LR optical module, such as a 1600LR module (a coherent optical module). Furthermore, the transmitting device 01, transmitting processing module 02, channel transmission medium 03, receiving processing module 04, and receiving device 05 in this communication system can all support bidirectional transmission or unidirectional transmission; specific support is not limited here.

[0192] Figure 2 for Figure 1 The diagram illustrates a data transmission process in a communication system. Figure 2 As shown, during the data transmission process from transmitting device 01 to receiving device 05, transmitting device 01 performs external code encoding on the data and then transmits the externally encoded data to transmitting processing module 02. Transmitting processing module 02 performs internal code encoding on the externally encoded data to obtain data with both external and internal code encoding, and transmits this encoded data to channel transmission medium 03. Channel transmission medium 03 transmits the externally and internally encoded data to receiving processing module 04. Receiving processing module 04 performs internal code decoding on the externally and internally encoded data and transmits the internally decoded data to receiving device 05. Receiving device 05 performs external code decoding on the internally decoded data.

[0193] It should be understood that the distinction between "internal" in "internal code" and "external" in "external code" is based solely on the distance between the entity performing the data operation and the channel transmission medium 03. The entity operating on the internal code is closer to the channel transmission medium, while the entity operating on the external code is farther away. In this embodiment, after data is sent from the transmitting device 01, it is transmitted to the channel transmission medium 03 via the transmitting processing module 02, and then from the channel transmission medium 03 via the receiving processing module 04 to the receiving device 05. The data encoded by the transmitting device 01 is farther from the channel transmission medium 03 than the data encoded by the transmitting processing module 02, and the data decoded by the receiving device 05 is farther from the channel transmission medium 03 than the data decoded by the receiving processing module 04. Therefore, the data encoded by the transmitting device 01 is called data encoded with the external code, the data encoded by the transmitting processing module 02 is called data encoded with the internal code, the data decoded by the receiving device 05 is called data decoded with the external code, and the data decoded by the receiving processing module 04 is called data decoded with the internal code. In one possible implementation, both the internal and external code encoding described above employ FEC encoding, thus forming a cascaded FEC transmission scheme. For example, the transmitting device 01 can use RS code for external code encoding, and the transmitting processing module 02 can use Hamming code for internal code encoding. Alternatively, the transmitting device 01 can use RS code for external code encoding, and the transmitting processing module 02 can use Bose-Chaudhuri-Hocquenghem (BCH) code for internal code encoding. A BCH code that corrects a single error is equivalent to a Hamming code. Again, the transmitting device 01 can use RS code for external code encoding, and the transmitting processing module 02 can use Polar code for internal code encoding.

[0194] Figure 3 This is a schematic diagram of another communication system used in an embodiment of this application. For example... Figure 3As shown, the communication system includes a transmitting device 01, a channel transmission medium 03, and a receiving device 05. The transmitting device 01 performs external code encoding and internal code encoding on the data. The encoded data is then sent to the transmission medium 03. The receiving device 05 decodes the data received from the transmission medium 03, performing internal code decoding and external code decoding. Taking a data center network as an example, the transmitting device 01 and the receiving device 05 can be devices such as switches, routers, or servers. The transmitting device 01 is also referred to as a client-side device or host-side device located at the transmitting end, and the receiving device 05 is also referred to as a client-side chip located at the receiving end. The channel transmission medium 03 can be optical fiber. The client-side device includes a client-side chip and an interface. The client-side chip is also referred to as a host-side chip. The transmitting device 01, channel transmission medium 03, and receiving device 05 in this communication system can all support bidirectional transmission or unidirectional transmission; specific limitations are not specified here. That is to say, Figure 3 The transmitting device 01 shown also integrates Figure 2 The function of the sending processing module 02 shown is as follows: Figure 3 The receiving device 05 shown also integrates Figure 2 The receiving end processing module 04 is shown to have the following functions. At this time, the transmitting end device 01 may also employ linear pluggable optics (LPO), co-packaged optics (CPO), or near packaged optics (NPO) technology.

[0195] It should be noted that, as Figure 2 and Figure 3As shown, in some specific applications, the data after internal encoding is further processed by DSP framing (simply called framing), which involves adding at least one pre-designed symbol sequence from among the following: Frame Alignment Word Sequence (FAWSequence), Training Symbol Sequence (TS), Reserved Symbols Sequence (RES), and Pilot Symbol Sequence (PS) to obtain the DSP frame to be transmitted. It should be understood that the added pre-designed symbols do not transmit information; the more symbols added, the lower the transmission efficiency and the higher the corresponding baud rate. For short-range transmission scenarios such as 2 km to 20 km, only a pilot symbol sequence is usually added to reduce the baud rate. In this case, the pilot symbols are used not only for carrier phase recovery but also for link training and frame boundary acquisition (also known as frame synchronization or frame alignment).

[0196] It should also be noted that the above content is an exemplary description of the application scenarios of the data processing method provided in the embodiments of this application, and does not constitute a limitation on the application scenarios of the data processing method. As those skilled in the art will know, as business needs change, the application scenarios can be adjusted according to the application needs, and the embodiments of this application do not list them one by one.

[0197] Figure 4 This is a schematic flowchart illustrating a data processing method provided in an embodiment of this application. It should be understood that this data processing method is applied at the sending end, for example, it can be specifically implemented through the methods described above. Figure 2 The shown origin processing module 02 can be implemented in this way, or for example, it can be implemented through the above-mentioned... Figure 3 The shown transmitting device 01 is implemented.

[0198] 101. Perform FEC encoding on multiple first data streams that have been RS encoded to obtain m second data streams.

[0199] In this embodiment, multiple first data streams are data streams encoded using the external code RS. In this embodiment, the code length of the RS code is counted in units of symbols; the symbols in the RS code can be called RS symbols. For example, the RS code uses RS(544,514) code, also known as KP4 code. The code length of the RS code is 544 RS symbols, meaning that the codeword of the RS code includes 544 RS symbols, and one RS symbol contains 10 bits.

[0200] Specifically, m is an integer greater than 0 and a positive integer multiple of 4, for example, m = 8, 16, 32 or 64, etc., which are positive integer multiples of 8. Or, m = 12 or 20, etc., which are positive integer multiples of 4.

[0201] In this embodiment, the FEC encoding performed on multiple first data streams can be called internal code encoding. Every K = 120 information bits in the first data stream is internally encoded to obtain an internal codeword containing N = 127 bits. For example, the internal code encoding uses Hamming (127, 120) code. Considering 1.6T transmission, assuming the existing 800LR data frame uses a scheme where 64 consecutive DP-16QAM symbols contain one pilot symbol and 63 payload symbols, the corresponding baud rate is 1700 × (127 / 120) × (64 / 63) / 8 ≈ 228.5 Gbd, which is lower than the baud rate (247.2 Gbd) of directly multiplexing the existing 800LR encoding and framing scheme. This allows for the use of lower bandwidth devices, resulting in lower cost and power consumption.

[0202] In some specific applications, convolutional interleaving is performed between the outer code encoding and the inner code encoding to improve overall coding performance. For example, convolutional interleaving is performed before inner code encoding so that the 120 information bits in each inner code codeword correspond to 12 RS symbols, and the corresponding 12 RS symbols come from 12 RS codewords. This makes the FEC concatenation scheme, which includes RS encoding and inner code encoding, have optimal performance. The convolutional interleaving process is described in detail below.

[0203] Specifically, the convolutional interleaver for convolutional interleaving includes r delay lines, each with a different number of storage elements. The delay line with the fewest storage elements has 0 storage elements. The difference in the number of storage elements between any two adjacent delay lines is Q, where r is an integer greater than 1 and Q is an integer greater than or equal to 1. Each storage element stores d bits, corresponding to d / 10 RS symbols, where d is an integer greater than or equal to 1 and a positive multiple of 10. Bits from the input data stream of the convolutional interleaver are sequentially input to the r delay lines according to their indices. Each time, d bits are input from and output from each delay line. In some applications, the convolutional interleaver outputs d bits at a time. In other applications, the convolutional interleaver outputs r×d bits at a time, where r×d bits come from the r delay lines and include the d bits output from each delay line. The continuous r×d bits in the data stream output by the convolutional interleaver include the d bits output by each delay line.

[0204] It should be understood that the r delay lines each comprise 0, Q, 2Q, ..., (r-1)Q storage units, with each unit storing d bits. The r delay lines correspond to r delay values, which include 0 bits, Q×d bits, 2Q×d bits, ..., (r-1)Q×d bits. The more bits a delay line includes in its delay values, the longer the delay (also called latency) of that delay line to the data stream. It should be understood that when a delay line contains no storage units, the delay is 0 bits, which is called zero-latency pass-through. It should be understood that the aforementioned storage units are also called delay elements.

[0205] Figure 5(a) is a schematic diagram of the first structure of convolutional interleaving in an embodiment of this application. As shown in Figure 5(a), the number of storage units in the r delay lines decreases sequentially according to the sequence number of the r delay lines. That is, delay line 0 has (r-1)Q storage units, each delay line decreases by Q storage units sequentially, and delay line r-1 has 0 storage units. Figure 5(b) is a schematic diagram of the second structure of convolutional interleaving in an embodiment of this application. As shown in Figure 5(b), the number of storage units in the r delay lines increases sequentially according to the sequence number of the r delay lines. That is, delay line 0 has 0 storage units, each delay line increases by Q storage units sequentially, and delay line r-1 has (r-1)Q storage units.

[0206] It should be noted that at any given moment, the input and output switches of the convolutional interleaver are located on the same delay line. After the current delay line receives and outputs d bits in a single input, the switch is switched to the next delay line. This ensures that the bits in the input data stream are sequentially input to the r delay lines according to their sequence numbers, and that the consecutive r×d bits in the output data stream include the d bits output from each delay line. The specific data read / write operations are as follows: d bits are read from the memory cell closest to the output port of the current delay line; the d bits stored in each memory cell of the current delay line are transferred to the next memory cell; then, d bits are written to the memory cell closest to the input port of the current delay line. Afterward, the switch is moved to the next delay line, and the above operations are repeated, and so on.

[0207] It should be understood that when the same parameters r, Q, and d are used, the convolutional interleaving process in Figure 5(a) and the convolutional interleaving process in Figure 5(b) are the inverse operations of each other. That is, when the sending-end processing module uses the convolutional interleaving structure shown in Figure 5(a), the corresponding convolutional deinterleaving in its receiving-end processing module uses the structure shown in Figure 5(b). Similarly, when the sending-end processing module uses the convolutional interleaving structure shown in Figure 5(b), the corresponding convolutional deinterleaving in its receiving-end processing module uses the structure shown in Figure 5(a).

[0208] To enhance the burst resistance of the overall cascaded FEC, a first interleaving is performed before or after internal code encoding. This first interleaving shuffles every K information bits to disrupt their order. This first interleaving is also known as bit shuffling.

[0209] In some possible scenarios, the first interleaving is performed after the internal code encoding. That is, the first data stream is first encoded with internal code, and then the data stream after internal code encoding is interleaved for the first time.

[0210] In some other possible scenarios, the first interleaving is performed before the internal code encoding. That is, the first data stream is first interleaved, and then the first interleaved first data stream is encoded.

[0211] In some other possible scenarios, considering that the first interleaving is only used to interleave K information bits to shuffle their order, and the parity bits do not participate in the first interleaving, the first interleaving and internal code encoding can also be processed in parallel. Specifically, the K information bits are represented by U. First, internal code encoding is performed to obtain the corresponding internal codeword (U,V), where the NK parity bits generated by the internal code encoding are represented by V. Then, the K information bits U in the codeword (U,V) are subjected to the first interleaving to obtain N bits (W,V), where the K bits obtained by the first interleaving of the K information bits U are represented by W. This is equivalent to the internal code encoding and the first interleaving being processed in parallel, that is, the K information bits U are subjected to internal code encoding to obtain NK parity bits V, and the K bits W obtained by the first interleaving of the K information bits U are combined with V to obtain N bits (W,V) after internal code encoding and the first interleaving.

[0212] In some specific applications, the first interleaving is used to perform a right circular shift of K information bits. bits, where the integer In other specific applications, the first interleaving is used to cyclically shift K information bits to the left by δ bits. In this case, the first interleaving is also called a circular shift. It should be noted that a right circular shift of K information bits... Each bit is equivalent to a left circular shift of K information bits. The following description of the circular shift operation uses a right circular shift as an example. Typically, the number of bits used in a right circular shift for the first interleaving of m data streams is... Not exactly the same, among which, The number of bits to circularly shift to the right for the i-th data stream out of m data streams. For example, in this embodiment, consider K = 120. It is an integer multiple of 10. The first interleaving can further improve the overall scheme's resistance to colored noise.

[0213] 102. Perform DP-16QAM symbol mapping and framing on m second data streams to obtain 1 DP-16QAM symbol stream.

[0214] In some specific applications, two internal codewords are obtained from each of the m second data streams, resulting in a total of 2m internal codewords, or 254×m bits. These codes are then shuffled to improve the burst immunity and colored noise immunity of the cascaded FEC scheme.

[0215] In some specific applications, one internal codeword is obtained from each of the m second data streams, resulting in a total of m internal codewords, or 127×m bits. These codes are then shuffled to improve the burst resistance and colored noise resistance of the cascaded FEC scheme.

[0216] Here, the operation of acquiring bits and shuffling their order is called second interleaving, also known as codeword interleaving. As an example, this second interleaving can be divided into two steps: first, a multiplexing operation to acquire multiple bits, and then interleaving those multiple bits. As another example, this second interleaving can be implemented in a single operation, achieving the same effect as the two-step implementation described above.

[0217] Multiple bits acquired from m second data streams are subjected to dual-polarization symbol mapping and framing to obtain a first dual-polarization symbol stream to be transmitted. Framing here is also called DSP framing. The following description uses DP-16QAM symbol mapping as an example for dual-polarization symbol mapping. DP-16QAM symbol mapping maps every 8 bits of the acquired bits to one dual-polarization 16QAM (DP-16QAM) symbol. Each DP-16QAM symbol includes one 16QAM symbol in the X-polarization direction and one 16QAM symbol in the Y-polarization direction, where the X-polarization and Y-polarization directions are orthogonal to each other. Furthermore, the 16QAM symbols in the X-polarization direction include both the in-phase component and the quadrature-phase component in the X-polarization direction, and the 16QAM symbols in the Y-polarization direction include both the in-phase component and the quadrature-phase component in the Y-polarization direction. It should be understood that DP-16QAM symbol mapping is also called 16QAM symbol mapping and polarization distribution. The aforementioned DP-16QAM symbol stream to be transmitted contains multiple DP-16QAM symbol sequences, and DSP framing is used to insert a preset target symbol sequence at a fixed position in each DP-16QAM symbol sequence. Therefore, the DP-16QAM symbol sequence is also called a DSP frame.

[0218] The following section provides a detailed description of possible implementation methods for dual-polarization symbol mapping and DSP framing.

[0219] Figure 6(a) is a schematic diagram of one implementation of dual-polarization symbol mapping and DSP framing in this application. As shown in Figure 6(a), DSP framing is performed after DP-16QAM symbol mapping, and DSP framing is an operation performed on symbols. First, multiple bits are obtained from m second data streams and their order is shuffled (also called second interleaving), and DP-16QAM symbol mapping is performed to obtain a second dual-polarization symbol stream, which can also be called the pre-framing symbol stream (or payload symbol stream). Then, DSP framing is performed on the second dual-polarization symbol stream. Specifically, target symbol sequences are inserted into the symbol streams in the X-polarization direction and the Y-polarization direction of the second dual-polarization symbol stream, respectively, to obtain the first dual-polarization symbol stream to be transmitted. It should be understood that the values ​​of the target symbol sequences inserted in the X-polarization direction and the target symbol sequences inserted in the Y-polarization direction may not be exactly the same. Here, they are collectively referred to as target symbol sequences without specific distinction. For example, the target symbol sequence includes at least one of the following: Frame Alignment Word Sequence (FAW Sequence), Training Symbol Sequence, Reserved Symbol Sequence, and Pilot Symbol Sequence. Optionally, reserved symbols may also be referred to as fixed stuff (FS), and frame alignment symbols may also be referred to as multi-frame alignment signal (MFAS).

[0220] In one possible scenario, the target symbol sequence is a pilot symbol sequence. In either the X-polarization or Y-polarization direction, each N... G One symbol at a fixed position among the symbols is the pilot symbol. As an example, every N... G The first symbol in the set is the pilot symbol. Typically, N G =32, 64, 96, or 128, etc. In the X-polarization or Y-polarization direction, each pilot symbol is one of 3+3j, 3-3j, -3+3j, or -3-3j, where j is the imaginary unit of a complex number. That is, each pilot symbol uses one of the outermost four symbols in the 16QAM constellation diagram.

[0221] In some specific applications, the DSP framing operation adds one pilot symbol to every 127 DP-16QAM symbols in every 96 × 127 = 12192 pre-framing DP-16QAM symbols (i.e., payload symbols), resulting in 96 × 128 = 12288 DP-16QAM symbols to be transmitted. That is, the pilot interval for DSP framing is 128 symbols. These 12288 DP-16QAM symbols to be transmitted are called a DSP frame. It should be understood that, in the X-polarization direction or the Y-polarization direction, every N... G The first symbol in the 128 symbols is the pilot symbol. Here, the 12192 pre-framing DP-16QAM symbols (i.e., payload symbols) are obtained by mapping 12192 × 8 = 97536 bits from m second data streams using DP-16QAM. Considering 1.6T transmission, the corresponding baud rate is 1700 × (127 / 120) × (128 / 127) / 8 ≈ 226.7 Gbps, which is lower than the baud rate (247.2 Gbps) of directly multiplexing the existing 800LR coding and framing scheme. Lower bandwidth devices can be used, resulting in lower cost and power consumption.

[0222] Figure 6(b) is a schematic diagram of another implementation of dual-polarization symbol mapping and DSP framing in this application embodiment. As shown in Figure 6(b), DSP framing is performed before DP-16QAM symbol mapping, and DSP framing is performed on a bit-by-bit basis. Specifically, m second data streams are interleaved a second time to obtain one third data stream, a target bit sequence is inserted into the third data stream to obtain a fourth data stream, and DP-16QAM symbol mapping is performed on the fourth data stream to obtain a first dual-polarization symbol stream. The target bit sequence is then processed by DP-16QAM symbol mapping to obtain a target symbol sequence.

[0223] Figure 6(c) is a schematic diagram of another implementation of dual-polarization symbol mapping and DSP framing in this application embodiment. As shown in Figure 6(c), DSP framing is performed before DP-16QAM symbol mapping. DSP framing is performed on a bit-by-bit basis, and the data after the second interleaving is represented by two data streams. Specifically, the m second data streams are second-interleaved to obtain two third data streams. The target bit sequence X and target bit sequence Y are inserted into the two third data streams respectively to obtain two fourth bit streams. The two fourth bit streams are then subjected to DP-16QAM symbol mapping to obtain the first dual-polarization symbol stream. Among them, the target bit sequence X is subjected to DP-16QAM symbol mapping to obtain the target symbol sequence in the X polarization direction, and the target bit sequence Y is subjected to DP-16QAM symbol mapping to obtain the target symbol sequence in the Y polarization direction.

[0224] Figure 6(d) is a schematic diagram of another implementation of dual-polarization symbol mapping and DSP framing in this application. As shown in Figure 6(d), DSP framing is performed before DP-16QAM symbol mapping. DSP framing is performed on a bit-by-bit basis, and the data after the second interleaving is represented by four data streams. Specifically, the m second data streams are second-interleaved to obtain four third data streams, and the target bit sequence X is inserted into each of the four third data streams. I Target bit sequence X Q Target bit sequence Y I Target bit sequence Y Q Four fourth bit streams are obtained, and DP-16QAM symbol mapping is performed on these four fourth bit streams to obtain the first dual-polarization symbol stream. The target bit sequence X... I After DP-16QAM symbol mapping, the I component of the target symbol sequence in the X polarization direction is obtained, and the target bit sequence X is obtained. Q After DP-16QAM symbol mapping, the Q component of the target symbol sequence in the X-polarization direction is obtained, and the target bit sequence Y is obtained. I After DP-16QAM symbol mapping, the I component of the target symbol sequence in the Y polarization direction is obtained, and the target bit sequence Y... Q The Q component of the target symbol sequence in the Y polarization direction is obtained by DP-16QAM symbol mapping.

[0225] It should be noted that in some specific scenarios, one dual-polarization symbol stream is described by two symbol streams: one is the symbol stream in the X-polarization direction, and the other is the symbol stream in the Y-polarization direction. In other specific scenarios, one dual-polarization symbol stream is described by four data streams, the first of which is the data stream of the I-path component of the dual-polarization symbol stream in the X-polarization direction (referred to as X). I The second data stream is the Q-path data stream of the dual-polarization symbol stream in the X-polarization direction (abbreviated as X). Q The third data stream is the data stream of the I-path component of the dual-polarization symbol stream in the Y-polarization direction (abbreviated as Y). I The fourth item is the data stream of the Q-path component of the dual-polarization symbol stream in the Y-polarization direction (abbreviated as Y). Q (Data flow).

[0226] The transmitting end sends a data frame (also called a DSP frame) from the aforementioned DP-16QAM symbol stream to the receiving end. The transmitted data frame will be transmitted through the channel to reach the receiving end. In some possible scenarios, the aforementioned DP-16QAM symbol stream to be transmitted undergoes digital-to-analog conversion (DAC) to obtain four analog signals, corresponding to the I component signal in the X-polarization direction, the Q component signal in the X-polarization direction, the I component signal in the Y-polarization direction, and the Q component signal in the Y-polarization direction, respectively, and the signals are transmitted to the receiving end through optical fiber.

[0227] The receiving end performs signal processing on the received data frames. It should be understood that the data frames received by the receiving end have been transmitted through the channel, which can be understood as distorted signals affected by noise or other impairments in the channel. That is, the data frames received by the receiving end are different from the data frames sent by the sending end. For example, the data frames received by the receiving end and the data frames sent by the sending end are not aligned, and the receiving end needs to perform frame synchronization based on the pilot symbols. The specific operations of the receiving end after receiving the data frames are not described in detail in this application; please refer to [reference needed]. Figure 1 The system architecture diagram shown illustrates, for example, the signal processing performed by the receiving-end DSP processor on the received data frames, including operations such as dispersion compensation, synchronization, and phase recovery.

[0228] In the first aspect of this application embodiment, two internal codewords are obtained from each of the m second data streams, resulting in a total of 2m internal codewords, or 254×m bits. These codes are then shuffled to improve the burst immunity and colored noise immunity of the cascaded FEC scheme. Here, m is a positive integer multiple of 4.

[0229] Figure 7 This is a schematic diagram illustrating one implementation of the mapping of 127 DP-16QAM symbols in this application. Figure 7As shown, considering every four second data streams out of the aforementioned m second data streams, two internal codewords are obtained from each second data stream, resulting in a total of 4×2×127 bits. After DP-16QAM mapping, 127 DP-16QAM symbols are obtained. These 127 DP-16QAM symbols serve as 127 payload symbols out of 128 consecutive DP-16QAM symbols in one DSP frame (including X-polarization and Y-polarization directions). The remaining symbol is the pilot symbol added during DSP framing. In this case, obtaining two internal codewords from each of the four second data streams, totaling 4×2×127 = 1016 bits, and obtaining 127 DP-16QAM symbols after DP-16QAM mapping, followed by the addition of one pilot symbol, allows for direct transmission. This means that no additional buffer is needed to store payload symbols during DPS framing, resulting in a simple implementation and low power consumption. The proposed scheme in the first aspect offers stronger burst resistance.

[0230] It should be noted that obtaining bits from m second data streams and then performing DP-16QAM symbol mapping to obtain one DP-16QAM symbol stream is called the second interleaving, where the operations performed on the m second data streams before the DP-16QAM symbol mapping are performed. Here, the 254 bits (two inner codewords) obtained from each second data stream are called the bit set. In some specific applications, the bit set can also be called the double codeword bit set, or other names.

[0231] The m bit sets (containing 2m codewords) from the aforementioned m second data streams undergo second interleaving and DP-16QAM symbol mapping to obtain M DP-16QAM symbols, denoted as S0, S1, S2, ..., S M-2 ,S M-1 Here, M = 254 × m / 8. Consider S. i For the i-th (0≤i≤M-1)th DP-16QAM symbol out of M DP-16QAM symbols, the 8 bits of the i-th (0≤i≤M-1)th DP-16QAM symbol out of M DP-16QAM symbols are denoted as

[0232] It should be understood that the m second data streams are counted starting from 0. Second data stream 0 is the 0th second data stream in the m second data streams, second data stream 1 is the 1st second data stream in the m second data streams, and so on. The m bit sets of the m second data streams are also counted starting from 0. Bit set 0 is the bit set of the 0th second data stream in the m second data streams (also called the 0th bit set), bit set 1 is the bit set of the 1st second data stream in the m second data streams (also called the 1st bit set), and so on. 8 bits It also starts counting from 0, bits. It is the 0th bit out of 8 bits. It is the first bit out of 8 bits, and so on.

[0233] In some specific applications, the m second data streams include second data stream 0 to second data stream m-1. The following conditions must be met:

[0234] Bit From the second data stream The 2nd × (i % 127) + i % 2nd bit in the bit set;

[0235] Bit From the second data stream The 2nd × (i % 127) + (i + 1) % 2nd bit in the bit set;

[0236] Bit From the second data stream The 2nd × (i % 127) + i % 2nd bit in the bit set;

[0237] Bit From the second data stream The 2nd × (i % 127) + (i + 1) % 2nd bit in the bit set;

[0238] Bit From the second data stream The 2nd × (i % 127) + i % 2nd bit in the bit set;

[0239] Bit From the second data stream The 2nd × (i % 127) + (i + 1) % 2nd bit in the bit set;

[0240] Bit From the second data stream The 2nd × (i % 127) + i % 2nd bit in the bit set;

[0241] Bit From the second data stream The 2nd (i%127)+(i+1)%2th bit in the bit set.

[0242] In the second aspect of this application embodiment, one internal codeword is obtained from each of the m second data streams, resulting in a total of m internal codewords (127 × m bits). These codewords are then shuffled to improve the burst immunity and colored noise immunity of the cascaded FEC scheme. Here, m is a positive integer multiple of 8. Considering every 8 second data streams of the aforementioned m second data streams, one internal codeword is obtained from each data stream, totaling 8 × 127 bits. After DP-16QAM mapping, 127 DP-16QAM symbols are obtained. These 127 DP-16QAM symbols serve as 127 payload symbols out of 128 consecutive DP-16QAM symbols in one DSP frame (including X-polarization and Y-polarization directions). The remaining symbol is a pilot symbol added during DSP framing. At this point, 8 × 127 = 1016 bits are obtained from each of the 8 second data streams. After DP-16QAM mapping, 127 DP-16QAM symbols are obtained. One pilot symbol is then added directly for transmission. In other words, no additional buffer is needed to store payload symbols during DPS framing, resulting in simple implementation and low power consumption. The second proposed solution also has lower latency.

[0243] For every 8 second data streams in the above m second data streams, one internal codeword is obtained from each data stream. The resulting 8 internal codeword bits, totaling 8×127 bits, are mapped by DP-16QAM to obtain 127 DP-16QAM symbols, which can be implemented in the following way.

[0244] Figure 8 This is a schematic diagram illustrating another implementation of the mapping to obtain 127 DP-16QAM symbols in this application. For example... Figure 8 As shown, four of the eight internal codewords contain a total of 4 × 127 = 508 bits. 4 × 126 = 504 bits of these 508 bits are mapped using DP-16QAM to obtain 63 DP-16QAM symbols. The remaining four bits from these four internal codewords, combined with four bits from the other four internal codewords (a total of eight bits), are mapped using DP-16QAM to obtain one DP-16QAM symbol. The remaining 504 bits from the other four internal codewords are then mapped using DP-16QAM to obtain 63 DP-16QAM symbols.

[0245] In some specific applications, the bits of the m codewords obtained from the m second data streams are represented by m / 2 bit sets, where each bit set contains the bits of two codewords. These m / 2 bit sets (i.e., the m codewords from the m second data streams) are then mapped using DP-16QAM symbols to obtain M DP-16QAM symbols, denoted as S0, S1, S2, ..., S... M-2 ,S M-1 Here, M = 127 × m / 8. Consider S. i For the i-th (0≤i≤M-1)th DP-16QAM symbol out of M DP-16QAM symbols, the 8 bits of the i-th (0≤i≤M-1)th DP-16QAM symbol out of M DP-16QAM symbols are denoted as

[0246] It should be understood that the m second data streams are counted starting from 0. Second data stream 0 is the 0th second data stream out of the m second data streams, second data stream 1 is the 1st second data stream out of the m second data streams, and so on. The m / 2 bit set is also counted starting from 0. Bit set 0 is the 0th bit set out of the m / 2 bit set, bit set 1 is the 1st bit set out of the m / 2 bit set, and so on. 8 bits It also starts counting from 0, bits. It is the 0th bit out of 8 bits. It is the first bit out of 8 bits, and so on.

[0247] The m / 2 bit set includes bit set 0 to bit set m / 2-1. The following conditions must be met:

[0248] Bit From the The 2nd (i%127)+i%2th bit in the set of bits;

[0249] Bit From the The 2nd × (i % 127) + (i + 1) % 2nd bit in the set of bits;

[0250] Bit From the The 2nd (i%127)+i%2th bit in the set of bits;

[0251] Bit From the The 2nd × (i % 127) + (i + 1) % 2nd bit in the set of bits;

[0252] Bit From the The 2nd (i%127)+i%2th bit in the set of bits;

[0253] Bit From the The 2nd × (i % 127) + (i + 1) % 2nd bit in the set of bits;

[0254] Bit From the The 2nd (i%127)+i%2th bit in the set of bits;

[0255] Bit From the The 2nd (i%127)+(i+1)%2th bit in the set of bits.

[0256] Here, "the above m codewords obtained from the m second data streams are represented by m / 2 bit sets, where each bit set contains 2 codewords" can be implemented in multiple ways.

[0257] In some specific applications, the k-th bit set (also called bit set k) in the m / 2 bit set contains a total of 254 bits of two codewords, which come from the second data stream. 127 bits of an internal code and a second data stream One internal code has 127 bits, of which For example, consider m = 16,

[0258] The 0th bit set contains two codewords from the second data stream 0 and the second data stream 4, respectively.

[0259] The first bit set contains two codewords from the second data stream 1 and the second data stream 5, respectively.

[0260] The second bit set contains two codewords from the second data stream 2 and the second data stream 6, respectively.

[0261] The third bit set contains two codewords from the second data stream 3 and the second data stream 7, respectively.

[0262] The fourth bit set contains two codewords from the second data stream 8 and the second data stream 12, respectively.

[0263] The fifth bit set contains two codewords from the second data stream 9 and the second data stream 13, respectively.

[0264] The 6th bit set contains two codewords from the second data stream 10 and the second data stream 14, respectively.

[0265] The 7th bit set contains two codewords from the second data stream 11 and the second data stream 15, respectively.

[0266] In other specific applications, the k-th bit set (also called bit set k) in the m / 2 bit set contains a total of 254 bits of two codewords, which come from the second data stream. 127 bits of an internal code and a second data stream One internal code has 127 bits, of which For example, consider m = 16,

[0267] The 0th bit set contains two codewords from the second data stream 0 and the second data stream 1, respectively.

[0268] The first bit set contains two codewords from the second data stream 2 and the second data stream 3, respectively.

[0269] The second bit set contains two codewords from the second data stream 4 and the second data stream 5, respectively.

[0270] The third bit set contains two codewords from the second data stream 6 and the second data stream 7, respectively.

[0271] The fourth bit set contains two codewords from the second data stream 8 and the second data stream 9, respectively.

[0272] The fifth bit set contains two codewords from the second data stream 10 and the second data stream 11, respectively.

[0273] The 6th bit set contains two codewords from the second data stream 12 and the second data stream 13, respectively.

[0274] The 7th bit set contains two codewords from the second data stream 14 and the second data stream 15, respectively.

[0275] Example 1: This example provides a specific implementation scheme for transmitting 1.6T service by the transmitting device 01, and using a linear block code with a code length of 127 bits and an information bit length of 120 bits for the internal code encoding, corresponding to m = 16 second data streams.

[0276] Figure 9 This is a schematic diagram illustrating one implementation method of obtaining a DP-16QAM symbol stream through data processing in this application. For example... Figure 9As shown, the eight AUI data streams of 1.6TAUI-8 are PAM4 decoded to obtain eight demodulated data streams. The PAM4 decoding is also called PAM4 demodulation. The eight demodulated data streams are then subjected to 8:16 symbol demultiplexing and alignment flag locking to obtain 16 locked data streams. Specifically, the 8:16 symbol demultiplexing includes p = eight 1:2 symbol demultiplexing operations. Each 1:2 symbol demultiplexing operation uses a round-robin method, distributing 40 bits at a time, to demultiplex the input first data stream into two output demultiplexed data streams.

[0277] The 16 locked data streams are deskewed by 40 bits to obtain q = 16 first data streams, also known as physical coding sublayer (PCS) data streams, simply denoted as PCSL. Next, the 16 first data streams undergo convolutional interleaving, internal code encoding, first interleaving (cyclic shift), second interleaving, DP-16QAM mapping, and DSP framing to obtain one DP-16QAM symbol stream. Here, internal code encoding uses a linear block code with a code length of 127 bits and an information bit length of 120 bits, such as Hamming(127,120). In DSP framing (also known as the framing operation), one pilot symbol is added to each of the 127 payload symbols, so that each DSP frame contains one pilot symbol and 127 payload symbols for every 128 DP-16QAM symbols.

[0278] The convolutional interleaver described above contains r = 3 delay lines, with a difference of Q = 12 between the number of storage units in each pair of adjacent delay lines. Each storage unit stores d = 40 bits. In convolutional interleaving, the d = 40 bits stored in each storage unit correspond to 4 RS symbols. To reduce the difficulty of high-speed implementation of the convolutional interleaver, Q is usually chosen to be a multiple of 4 or 8; for example, Q can also be chosen as 16.

[0279] In this embodiment, the first interleaving (cyclic shift) is a cyclic shift operation performed on the 12 RS symbols corresponding to the 120 information bits in each inner codeword, with the symbol as the granularity. This involves cyclically shifting the 120 information bits (u0, u1, ..., u...) of each Hamming (127, 120) codeword C in the data stream i. 118 ,u 119 Perform a right circular shift. Each bit yields a sequence W consisting of 120 bits, denoted as (w0, w1, ..., w...). 118 ,w 119 ),in, If 0 ≤ i < 16, 0 ≤ j < 120, then the 127 bits obtained after cyclic shifting the codeword C are represented as (w0, w1, ..., w 118 ,w 119 v0, v1, ..., v5, v6), where v0, v1, ..., v5, v6 are the 7 parity bits in the Hamming codeword. It is a multiple of 10, and All are greater than 10 and less than 120.

[0280] To make concatenated codes more resistant to bursts The possible values ​​are 20, 30, 40, 70, and 80. The following example demonstrates a circular shift for a data stream with m = 16 data streams. The values ​​of are shown in Table 1 below.

[0281] Table 1

[0282]

[0283] Figure 10 This is a schematic diagram illustrating an application scenario where DP-16QAM symbols are mapped in an embodiment of this application. For example... Figure 10 As shown, two internal codewords (whose information bits have been cyclically shifted and their positions changed) are obtained from each of the m=16 second data streams, resulting in a total of 32 internal codewords, or 254×16=4064 bits. These bits are then shuffled to improve the burst resistance and colored noise resistance of the cascaded FEC scheme.

[0284] Here, the two internal codewords obtained from each second data stream are called the bit set, which consists of 254 bits in total. The bit set contains two information bit sequences, each containing 120 information bits whose positions are scrambled using a cyclic method.

[0285] The m=16 bit sets (containing 32 internal codewords) in the above m=16 second data streams are subjected to second interleaving and DP-16QAM symbol mapping to obtain M=508 DP-16QAM symbols, denoted as S0, S1, S2, ..., S 506 ,S 507 Consider S i For the i-th (0≤i≤507) DP-16QAM symbol in M=508 DP-16QAM symbols, the 8 bits of the i-th (0≤i≤507) DP-16QAM symbol in M=508 DP-16QAM symbols are denoted as Here, we can assume that the 8 bits correspond to 8 bit classes.

[0286] In this embodiment, the following second interleaving method is considered:

[0287] Bit From the second data stream The 2nd × (i % 127) + i % 2nd bit in the bit set;

[0288] Bit From the second data stream The 2nd × (i % 127) + (i + 1) % 2nd bit in the bit set;

[0289] Bit From the second data stream The 2nd × (i % 127) + i % 2nd bit in the bit set;

[0290] Bit From the second data stream The 2nd × (i % 127) + (i + 1) % 2nd bit in the bit set;

[0291] Bit From the second data stream The 2nd × (i % 127) + i % 2nd bit in the bit set;

[0292] Bit From the second data stream The 2nd × (i % 127) + (i + 1) % 2nd bit in the bit set;

[0293] Bit From the second data stream The 2nd × (i % 127) + i % 2nd bit in the bit set;

[0294] Bit From the second data stream The 2nd (i%127)+(i+1)%2th bit in the bit set.

[0295] Using the second interleaving method described above, each bit set corresponds relatively evenly to 8 bit types. For example, in the 254 bits of the two internal codewords contained in the 0th bit set, 32 bits correspond to bit type 0, 32 bits correspond to bit type 1, 31 bits correspond to bit type 2, 31 bits correspond to bit type 3, 32 bits correspond to bit type 4, 32 bits correspond to bit type 5, 32 bits correspond to bit type 6, and 32 bits correspond to bit type 7, exhibiting good burst resistance. For instance, using the cyclic shift scheme shown in Table 1, number 1, it can tolerate 322 consecutive burst errors of DP-16QAM symbols (2576 bits); using the cyclic shift scheme shown in Table 1, number 2, it can tolerate 347 consecutive burst errors of DP-16QAM symbols (2776 bits); and using the cyclic shift scheme shown in Table 1, number 3, it can tolerate 352 consecutive burst errors of DP-16QAM symbols (2816 bits). The existing 800LR scheme has a burst error resistance capability of approximately 190 DP-16QAM symbols (1520 bits), meaning that the scheme provided in this embodiment has a very good burst error resistance capability.

[0296] In addition, every 4-bit set is mapped by DP-16QAM to obtain 127 DP-16QAM symbols, which are then used as 127 payload symbols in a DSP frame of 128 consecutive DP-16QAM symbols.

[0297] Figure 11 This is a schematic diagram of the structure of a DSP frame. For example... Figure 11 As shown, in any polarization direction, a DSP frame contains 96 × 128 = 12288 DP-16QAM symbols. Within a DSP frame, 128 consecutive DP-16QAM symbols include one pilot symbol and 127 payload symbols. Therefore, no additional buffer is needed to store payload symbols during DPS framing, resulting in simple implementation and low power consumption. Furthermore, the 96 pilot symbols in a single DSP frame can reuse the existing 96 pilot symbols from the 800LR, facilitating compatibility with 800LR implementations.

[0298] Using the data processing method given in this embodiment, the baud rate corresponding to one DP-16QAM symbol stream to be transmitted is approximately 226.7 Gbd, which is about 10% lower than the 247.2 Gbd of the existing 800LR solution. It requires less device bandwidth, is simple to implement, consumes less power, and has a lower cost. It can be applied to transmission scenarios such as data center interconnection and data center networks where power consumption and cost requirements are strict.

[0299] Figure 12 This is a schematic diagram illustrating another implementation method for obtaining a DP-16QAM symbol stream through data processing in this application. It differs from... Figure 9The embodiments shown are as follows: Figure 12 As shown, in some specific applications, the cyclic shift operation is performed before the internal code encoding, which can also achieve the effect of the above embodiment 1. It has good anti-burst capability, is simple to implement, has low power consumption, and has a low baud rate and low cost. It can be applied to transmission scenarios such as data center interconnection and data center network where power consumption and cost requirements are strict.

[0300] Example 2: Based on Example 1, consider obtaining one internal codeword from each of the m=16 second data streams, for a total of 16 internal codewords, i.e., 127×16=2032 bits, and shuffling their order to improve the burst resistance and colored noise resistance of the cascaded FEC scheme.

[0301] Figure 13 This is a schematic diagram illustrating another application scenario of the DP-16QAM symbol mapped in the embodiments of this application. For example... Figure 13 As shown, the m=16 internal codewords obtained from the m=16 second data streams are represented by m / 2=8 bit sets, where each bit set contains 2 internal codewords. More specifically, the 2 codewords in the 0th bit set come from second data stream 0 and second data stream 4, respectively; the 2 codewords in the 1st bit set come from second data stream 1 and second data stream 5, respectively; the 2 codewords in the 2nd bit set come from second data stream 2 and second data stream 6, respectively; the 2 codewords in the 3rd bit set come from second data stream 3 and second data stream 7, respectively; the 2 codewords in the 4th bit set come from second data stream 8 and second data stream 12, respectively; the 2 codewords in the 5th bit set come from second data stream 9 and second data stream 13, respectively; the 2 codewords in the 6th bit set come from second data stream 10 and second data stream 14, respectively; and the 2 codewords in the 7th bit set come from second data stream 11 and second data stream 15, respectively.

[0302] The above 8 bit sets (containing 16 internal codewords) are mapped to M = 254 DP-16QAM symbols through DP-16QAM symbol mapping, denoted as S0, S1, S2, ..., S 252 ,S 253 Consider S i For the i-th (0≤i≤253) DP-16QAM symbol in M=254 DP-16QAM symbols, the 8 bits of the i-th (0≤i≤253) DP-16QAM symbol in M=254 DP-16QAM symbols are denoted as Here, we can assume that the 8 bits correspond to 8 bit classes.

[0303] In this embodiment, the following second interleaving method is considered:

[0304] Bit From the second data stream The 2nd × (i % 127) + i % 2nd bit in the bit set;

[0305] Bit From the second data stream The 2nd × (i % 127) + (i + 1) % 2nd bit in the bit set;

[0306] Bit From the second data stream The 2nd × (i % 127) + i % 2nd bit in the bit set;

[0307] Bit From the second data stream The 2nd × (i % 127) + (i + 1) % 2nd bit in the bit set;

[0308] Bit From the second data stream The 2nd × (i % 127) + i % 2nd bit in the bit set;

[0309] Bit From the second data stream The 2nd × (i % 127) + (i + 1) % 2nd bit in the bit set;

[0310] Bit From the second data stream The 2nd × (i % 127) + i % 2nd bit in the bit set;

[0311] Bit From the second data stream The 2nd (i%127)+(i+1)%2th bit in the bit set.

[0312] Using the second interleaving method described above, each bit set corresponds relatively evenly to 8 bit types. For example, in the 254 bits of the two inner codewords contained in the 0th codeword bit sequence, 32 bits correspond to bit type 0, 32 bits correspond to bit type 1, 31 bits correspond to bit type 2, 31 bits correspond to bit type 3, 32 bits correspond to bit type 4, 32 bits correspond to bit type 5, 32 bits correspond to bit type 6, and 32 bits correspond to bit type 7, exhibiting good burst resistance. For instance, using the cyclic shift scheme shown in Table 1, number 1, it can tolerate 195 consecutive burst errors of DP-16QAM symbols (1560 bits); using the cyclic shift scheme shown in Table 1, number 2, it can tolerate 220 consecutive burst errors of DP-16QAM symbols (1760 bits); and using the cyclic shift scheme shown in Table 1, number 3, it can tolerate 208 consecutive burst errors of DP-16QAM symbols (1664 bits). The existing 800LR scheme has a burst error resistance capability of approximately 190 DP-16QAM symbols (1520 bits). In other words, the scheme provided in this embodiment has a better burst error resistance capability compared with the existing scheme.

[0313] Furthermore, every 4-bit set is mapped by DP-16QAM to obtain 127 DP-16QAM symbols, which are then used as 127 payload symbols out of a consecutive 128 DP-16QAM symbols in a single DSP frame (including X-polarization and Y-polarization directions). The remaining symbol is used as a pilot symbol added during DSP framing. In this way, no additional buffer is needed to store the payload symbols during DPS framing, resulting in a simple implementation and low power consumption.

[0314] Using the data processing method given in this embodiment, the baud rate corresponding to one DP-16QAM symbol stream to be transmitted is approximately 226.7 Gbd, which is about 10% lower than the 247.2 Gbd of the existing 800LR solution. It requires less device bandwidth, is simple to implement, consumes less power, and has a lower cost. It can be applied to transmission scenarios such as data center interconnection and data center networks where power consumption and cost requirements are strict.

[0315] Example 3: Based on Example 2, another representation of the 8-bit set is given.

[0316] Figure 14 This is a schematic diagram illustrating another application scenario of the DP-16QAM symbol mapped in the embodiments of this application. For example... Figure 14As shown, the m=16 inner codewords obtained from the m=16 second data streams are represented by m / 2=8 bit sets, where each bit set contains 2 inner codewords. More specifically, the 2 codewords in the 0th bit set come from the second data stream 0 and the second data stream 1, respectively; the 2 codewords in the 1st bit set come from the second data stream 2 and the second data stream 3, respectively; the 2 codewords in the 2nd bit set come from the second data stream 4 and the second data stream 5, respectively; the 2 codewords in the 3rd bit set come from the second data stream 6 and the second data stream 7, respectively; the 2 codewords in the 4th bit set come from the second data stream 8 and the second data stream 9, respectively; the 2 codewords in the 5th bit set come from the second data stream 10 and the second data stream 11, respectively; the 2 codewords in the 6th bit set come from the second data stream 12 and the second data stream 13, respectively; and the 2 codewords in the 7th bit set come from the second data stream 14 and the second data stream 15, respectively.

[0317] The above embodiments use m=16 as an example to introduce the data processing method proposed in this application. It can also be easily extended to scenarios such as m=32, 64, 8, etc., which are known to those skilled in the art. The embodiments of this application will not list them one by one.

[0318] Figure 15 This is a schematic diagram of a data processing device in an embodiment of this application. The data processing device is applied at the sending end, such as... Figure 15 As shown, the data processing device includes a first processing unit 201 and a second processing unit 202. The first processing unit 201 is used to perform the operation of step 101 in the above embodiment, and the second processing unit 202 is used to perform the operation of step 102 in the above embodiment.

[0319] Figure 16 This is another schematic diagram of the data processing device in an embodiment of this application. This data processing device is applied at the receiving end, such as... Figure 16 As shown, the data processing device includes a receiving unit 301 and a processing unit 302. The receiving unit 301 is used to receive signals from the transmitting end, and the processing unit 302 is used to process the received signals accordingly, for example, the processing unit 302 is used to perform operations such as FEC decoding and deconvolution interleaving.

[0320] It should be understood that Figure 15 and Figure 16The provided data processing device can also be implemented in other ways. For example, the unit division in the above device is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system. In addition, the functional units in the various embodiments of this application may be integrated into one processing unit, or they may be independent physical units, or two or more functional units may be integrated into one processing unit. The integrated unit described above can be implemented in hardware or in the form of software functional units.

[0321] Figure 17 This is a schematic diagram of one structure of the optical module in an embodiment of this application. Figure 17 As shown, the optical module includes a processor 401 and an interface 402. The interface 402 can be a transceiver or an input / output interface, used to receive signals from other devices and transmit them to the processor 401, or to send signals from the processor 401 to other devices. Optionally, the optical module may also include a memory 403, which stores program instructions and data.

[0322] In one possible scenario, the optical module is applied at the transmitting end, and the processor 401 is used to execute the operations of steps 101 and 102 in the above embodiments. For example, the processor 401 includes... Figure 15 The first processing unit 201 and the second processing unit 202 are shown. As an example, after executing steps 101 and 102 in the above embodiments, the processor 401 obtains a data stream and sends it through interface 402. In this example, interface 402 can specifically refer to an electrical interface. As another example, the processor 401 executes steps 101 and 102 in the above embodiments to obtain a data stream. The modulator in the optical module performs electro-optical conversion and other signal processing based on the data stream to obtain an optical signal, and then sends the optical signal through interface 402. In this example, interface 402 can specifically refer to an optical interface.

[0323] In another possible scenario, the optical module is applied at the receiver, and the processor 401 is used to process the received signal, for example, performing operations such as FEC decoding and deconvolution interleaving. For example, the processor 401 includes... Figure 16The processing unit 302 shown is illustrated. As an example, the interface receives an optical signal transmitted through a channel. The demodulator in the optical module performs signal processing such as photoelectric conversion on the optical signal to obtain a data stream. The processor 401 performs corresponding processing operations on the data stream. In this example, interface 402 specifically refers to an optical interface. As another example, the demodulator in the optical module performs signal processing such as photoelectric conversion on the received optical signal to obtain a data stream, and transmits the data stream to the processor 401 through interface 402. The processor 401 performs corresponding processing operations on the data stream. In this example, interface 402 specifically refers to an electrical interface.

[0324] Typically, an optical module consists of optoelectronic devices, a processor, and an interface. The optoelectronic devices include transmitting and receiving devices. The transmitting end of the optical module converts electrical signals into optical signals and transmits them through optical fibers. The receiving end of the optical module receives the optical signals and converts them back into electrical signals.

[0325] It should be noted that the types of optical modules in this application embodiment include, but are not limited to, normal optical modules, near package optics (NPO) modules, and co-packaged optics (CPO) modules. Normal optical modules can perform functions including, but not limited to, digital signal processing (DSP) and clock data recovery (CDR). For example, a normal optical module converts analog signals to digital signals, performs DSP on the digital signals, and then converts them back to analog signals before sending them to the host device. Because DSP requires retiming, a normal optical module can also be called a retimed module. Normal optical modules connect to the host device via an attachment unit interface (AUI). NPO and CPO modules do not have pluggable physical packages and are closer to the host device. NPO and CPO modules can also be called optical engines. NPO or CPO technology is a technology that "packages" the host device (or host chip) and the optical engine. When NPO technology is used to encapsulate the host-side device and the optical engine, the optical engine can be called an NPO module. When CPO technology is used to encapsulate the host-side device and the optical engine, the optical engine can be called a CPO module.

[0326] Figure 18 This is a schematic diagram of the structure of a network device in an embodiment of this application. Figure 18As shown, the network device includes a host-side device 501 and an optical module 502. In one possible scenario, the network device acts as a data transmitter, with the host-side device 501 sending electrical signals to the optical module 502. The optical module 502 converts the electrical signals into optical signals and transmits them through a channel. In another possible scenario, the network device acts as a data receiver, with the optical module 502 converting the received optical signals into electrical signals and sending them to the host-side device 501. For example, the host-side device 501 may specifically be a switch, router, or server. It should be understood that the network device in this embodiment has both transmitting and receiving functions.

[0327] This application also provides an Optical Transport Network (OTN) device, which includes line-side equipment and client-side equipment. The client-side equipment may also be referred to as a tributary-side equipment in some scenarios. The line-side equipment includes a processor and an interface. In one possible scenario, the OTN device is used at the transmitting end, and the processor is used to execute steps 101 and 102 in the above embodiments. In another possible scenario, the OTN device is used at the receiving end, and the processor is used to execute the inverse operations of steps 101 and 102 in the above embodiments. The interface can be a transceiver or an input / output interface, used to receive signals from other devices besides the line-side equipment and transmit them to the processor, or to send signals from the processor to other devices besides the line-side equipment.

[0328] This application also provides a chip. The chip integrates circuitry for implementing the functions of the processor 401 described above, and one or more interfaces. As an example, the chip integrates a memory. As another example, when the chip does not integrate a memory, it can be connected to an external memory via the interface. The chip can perform the method steps of any one or more of the foregoing embodiments. Alternatively, the chip can implement the actions performed by the processing and transmission device in the foregoing embodiments based on program code stored in the memory.

[0329] As an example, the chip in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor, any conventional processor, or a processing circuit that implements a specific function.

[0330] This application also provides a computer-readable storage medium including a program or instructions that, when run on a computer, cause the method performed as described in the above method embodiments to be implemented.

[0331] It should be understood that the processor mentioned in the embodiments of this application can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc. When implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. The memory can exist independently and be connected to the processor, or the memory can be integrated with the processor.

[0332] As an example, the processor in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor, any conventional processor, or a processing circuit that implements a specific function.

[0333] In embodiments of this application, the memory may be random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium may also be a component of the processor. The processor and storage medium may reside in an ASIC. Additionally, the ASIC may reside in a network device or a terminal device. Alternatively, the processor and storage medium may exist as discrete components in the network device or terminal device.

[0334] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof.

[0335] When implemented in hardware, the data transmission method provided in this application embodiment may be implemented without reading software code or instructions. For example, it may be implemented by CPU, DSP, ASIC, FPGA, other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.

[0336] When implemented using software, it can be implemented entirely or partially in the form of a computer program product. A computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, all or part of the processes or functions of the embodiments of this application are performed. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a network device, a terminal device, or other programmable device. The computer program or instructions can be stored in or transmitted through a computer-readable storage medium. The computer-readable storage medium can be any available medium that a computer can access, or a data storage device such as a server integrating one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a Digital Versatile Disc (DVD); or it can be a semiconductor medium, such as a solid-state disk (SSD).

[0337] Finally, it should be noted that the above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A data processing method, characterized in that, include: Forward error correction (FEC) encoding is performed on multiple first data streams that have undergone Reed-Solomon RS encoding to obtain m second data streams, where m is a positive integer multiple of 4. The codewords after FEC encoding consist of 127 bits, which are obtained by encoding 120 information bits through FEC. The m second data streams are subjected to dual-polarization hexadecimal quadrature amplitude modulation (DP-16QAM) symbol mapping and framing to obtain one DP-16QAM symbol stream. The 127 DP-16QAM symbols in the DP-16QAM symbol stream are obtained by mapping the 8 codewords in the m second data streams with DP-16QAM symbols.

2. The method according to claim 1, characterized in that, The DP-16QAM symbol stream includes at least one data frame. Each of the at least one data frame contains 128 consecutive DP-16QAM symbols, including one pilot symbol and 127 payload symbols. The 127 payload symbols are obtained by mapping 8 codewords from the m second data streams through DP-16QAM symbols.

3. The method according to claim 2, characterized in that, Each data frame includes 96 pilot symbols and 12,192 payload symbols.

4. The method according to any one of claims 1 to 3, characterized in that, The eight codewords include two codewords from each of the four second data streams.

5. The method according to claim 4, characterized in that, In the four second data streams, two bits from each of the two codewords, totaling eight bits, are mapped using DP-16QAM symbols to obtain one DP-16QAM symbol.

6. The method according to claim 4 or 5, characterized in that, In each of the four second data streams, the z-th bit and the (z+1)-th bit (a total of 8 bits) of the two codewords are mapped by DP-16QAM symbols to obtain one DP-16QAM symbol, where 0 ≤ z ≤ 252, and z is an even number.

7. The method according to any one of claims 4 to 6, characterized in that, In the m second data streams, each second data stream contains two codewords forming a bit set. These m bit sets from the m second data streams are mapped using DP-16QAM symbols to obtain M DP-16QAM symbols, where M = 254 × m / 8. The mapping represents the 8 bits of the i-th DP-16QAM symbol among the M DP-16QAM symbols. The m second data streams include second data stream 0 to second data stream m-1; The following conditions must be met: From the second data stream The 2nd × (i % 127) + i % 2nd bit in the bit set; From the second data stream The 2nd × (i % 127) + (i + 1) % 2nd bit in the bit set; From the second data stream The 2nd × (i % 127) + i % 2nd bit in the bit set; From the second data stream The 2nd × (i % 127) + (i + 1) % 2nd bit in the bit set; From the second data stream The 2nd × (i % 127) + i % 2nd bit in the bit set; From the second data stream The 2nd × (i % 127) + (i + 1) % 2nd bit in the bit set; From the second data stream The 2nd × (i % 127) + i % 2nd bit in the bit set; From the second data stream The 2nd (i%127)+(i+1)%2th bit in the bit set.

8. The method according to any one of claims 1 to 3, characterized in that, The eight codewords include one codeword from each of the eight second data streams, where m is a positive integer multiple of 8.

9. The method according to claim 8, characterized in that, The 504 bits from four of the eight codewords are mapped using DP-16QAM symbols to obtain 63 DP-16QAM symbols. The 504 bits from the other four codewords are also mapped using DP-16QAM symbols to obtain 63 DP-16QAM symbols. The remaining four bits from the four codewords and the remaining four bits from the other four codewords (a total of eight bits) are mapped using DP-16QAM symbols to obtain one DP-16QAM symbol.

10. The method according to claim 8 or 9, characterized in that, In each of the four codewords out of the eight codewords, the c-th bit and the (c+1)-th bit (a total of eight bits) are mapped by DP-16QAM symbols to obtain one DP-16QAM symbol, where 0 ≤ c ≤ 124 and c is an even number; The 126th bit of each of four of the eight codewords and the 0th bit of each of the other four codewords, a total of eight bits, are mapped by DP-16QAM symbols to obtain one DP-16QAM symbol. In the other four codewords of the eight codewords, the t-th bit and the (t+1)-th bit (a total of eight bits) are mapped by DP-16QAM symbols to obtain one DP-16QAM symbol, where 1 ≤ t ≤ 125, and t is an odd number.

11. The method according to any one of claims 8 to 10, characterized in that, In the m second data streams, two codewords from any two second data streams constitute one bit set. The m / 2 bit sets contain m codewords from the m second data streams. These m / 2 bit sets are mapped using DP-16QAM symbols to obtain M DP-16QAM symbols, where M = 127 × m / 8. The mapping represents the 8 bits of the i-th DP-16QAM symbol among the M DP-16QAM symbols. The following conditions must be met: From the The 2nd (i%127)+i%2th bit in the set of bits; From the The 2nd × (i % 127) + (i + 1) % 2nd bit in the set of bits; From the The 2nd (i%127)+i%2th bit in the set of bits; From the The 2nd × (i % 127) + (i + 1) % 2nd bit in the set of bits; From the The 2nd (i%127)+i%2th bit in the set of bits; From the The 2nd × (i % 127) + (i + 1) % 2nd bit in the set of bits; From the The 2nd (i%127)+i%2th bit in the set of bits; From the The 2nd (i%127)+(i+1)%2th bit in the set of bits.

12. The method according to claim 11, characterized in that, The m second data streams include second data stream 0 to second data stream m-1, and the bit set k in the m / 2 bit set includes two codewords that come from the second data streams respectively. Second data stream 13. The method according to claim 11, characterized in that, The m second data streams include second data stream 0 to second data stream m-1, and the bit set k in the m / 2 bit set includes two codewords that come from the second data streams respectively. Second data stream 14. The method according to any one of claims 1 to 13, characterized in that, The 120 information bits are cyclically shifted before or after the FEC encoding.

15. The method according to any one of claims 1 to 14, characterized in that, Before the FEC encoding, the multiple first data streams undergo convolutional interleaving, and the 120 information bits correspond to 12 RS symbols, which are derived from 12 RS codewords.

16. The method according to any one of claims 1 to 15, characterized in that, m = 8, 16, 32 or 64.

17. A data processing method, characterized in that, include: Receive one dual-polarization hexadecimal quadrature amplitude modulation (DP-16QAM) symbol stream, wherein the one DP-16QAM symbol stream is obtained by DP-16QAM symbol mapping and framing of m second data streams, the 127 DP-16QAM symbols in the DP-16QAM symbol stream are obtained by DP-16QAM symbol mapping of 8 codewords in the m second data streams, the m second data streams are obtained by forward error correction (FEC) encoding of multiple first data streams that have undergone Reed-Solomon RS encoding, m is a positive integer multiple of 4, the codewords after FEC encoding include 127 bits, and the 127 bits of the codeword are obtained by FEC encoding 120 information bits.

18. A data processing apparatus, characterized in that, The data processing device includes a first processing unit and a second processing unit; The first processing unit is configured to: perform forward error correction (FEC) encoding on multiple first data streams that have undergone Reed-Solomon RS encoding to obtain m second data streams, where m is a positive integer multiple of 4, and the codeword after FEC encoding includes 127 bits, wherein the 127 bits of the codeword are obtained by encoding 120 information bits through FEC. The second processing unit is used to: perform dual polarization hexadecimal quadrature amplitude modulation (DP-16QAM) symbol mapping and framing on the m second data streams to obtain one DP-16QAM symbol stream, wherein the 127 DP-16QAM symbols in the DP-16QAM symbol stream are obtained by mapping the 8 codewords in the m second data streams with DP-16QAM symbols.

19. The data processing apparatus according to claim 18, characterized in that, The DP-16QAM symbol stream includes at least one data frame. Each of the at least one data frame contains 128 consecutive DP-16QAM symbols, including one pilot symbol and 127 payload symbols. The 127 payload symbols are obtained by mapping 8 codewords from the m second data streams through DP-16QAM symbols.

20. The data processing apparatus according to claim 19, characterized in that, Each data frame includes 96 pilot symbols and 12,192 payload symbols.

21. The data processing apparatus according to any one of claims 18 to 20, characterized in that, The eight codewords include two codewords from each of the four second data streams.

22. The data processing apparatus according to claim 21, characterized in that, In the four second data streams, two bits from each of the two codewords, totaling eight bits, are mapped using DP-16QAM symbols to obtain one DP-16QAM symbol.

23. The data processing apparatus according to claim 21 or 22, characterized in that, In each of the four second data streams, the z-th bit and the (z+1)-th bit (a total of 8 bits) of the two codewords are mapped by DP-16QAM symbols to obtain one DP-16QAM symbol, where 0 ≤ z ≤ 252, and z is an even number.

24. The data processing apparatus according to any one of claims 21 to 23, characterized in that, In the m second data streams, each second data stream contains two codewords forming a bit set. These m bit sets from the m second data streams are mapped using DP-16QAM symbols to obtain M DP-16QAM symbols, where M = 254 × m / 8. The mapping represents the 8 bits of the i-th DP-16QAM symbol among the M DP-16QAM symbols. The m second data streams include second data stream 0 to second data stream m-1; The following conditions must be met: From the second data stream The 2nd × (i % 127) + i % 2nd bit in the bit set; From the second data stream The 2nd × (i % 127) + (i + 1) % 2nd bit in the bit set; From the second data stream The 2nd × (i % 127) + i % 2nd bit in the bit set; From the second data stream The 2nd × (i % 127) + (i + 1) % 2nd bit in the bit set; From the second data stream The 2nd × (i % 127) + i % 2nd bit in the bit set; From the second data stream The 2nd × (i % 127) + (i + 1) % 2nd bit in the bit set; From the second data stream The 2nd × (i % 127) + i % 2nd bit in the bit set; From the second data stream The 2nd (i%127)+(i+1)%2th bit in the bit set.

25. The data processing apparatus according to any one of claims 18 to 20, characterized in that, The eight codewords include one codeword from each of the eight second data streams, where m is a positive integer multiple of 8.

26. The data processing apparatus according to claim 25, characterized in that, The 504 bits from four of the eight codewords are mapped using DP-16QAM symbols to obtain 63 DP-16QAM symbols. The 504 bits from the other four codewords are also mapped using DP-16QAM symbols to obtain 63 DP-16QAM symbols. The remaining four bits from the four codewords and the remaining four bits from the other four codewords (a total of eight bits) are mapped using DP-16QAM symbols to obtain one DP-16QAM symbol.

27. The data processing apparatus according to claim 25 or 26, characterized in that, In each of the four codewords out of the eight codewords, the c-th bit and the (c+1)-th bit (a total of eight bits) are mapped by DP-16QAM symbols to obtain one DP-16QAM symbol, where 0 ≤ c ≤ 124 and c is an even number; The 126th bit of each of four of the eight codewords and the 0th bit of each of the other four codewords, a total of eight bits, are mapped by DP-16QAM symbols to obtain one DP-16QAM symbol. In the other four codewords of the eight codewords, the t-th bit and the (t+1)-th bit (a total of eight bits) are mapped by DP-16QAM symbols to obtain one DP-16QAM symbol, where 1 ≤ t ≤ 125, and t is an odd number.

28. The data processing apparatus according to any one of claims 25 to 27, characterized in that, In the m second data streams, two codewords from any two second data streams constitute one bit set. The m / 2 bit sets contain m codewords from the m second data streams. These m / 2 bit sets are mapped using DP-16QAM symbols to obtain M DP-16QAM symbols, where M = 127 × m / 8. The mapping represents the 8 bits of the i-th DP-16QAM symbol among the M DP-16QAM symbols. The following conditions must be met: From the The 2nd (i%127)+i%2th bit in the set of bits; From the The 2nd × (i % 127) + (i + 1) % 2nd bit in the set of bits; From the The 2nd (i%127)+i%2th bit in the set of bits; From the The 2nd × (i % 127) + (i + 1) % 2nd bit in the set of bits; From the The 2nd (i%127)+i%2th bit in the set of bits; From the The 2nd × (i % 127) + (i + 1) % 2nd bit in the set of bits; From the The 2nd (i%127)+i%2th bit in the set of bits; From the The 2nd (i%127)+(i+1)%2th bit in the set of bits.

29. The data processing apparatus according to claim 28, characterized in that, The m second data streams include second data stream 0 to second data stream m-1, and the bit set k in the m / 2 bit set includes two codewords that come from the second data streams respectively. Second data stream 30. The data processing apparatus according to claim 28, characterized in that, The m second data streams include second data stream 0 to second data stream m-1, and the bit set k in the m / 2 bit set includes two codewords that come from the second data streams respectively. Second data stream 31. The data processing apparatus according to any one of claims 18 to 30, characterized in that, The 120 information bits are cyclically shifted before or after the FEC encoding.

32. The data processing apparatus according to any one of claims 18 to 31, characterized in that, Before the FEC encoding, the multiple first data streams undergo convolutional interleaving, and the 120 information bits correspond to 12 RS symbols, which are derived from 12 RS codewords.

33. The data processing apparatus according to any one of claims 18 to 32, characterized in that, m = 8, 16, 32 or 64.

34. A data processing apparatus, characterized in that, The data processing device includes a receiving unit; The receiving unit is configured to: receive one dual-polarization hexadecimal quadrature amplitude modulation (DP-16QAM) symbol stream, wherein the one DP-16QAM symbol stream is obtained by mapping and framing m second data streams through DP-16QAM symbols; the 127 DP-16QAM symbols in the DP-16QAM symbol stream are obtained by mapping 8 codewords from the m second data streams through DP-16QAM symbols; the m second data streams are obtained by forward error correction (FEC) encoding of multiple first data streams that have undergone Reed-Solomon RS encoding; m is a positive integer multiple of 4; the codewords encoded by the FEC include 127 bits, and the 127 bits of the codeword are obtained by encoding 120 information bits through the FEC.

35. A chip, characterized in that, The chip is used to perform the method as described in any one of claims 1 to 17.

36. An optical module, characterized in that, The optical module includes a processor and an interface, the interface being used for transmitting and receiving signals, and the processor being used for performing the method as described in any one of claims 1 to 17.

37. A network device, characterized in that, The network device includes a host-side device and an optical module as described in claim 36; the optical module is used to convert electrical signals from the host-side device into optical signals and transmit the optical signals, or the optical module is used to convert received optical signals into electrical signals and transmit the electrical signals to the host-side device.

38. A communication system, characterized in that, It includes a plurality of network devices as described in claim 37, wherein the plurality of network devices are used to send optical signals to each other.

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