Channel quality driven qc-lDPC low complexity quantized matched decoding method and system

Abstract

The application discloses a channel quality driven QC-LDPC low complexity quantization matched decoding method and system, and belongs to the technical field of wireless communication. The method comprises five steps of quantization mode configuration, LLR fixed-point mapping, iteration information buffering, node message updating and hard decision check. Firstly, in the FPGA dynamic quantization configuration module, the target fixed-point quantization format is determined according to the channel quality characteristic quantity of the current decoding frame and the pre-labeled quantization error evaluation result; secondly, the dynamic range determination, scaling, rounding, saturation limiting and signed complement mapping of the log-likelihood ratio soft information output by the demodulation end are completed through the soft information fixed-pointing channel; then, the post-processing soft information, extrinsic information and iteration intermediate information are organized by using the on-chip post-processing information storage unit and the check node information buffering structure; further, the iteration message updating between the check node and the variable node is completed through the node message updating channel; finally, the hard decision sequence is verified according to the QC-LDPC check equation through the hard decision check channel, and the iteration is terminated in advance when all the parity check equations are satisfied. The method can balance the decoding reliability, throughput efficiency and hardware resource overhead under the dynamic channel, and is suitable for the development and implementation of the LDPC decoder for 5G NR.

Description

Technical Field

[0001] This invention belongs to the field of wireless communication technology, and particularly relates to a channel quality-driven QC-LDPC low-complexity quantization matching decoding method and system. Background Technology

[0002] 5G New Radio (5G NR) systems, designed for high-speed, low-latency, and highly reliable wireless transmission scenarios, place high demands on the processing efficiency and engineering complexity of physical layer channel coding and decoding. Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes, as a crucial channel coding scheme used in 5G NR data channels, directly impact the data recovery quality at the receiver due to their decoding performance and implementation efficiency. Therefore, researching QC-LDPC decoding implementation methods suitable for 5G NR receivers is of great significance for improving wireless link reliability and baseband processing real-time performance.

[0003] Existing QC-LDPC decoding methods mainly include the belief propagation algorithm, the sum-product algorithm, the minimum-sum algorithm, and their improved versions. These methods can achieve error correction through iterative message passing between variable nodes and check nodes. Among them, the sum-product algorithm has good decoding performance but high computational complexity; the minimum-sum algorithm reduces implementation complexity by simplifying the node message update process, making it more suitable for hardware platform deployment. In actual hardware implementations, decoders typically need to perform fixed-point quantization on the input soft information and iterative messages to reduce storage and computational resource consumption. However, fixed quantization formats often struggle to adapt to different channel qualities and soft information distributions simultaneously, resulting in a mismatch between decoding performance, resource overhead, and real-time processing capabilities.

[0004] Field-Programmable Gate Arrays (FPGAs) feature parallel processing, pipelined registers, on-chip storage, and reconfigurable logic, making them suitable for implementing computational processes with high repetition and regular data paths in iterative decoding. For QC-LDPC decoding, fixed-point quantization, message buffering, node updates, and decision verification collectively determine the decoder's resource consumption and processing efficiency. By combining channel state changes and fixed-point quantization characteristics to coordinate data representation accuracy and hardware processing overhead during the decoding process, it is possible to improve hardware implementation efficiency while ensuring decoding reliability, thus providing support for the engineering implementation of QC-LDPC decoders in 5G NR receivers. Summary of the Invention

[0005] In view of this, the purpose of this invention is to propose a channel quality-driven QC-LDPC low-complexity quantization matching decoding method and system. This method addresses the technical problems of low resource utilization of fixed-quantization bit-width decoders in dynamic channels, insufficient accuracy of soft information representation under low bit-width conditions, and difficulty in accommodating multiple fixed-point quantization formats in the node update data path. It sets up a fixed-point quantization path, an iterative information buffer structure, a node message update path, and a hard-decision verification path in the FPGA decoder, and organizes the quantization mode configuration, LLR fixed-point mapping, iterative information buffer, node message update, and hard-decision verification into a decoding flow suitable for FPGA implementation.

[0006] To achieve the above objectives, the technical solution adopted by this invention is: a channel quality-driven QC-LDPC low-complexity quantization matching decoding method, comprising the following steps:

[0007] S101: Quantization mode configuration. The channel quality characterization quantity corresponding to the current decoding frame is obtained through the dynamic quantization configuration module, and the target fixed-point quantization format is configured among multiple fixed-point quantization formats in combination with the pre-calibrated quantization error evaluation results. The channel quality characterization quantity includes signal-to-noise ratio, bit error rate estimation result, amplitude distribution of initial log-likelihood ratio soft information, or a combination thereof.

[0008] S102: LLR fixed-point mapping. Through the soft information fixed-point path, according to the target fixed-point quantization format, the log-likelihood ratio soft information output by the demodulation end is subjected to dynamic range determination, scaling, rounding, saturation limiting and signed two's complement mapping to obtain fixed-point soft information consistent with the target fixed-point quantization format;

[0009] S103: Iteration information cache. Through the on-chip iteration information cache structure, the fixed-point soft information is written as the prior soft information of the variable node into the posterior information storage unit, and the posterior information storage unit and the verification node information cache structure are used to organize the posterior soft information of the variable node, the external information of the verification node, and the iteration intermediate information, respectively.

[0010] S104: Node Message Update. Through the node message update path, based on the connection relationship between the check nodes and variable nodes corresponding to the QC-LDPC check matrix, the messages from variable nodes to check nodes and from check nodes to variable nodes are iteratively updated; among them, the check node update process adopts the search for the minimum and second smallest amplitude values ​​and the sign XOR operation, and the variable node update process adopts the accumulation of external information, the removal of the current edge, and the fusion of prior soft information;

[0011] S105: Hard Decision Verification. Through the hard decision verification path, after each iteration, a hard decision sequence is generated based on the posterior soft information of the variable nodes, and verified according to the QC-LDPC parity check equation. If the hard decision sequence satisfies all parity check equations, decoding convergence is determined, and the decoding result is output. If the hard decision sequence does not satisfy all parity check equations and the maximum number of iterations has not been reached, the process returns to step S104 to proceed to the next iteration. If the hard decision sequence does not satisfy all parity check equations and the maximum number of iterations has been reached, the current decoding frame processing ends, the current hard decision sequence is output, and the decoding success flag remains unset.

[0012] This invention also proposes a channel quality-driven QC-LDPC low-complexity quantization matching decoding system. The system is deployed in an FPGA decoder and includes a dynamic quantization configuration module, a soft information fixed-point mapping module, a posteriori information storage module, a node message update module, a hard decision verification module, and a control module. Under the scheduling of the control module, each module sequentially completes input buffering, quantization configuration, fixed-point mapping, iterative message update, hard decision verification, and result output based on the fixed-point mapping path, on-chip storage resources, pipelined node update path, and hard decision verification path in the FPGA.

[0013] The beneficial effects of this invention are as follows: Selecting a fixed-point quantization format based on the channel quality characteristics of the current decoded frame and the pre-calibrated quantization error evaluation results allows for a match between decoding reliability and hardware resources; alternating reading and writing of a posteriori soft information and iterative intermediate information through dual-port memory enables continuous operation of the decoding pipeline; updating the check node through minimum and second-smallest value searches and sign XOR reduces the pressure on hardware resources and timing from complex function operations in the sum-product algorithm; and terminating subsequent iterations when the check equation is satisfied through hard-decision verification reduces invalid iterations after the check is satisfied. Attached Figure Description

[0014] Figure 1 This invention relates to a step diagram of a channel quality-driven QC-LDPC low-complexity quantization matching decoding process.

[0015] Figure 2 This is a diagram showing the relationship between the channel quality characterization parameters and the fixed-point quantization format configuration involved in this invention.

[0016] Figure 3 This is a hardware architecture diagram of the quantization matching decoding involved in the present invention.

[0017] Figure 4 This is a structural diagram of the a posteriori information storage unit involved in the present invention.

[0018] Figure 5 This is a structural diagram of the verification node calculation unit involved in the present invention. Detailed Implementation

[0019] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The following embodiments are used to illustrate the FPGA hardware implementation process of the present invention and are not intended to limit the present invention to a specific device model, interface name, cache depth, quantization threshold or RTL code form.

[0020] This embodiment takes the QC-LDPC decoder of the 5G NR receiver as the object, uses the log-likelihood ratio soft information output by the demodulation end as the decoding input, uses the channel quality characterization of the current decoding frame as the quantization configuration basis, and completes the decoding in the FPGA through the fixed-point path, iterative information buffer, node message update path and hard decision verification path. Figure 1 Used to summarize the overall process of this embodiment; Figures 2 to 5 Used to help explain the quantitative configuration relationship, hardware data path, storage structure, and verification node computing structure.

[0021] like Figure 1 As shown, the decoding process in this embodiment includes S101 to S105, specifically including the following steps:

[0022] S101: Quantization mode configuration. The channel quality characterization quantity corresponding to the current decoding frame is obtained through the dynamic quantization configuration module, and the target fixed-point quantization format is configured among multiple fixed-point quantization formats in combination with the pre-calibrated quantization error evaluation results. The channel quality characterization quantity includes signal-to-noise ratio, bit error rate estimation result, amplitude distribution of initial log-likelihood ratio soft information, or a combination thereof.

[0023] S102: LLR fixed-point mapping. Through the soft information fixed-point path, according to the target fixed-point quantization format, the log-likelihood ratio soft information output by the demodulation end is subjected to dynamic range determination, scaling, rounding, saturation limiting and signed two's complement mapping to obtain fixed-point soft information consistent with the target fixed-point quantization format;

[0024] S103: Iteration information cache. Through the on-chip iteration information cache structure, the fixed-point soft information is written as the prior soft information of the variable node into the posterior information storage unit, and the posterior information storage unit and the verification node information cache structure are used to organize the posterior soft information of the variable node, the external information of the verification node, and the iteration intermediate information, respectively.

[0025] S104: Node Message Update. Through the node message update path, based on the connection relationship between the check nodes and variable nodes corresponding to the QC-LDPC check matrix, the messages from variable nodes to check nodes and from check nodes to variable nodes are iteratively updated; among them, the check node update process adopts the search for the minimum and second smallest amplitude values ​​and the sign XOR operation, and the variable node update process adopts the accumulation of external information, the removal of the current edge, and the fusion of prior soft information;

[0026] S105: Hard Decision Verification. Through the hard decision verification path, after each iteration, a hard decision sequence is generated based on the posterior soft information of the variable nodes, and verified according to the QC-LDPC parity check equation. If the hard decision sequence satisfies all parity check equations, decoding convergence is determined, and the decoding result is output. If the hard decision sequence does not satisfy all parity check equations and the maximum number of iterations has not been reached, the process returns to step S104 to proceed to the next iteration. If the hard decision sequence does not satisfy all parity check equations and the maximum number of iterations has been reached, the current decoding frame processing ends, the current hard decision sequence is output, and the decoding success flag remains unset.

[0027] In step S101, the dynamic quantization configuration module receives the channel quality characterization corresponding to the current decoded frame. The channel quality characterization can be provided by the demodulation unit or an external channel quality estimation module, and may include signal-to-noise ratio, bit error rate estimation results, amplitude distribution of initial LLR soft information, or a combination thereof. The dynamic quantization configuration module matches the aforementioned channel quality characterization with pre-calibrated quantization error evaluation results, and determines the target fixed-point quantization format of the current decoded frame from multiple sets of fixed-point quantization formats.

[0028] In one implementation, such as Figure 2 As shown, the multiple fixed-point quantization formats include , and .in Represents a fixed-point format. This indicates that a signed fixed-point number format is used. Indicates the total bit width. Indicates the decimal places. Figure 2 The inputs and outputs in the code represent the transmission direction of the decoded frame data stream before and after quantization configuration. The input data corresponds to the soft information to be decoded output from the demodulator, and the output data corresponds to the fixed-point soft information after the target fixed-point quantization format configuration is completed. When the channel quality characteristics indicate a high decoding reliability margin, the code is selected... To reduce storage and computation bit width; when the channel quality indicator is at an intermediate level, select To balance decoding reliability and implementation complexity; when channel quality is poor and high precision of soft information representation is required, [the appropriate method] is selected. To reduce the impact of quantization errors on decoding convergence, the dynamic quantization configuration module, during decoder operation, adjusts the quantization configuration according to... Figure 2 The channel quality level and quantization format mapping relationship shown selects the target fixed-point quantization format; when the signal-to-noise ratio and bit error rate estimation results are used in combination, mode determination is performed based on the pre-established mapping relationship.

[0029] The quantization error evaluation results can be pre-calibrated before system deployment. Within the simulation calibration range of 0–5 dB, the signal-to-noise ratio is divided into three statistical intervals: 0–3 dB, 3–4 dB, and 4–5 dB. For each statistical interval, the mean square error of the bit error rate between the floating-point decoding results and the decoding results of different fixed-point quantization formats is calculated according to the following formula:

[0030]

[0031] in, Indicates the candidate fixed-point quantization format index. This represents the total number of candidate fixed-point quantization formats. This indicates the number of signal-to-noise ratio (SNR) statistics points within the current preset SNR range. Indicates the first Candidate fixed-point quantization formats in the first Fixed-point decoding bit error rate at each signal-to-noise ratio statistical point This represents the corresponding floating-point decoding error rate. The above partitioning calibration results are used to establish the mapping relationship between channel quality level and target fixed-point quantization format; high-precision format is preferred for low signal-to-noise ratio ranges, medium-precision format is used for intermediate ranges, and low-bit-width format is used for high signal-to-noise ratio ranges.

[0032] In step S102, the soft information localization module performs localization mapping on the LLR soft information output from the demodulation end according to the target localization quantization format. For a target total bit width of... The signed fixed-point format of an integer can represent the range of:

[0033]

[0034] in, express The representable range of bit signed integers. This represents the total bit width of the target fixed-point quantization format, and has the same meaning as the total bit width parameter in the aforementioned fixed-point format. The soft information fixed-point quantization module processes the input soft information. Perform decimal scaling and rounding to obtain the integer code value before saturation constraint. and to Integer code value obtained by performing saturation limiting They respectively satisfy:

[0035]

[0036] in, This represents the integer code value before saturation after rounding. This represents the integer code value after saturation limiting. Indicates the decimal width of the target fixed-point quantization format; This means restricting the input value to a closed interval. Inside, Indicates will Round to the nearest integer. When there are two equally spaced integers, the rounding is performed in a fixed, preset direction to avoid sign distortion caused by two's complement wrapping.

[0037] When back-mapping integer code values ​​to fixed-point soft information amplitudes, the following conditions must be met:

[0038]

[0039] in, This represents the quantized back-mapping value. The aforementioned fixed-point soft information is used for subsequent variable node initialization and iterative updates.

[0040] In step S103, the iterative information caching module writes the fixed-point soft information as the prior soft information of the variable nodes into the posterior information storage unit, and organizes the posterior soft information of the variable nodes, the external information of the verification nodes, and the iterative intermediate information according to the edge connection relationship corresponding to the QC-LDPC verification matrix. For example... Figure 4 As shown, the posterior information storage unit uses at least two dual-port storage banks for alternating read and write operations. When one storage bank reads the posterior soft information of the variable node from the previous stage, the other storage bank writes the update result of the current stage; when the next frame of data arrives, the read and write roles of the two storage banks are reversed. Figure 4 middle, This indicates the write enable signal. This indicates that the read enable signal is being read. Indicates the input data bus. Indicates the RAM output data bus; and These indicate that write enable and read enable are active, respectively. When 8-bit or 12-bit signed fixed-point data is transmitted through a 16-bit storage interface, high-order bit extension is performed based on the sign bit to maintain the sign and value of the fixed-point data.

[0041] Through the aforementioned alternating read-write structure, the reading of posterior soft information of variable nodes and the writing of update results can be performed in parallel on different storage banks, thereby reducing the need for additional storage depth and supporting continuous operation of the iterative decoding pipeline. The parity node information cache structure is used to cache information outside the parity node and intermediate results of amplitude / symbol, enabling the node message update module to complete message updates edge by edge according to the parity matrix edge connection order.

[0042] In step S104, the node message update module performs a minimum sum decoding update based on the variable node set and check node set defined by the QC-LDPC check matrix. Let the maximum number of iterations be... , No. Round iteration satisfies ; Variable node Send to the verification node The message is Verification node Send to variable node The message is Then, the check node update includes sign term calculation, magnitude term calculation, and message reassembly. Before the first iteration, the initial messages from the variable node to the check node satisfy... .

[0043] The symbolic terms of the verification node to variable node message satisfy:

[0044]

[0045] in, Indicates the verification node Output along the current edge to the variable node The symbolic item, Indicates and verifies the node A set of connected variable nodes. This indicates removing the current variable node from the set. The remaining variable nodes after that. Symbolic function. Defined as: when hour, ;when hour, .

[0046] The magnitude term of the verification node to variable node message satisfies:

[0047]

[0048] in, Indicates the verification node Output along the current edge to the variable node The magnitude term. In the hardware implementation, the magnitude after removing the current edge is determined by searching for the minimum and second minimum values.

[0049] The update message from the verification node to the variable node satisfies:

[0050]

[0051] like Figure 5As shown, the verification node calculation unit adopts a multi-stage pipeline structure. The first stage extracts the amplitude and separates the symbols from the input message; the second stage completes the search for the minimum and second minimum values ​​and the global symbol calculation; the third stage selects the corresponding amplitude based on the current edge position and corrects the symbol item; the fourth stage reassembles the amplitude item and the symbol item and outputs the update message from the verification node to the variable node. Figure 5 The data multiplication in the code represents the recombination of magnitude and sign terms in the output, and is not limited to implementation using ordinary numerical multipliers; this structure conforms to the minimum-sum decoding criterion and can reduce the depth of single-level combinational logic. To avoid conflicts with the decimal width of fixed-point formats... Confusion, Figure 5 The last term index of the parallel input / output branch is uniformly denoted as... ,Right now and ;in This indicates the number of parallel input / output branches in the check node computation unit, and CUU represents the check node update unit.

[0052] The message update from the variable node to the check node satisfies:

[0053]

[0054] in, Represents the variable node A set of connected verification nodes. Represents variable nodes The prior LLR soft information. This formula is used to generate the variable node to the verification node message after removing the current edge out-of-edge information. The summation subscripts in... Represents a set Except for the current verification node Other check node indexes besides.

[0055] The update of the posterior soft information of the variable node satisfies:

[0056]

[0057] in, Indicates the first After round of iterations, the variable nodes The posterior soft information is obtained by fusing the extrinsic information with the prior soft information in the variable node update unit. Before the variable node update result is written back to the storage unit, bit width control, rounding, and saturation processing are performed according to the current target fixed-point quantization format to prevent overflow of the calculation result and ensure data path consistency under different quantization modes.

[0058] In step S105, the hard decision verification module generates a hard decision sequence based on the posterior soft information of the variable nodes. The hard decision generation satisfies:

[0059]

[0060] in, Represents variable nodes The hard decision value, Represents a hard decision function; when The judgment is 0 when it is non-negative. The result is 1 if it is negative.

[0061] The check decision of the hard decision sequence satisfies:

[0062]

[0063] in, This represents the QC-LDPC verification matrix. This represents a hard-decision sequence; the expression is valid in a binary field. The modulo-2 operation holds. If the hard decision sequence satisfies all parity check equations, the current decoding frame is determined to have converged, and the decoding result is output; if the hard decision sequence does not satisfy all parity check equations and the current iteration number is less than the maximum iteration number, the process returns to step S104 to continue updating the node message. Indicates transpose, the right side of the equation This represents a column vector of all zeros with the same dimension as the number of parity check nodes. If the hard decision sequence does not satisfy all parity check equations and the maximum number of iterations has been reached, then the current decoding frame processing ends, the current hard decision sequence is output, and the decoding success flag remains unset.

[0064] like Figure 3 As shown, in one implementation of an FPGA system, the quantization matching decoding hardware architecture includes a soft information input and fixed-point path, a dynamic quantization configuration module, a posterior information storage module, a verification node information cache structure, a node message update module, a hard decision verification module, and a control module. Figure 3 The channel prior information in the code is used to represent the channel quality representation quantity corresponding to the current decoding frame or the quantization configuration basis generated by the channel quality representation quantity. Figure 3 The quantization bit width configuration in the quantization field is used to represent the target fixed-point quantization format configuration; Figure 3The information calculation unit in this embodiment corresponds to the node message update module. The soft information input and fixed-point mapping path receives LLR soft information from the demodulation end and outputs fixed-point soft information in the target fixed-point quantization format; the dynamic quantization configuration module configures the target fixed-point quantization format according to the channel quality characterization; the a posteriori information storage module and the verification node information cache structure provide read / write cache for iterative message updates; the node message update module completes message updates for verification nodes and variable nodes; the hard decision verification module outputs the hard decision sequence and verification status; the control module schedules each module according to the processing order of input cache, quantization configuration, fixed-point mapping, node message iterative update, hard decision verification, and result output. In one implementation, the top-level interface also includes a channel quality mode indicator, a maximum iteration count configuration, decoded output data, and a decoding success flag; when the maximum iteration count is reached and the verification still fails, the decoding success flag remains unset.

[0065] In one implementation, the FPGA hardware platform uses a Xilinx Zynq-7020 series xc7z020clg400 device. The synthesis results show that the decoder resource usage includes 4384 LUTs, 128 LUTRAMs, 6190 FFs, 16 BRAMs, and 43 I / Os. With a maximum of 20 iterations, the decoder takes 13.085 μs for one decoding cycle. The decoding throughput can be expressed as:

[0066]

[0067] in, Indicates the length of the information bits. Indicates the system clock frequency. This represents the number of decoding iterations used in the throughput estimation, taking the maximum number of decoding iterations in the worst case. This indicates the number of clock cycles consumed in each iteration. When the information bit length is 256 and the system clock frequency is 100 MHz, the decoder throughput is 19.56 Mbps; based on the same throughput model, when the information bit length is 4096 and the system clock frequency is 150 MHz, the theoretical throughput estimate can reach 469.47 Mbps.

[0068] Furthermore, a time margin is established under a 100 MHz master clock constraint. The time margin is 2.889 ns. The time margin is 0.145 ns; under a 150 MHz master clock constraint, the establishment time margin is... The hold time is 1.416 ns, with a hold time margin. The value is 0.129 ns, indicating that the decoding system can still meet timing constraints at higher clock frequencies.

[0069] The above embodiments are used to illustrate the technical solutions of the present invention and are not intended to limit the scope of protection of the present invention. Any equivalent substitutions or modifications made based on the technical concept of the present invention regarding channel quality thresholds, quantization bit width combinations, number of memory modules, node processing parallelism, pipeline partitioning, early termination strategies for verification, or FPGA device models should fall within the scope of protection of the present invention.

Claims

1. A channel quality-driven QC-LDPC low-complexity quantization matching decoding method, characterized in that, The method is executed in an FPGA decoder, which includes a dynamic quantization configuration module, a soft information fixed-point path, an on-chip iterative information buffer structure, a node message update path, and a hard decision verification path; the method includes the following steps: S101: Quantization mode configuration. The channel quality characterization quantity corresponding to the current decoding frame is obtained through the dynamic quantization configuration module, and the target fixed-point quantization format is configured among multiple fixed-point quantization formats in combination with the pre-calibrated quantization error evaluation results. The channel quality characterization quantity includes signal-to-noise ratio, bit error rate estimation result, amplitude distribution of initial log-likelihood ratio soft information, or a combination thereof. S102: LLR fixed-point mapping. Through the soft information fixed-point path, according to the target fixed-point quantization format, the log-likelihood ratio soft information output by the demodulation end is subjected to dynamic range determination, scaling, rounding, saturation limiting and signed two's complement mapping to obtain fixed-point soft information consistent with the target fixed-point quantization format; S103: Iteration information cache. Through the on-chip iteration information cache structure, the fixed-point soft information is written as the prior soft information of the variable node into the posterior information storage unit, and the posterior information storage unit and the verification node information cache structure are used to organize the posterior soft information of the variable node, the external information of the verification node, and the iteration intermediate information, respectively. S104: Node Message Update. Through the node message update path, based on the connection relationship between the check nodes and variable nodes corresponding to the QC-LDPC check matrix, the messages from variable nodes to check nodes and from check nodes to variable nodes are iteratively updated; among them, the check node update process adopts the search for the minimum and second smallest amplitude values ​​and the sign XOR operation, and the variable node update process adopts the accumulation of external information, the removal of the current edge, and the fusion of prior soft information; S105: Hard Decision Verification. Through the hard decision verification path, after each iteration, a hard decision sequence is generated based on the posterior soft information of the variable nodes, and verified according to the QC-LDPC parity check equation. If the hard decision sequence satisfies all parity check equations, decoding convergence is determined, and the decoding result is output. If the hard decision sequence does not satisfy all parity check equations and the maximum number of iterations has not been reached, the process returns to step S104 to proceed to the next iteration. If the hard decision sequence does not satisfy all parity check equations and the maximum number of iterations has been reached, the current decoding frame processing ends, the current hard decision sequence is output, and the decoding success flag remains unset.

2. The method according to claim 1, characterized in that, In step S101, the multiple sets of fixed-point quantization formats include , and ,in Represents a fixed-point format. This indicates that a signed fixed-point number format is used. Indicates the total bit width. The decimal width is indicated; the quantization error evaluation results are pre-calibrated as follows: within the simulation calibration range of 0–5 dB, the signal-to-noise ratio is divided into three statistical intervals: 0–3 dB, 3–4 dB, and 4–5 dB; for each statistical interval, the mean square error of the bit error rate between the floating-point decoding result and the decoding results of different fixed-point quantization formats is calculated; let the total number of candidate fixed-point quantization formats be... , No. The mean square error of the bit error rate of the candidate fixed-point quantization formats within the current statistical interval satisfies: in, Indicates the candidate fixed-point quantization format index. This represents the total number of candidate fixed-point quantization formats. This indicates the number of signal-to-noise ratio (SNR) statistics points within the current preset SNR range. Indicates the first Candidate fixed-point quantization formats in the first Fixed-point decoding bit error rate at each signal-to-noise ratio statistical point This represents the corresponding floating-point decoding error rate; it is selected when the channel quality characteristic indicates a high decoding reliability margin. When the channel quality indicator is at an intermediate level, select When the channel quality is poor and the accuracy of soft information representation is required, choose When the signal-to-noise ratio and bit error rate estimation results are used in combination, the dynamic quantization configuration module determines the target fixed-point quantization format based on the pre-established mapping relationship between channel quality level and quantization format.

3. The method according to claim 1, characterized in that, In step S102, the range of signed integer representations of the target fixed-point quantization format satisfies: in, express The representable range of bit signed integers. This represents the total bit width of the target fixed-point quantization format, and has the same meaning as the total bit width parameter in the aforementioned fixed-point format. Input soft information Perform decimal scaling and rounding to obtain the integer code value before saturation constraint. and to Integer code value obtained by performing saturation limiting They respectively satisfy: in, This represents the integer code value before saturation after rounding. This represents the integer code value after saturation limiting. Indicates the decimal width of the target fixed-point quantization format; This means restricting the input value to a closed interval. Inside, Indicates will Round to the nearest integer. When there are two equally spaced integers, the rounding is performed in a fixed, preset direction to avoid sign distortion caused by two's complement wrapping. When back-mapping integer code values ​​to fixed-point soft information amplitudes, the following conditions must be met: in, This represents the quantized back-mapping value, used to characterize the fixed-point soft information entering the subsequent decoding data path.

4. The method according to claim 1, characterized in that, In step S103, the a posteriori information storage unit includes at least two dual-port storage units; while the current storage unit reads the a posteriori soft information of the variable node of the previous stage, the other storage unit writes the update result of the current stage, and the read and write roles are reversed when the next frame of data arrives, thereby supporting the continuous operation of the iterative decoding pipeline.

5. The method according to claim 1, characterized in that, In step S104, let the maximum number of iterations be... , No. Round iteration satisfies ; Variable node Send to the verification node The message is Verification node Send to variable node The message is The check node update includes sign term calculation, magnitude term calculation, and message reassembly; before the first iteration, the initial messages from the variable node to the check node satisfy... . The symbol term satisfies: in, Indicates the verification node Output along the current edge to the variable node The symbolic item, Indicates and verifies the node A set of connected variable nodes, where the product index is... This indicates removing the current variable node from the set. The remaining variable nodes that participate in the calculation of the symbolic term. Symbolic function. Defined as: when hour, ;when hour, . The magnitude term satisfies: in, Indicates the verification node Output along the current edge to the variable node The magnitude term; in the hardware implementation, the magnitude after removing the current edge is determined by searching for the minimum and second minimum values. The update message from the verification node to the variable node satisfies: The update message from the variable node to the check node satisfies: in, Represents the variable node A set of connected verification nodes. Represents variable nodes The prior log-likelihood ratio is soft information; this formula is used to generate variable node to verification node messages after removing current edge out-of-edge information. The summation subscripts in... Represents a set Except for the current verification node Other check node indexes besides. The update of the posterior soft information of the variable node satisfies: in, Indicates the first After round of iterations, the variable nodes The posterior soft information is obtained by the variable node update unit through the fusion of extrinsic information and prior soft information.

6. The method according to claim 5, characterized in that, In step S104, the information calculation unit used for searching the minimum and second smallest amplitude values ​​adopts a pipelined structure of cascading comparison unit and multiplexing unit, which splits the multiple inputs associated with the same verification node into multiple levels of pairwise comparison and selection, so as to reduce the depth of single-level combinational logic and improve timing margin.

7. The method according to claim 5, characterized in that, In step S105, the hard decision generation satisfies: in, Represents variable nodes The hard decision value, Represents a hard decision function; when The judgment is 0 when it is non-negative. The result is 1 if it is negative. The check decision of the hard decision sequence satisfies: in, Represents the QC-LDPC verification matrix. This represents a hard-decision sequence; the expression is valid in a binary field. The modulo-2 operation holds. If the hard decision sequence satisfies all parity check equations, then the current decoding frame is determined to have converged; if the hard decision sequence does not satisfy all parity check equations and the current iteration number is less than the maximum iteration number, then return to step S104 to continue executing the node message update. Indicates transpose, the right side of the equation This represents a column vector of all zeros with the same dimension as the number of parity check nodes. If the hard decision sequence does not satisfy all parity check equations and the maximum number of iterations has been reached, then the current decoding frame processing ends, the current hard decision sequence is output, and the decoding success flag remains unset.

8. A channel quality-driven QC-LDPC low-complexity quantization matching decoding system, characterized in that, It includes a dynamic quantization configuration module, a soft information positioning module, a post-hoc information storage module, a node message update module, a hard decision verification module, and a control module; The dynamic quantization configuration module is used to obtain the channel quality characterization quantity corresponding to the current decoding frame, and configure the target fixed-point quantization format among multiple fixed-point quantization formats in combination with the pre-calibrated quantization error evaluation results. The soft information fixed-point quantization module is used to perform dynamic range determination, scaling, rounding, saturation limiting and signed two's complement mapping on the log likelihood ratio soft information output by the demodulation end according to the target fixed-point quantization format, so as to obtain fixed-point soft information consistent with the target fixed-point quantization format. The posterior information storage module is used to write the fixed-point soft information as the variable node prior soft information into the posterior information storage unit, and organize the variable node posterior soft information, the external information of the verification node and the iteration intermediate information respectively through the posterior information storage unit and the verification node information cache structure. The node message update module is used to iteratively update the messages from variable nodes to check nodes and from check nodes to variable nodes based on the connection relationship between check nodes and variable nodes corresponding to the QC-LDPC check matrix. The hard decision verification module is used to generate a hard decision sequence based on the posterior soft information of the variable nodes after each iteration, and to verify the hard decision sequence according to the QC-LDPC verification equation to determine whether the current decoding frame has converged and output a decoding success flag. When the maximum number of iterations is reached and all parity check equations are still not satisfied, the current decoding frame processing ends, the current hard decision sequence is output, and the decoding success flag is kept in an unset state. The control module is used to schedule the above modules in the processing order of input buffering, quantization configuration, fixed-point mapping, iterative message update, hard decision verification and result output, and output the decoding status.

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