Single-wire asynchronous communication adaptive time slot compensation sampling circuit and sampling method

Abstract

The disclosure provides a single-wire asynchronous communication adaptive time slot compensation sampling circuit and a sampling method, and relates to the field of communication. The sampling circuit comprises a baud rate detection circuit, a truncation and adaptive time slot selection circuit, a baud rate generation circuit, a time slot detection and sampling circuit and a received data detection circuit. The baud rate detection circuit detects baud rate information of a synchronization sequence signal and writes the baud rate information into a baud rate register BRR[N:0]. The truncation and adaptive time slot selection circuit determines an oversampling multiple of a data signal. When BRR[N:4] is not zero, the oversampling multiple is 16 times. When BRR[N:4] is zero, the oversampling multiple is 8 times. The time slot detection and sampling circuit determines a total number of sampling points contained in a baud rate time and a time slot of each sampling point. The received data detection circuit oversamples a bit based on the total number of sampling points contained in the baud rate time and the time slot of each sampling point. The problem that a faster baud rate range data signal sent by a sender cannot be oversampled is solved.

Description

Technical Field

[0001] This disclosure relates to the field of communication technology, specifically to a single-wire asynchronous communication adaptive time slot compensation sampling circuit and sampling method. Background Technology

[0002] In single-wire communication protocols, both communicating parties typically sample the data sent by the other party based on their own clock, which falls under the category of asynchronous communication. Current single-wire asynchronous communication methods, such as but not limited to UART (Universal Asynchronous Receiver / Transmitter, a serial, asynchronous, full-duplex communication protocol), generally determine the transmit / receive rate (the duration of one bit) based on pre-configured registers. After obtaining the transmit / receive rate, the register configuration value is first divided into integer and fractional parts, and then one bit is divided into 16 sampling points. Sampling is performed on sampling points 7, 8, and 9 of the 16 sampling points. In some chained single-wire communication scenarios, the master and slave devices may not be able to agree on the transmit / receive rate in advance. In this scenario, the sender in the master and slave devices usually sends a preamble before formal communication, and the receiver in the master and slave devices calculates the communication rate from the preamble and divides the received data into sampling points based on this communication rate, sampling as close to the middle of one bit as possible.

[0003] In related technologies, communication rate calculation based on Preamble is based on a 16-slot oversampling strategy using fractional frequency division. Based on register configuration and various complex logic calculations, the fractional part is evenly distributed among 16 sampling points within 1 bit. This results in the inability to support oversampling of data signals with faster baud rates sent by the sender, making the baud rate range supported by the sampling circuit relatively narrow. Summary of the Invention

[0004] The main objective of this disclosure is to provide an adaptive time slot compensation sampling circuit and sampling method for single-line asynchronous communication, so as to improve the problem of not being able to support oversampling of data signals with faster baud rate ranges sent by the sender, and to enable the sampling circuit to support a wider baud rate range.

[0005] To achieve the above objectives, the first aspect of this disclosure provides a single-wire asynchronous communication adaptive time slot compensation sampling circuit. This sampling circuit includes: a baud rate detection circuit, a truncation and adaptive time slot selection circuit, a baud rate generation circuit, a time slot detection and sampling circuit, and a received data detection circuit. The baud rate detection circuit is configured to detect the baud rate information of the received synchronization sequence signal and write the detected baud rate information into a baud rate register. The N+1 bits of the baud rate register are sequentially defined as BRR[N:0] (BRR stands for Baud). Rate (or baud rate, which represents the number of signal changes transmitted per second in serial communication); where N is a positive integer greater than 4; the truncation and adaptive time slot selection circuit is configured to: determine the oversampling factor of the data signal corresponding to the synchronization sequence signal based on the value stored in BRR[N:4] of BRR[N:0], and determine the time slot base coefficient and time slot compensation coefficient of the time slot corresponding to each sampling point based on the oversampling factor and the value stored in BRR[N:0]; wherein, when the value stored in BRR[N:4] is not zero, the oversampling factor is 16 times. When the value stored in BRR[N:4] is zero, the oversampling factor is 8 times; the baud rate generation circuit is configured to determine the baud rate time based on the baud rate information; the time slot detection and sampling circuit is configured to determine the total number of sampling points included in the baud rate time and the time slot corresponding to each sampling point based on the oversampling factor, the time slot basic part coefficient and the time slot compensation part coefficient of the time slot corresponding to each sampling point; the received data detection circuit is configured to oversample each bit in the data signal based on the total number of sampling points included in the baud rate time and the time slot corresponding to each sampling point.

[0006] In some embodiments of this disclosure, the time slot basic coefficient and time slot compensation coefficient corresponding to each sampling point are determined based on the oversampling factor and the value stored in BRR[N:0]. This includes: when the oversampling factor is 16 times, determining the time slot basic coefficient corresponding to each sampling point based on the value stored in BRR[N:4] of BRR[N:0]; and determining the sum of the time slot compensation coefficients corresponding to all sampling points in the baud rate time based on the value stored in BRR[3:0] of BRR[N:0].

[0007] In some embodiments of this disclosure, the time slot compensation coefficient corresponding to each sampling point is determined based on the oversampling factor and the value stored in BRR[3:0], including: truncating BRR[3:0] to obtain a first storage segment BRR_QUO[2:0] and a second storage segment BRR_REM[0], wherein the first storage segment BRR_QUO[2:0] is equal to BRR[3:1] in BRR[3:0], and the second storage segment BRR_REM[0] is equal to BRR[0] in BRR[3:0]; defining the time slot corresponding to the first 8 sampling points out of the 16 sampling points arranged in chronological order in the baud rate time as The first half of the baud rate time is defined as the second half of the baud rate time, which is the time slot corresponding to the last 8 sampling points out of the 16 sampling points arranged in chronological order in the baud rate time. Based on the values ​​stored in the first storage segment BRR_QUO[2:0], the first half and the second half of the baud rate time are symmetrically compensated so that the sum of the time slot compensation coefficients of the symmetrical compensation to the first half of the baud rate time is equal to the sum of the time slot compensation coefficients of the symmetrical compensation to the second half of the baud rate time. Based on the values ​​stored in the second storage segment BRR_REM[0], the first half or the second half of the baud rate time is asymmetrically compensated.

[0008] In some embodiments of this disclosure, symmetrical compensation is performed on the first and second halves of the baud rate time based on the values ​​stored in the first storage segment BRR_QUO[2:0]. This includes: compensating the eight time slots of the first half of the baud rate time sequentially from front to back, based on the values ​​stored in the first storage segment BRR_QUO[2:0], using the clock cycle on which the single-wire asynchronous communication adaptive time slot compensation sampling circuit is based; and compensating the eight time slots of the second half of the baud rate time sequentially from front to back, based on the values ​​stored in the first storage segment BRR_QUO[2:0], using the clock cycle on the basis of the clock cycle. The number of clock cycles for symmetrical compensation in each time slot is at most one.

[0009] In some embodiments of this disclosure, asymmetric compensation is performed on the first or second half of the baud rate time based on the values ​​stored in the second storage segment BRR_REM[0]. This includes: compensating one of the time slots in the first half of the baud rate time that has not been symmetrically compensated based on the values ​​stored in the second storage segment BRR_REM[0]; or, compensating one of the time slots in the second half of the baud rate time that has not been symmetrically compensated based on the values ​​stored in the second storage segment BRR_REM[0].

[0010] In some embodiments of this disclosure, determining the time slot basic coefficient and time slot compensation coefficient corresponding to each sampling point based on the oversampling factor and the value stored in BRR[N:0] includes: when the oversampling factor is 8 times, determining the time slot basic coefficient corresponding to each sampling point based on the value stored in BRR[N:3] of BRR[N:0]; and determining the sum of the time slot compensation coefficients corresponding to all sampling points in the baud rate time based on the value stored in BRR[2:0] of BRR[N:0].

[0011] In some embodiments of this disclosure, the time slot compensation coefficient corresponding to each sampling point is determined based on the oversampling factor and the value stored in BRR[2:0]. This includes: truncating BRR[2:0] to obtain a first storage segment BRR_QUO[1:0] and a second storage segment BRR_REM[0], wherein the first storage segment BRR_QUO[1:0] is equal to BRR[2:1] in BRR[2:0], and the second storage segment BRR_REM[0] is equal to BRR[0] in BRR[2:0]; defining the time slot corresponding to the first 4 sampling points out of the 8 sampling points arranged in chronological order in the baud rate time as... The first half of the baud rate time is defined as the second half of the baud rate time, which is the time slot corresponding to the last four of the eight sampling points arranged in chronological order in the baud rate time. Based on the values ​​stored in the first storage segment BRR_QUO[1:0], symmetrical compensation is performed on the first half and the second half of the baud rate time, so that the sum of the time slot compensation coefficients of the symmetrical compensation to the first half of the baud rate time is equal to the sum of the time slot compensation coefficients of the symmetrical compensation to the second half of the baud rate time. Based on the values ​​stored in the second storage segment BRR_REM[0], asymmetrical compensation is performed on the first half or the second half of the baud rate time.

[0012] In some embodiments of this disclosure, symmetrical compensation is performed on the first and second halves of the baud rate time based on the values ​​stored in the first storage segment BRR_QUO[1:0]. This includes: compensating the four time slots of the first half of the baud rate time sequentially from front to back, based on the values ​​stored in the first storage segment BRR_QUO[1:0], using the clock cycle on which the single-wire asynchronous communication adaptive time slot compensation sampling circuit is based; and compensating the four time slots of the second half of the baud rate time sequentially from front to back, based on the values ​​stored in the first storage segment BRR_QUO[1:0], using the clock cycle as the unit; wherein, the number of clock cycles for symmetrical compensation of each time slot is at most 1.

[0013] In some embodiments of this disclosure, asymmetric compensation is performed on the first or second half of the baud rate time based on the values ​​stored in the second storage segment BRR_REM[0]. This includes: compensating one of the time slots in the first half of the baud rate time that has not been symmetrically compensated based on the values ​​stored in the second storage segment BRR_REM[0]; or, compensating one of the time slots in the second half of the baud rate time that has not been symmetrically compensated based on the values ​​stored in the second storage segment BRR_REM[0].

[0014] In some embodiments of this disclosure, the total number of sampling points included in the baud rate time and the time slot corresponding to each sampling point are determined based on the oversampling factor and the time slot base coefficient and time slot compensation coefficient of the time slot corresponding to each sampling point. This includes: using the oversampling factor as the total number of sampling points included in the baud rate time; using the product of the time slot base coefficient of the time slot corresponding to each sampling point and the clock period on which the single-wire asynchronous communication adaptive time slot compensation sampling circuit is based as the time slot base time corresponding to each sampling point; using the product of the time slot compensation coefficient of the time slot corresponding to each sampling point and the clock period as the time slot compensation time corresponding to each sampling point; and using the sum of the time slot base time and time slot compensation time corresponding to each sampling point as the time slot corresponding to each sampling point.

[0015] In some embodiments of this disclosure, detecting the baud rate information of the received synchronization sequence signal includes: detecting the received synchronization sequence signal to obtain the pulse width of a one-bit signal; and determining the baud rate information based on the quotient obtained by dividing the pulse width by the clock period on which the single-line asynchronous communication adaptive time slot compensation sampling circuit is based.

[0016] The second aspect of this disclosure provides a chip that includes any of the single-wire asynchronous communication adaptive time slot compensation sampling circuits provided in the first aspect of this disclosure.

[0017] A third aspect of this disclosure provides an electronic device that includes the chip provided in the second aspect of this disclosure.

[0018] The fourth aspect of this disclosure provides an adaptive time slot compensation sampling method for single-line asynchronous communication. The sampling method includes: detecting the baud rate information of a received synchronization sequence signal and writing the detected baud rate information into a baud rate register; defining the N+1 storage bits of the baud rate register as BRR[N:0]; where N is a positive integer greater than 4; determining the oversampling factor of the data signal corresponding to the synchronization sequence signal based on the value stored in BRR[N:4] of BRR[N:0], and determining the time slot base of the time slot corresponding to each sampling point based on the oversampling factor and the value stored in BRR[N:0]. The oversampling factor is divided into coefficients and time slot compensation coefficients; when the value stored in BRR[N:4] is not zero, the oversampling factor is 16 times; when the value stored in BRR[N:4] is zero, the oversampling factor is 8 times; the baud rate time is determined based on the baud rate information; based on the oversampling factor, and the time slot basic coefficients and time slot compensation coefficients corresponding to each sampling point, the total number of sampling points included in the baud rate time and the time slot corresponding to each sampling point are determined; based on the total number of sampling points included in the baud rate time and the time slot corresponding to each sampling point, each bit in the data signal is oversampled.

[0019] The single-line asynchronous communication adaptive time slot compensation sampling circuit and sampling method provided in this embodiment detect the baud rate information of the received synchronization sequence signal in real time through the baud rate detection circuit. The truncation and adaptive time slot selection circuit determines whether to use an oversampling factor of 16 times or 8 times based on whether the value stored in BRR[N:4] is zero. The time slot detection and sampling circuit determines the total number of sampling points contained in the baud rate time and the time slot corresponding to each sampling point based on the oversampling factor and the time slot basic part coefficient and time slot compensation part coefficient of the time slot corresponding to each sampling point. Then, the received data detection circuit oversamples each bit in the data signal based on the total number of sampling points contained in the baud rate time and the time slot corresponding to each sampling point. Since the synchronization sequence signal reflects the baud rate of its corresponding data signal, a non-zero value in BRR[N:4] indicates a slower baud rate, allowing for a 16x oversampling strategy. Conversely, a zero value in BRR[N:4] indicates a faster baud rate, making the 16x oversampling strategy unsuitable. In this case, an automatic switch to an 8x oversampling strategy is possible, enabling oversampling of data signals with faster baud rates from the transmitter. This addresses the inability to oversample data signals with faster baud rates from the transmitter, resulting in a wider baud rate range supported by the sampling circuit. Furthermore, the oversampling strategy can be determined solely by whether the value in BRR[N:4] is zero, eliminating the need for complex logical calculations and reducing the computational burden when selecting an oversampling strategy. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the specific embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the specific embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 A schematic block diagram of a single-wire asynchronous communication adaptive time slot compensation sampling circuit provided in an embodiment of this disclosure; Figure 2 A waveform diagram of a synchronization sequence signal provided in an embodiment of this disclosure; Figure 3 A flowchart illustrating the process of determining the oversampling factor of a data signal according to an embodiment of this disclosure; Figure 4 A schematic diagram of the time-slot base portion of a 16-time-slot configuration provided in an embodiment of this disclosure; Figure 5A schematic diagram of a compensated 16-timeslot configuration provided in an embodiment of this disclosure; Figure 6 A schematic diagram of the 8-timeslot basic portion provided in an embodiment of this disclosure; Figure 7 A schematic diagram of a compensated 8-timeslot configuration provided in an embodiment of this disclosure; Figure 8 This is a flowchart illustrating a single-line asynchronous communication adaptive time slot compensation sampling method provided in an embodiment of this disclosure.

[0022] It should be noted that the elements in the attached diagram are schematic and not drawn to scale. Detailed Implementation

[0023] To enable those skilled in the art to better understand the present disclosure, the technical solutions of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present disclosure, and not all embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present disclosure.

[0024] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0025] In this disclosure, the terms "upper," "middle," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily used to better describe this disclosure and its embodiments, and are not intended to limit the indicated devices, elements, or components to having a particular orientation, or to be constructed and operated in a particular orientation.

[0026] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0027] It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0028] Example 1 To address the aforementioned issues, this disclosure provides a single-line asynchronous communication adaptive time slot compensation sampling circuit, designed to improve the inability to support oversampling of data signals with faster baud rates transmitted by the sender, thereby enabling the sampling circuit to support a wider range of baud rates. Figure 1 A schematic block diagram of a single-wire asynchronous communication adaptive time slot compensation sampling circuit according to an embodiment of the present disclosure is shown, such as Figure 1 As shown, the sampling circuit includes: a baud rate detection circuit, a truncation and adaptive time slot selection circuit, a baud rate generation circuit, a time slot detection and sampling circuit, and a received data detection circuit.

[0029] Among them, reference Figure 1 , Figure 2 and Figure 3The baud rate detection circuit is configured to detect the baud rate information of the received synchronous signal (SYNC, used to identify the start point and rate of a message) to obtain the baud rate information data of the single-wire communication, and write the detected baud rate information into the baud rate register. The N+1 storage bits of the baud rate register are sequentially defined as BRR[N:0]; where N is a positive integer greater than 4, meaning the total number of storage bits in the baud rate register is N+1 bits, defined as BRR[N:0]. For example, the (i+1)th storage bit of the baud rate register is the baud rate register BRR[i]. When detecting the baud rate information of the received synchronous signal, the clock signal on which the single-wire asynchronous communication adaptive time slot compensation sampling circuit is based can be used for measurement. That is, the communication end where the single-wire asynchronous communication adaptive time slot compensation sampling circuit is located is the receiving end, and the receiving end itself has a clock to provide the clock signal. When the baud rate detection circuit detects the baud rate information of the synchronization sequence signal received by the receiver, a clock is needed to measure the time. At this time, the total duration or pulse width of the synchronization sequence signal is measured in units of the clock cycle of the receiver's own clock signal. During the measurement process, if a duration less than one clock cycle is encountered, decimal processing methods such as, but not limited to, "rounding" or "rounding" can be used to obtain the baud rate information measured in units of the clock cycle of the receiver's own clock signal.

[0030] refer to Figure 1 and Figure 3 The truncation and adaptive time slot selection circuit is configured to determine the oversampling factor of the data signal corresponding to the synchronization sequence signal based on the value stored in BRR[N:4] of BRR[N:0], and can directly read the value stored in BRR[N:4] without calculation. When determining the oversampling factor of the data signal corresponding to the synchronization sequence signal based on the value stored in BRR[N:4] of BRR[N:0], the following processing methods are included: When the value stored in BRR[N:4] is not zero, that is, the value stored in BRR[N:4] is greater than zero, it indicates that the baud rate of the data signal corresponding to the synchronization sequence signal is relatively slow, and a 16x oversampling strategy can be adopted, so the oversampling factor can be 16x; when the value stored in BRR[N:4] is zero, the baud rate of the data signal corresponding to the synchronization sequence signal is relatively fast, and the clock signal of the communication end where the single-wire asynchronous communication adaptive time slot compensation sampling circuit is located is difficult to implement the 16x oversampling strategy. At this time, it can automatically switch to an 8x oversampling strategy to implement the 8x oversampling strategy, setting the oversampling factor to 8x. That is, the truncation and adaptive time slot selection circuit determines whether to use a 16x or 8x oversampling factor based on whether the value stored in BRR[N:4] is zero. Figure 1In this context, RX represents the received signal, which includes the synchronization sequence signal and the data signal.

[0031] refer to Figure 1 The truncation and adaptive time slot selection circuit also determines the basic and compensation coefficients of the time slot corresponding to each sampling point based on the oversampling factor and the value stored in BRR[N:0]. It should be noted that the oversampling strategy with an oversampling factor of 8 or 16 means that one bit of the data signal corresponding to the synchronization sequence signal is divided into 8 or 16 sampling time slots, and each sampling time slot can be used as a sampling point. Whether some or all of the 8 or 16 sampling time slots are subsequently selected as the actual sampling points does not affect the division of the 8 or 16 sampling time slots or sampling points.

[0032] refer to Figure 1 The baud rate generation circuit is configured to determine the baud rate time based on the baud rate information (e.g., ...). Figure 1 In this context, SLOT_INFO represents the baud rate time. This baud rate time can be used as both the transmitting and receiving baud rate time. Based on the aforementioned principle of baud rate information detection, multiplying the baud rate information by the clock period of the clock signal at the communication terminal where the single-wire asynchronous communication adaptive time slot compensation sampling circuit is located yields a baud rate time with a small error, while meeting the allowable error. This baud rate time is approximately equal to the time span of one bit in the data signal.

[0033] refer to Figure 1 The time slot detection and sampling circuit is configured to determine the total number of sampling points included in the baud rate time and the time slot corresponding to each sampling point based on the oversampling factor and the time slot basic part coefficient and time slot compensation part coefficient of the time slot corresponding to each sampling point. That is, the time slot corresponding to each sampling point includes two parts: one part is the time slot basic part determined based on the time slot basic part coefficient, and the other part is the time slot compensation part determined based on the time slot compensation part coefficient. The time slot basic part coefficients of the time slots corresponding to all sampling points included in the baud rate time can be the same, but the time slot compensation part coefficients of the time slots corresponding to different sampling points can be different, so that the time slots corresponding to different sampling points can be the same or different. It should be noted that in the embodiments and figures of this disclosure, "slot" refers to a time slot, where a time slot refers to dividing one bit into 8 or 16 equal parts, each part being called a time slot.

[0034] refer to Figure 1The receiving data detection circuit is configured to oversample each bit of the data signal based on the total number of sampling points contained in the baud rate time and the time slot corresponding to each sampling point. Although the oversampling is based on an oversampling factor of 8 or 16, when determining whether the level signal of each bit is low or high, it can either select only the level signals collected from a portion of the sampling points as a basis to obtain the level signal of each bit through some filtering or calculation method; or it can select the level signals collected from all sampling points as a basis to obtain the level signal of each bit through some filtering or calculation method.

[0035] In the above method, since the synchronization sequence signal reflects the baud rate of its corresponding data signal, when the value stored in BRR[N:4] is not zero, it indicates that the baud rate of the data signal corresponding to the synchronization sequence signal is relatively slow, and a 16x oversampling strategy can be adopted; when the value stored in BRR[N:4] is zero, it indicates that the baud rate of the data signal corresponding to the synchronization sequence signal is relatively fast, and the 16x oversampling strategy cannot be supported. It can automatically switch to an 8x oversampling strategy to execute the 8x oversampling strategy, thereby enabling oversampling of data signals with faster baud rates sent by the transmitter. This improves the problem of not being able to support oversampling of data signals with faster baud rates sent by the transmitter, making the baud rate range supported by the sampling circuit wider. This disclosure, by adopting an adaptive time slot number (oversampling factor) selection method, can expand to a faster baud rate range compared to the traditional 16-time slot sampling method; and it can adaptively adapt the time slot sampling method, compatible with faster baud rates. For example, when the baud rate of the data signal transmitted by the transmitting end is too fast, and the clock signal of this circuit at the receiving end cannot support 16-slot sampling, it can automatically switch to 8-slot sampling. In terms of baud rate compatibility, the frequency range can be doubled compared to ordinary 16-slot sampling. Moreover, the above method only needs to determine the corresponding oversampling strategy based on whether the value stored in BRR[N:4] is zero, without performing various complex logical calculations, thus reducing the computational load when selecting the oversampling strategy.

[0036] The following combination Figures 1 to 8 A detailed description of the adaptive time-slot compensation sampling circuit for single-wire asynchronous communication is provided. It should be understood that... (The rest of the text is missing.) Figures 1 to 8 This description is only intended for the use of a single-wire asynchronous communication adaptive time slot compensation sampling circuit and is not intended to limit the protection scope of the single-wire asynchronous communication adaptive time slot compensation sampling circuit.

[0037] There are various ways to detect the baud rate information of the received synchronization sequence signal, and some methods are described below as examples.

[0038] For example, refer to Figure 2Detecting the baud rate information of the received synchronization sequence signal can include: detecting the received synchronization sequence signal to obtain the pulse width of a one-bit signal; and determining the baud rate information based on the quotient obtained by dividing the pulse width by the clock period on which the single-wire asynchronous communication adaptive time slot compensation sampling circuit is based. This simplifies the complexity of baud rate information by measuring the pulse width of a one-bit signal in units of the clock period of the clock signal on which the single-wire asynchronous communication adaptive time slot compensation sampling circuit is based. The above method does not require configuring the operating baud rate for either the master transmitting end or the slave receiving end; it can automatically detect the transmitted and received baud rate information through the synchronization sequence signal.

[0039] For example, refer to Figure 2 The baud rate detection circuit can detect the synchronization sequence signal sent by the other party to calculate the pulse width length of 8 bits or 4 bits in the synchronization sequence signal, thus obtaining the baud rate information BRR[N:0]. (Reference) Figure 2 In this context, Start stands for Start-bit, which is the start bit added to the 8-bit data; Stop stands for Stop-bit, which is the end bit added to the 8-bit data.

[0040] In some embodiments, baud rate information can be identified based on a synchronization sequence signal (e.g., a synchronization sequence signal is 0x55 (01010101 (alternating 01)) or 0x5, where "0x" is a prefix used to identify that the number is a hexadecimal number) by recognizing the duration of the synchronization sequence signal and the sampled sequence value.

[0041] For example, pulse width detection can be performed on a 10-bit synchronization sequence signal (0101_0101_01) or a 6-bit synchronization sequence signal (0101_01) (where pulse width specifically refers to the period of time during which the pulse reaches its maximum value). By using the pulse width of each bit or the total pulse width, the pulse width of 1 bit of data can be calculated, and the pulse width of 1 bit of data is equivalent to the baud rate information. The bit width of the baud rate register can be determined according to the minimum baud rate information required by the application, such as the baud rate register BRR[N:0], where BRR[N:4] or BRR[N:3] is the basic part coefficient of the time slot (also called the integer part time) for each sampling point, and BRR[3:0] or BRR[2:0] is the time slot compensation part coefficient (also called the extra compensation time, i.e., the fractional part time) for each sampling point.

[0042] refer to Figure 3When determining the oversampling factor of the data signal corresponding to the synchronization sequence signal based on the value stored in BRR[N:4] based on BRR[N:0], the following adaptive time slot allocation strategy can be adopted. When no corresponding integer is found in any time slot of the detected baud rate information, i.e., the value stored in BRR[N:4] is 0, the 16-time slot allocation strategy (oversampling factor of 16) will be abandoned, and the 8-time slot allocation strategy (oversampling factor of 8) will be used. In this case, BRR[N:3] will be considered the integer part, and BRR[2:0] will be considered the compensation part. When the value stored in BRR[N:4] is not 0, the 16-time slot allocation strategy will be used, with BRR[N:4] considered the integer part and BRR[3:0] considered the compensation part.

[0043] For example, determining the basic time slot coefficients and time slot compensation coefficients for each sampling point based on the oversampling factor and the values ​​stored in BRR[N:0] can include: when the oversampling factor is 16, determining the basic time slot coefficients for each sampling point based on the values ​​stored in BRR[N:4] of BRR[N:0]; and determining the sum of the time slot compensation coefficients for all sampling points in the baud rate time based on the values ​​stored in BRR[3:0] of BRR[N:0]. That is, when the oversampling factor is 16, the values ​​stored in BRR[N:4] are used as the basic time slot coefficients for each sampling point. The sum of the time slot compensation coefficients for all sampling points in the baud rate time is determined based on the values ​​stored in BRR[3:0]. Thus, the basic time slot coefficients and the sum of all time slot compensation coefficients can be determined directly by truncation reading.

[0044] After determining the sum of the time slot compensation coefficients corresponding to all sampling points in the baud rate time based on the values ​​stored in BRR[3:0] based on BRR[N:0], the time slot compensation coefficients corresponding to each sampling point can be determined based on the oversampling factor and the values ​​stored in BRR[3:0], which facilitates the subsequent determination of the time slot corresponding to each sampling point.

[0045] When determining the time slot compensation coefficients corresponding to each sampling point based on the oversampling factor and the values ​​stored in BRR[3:0], a variety of methods can be used, some of which are exemplified below.

[0046] For example, refer to Figure 1 , Figure 4 and Figure 5 The time slot compensation coefficients corresponding to each sampling point are determined based on the oversampling factor and the values ​​stored in BRR[3:0]. This can include the following steps: Truncate BRR[3:0] to obtain the first storage segment BRR_QUO[2:0] and the second storage segment BRR_REM[0], where the first storage segment BRR_QUO[2:0] is equal to BRR[3:1] in BRR[3:0], and the second storage segment BRR_REM[0] is equal to BRR[0] in BRR[3:0]. The time slots corresponding to the first 8 sampling points out of the 16 sampling points arranged in chronological order in the baud rate time are defined as the first half of the baud rate time, and the time slots corresponding to the last 8 sampling points out of the 16 sampling points arranged in chronological order in the baud rate time are defined as the second half of the baud rate time. Based on the values ​​stored in the first storage segment BRR_QUO[2:0], symmetrical compensation is performed on the first half and the second half of the baud rate time, so that the sum of the time slot compensation coefficients for the first half of the baud rate time is equal to the sum of the time slot compensation coefficients for the second half of the baud rate time. That is, the values ​​stored in the first storage segment BRR_QUO[2:0] are equal to the sum of the time slot compensation coefficients for the first half of the baud rate time and also equal to the sum of the time slot compensation coefficients for the second half of the baud rate time. It can compensate for both the first half and the second half of the baud rate time, so it is called symmetrical compensation.

[0047] Based on the values ​​stored in the second storage segment BRR_REM[0], asymmetric compensation is performed on either the first or second half of the baud rate time. That is, the values ​​stored in the second storage segment BRR_REM[0] can only compensate for the first half of the baud rate time, or only for the second half of the baud rate time. Since only one part of the first or second half of the baud rate time can be compensated, it is called asymmetric compensation.

[0048] The baud rate generator shown in Related Technology 1 only explains that the fractional frequency division value is distributed from two regions, one starting from the maximum sampling bit and the other from the minimum sampling bit, symmetrically distributed towards the center. However, it does not explain how the distributed sampling points are determined. Related Technology 2 shows a UART sampling pulse generation circuit and method with fractional frequency division function, which only uses a lookup table for fractional frequency division. Although this determines the sampling points for the fractional frequency division value, the introduction of the lookup table circuit also introduces significant overhead. Related Technology 3 shows a UART fractional correction circuit and method that uses shift, inversion, and comparison algorithms to generate the baud rate. Compared to the three related technologies mentioned above, these methods can complete the time slot configuration for each sampling point in the baud rate time without performing various complex logical calculations, thus simplifying the computational load.

[0049] Regarding the method of symmetrical compensation for the first half and the second half of the baud rate time based on the values ​​stored in the first storage segment BRR_QUO[2:0], there are many ways to do so, and some methods are exemplified below.

[0050] For example, refer to Figure 1 , Figure 4 and Figure 5 Based on the values ​​stored in the first storage segment BRR_QUO[2:0], symmetrical compensation is performed on the first and second halves of the baud rate time. This can include: using the clock cycle on which the single-wire asynchronous communication adaptive time slot compensation sampling circuit is based as the unit, compensating the eight time slots of the first half of the baud rate time sequentially from front to back based on the values ​​stored in the first storage segment BRR_QUO[2:0] in clock cycle order; and compensating the eight time slots of the second half of the baud rate time sequentially from front to back based on the values ​​stored in the first storage segment BRR_QUO[2:0] in clock cycle order. The maximum number of clock cycles for symmetrical compensation in each time slot is one. This simplifies the complexity of time slot compensation.

[0051] For example, refer to Figure 1 , Figure 4 and Figure 5 Based on the values ​​stored in the second storage segment BRR_REM[0], asymmetric compensation is performed on the first or second half of the baud rate time. This can include: compensating one of the time slots in the first half of the baud rate time that has not undergone symmetric compensation based on the values ​​stored in the second storage segment BRR_REM[0]; or, compensating one of the time slots in the second half of the baud rate time that has not undergone symmetric compensation based on the values ​​stored in the second storage segment BRR_REM[0]. This ensures that the number of clock cycles for each time slot to be symmetrically and asymmetrically compensated is at most one, minimizing the duration difference between time slots.

[0052] For example, refer to Figure 4 and Figure 5 In the 16-slot adaptive compensation (oversampling factor of 16), BRR[3:0] is truncated to obtain the first storage segment BRR_QUO[2:0] and the second storage segment BRR_REM[0], where BRR_QUO[2:0] = BRR[3:1] and BRR_REM[0] = BRR[0]. The first storage segment BRR_QUO[2:0] is the symmetrical compensation for the first or second half of the 16-slot (time slots corresponding to 16 sampling points). The second storage segment BRR_REM[0] is the asymmetrical compensation part, which can be selected by default to compensate for the first half of the 16-slot (time slots corresponding to 16 sampling points).

[0053] As follows Figure 5 Taking the example shown, BRR[N:0]=0x13 (BRR[N:4]=1, BRR[3:0]=3 (binary value corresponds to 11)). Based on the baud rate information, the integer part of each time slot is 1, and the fractional part is 3. Therefore, only 3 out of 16 time slots can obtain compensation (i.e., only 3 sampling points have a time slot compensation coefficient of 1, and the others are 0). Through the above truncation compensation method, we can obtain BRR_QUO[2:0]=1 for the first storage segment and BRR_REM[0]=1 for the second storage segment. (Reference) Figure 5 The first half of the time slots corresponding to the 16 sampling points is compensated twice (2 clock cycles), for example, in slots 1 and 2. The second half of the time slots corresponding to the 16 sampling points is compensated once (1 clock cycle), that is, in slot 9.

[0054] The low-hardware-overhead time-slot compensation sampling method described above uses only truncation, eliminating the need for additional logic gates during digital chip physical implementation. Through this simple time-slot compensation method, the time-slot compensation coefficient information can be obtained using only truncation, evenly distributing the compensated time slots across both ends of a single bit of data (16 time slots).

[0055] For example, refer to Figure 1 , Figure 3 , Figure 6 and Figure 7 The determination of the basic time slot coefficients and time slot compensation coefficients corresponding to each sampling point based on the oversampling factor and the values ​​stored in BRR[N:0] can include: when the oversampling factor is 8 times, determining the basic time slot coefficients corresponding to each sampling point based on the values ​​stored in BRR[N:3] of BRR[N:0]; and determining the sum of the time slot compensation coefficients corresponding to all sampling points in the baud rate time based on the values ​​stored in BRR[2:0] of BRR[N:0]. That is, when the oversampling factor is 8 times, the values ​​stored in BRR[N:3] are used as the basic time slot coefficients corresponding to each sampling point. The sum of the time slot compensation coefficients corresponding to all sampling points in the baud rate time is determined based on the values ​​stored in BRR[2:0]. Therefore, the basic time slot coefficients and the sum of all time slot compensation coefficients can be determined directly by truncation reading.

[0056] After determining the sum of the time slot compensation coefficients corresponding to all sampling points in the baud rate time based on the values ​​stored in BRR[2:0] based on BRR[N:0], the time slot compensation coefficients corresponding to each sampling point can be determined based on the oversampling factor and the values ​​stored in BRR[2:0], which facilitates the subsequent determination of the time slot corresponding to each sampling point.

[0057] When determining the time slot compensation coefficients corresponding to each sampling point based on the oversampling factor and the values ​​stored in BRR[2:0], a variety of methods can be used, some of which are exemplified below.

[0058] For example, refer to Figure 1 , Figure 3 , Figure 6 and Figure 7 The time slot compensation coefficients corresponding to each sampling point are determined based on the oversampling factor and the values ​​stored in BRR[2:0]. This can include the following steps: Truncate BRR[2:0] to obtain the first storage segment BRR_QUO[1:0] and the second storage segment BRR_REM[0], where the first storage segment BRR_QUO[1:0] is equal to BRR[2:1] in BRR[2:0], and the second storage segment BRR_REM[0] is equal to BRR[0] in BRR[2:0]. The time slots corresponding to the first four sampling points out of the eight sampling points arranged in chronological order in the baud rate time are defined as the first half of the baud rate time, and the time slots corresponding to the last four sampling points out of the eight sampling points arranged in chronological order in the baud rate time are defined as the second half of the baud rate time. Based on the values ​​stored in the first storage segment BRR_QUO[1:0], symmetrical compensation is performed on the first half and the second half of the baud rate time, so that the sum of the time slot compensation coefficients for the first half of the baud rate time is equal to the sum of the time slot compensation coefficients for the second half of the baud rate time. That is, the values ​​stored in the first storage segment BRR_QUO[1:0] are equal to the sum of the time slot compensation coefficients for the first half of the baud rate time and also equal to the sum of the time slot compensation coefficients for the second half of the baud rate time. It can compensate for both the first half and the second half of the baud rate time, so it is called symmetrical compensation.

[0059] Based on the values ​​stored in the second storage segment BRR_REM[0], asymmetric compensation is performed on either the first or second half of the baud rate time. That is, the values ​​stored in the second storage segment BRR_REM[0] can only compensate for the first half of the baud rate time, or only for the second half of the baud rate time. Since only one part of the first or second half of the baud rate time can be compensated, it is called asymmetric compensation.

[0060] Compared to the three related technologies mentioned above, the above method can complete the time slot configuration for each sampling point in the baud rate time without performing various complex logical calculations, thereby simplifying the amount of computation.

[0061] Regarding the method of symmetrical compensation for the first half and the second half of the baud rate time based on the values ​​stored in the first storage segment BRR_QUO[1:0], there are many ways to do so, and some methods are exemplified below.

[0062] For example, refer to Figure 1 , Figure 3 , Figure 6 and Figure 7 Based on the values ​​stored in the first storage segment BRR_QUO[1:0], symmetrical compensation is performed on the first and second halves of the baud rate time. This can include: using the clock cycle on which the single-wire asynchronous communication adaptive time slot compensation sampling circuit is based as the unit, compensating the four time slots of the first half of the baud rate time sequentially from front to back based on the values ​​stored in the first storage segment BRR_QUO[1:0] in clock cycle order; and compensating the four time slots of the second half of the baud rate time sequentially from front to back based on the values ​​stored in the first storage segment BRR_QUO[1:0] in clock cycle order. The maximum number of clock cycles for symmetrical compensation in each time slot is one. This simplifies the complexity of time slot compensation.

[0063] For example, refer to Figure 1 , Figure 3 , Figure 6 and Figure 7 Based on the values ​​stored in the second storage segment BRR_REM[0], asymmetric compensation is performed on the first or second half of the baud rate time. This can include: compensating one of the time slots in the first half of the baud rate time that has not undergone symmetric compensation based on the values ​​stored in the second storage segment BRR_REM[0]; or, compensating one of the time slots in the second half of the baud rate time that has not undergone symmetric compensation based on the values ​​stored in the second storage segment BRR_REM[0]. This ensures that the number of clock cycles for each time slot to be symmetrically and asymmetrically compensated is at most one, minimizing the duration difference between time slots.

[0064] For example, refer to Figure 1 , Figure 6 and Figure 7 In the 8-slot adaptive compensation (oversampling factor of 8), BRR[2:0] is truncated to obtain the first storage segment BRR_QUO[1:0] and the second storage segment BRR_REM[0], where BRR_QUO[1:0] = BRR[2:1] and BRR_REM[0] = BRR[0]. The first storage segment BRR_QUO[1:0] is the symmetrical compensation for the first or second half of the 8-slot (the time slots corresponding to the 8 sampling points). The second storage segment BRR_REM[0] is the asymmetrical compensation part, which can be selected by default to compensate for the first half of the 8-slot (the time slots corresponding to the 8 sampling points).

[0065] As follows Figure 7 Taking BRR[N:0] = 0x0C (BRR[N:3] = 1, BRR[2:0] = 4 (binary value corresponds to 100)), we know from the baud rate information that the integer part of each time slot is 1 and the fractional part is 4. Therefore, only 4 out of 8 time slots can obtain compensation (i.e., only 4 sampling points have a time slot compensation coefficient of 1, the others are 0). Through the above truncation compensation method, we can obtain the first storage segment BRR_QUO[1:0] = 10 and the second storage segment BRR_REM[0] = 0. (Reference) Figure 7 The first half of the time slots corresponding to the 8 sampling points is compensated twice (for 2 clock cycles), for example, in slots 1 and 2. The second half of the time slots corresponding to the 8 sampling points is compensated twice (for 2 clock cycles), for example, in slots 5 and 6.

[0066] The low-hardware-overhead time-slot compensation sampling method described above uses only truncation, eliminating the need for additional logic gates during digital chip physical implementation. Through this simple time-slot compensation method, the time-slot compensation coefficient information can be obtained using only truncation, evenly distributing the compensated time slots across both ends of a single bit of data (8 time slots).

[0067] For example, refer to Figure 1 The truncation and adaptive time slot selection circuit can process the baud rate information and determine whether the detected baud rate meets the 16-time slot sampling method. Specifically, if BRR[N:4] is greater than 0, the SLOT_SEL signal sent to the time slot detection and sampling circuit will output 1, indicating that 16 time slots (oversampling factor of 16) are used for sampling; if BRR[N:4] is equal to 0, the SLOT_SEL signal sent to the time slot detection and sampling circuit will output 0.

[0068] Additionally, refer to Figure 1 The truncation and adaptive time slot selection circuit can also separate the integer and fractional parts of BRR[N:0], and obtain the time slot base coefficients and time slot compensation coefficients by truncation. The time slot compensation coefficients obtained here do not require calculation; they can be directly obtained from the low-order bits of BRR, thus simplifying computational complexity. That is, after decoding the baud rate information data, the truncation and adaptive time slot selection circuit adaptively divides the subsequent 1-bit data signal into 8 or 16 sampling time slots, only shifting the baud rate information data twice to obtain the oversampling factor information and time slot compensation information, and then sampling the 1-bit data signal.

[0069] refer to Figure 1 The time slot detection and sampling circuit adjusts the time slot of each sampling point according to the baud rate time, the basic coefficient of the time slot and the compensation coefficient of the time slot, and adaptively realizes 16-time slot compensated oversampling and 8-time slot compensated oversampling control.

[0070] For example, determining the total number of sampling points in the baud rate time and the time slot corresponding to each sampling point based on the oversampling factor and the time slot base coefficient and time slot compensation coefficient for each sampling point can include: using the oversampling factor as the total number of sampling points in the baud rate time. For example, when the oversampling factor is 8 times, the total number of sampling points in the baud rate time is 8; when the oversampling factor is 16 times, the total number of sampling points in the baud rate time is 16.

[0071] For example, determining the total number of sampling points included in the baud rate time and the time slot corresponding to each sampling point based on the oversampling factor and the time slot basic coefficient and time slot compensation coefficient of the time slot corresponding to each sampling point may further include: multiplying the time slot basic coefficient of the time slot corresponding to each sampling point by the clock period on which the single-wire asynchronous communication adaptive time slot compensation sampling circuit is based, as the time slot basic time corresponding to each sampling point, thereby facilitating the determination of the time slot basic time in the time slot corresponding to each sampling point; multiplying the time slot compensation coefficient of the time slot corresponding to each sampling point by the clock period, as the time slot compensation time corresponding to each sampling point, thereby facilitating the determination of the time slot compensation time in the time slot corresponding to each sampling point; and summing the time slot basic time and time slot compensation time corresponding to each sampling point as the time slot corresponding to each sampling point, thereby obtaining the time slot duration of the time slot corresponding to each sampling point.

[0072] refer to Figure 1 The receiving data detection circuit analyzes and processes the data signal to obtain a 0 / 1 level by using the sampling enable signal (SMP_EN) sent by the previous time slot detection and sampling circuit and the data signal (RX) sent by the peer.

[0073] It should be understood that the single-line asynchronous communication adaptive time slot compensation sampling circuit of this disclosure may include other components in addition to the components shown above, and these components are all within the protection scope of the single-line asynchronous communication adaptive time slot compensation sampling circuit of this disclosure.

[0074] It should be noted that the single-wire asynchronous communication adaptive time slot compensation sampling circuit shown above in this disclosure can be applied to all low-speed single-wire asynchronous communication methods, such as but not limited to UART, LIN (Local Interconnect Network), and ONEWIRE (1-Wire protocol, a single-bus communication protocol that uses a single signal line to achieve bidirectional data transmission).

[0075] Example 2 This disclosure provides a chip, which includes any of the single-wire asynchronous communication adaptive time slot compensation sampling circuits provided in Embodiment 1 of this disclosure.

[0076] Example 3 This disclosure provides an electronic device, which includes the chip provided in Embodiment 2 of this disclosure.

[0077] Example 4 This disclosure provides an adaptive time-slot compensation sampling method for single-line asynchronous communication, referring to... Figure 8 The sampling method mainly includes the following steps: In step S801, the baud rate information of the received synchronization sequence signal is detected and written into the baud rate register; the N+1 storage bits of the baud rate register are defined sequentially as BRR[N:0]; where N is a positive integer greater than 4; In step S802, the oversampling factor of the data signal corresponding to the synchronization sequence signal is determined based on the value stored in BRR[N:4] of BRR[N:0]. The time slot basic coefficient and time slot compensation coefficient of the time slot corresponding to each sampling point are determined based on the oversampling factor and the value stored in BRR[N:0]. Among them, when the value stored in BRR[N:4] is not zero, the oversampling factor is 16 times; when the value stored in BRR[N:4] is zero, the oversampling factor is 8 times. In step S803, the baud rate time is determined based on the baud rate information; In step S804, based on the oversampling factor and the time slot basic coefficient and time slot compensation coefficient of the time slot corresponding to each sampling point, the total number of sampling points included in the baud rate time and the time slot corresponding to each sampling point are determined. In step S805, each bit in the data signal is oversampled based on the total number of sampling points contained in the baud rate time and the time slot corresponding to each sampling point.

[0078] It should be noted that, in addition to the method steps shown above, the single-line asynchronous communication adaptive time slot compensation sampling method provided in this disclosure embodiment may also include the related steps shown in Embodiment 1, all of which are within the protection scope of the single-line asynchronous communication adaptive time slot compensation sampling method provided in this disclosure embodiment.

[0079] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0080] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this disclosure may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0081] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims. Although embodiments of this disclosure have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this disclosure, and all such modifications and variations fall within the scope defined by the appended claims.

Claims

1. A single-wire asynchronous communication adaptive time slot compensation sampling circuit, characterized in that, include: The baud rate detection circuit is configured to detect the baud rate information of the received synchronization sequence signal and write the detected baud rate information into the baud rate register. The N+1 bits of the baud rate register are defined sequentially as BRR[N:0]; where N is a positive integer greater than 4; The truncation and adaptive time slot selection circuit is configured to: determine the oversampling factor of the data signal corresponding to the synchronization sequence signal based on the value stored in BRR[N:4] of BRR[N:0], and determine the time slot basic coefficient and time slot compensation coefficient of the time slot corresponding to each sampling point based on the oversampling factor and the value stored in BRR[N:0]; wherein, when the value stored in BRR[N:4] is not zero, the oversampling factor is 16 times; when the value stored in BRR[N:4] is zero, the oversampling factor is 8 times; A baud rate generation circuit is configured to determine baud rate timing based on the baud rate information; The time slot detection and sampling circuit is configured to: determine the total number of sampling points contained in the baud rate time and the time slot corresponding to each sampling point based on the oversampling factor, the time slot basic part coefficient and the time slot compensation part coefficient of the time slot corresponding to each sampling point; The receiving data detection circuit is configured to oversample each bit in the data signal based on the total number of sampling points contained in the baud rate time and the time slot corresponding to each sampling point.

2. The single-line asynchronous communication adaptive time slot compensation sampling circuit as described in claim 1, characterized in that, Based on the oversampling factor and the value stored in BRR[N:0], the time slot basic coefficient and time slot compensation coefficient corresponding to each sampling point are determined, including: When the oversampling factor is 16 times, the time slot basic part coefficient corresponding to each sampling point is determined based on the value stored in BRR[N:4] of BRR[N:0]. Based on the values ​​stored in BRR[3:0] of BRR[N:0], the sum of the time slot compensation coefficients corresponding to all sampling points in the baud rate time is determined.

3. The single-line asynchronous communication adaptive time slot compensation sampling circuit as described in claim 2, characterized in that, The time slot compensation coefficients corresponding to each sampling point are determined based on the oversampling factor and the values ​​stored in BRR[3:0], including: The BRR[3:0] is truncated to obtain the first storage segment BRR_QUO[2:0] and the second storage segment BRR_REM[0], wherein the first storage segment BRR_QUO[2:0] is equal to BRR[3:1] in the BRR[3:0], and the second storage segment BRR_REM[0] is equal to BRR[0] in the BRR[3:0]. The time slots corresponding to the first 8 sampling points out of the 16 sampling points arranged in chronological order in the baud rate time are defined as the first half of the baud rate time, and the time slots corresponding to the last 8 sampling points out of the 16 sampling points arranged in chronological order in the baud rate time are defined as the second half of the baud rate time. Based on the values ​​stored in the first storage segment BRR_QUO[2:0], symmetric compensation is performed on the first half and the second half of the baud rate time, so that the sum of the time slot compensation coefficients of the first half of the baud rate time is equal to the sum of the time slot compensation coefficients of the second half of the baud rate time. Based on the value stored in the second storage segment BRR_REM[0], asymmetric compensation is performed on the first half or the second half of the baud rate time.

4. The single-wire asynchronous communication adaptive time slot compensation sampling circuit as described in claim 3, characterized in that, Based on the values ​​stored in the first storage segment BRR_QUO[2:0], symmetry compensation is performed on the first half and the second half of the baud rate time, including: Using the clock cycle on which the single-wire asynchronous communication adaptive time slot compensation sampling circuit is based as the unit, and based on the values ​​stored in the first storage segment BRR_QUO[2:0], the eight time slots of the first half of the baud rate time are compensated sequentially from front to back in chronological order; Using the clock cycle as the unit, based on the values ​​stored in the first storage segment BRR_QUO[2:0], the eight time slots of the second half of the baud rate time are compensated sequentially from front to back in chronological order; The maximum number of clock cycles that are symmetrically compensated for in each time slot is one.

5. The single-wire asynchronous communication adaptive time slot compensation sampling circuit as described in claim 4, characterized in that, Based on the value stored in the second storage segment BRR_REM[0], asymmetric compensation is performed on the first half or the second half of the baud rate time, including: Based on the value stored in the second storage segment BRR_REM[0], compensation is performed on one of the time slots in the first half of the baud rate time that has not undergone symmetry compensation; or, Based on the value stored in the second storage segment BRR_REM[0], compensation is performed on one of the time slots in the latter half of the baud rate time that has not been symmetrically compensated.

6. The single-wire asynchronous communication adaptive time slot compensation sampling circuit as described in claim 1, characterized in that, Based on the oversampling factor and the value stored in BRR[N:0], the time slot base coefficient and time slot compensation coefficient corresponding to each sampling point are determined, including: When the oversampling factor is 8 times, the time slot basic part coefficient corresponding to each sampling point is determined based on the value stored in BRR[N:3] of BRR[N:0]. Based on the values ​​stored in BRR[2:0] of BRR[N:0], the sum of the time slot compensation coefficients corresponding to all sampling points in the baud rate time is determined.

7. The single-wire asynchronous communication adaptive time slot compensation sampling circuit as described in claim 6, characterized in that, The time slot compensation coefficients corresponding to each sampling point are determined based on the oversampling factor and the values ​​stored in BRR[2:0], including: The BRR[2:0] is truncated to obtain the first storage segment BRR_QUO[1:0] and the second storage segment BRR_REM[0], wherein the first storage segment BRR_QUO[1:0] is equal to BRR[2:1] in the BRR[2:0], and the second storage segment BRR_REM[0] is equal to BRR[0] in the BRR[2:0]. The time slots corresponding to the first four sampling points out of the eight sampling points arranged in chronological order in the baud rate time are defined as the first half of the baud rate time, and the time slots corresponding to the last four sampling points out of the eight sampling points arranged in chronological order in the baud rate time are defined as the second half of the baud rate time. Based on the values ​​stored in the first storage segment BRR_QUO[1:0], symmetric compensation is performed on the first half and the second half of the baud rate time, so that the sum of the time slot compensation coefficients of the first half of the baud rate time is equal to the sum of the time slot compensation coefficients of the second half of the baud rate time. Based on the value stored in the second storage segment BRR_REM[0], asymmetric compensation is performed on the first half or the second half of the baud rate time.

8. The single-wire asynchronous communication adaptive time slot compensation sampling circuit as described in claim 7, characterized in that, Based on the values ​​stored in the first storage segment BRR_QUO[1:0], symmetry compensation is performed on the first half and the second half of the baud rate time, including: Using the clock cycle on which the single-wire asynchronous communication adaptive time slot compensation sampling circuit is based as the unit, and based on the values ​​stored in the first storage segment BRR_QUO[1:0], the four time slots of the first half of the baud rate time are compensated sequentially from front to back in chronological order; Using the clock cycle as the unit, based on the values ​​stored in the first storage segment BRR_QUO[1:0], the four time slots of the second half of the baud rate time are compensated sequentially from front to back in chronological order; The maximum number of clock cycles that are symmetrically compensated for in each time slot is one.

9. The single-wire asynchronous communication adaptive time slot compensation sampling circuit as described in claim 8, characterized in that, Based on the value stored in the second storage segment BRR_REM[0], asymmetric compensation is performed on the first half or the second half of the baud rate time, including: Based on the value stored in the second storage segment BRR_REM[0], compensation is performed on one of the time slots in the first half of the baud rate time that has not undergone symmetry compensation; or, Based on the value stored in the second storage segment BRR_REM[0], compensation is performed on one of the time slots in the latter half of the baud rate time that has not been symmetrically compensated.

10. The single-wire asynchronous communication adaptive time slot compensation sampling circuit as described in claim 1, characterized in that, Based on the oversampling factor, and the time slot base coefficient and time slot compensation coefficient corresponding to each sampling point, the total number of sampling points included in the baud rate time and the time slot corresponding to each sampling point are determined, including: The oversampling factor is taken as the total number of sampling points included in the baud rate time; The product of the time slot base coefficient corresponding to each sampling point and the clock period on which the single-line asynchronous communication adaptive time slot compensation sampling circuit is based is used as the time slot base time corresponding to each sampling point. The product of the time slot compensation coefficient corresponding to each sampling point and the clock period is used as the time slot compensation time corresponding to each sampling point. The sum of the base time and the compensation time of the time slot corresponding to each sampling point is taken as the time slot corresponding to each sampling point.

11. The single-wire asynchronous communication adaptive time slot compensation sampling circuit as described in claim 1, characterized in that, The baud rate information of the received synchronization sequence signal is detected, including: The received synchronization sequence signal is detected to obtain the pulse width of a one-bit signal; The baud rate information is determined by dividing the pulse width by the clock period on which the single-line asynchronous communication adaptive time slot compensation sampling circuit is based.

12. A chip, characterized in that, The chip includes a single-line asynchronous communication adaptive time slot compensation sampling circuit as described in any one of claims 1 to 11.

13. An electronic device, characterized in that, The electronic device includes the chip as described in claim 12.

14. A single-line asynchronous communication adaptive time slot compensation sampling method, characterized in that, include: The baud rate information of the received synchronization sequence signal is detected, and the detected baud rate information is written into the baud rate register; The N+1 bits of the baud rate register are defined sequentially as BRR[N:0]; where N is a positive integer greater than 4; The oversampling factor of the data signal corresponding to the synchronization sequence signal is determined based on the value stored in BRR[N:4] of BRR[N:0]. The time slot basic coefficient and time slot compensation coefficient of the time slot corresponding to each sampling point are determined based on the oversampling factor and the value stored in BRR[N:0]. Wherein, when the value stored in BRR[N:4] is not zero, the oversampling factor is 16 times; when the value stored in BRR[N:4] is zero, the oversampling factor is 8 times. Determine the baud rate time based on the baud rate information; Based on the oversampling factor, and the time slot basic coefficient and the time slot compensation coefficient corresponding to each sampling point, the total number of sampling points included in the baud rate time and the time slot corresponding to each sampling point are determined. Based on the total number of sampling points contained in the baud rate time and the time slot corresponding to each sampling point, each bit in the data signal is oversampled.

Images