Hierarchical adaptation of nonlinear equalizers with linear and nonlinear parametric components

Abstract

Hierarchical adaptation of nonlinear equalizers with linear and nonlinear parametric components is disclosed. A receiver, equalizer, and associated methods with hierarchical adaptation of linear and nonlinear components of equalization parameters are provided. An illustrative receiver includes an equalizer that provides an equalized signal to one or more symbol decision elements, each employing a plurality of decision thresholds to render a symbol decision, an equalization error calculator that determines an equalization error signal by subtracting a target level corresponding to the symbol decision from the equalized signal, and an adaptation module that adapts at least one of a received signal gain, a filter coefficient of the equalizer, and a sampling clock phase using the equalization error. The illustrative receiver further includes an envelope detector that measures an envelope of the equalized signal, and a controller that determines an equalization parameter adjustment based on the envelope and determines a gain-adjusted target level by applying the equalization parameter adjustment to the target level in proportion to an associated symbol of the target level.

Description

Background Technology

[0001] Digital communication occurs between transmitting and receiving devices via an intermediate communication medium or "channel" (e.g., fiber optic cable or insulated copper wire). Each transmitting device typically transmits symbols at a fixed symbol rate, while each receiving device detects (potentially corrupted) symbol sequences and attempts to reconstruct the transmitted data. A "symbol" is a state or critical condition of the channel that lasts for a fixed period of time, called a "symbol interval." For example, a symbol can be a voltage or current level, an optical power level, a phase value, or a specific frequency or wavelength. The change from one channel state to another is called a symbol transition. Each symbol can represent (i.e., encode) one or more bits of data. Alternatively, data can be represented by symbol transitions or by a sequence of two or more symbols.

[0002] Many digital communication links use only one bit per symbol; a binary "0" is represented by one symbol (e.g., a voltage or current signal within a first range), and a binary "1" is represented by another symbol (e.g., a voltage or current signal within a second range), but higher-order signal constellations are known and frequently used. In 4-level pulse amplitude modulation ("PAM4"), each symbol interval can carry any of four symbols labeled -3, -1, +1, and +3. Two binary bits can thus be represented by each symbol.

[0003] Channel non-ideals produce dispersion, which can cause each symbol to interfere with its neighboring symbols, a result known as inter-symbol interference (ISI). ISI can make it difficult for receiving equipment to determine which symbols were transmitted in each interval, especially when such ISI is combined with added noise.

[0004] To combat noise and ISI, receiving equipment can employ various equalization techniques. Linear equalizers typically require a balance between reducing ISI and avoiding noise amplification. Decision feedback equalizers (DFEs) are generally preferred because they can combat ISI without inherently amplifying noise. As the name suggests, DFEs employ a feedback path to remove the ISI effects originating from pre-determined symbols. Other potentially suitable equalization and demodulation techniques are available in relevant academic literature, including, for example, peak detectors and partial response equalization. Most of these techniques employ some form of channel characteristic or receiver adaptation to enhance performance and suitability for use in challenging conditions. While desirable, the implementation of such characteristics must be within strict complexity constraints (limitations on area and power requirements). Despite the existence of many such implementations, there is still significant room for improvement, especially when dealing with channel nonlinearities, such as those encountered in fiber optic cables. Summary of the Invention

[0005] Accordingly, this paper provides a receiver, equalizer, and associated method for hierarchical adaptation of linear and nonlinear components with equalization parameters. An illustrative receiver includes: an equalizer that provides an equalized signal to one or more symbol decision elements, each employing multiple decision thresholds to represent symbol decisions; an equalization error calculator that determines an equalization error signal by subtracting a target level corresponding to the symbol decision from the equalized signal; and an adaptation module that uses the equalization error to adapt at least one of the following: received signal gain, equalizer filter coefficients, and sampling clock phase. The illustrative receiver further includes: an envelope detector that measures the envelope of the equalized signal; and a controller that determines equalization parameter adjustments based on the envelope and determines a gain-adjusted target level by applying the equalization parameter adjustments in proportion to the associated symbol of the target level.

[0006] An illustrative receiving method includes: (1) providing an equalized signal to one or more symbol decision elements, each symbol decision element employing multiple decision thresholds to represent symbol decisions; (2) determining an equalization error signal by subtracting a target level corresponding to the symbol decision from the equalized signal; (3) using the equalization error to adapt at least one of the following: received signal gain, equalizer filter coefficients, and sampling clock phase; (4) measuring the envelope of the equalized signal; (5) determining an equalization parameter adjustment based on the envelope; and (6) calculating a gain-adjusted target level by applying the equalization parameter adjustment in proportion to the symbol associated with the target level.

[0007] The paper also discloses a semiconductor intellectual property core for generating a receiver circuit system for implementing the above methods. This core can reside on a non-transitory information storage medium, such as a disk drive, a solid-state drive, a non-volatile semiconductor memory device, or even a volatile memory array configured for storing information indefinitely.

[0008] Each of the foregoing embodiments can be implemented individually or in combination, and can be implemented in any suitable combination with any one or more of the following optional features: 1. The target level is determined independently to account for nonlinearity in the equalized signal. 2. The equalization parameter adjustment has an amplitude smaller than the amount corresponding to the least significant bit of each target level as represented in the equalization error calculator. 3. The controller uses a higher bit resolution than the equalization error calculator to represent each target level. 4. The level finder can be configured to determine the median signal level for each symbol. 5. The controller uses the level finder to determine a refined version of the gain-adjusted target level. 6. The level finder further operates as an envelope detector. 7. The equalizer is a decision feedback equalizer, comprising: a pre-compensation unit that uses one or more symbol decision elements to generate provisional symbol decisions, each symbol decision element using a comparator configured to compare the equalized signal with a plurality of decision thresholds that take into account the channel response to a set of speculative symbols, including speculative current symbols and speculative prior symbols, which are different for different decision elements; a register configured to track the prior symbol decisions of the decision feedback equalizer; and a multiplexer configured to supply current symbol decisions selected from provisional symbol decisions to the register based on prior symbol decisions. 8. The target levels used by the equalization error calculator include independent target levels for each combination of current symbol decisions and prior symbol decisions. 9. After determining a refined version, the controller determines adjustments to the refined version of the target levels to anchor these target levels to the gain-adjusted target levels. Attached Figure Description

[0009] Figure 1 It is a planar view of a patterned wafer containing integrated circuit devices.

[0010] Figure 2 This is a block diagram illustrating an application-specific integrated circuit (ASIC).

[0011] Figure 3A This is a perspective view illustrating a fiber optic cable connector.

[0012] Figure 3B An illustrative fiber optic cable is shown.

[0013] Figure 3C This is a block diagram illustrating fiber optic cables.

[0014] Figure 4A An illustrative implementation of the decision feedback equalizer (DFE) is shown.

[0015] Figure 4BAn illustrative DFE employing a single-tap pre-compensation unit is shown.

[0016] Figure 4C An illustrative DFE with fully unrolled pre-compensation elements is shown.

[0017] Figure 4D An illustrative parallelization of DFE is shown.

[0018] Figure 5 An illustrative eye diagram is shown.

[0019] Figure 6 An illustrative bathtub curve is shown.

[0020] Figure 7 This is a flowchart illustrating the adaptive equilibrium method. Detailed Implementation

[0021] Although specific details of embodiments are provided in the accompanying drawings and the following description, they do not limit this disclosure. Rather, these details provide a basis for those skilled in the art to identify alternative forms, equivalents, and modifications that are included within the scope of the appended claims.

[0022] Figure 1 A plan view of a semiconductor wafer 100 is shown, patterned to form an array of integrated circuits 102. This array can be diced into IC chips and packaged as modular components for assembly into electronic devices. The IC chips can be individually packaged or combined into multi-chip modules using an interposer and / or a packaging substrate. In either case, ball grid arrays or lead frames are used to provide external contacts for (typically via a printed circuit board) electrical connection to other circuit components. Each IC chip can implement digital logic, analog functions, and / or mixed-signal circuit systems.

[0023] Wafer patterning is performed by a semiconductor fabrication plant (“fab”) using a series of cleaning, alignment, deposition, patterning, etching, implantation, and related processes. The “recipe” (a sequence of patterning and process steps) used determines the functionality of the resulting integrated circuit. The recipe is specified for the fab’s customers or for electronic device designers working for companies that own the fab. Designers facilitate the design process by relying on modular placement design cells to realize the desired components of the integrated circuit, arranging and connecting these modular placement design cells as needed to achieve multiple functions of the desired device. These modular cells can be predefined cells from existing libraries or from suppliers that specialize in designing the desired type of components. Each modular cell has a defined interface and behavior that has been verified by its creator. While each modular cell may require significant time and investment to create, the availability of modular cells for reuse and further development greatly reduces product cycle time and enables better products. Predefined cells can be organized hierarchically, where a given cell is incorporated into one or more lower-level cells, and further incorporated into higher-level cells. Predefined modular units are also known as cells, blocks, cores, and macros. These terms have different meanings and variations ("IP core", "soft macro"), but are often used interchangeably.

[0024] Modular cells can be expressed in different ways, such as as Hardware Description Language (HDL) files or as fully routed designs that can be directly printed to create a range of manufacturing process masks. Fully routed design files are typically process-specific, meaning additional design work is often required to migrate the modular cells to different processes or manufacturers. Modular cells in HDL form require subsequent synthesis, placement, and routing steps to realize, but they are process-independent, meaning different manufacturers can apply their preferred automated synthesis, placement, and routing processes to realize the cells using a wide range of manufacturing processes. Due to their higher-level representation, HDL cells are more accommodating to the use of modified and variable design parameters, while fully routed cells offer better predictability in terms of area requirements, reliability, and performance.

[0025] While there are no fixed rules, digital module designs are more typically specified in HDL form, while analog and mixed-signal units are more often specified in lower-level physical descriptions. In either case, such semiconductor IP cores can be maintained in a design database residing on a non-transitory information storage medium, such as a hard disk, flash drive, or any known cloud-based abstraction of non-volatile information storage. Once the device has been fully designed, commercially available software can convert the semiconductor IP cores and other integrated circuit components into semiconductor mask patterns, which are also stored on a non-transitory information storage medium. These patterns can then be transferred to various process units on appropriate assembly lines in integrated circuit manufacturing plants used to form and package IC chips.

[0026] Figure 2 An illustrative high-speed serializer / deserializer (“SerDes”) retimer chip 210 is shown, which serves as an example herein of an integrated circuit device that can be manufactured in the manner described. Chip 210 includes: a SerDes module 211 with contacts for receiving and transmitting high-speed serial bit streams across four channels in one direction; an additional SerDes module 212 with contacts for receiving and transmitting high-speed serial bit streams across four channels in another direction; and core logic 213 for implementing a channel communication protocol while buffering the bit streams between the two directions. Although four channels are shown here, the actual number can be larger or smaller as needed.

[0027] It also includes various support modules and contacts 214, 215, such as power regulation and distribution, clock generation, digital input / output lines for control, and a JTAG module for built-in self-test. Chip designers can design devices by placing predefined modular units for serializers, deserializers, power supplies, clock generators, I / O cells, and JTAG; and route the interconnections between modular units with a little supporting logic.

[0028] The receiver or "deserializer" implements the receiving function of chip 210, implementing any suitable equalization technique, such as peak detection, linear equalization, partial response equalization, and decision feedback equalization (DFE). In many cases, DFE is preferred and will be used here to provide context for explaining the operation of the hierarchical adaptation process disclosed herein. However, the reader will recognize the applicability of this process to other equalizers, or more generally, to other receivers of wired or wireless digital signals.

[0029] The packaged chip 210 can be integrated, for example, into a network port of an electronic system, into an optical module, or into a cable connector (such as...). Figure 3A The cable connector shown is included. Connector frame 302 houses printed circuit board (PCB) assembly 304, which is configured with edge connector contacts 306 that mate with contacts in a receptacle of a host device's network interface port to transmit and receive electrical signals. PCB assembly 304 includes one or more packaged integrated circuit (IC) chips or discrete electrical components mounted on contact pads on the PCB. For example, PCB assembly 304 may include a retimer chip 210 to equalize received signals, recover data, and retransmit recovered data, optionally providing error correction, signal format conversion, and channel deskew.

[0030] PCB assembly 304 includes an optical coupling module 310 that couples an integrated photodetector and photoemitter to one or more optical paths. When mated with the optical coupling module 310, a ferrule 312 aligns one or more optical fibers of the fiber optic cable 314 with one or more optical paths. The optical coupling module 310 can typically use lenses and prisms to define the optical path of the optical signal between the coupled optical fiber and the photodetector and photoemitter, although other optical elements (e.g., mirrors, gratings) will also be suitable. The fiber optic cable connector may further include a cover and a finger grip 316 to protect other components from damage during normal use.

[0031] Figure 3B A perspective view of an illustrative cable 314 is shown, which may include... Figure 3A The cable includes end connectors. Such cables can be used to provide high-bandwidth communication links between devices in routed networks such as those used for data centers, server farms, and interconnect switching. The routed network may be, for example, part of the Internet, a wide area network (WAN), or a local area network (LAN), or may include, for example, the Internet, a WAN, or a LAN. The linked devices may be computers, switches, routers, etc. The cable includes a first connector 300 and a second connector 301 connected via optical fiber in cable 314. Each connector 300, 301 includes a retimer chip 210 (also referred to as a data recovery and remodulation (“DRR”) device) that performs clocking and data recovery of incoming data streams, which are then remodulated and retransmitted as outgoing data streams. Each DRR device processes the data stream traveling in each direction, optionally converting between non-return-to-zero (“NRZ”) and level 4 pulse amplitude modulation (“PAM4”) or between other different signaling formats, including electrical-to-optical and optical-to-electrical.

[0032] Figure 3C yes Figure 3B The diagram illustrates the functional block diagram of the cable. Connector 300 includes an edge connector terminal 306 adapted to mate with a standards-compliant Ethernet port in a first host device to receive electrical signals carrying outgoing data streams from the host device and to provide electrical signals carrying incoming data streams to the host device. Similarly, connector 301 includes an edge connector contact 306 adapted to an Ethernet port in a second host device. Connector 300 includes a first DRR device 210 for performing recovery and remodulation of the data streams entering and leaving the cable at connector 300, and connector 301 includes a second DRR device 210 for performing recovery and remodulation of the data streams entering and leaving the cable at connector 301.

[0033] DRR device 210 may be an integrated circuit mounted on a printed circuit board and connected to edge connector contacts via circuit board traces. The printed circuit board in each connector may further support optical transceivers 324, 325, which convert data streams between electrical and optical signal formats for transmission via optical fiber 326 in cable 314. In at least some of the contemplated embodiments, the printed circuit board also each supports a microcontroller unit (MCU) 328. Each DRR device 210 is coupled to a corresponding MCU device 328, which configures the operation of the DRR device via a two-wire bus. Upon power-up, the MCU device 328 loads equalization parameters from flash memory 329 into the configuration register 336 of the DRR device. A host device can access the MCU device 328 via a second two-wire bus, which operates according to the I2C bus protocol and / or the faster MDIO protocol. Using this access to the MCU device 328, the host device can adjust the cable's operating parameters and monitor the cable's performance.

[0034] Each DRR device 210 includes a transmitter and receiver set 330 for communicating with a host device and a transmitter and receiver set 332 for transmitting and receiving via a communication channel along the length of the cable. The illustrated cable supports N bidirectional communication channels, each transmitting via optical fiber using wavelength multiplexing. The DRR device optionally includes a memory 334 for providing a first-in-first-out (FIFO) buffer between the transmitter and receiver sets 330, 332. An embedded controller 338 coordinates the operation of the transmitters and receivers by, for example, setting initial equalization parameters and ensuring that a training phase is completed across all channels and links before enabling the transmitters and receivers to enter the data transmission phase. The embedded controller 338 uses a set of registers 336 to receive command and parameter values ​​and provide responses that potentially include status information and performance data.

[0035] The receiver employs a suitable equalization technique, such as, for example, decision feedback equalization (DFE). Figure 4A An illustrative implementation of a DFE configured for PAM4 is shown. A continuous-time linear equalizer (“CTLE”) filter 402 provides analog filtering to band-limit the signal spectrum while boosting the high-frequency components of the received signal RX_IN. An analog-to-digital converter (“ADC”) 404 digitizes the filtered signal, and a digital feedforward equalizer (“FFE”) filter 406 (also known as a “front-end” filter) minimizes leading-edge ISI while optionally reducing the length of the channel impulse response. A summer 408 subtracts the feedback signal provided by the feedback filter 410 from the output of the FFE filter 406 to minimize the effect of trailing-edge ISI in the equalized signal. A decision element 412 (sometimes called a “limiter”) operates on the equalized signal to determine which symbol it represents in each symbol interval. The resulting symbol decision stream is represented as A. k , where k is the time index.

[0036] In the illustrated example, assuming the symbol is PAM4 (-3, -1, +1, +3), the comparators employed by decision element 412 use limiter thresholds of -2, 0, and +2, respectively. (For generality, the units used to express the symbol and thresholds are omitted, but for illustrative purposes, they can be assumed to be volts.) The comparator outputs can collectively serve as a thermometer-encoded digital representation of the output symbol decision, or a digitizer can optionally be used to convert the comparator outputs into a binary representation, for example, 00 for -3, 01 for -1, 10 for +1, and 11 for +3. Alternatively, Gray encoding can be used.

[0037] DFE utilizes decision-making with storage of recently output symbols (A) k-1 A k-2 A k-N Where N is the filter coefficient F i A feedback filter 410 generates a feedback signal from a series of delay elements D (e.g., latches, flip-flops, or shift registers). A set of multipliers determines the product of each symbol with its corresponding filter coefficient, and an array of summing elements combines these products to obtain the feedback signal.

[0038] The illustrative DFE implementation further includes an equalization error calculator 414, in this case a subtraction element that subtracts the output symbol decision A from the equalized signal. kThe equalization error can be employed by the adaptation unit 416 and the clock recovery module 418. The adaptation unit 416 can adjust the coefficients of the FFE filter 406 and the feedback filter 410. In addition to adjusting the FFE filter coefficients, or as an alternative, the adaptation unit 416 can adjust the gain control amplifier operating on the received signal. The adaptation unit 416 can employ any suitable adaptation technique, such as those found in the published literature, designed to minimize the desired amplitude of the equalization error signal. The clock recovery module can also employ the equalization error alone, or a combination of the equalization error with symbol decisions, the equalized signal, or the received signal, to generate a sampling clock for the ADC 404. Various suitable clock recovery techniques are disclosed in the published literature.

[0039] Figure 4A The illustrative implementation further includes a multi-mode level lookup unit 420, which includes a dual-level lookup unit 421 having an input multiplexer 422 and an output demultiplexer 424. A mode selection signal MODE causes the input multiplexer 422 to select one of the following: the unequalized signal at the input of the FFE filter 406, the equalized signal at the input of the decision element 412, and the equalization error signal calculated by the summer 418. The MODE signal also causes the demultiplexer 424 to direct the detected signal level to one of the following: a signal range output, an eye opening / target level output, and an error level output.

[0040] The dual-level lookup unit 421 is described in detail in commonly owned U.S. Patent 11,018,656, issued May 25, 2021, entitled "A Multi-Function Signal Measurement Circuit for ADC-based SerDes," which is incorporated herein by reference in its entirety. Operating parameters of the level lookup unit include step size, symbol pattern (to indicate desired eye and / or potentially interfering symbols), and initial accumulator settings, which can be set independently for each in the dual-level lookup unit. When the stream of output symbol decisions matches a given pattern of the level lookup unit, the level lookup unit updates its accumulator using the provided up and down step sizes. A feedback path is used to drive the accumulator content to a level determined by the ratio of the up and down step sizes, such that the content represents a level to which the input signal has a given probability of exceeding that level. Therefore, as an example, the dual-level lookup unit 421 can determine the upper and lower levels of an unequalized signal range, at which the probability of the level being exceeded is, for example, 2. -10 and 1-2 -10(Approximately 0.001 and 0.999, respectively). The signal envelope can be derived from the unequalized signal range, for example, by taking the maximum value of the down-level amplitude and the up-level amplitude.

[0041] Looking ahead for now, Figure 5 An illustrative eye diagram of the PAM4 signal at the input of decision element 412 is shown. This diagram represents the superposition of all possible signal combinations (with added noise and inter-symbol interference) that may occur during the transition from the previous sampling interval to the current sampling interval. The eye diagram reveals three eyes: the first eye E near the -2 limiter threshold. -2 The larger eye is the second eye E0 near the +0 limiter threshold, and the third eye E2 near the +2 limiter threshold. Larger eyes provide greater separation between the typical signal level and the limiter threshold, thus enabling the system to better tolerate noise and thereby providing a reduced error rate.

[0042] Each eye has an upper eyelid and a lower eyelid. For example, the upper eyelid of eye E2 is formed by an equalized signal representing +3 in the current symbol interval, and the lower eyelid is formed by an equalized signal representing +1 in the current interval. Figure 6 This is an illustrative "bathtub" diagram, which shows the cumulative distribution function ("CDF") 602 of the upper eyelid, representing the probability that a +3 equalized signal has a value below a given amplitude. Figure 6 An approximate probability distribution function (PDF) 603 corresponding to the derivative of CDF 602 is also shown (not on scale).

[0043] For the lower eyelid, Figure 6 The diagram illustrates CDF 604 and approximate PDF 605, where CDF 604 represents the probability that an equalized signal representing +1 has a value higher than a given amplitude, and approximate PDF 605 corresponds to the amplitude of the derivative of CDF 604. PDF 605 has a peak value that is approximately normally distributed, while PDF 603 has a skewed peak value that can be attributed to the nonlinearity of the optical channel. Level finder 421 may accordingly determine that, for a given signal probability, the upper eyelid of eye E2 appears at point 606 (shown at an amplitude of approximately 2.19) and the lower eyelid appears at point 608 (shown at approximately 1.59). To minimize the symbol or bit error rate, the limiter threshold should be located in the middle between the two eyelids, i.e., 1.89 in this example, rather than... Figure 4A The +2 shown. In this way, the limiter threshold for each eye can be set or adapted to minimize the error rate.

[0044] In a similar manner, the level lookup unit 421 can determine the median of each PDF 603, 605 using equal up / down steps, which can be used as the "target level" for calculating the equalization error. Such medians can be determined individually for each symbol pattern of interest, allowing channel nonlinearity to be removed from the equalization error calculation. When the equalization error is linearized in this way, the performance of the adaptation unit and timing recovery module is improved.

[0045] Return to Figure 4A The dual-level lookup unit 420 accepts programmable symbol pattern selection, enabling the receiver's controller to iterate the level lookup unit in several options to measure the size of each eye and the target level for each symbol pattern. The mode selection signal causes the input multiplexer 422 to forward the limiter input signal to the dual-level lookup unit (and causes the demultiplexer 424 to forward the adaptively determined level of the lookup unit to a register for storing eye opening and target level information). For the selected symbol pattern, the level lookup unit operates to find the lower edge (where the limiter input has only a given probability of falling below the edge), the upper edge (where the limiter input has only a given probability of rising above the edge), or the median. The controller can then set a decision threshold in the middle between these edges to minimize the error probability and can use these target levels to linearize the equalization error calculation.

[0046] exist Figure 4A In this embodiment, the feedback filter 410 must complete its operation within less than one symbol interval because its output depends in part on the immediately preceding decision. At very high data rates, one symbol interval does not provide sufficient time to complete filter multiplication and feedback subtraction. Accordingly, one solution already proposed in the literature is to "unroll" the feedback filter.

[0047] Figure 4B It shows Figure 4A An illustrative variant of this, which expands the feedback filter using a single tap. Figure 4B The embodiment employs the same front-end filter 406, but the summer 408 subtracts the feedback signal to remove trailing edge ISI caused by all symbols except the immediately preceding symbol. For each possible value of the immediately preceding symbol, the pre-compensation unit 432 provides decision elements 434A-434D. Decision element 434A speculatively assumes the preceding symbol is -3, and does not subtract the ISI (-3) caused by that symbol. F1, where F1 is the coefficient of the first tap in the original feedback filter 410, is the limiter threshold of comparators 436A-436C, which has been adjusted relative to the comparator threshold of decision element 412 by adding -3. F1 is adjusted so that decision element 434A can form a provisional symbol decision based on this speculative assumption.

[0048] Similarly, decision elements 434B, 434C, and 434D employ comparators with appropriately adjusted thresholds to present provisional decisions under speculative assumptions that the prior symbols are -1, +1, and +3, respectively. Pre-compensation unit 432 supplies these provisional decisions to multiplexer 440, which, based on the immediately preceding symbol decision A stored by delay element 442,... k-1 To select an appropriate provisional decision. The feedback filter 444 has a reduced number of taps (filter coefficients), but otherwise operates similarly to the feedback filter 410.

[0049] Although this expansion step increases the number of elements in the DFE loop (i.e., the loop including summer 408, pre-compensation unit 432, multiplexer 230, delay element 442, and feedback filter 444), only the elements in the inner loop (i.e., the loop including multiplexer 440 and delay element 442) need to perform their operations in less than one symbol interval. The remaining DFE loop elements can spend up to two symbol intervals to complete their pipelined operations. If completing the feedback filter operation in time remains a challenge, further expansion can be performed.

[0050] The disclosed principles can be as follows Figure 4C The image is expanded. Figure 4C An illustrative variant is shown in which the N-tap feedback filter has been fully expanded. This embodiment still uses the front-end filter 406, but the summer 408 is eliminated because the feedback filter has been fully expanded. The function of the summer 408 has been completely replaced by a pre-compensation unit 452, which provides a separate decision element for each combination of the N prior symbols. Digitizers 438A-438M supply provisional decisions to a large multiplexer 440, which selects a provisional decision from the set based on the N prior symbol decisions stored in a shift register, thereby producing a sequence of symbol decisions Ak.

[0051] With the cardinality of the symbol set being P and the number of feedback filter coefficients being N, the number of decision elements in the pre-compensation unit 452 is M = P. N Therefore, for a PAM4 system with a 3-tap feedback filter (i.e., P=4), the number of decision elements will be 4. 3 =64. Since each decision element uses P-1 comparators, the pre-compensation unit uses L=(P-1)P. NThere are 192 comparators, or 192 comparators for a 3-tap PAM4 DFE example. Therefore, with each increase in trailing edge ISI length and symbol set cardinality, the size of the pre-compensation unit grows exponentially, and the size of the multiplexer 440 also grows exponentially. However, the elimination of feedback loops eliminates the associated time constraints, and the front-end filter can be designed to limit the trailing edge ISI to a manageable size. Furthermore, the various limiter thresholds Si can be independently customized for their associated symbol modes, allowing any channel nonlinearity to be accounted for. To linearize the equalization error calculation as previously discussed, the target level module 454 determines the target level associated with each symbol mode, enabling the subtraction element 414 to remove channel nonlinearity. When calculating the equalization error, the subtraction element 414 may need to account for the timing delay between the unequalized signal and the corresponding target level signal.

[0052] exist Figure 4C In a DFE, only one symbol decision is output per clock cycle. At particularly high data rates, it may be necessary or desirable to apply parallelization techniques to output multiple symbol decisions per clock cycle, as done in, for example, U.S. Patent 9,071,479 (“High-speed parallel decision feedback equalizer”) and U.S. Patent 9,935,800 (“Reduced complexity precompensation for decisionfeedback equalizer”), each of which is hereby incorporated herein by reference in its entirety. Figure 4DAn illustrative parallel DFE embodiment with a parallelism of Q is shown. A set of sample-and-hold units 401-1 to 401-Q sequentially and cyclically capture samples of a buffered analog signal, each sample-and-hold unit (in a time-interleaved manner) providing a stable output for up to Q clock cycles. A set of analog-to-digital converters 402-1 to 402-Q operate on the sample-and-hold outputs to obtain digitized values. A parallelized front-end filter 466 combines the digitized values ​​to provide a parallel set of limiter input values ​​(i.e., those values ​​that would otherwise be sequentially produced by the front-end filter 406). A set of pre-compensation units 452-1 to 452-Q operate on the parallel set of limiter inputs to produce Q sets of provisional decisions in parallel. Parallelized recursive selection multiplexer arrangement 468 (such as the parallelized recursive selection multiplexer arrangement disclosed in U.S. Patent 9,071,479 (“High-speed parallel decision feedback equalizer”)) operates on Q sets of provisional decisions to produce a parallel set of Q output symbol decisions.

[0053] In this example, the dual-level finder 470 operates on the selected digital signal and, moreover, has been parallelized to operate on a parallel set of the selected digital signals. The target level module 462 is a similarly parallelized version of module 454. The equalization error calculator 464 represents a parallel set of subtraction elements, each subtracting the target level of the output symbol decision from each corresponding limiter input to provide a parallel set of error signals. The mode signal causes the parallel set of input multiplexer 522 to forward a parallel set of Q received signals, a parallel set of Q limiter input signals, or a parallel set of Q error signals. The dual-level finder 520 operates on the parallel set of the selected signals to perform the same measurement as described above.

[0054] Returning to the target level module 454, the target level in the absence of any channel nonlinearity will be A k-n The sign values ​​are -3, -1, +1, and +3. The cursor coefficient f0 is typically normalized to one, but is retained here to be incorporated into the adaptive gain control. Limiting this example to N=1, there will be 16 target levels. Using the nonlinear term g, these target levels become... (1) The target level for adjacent symbol values ​​(where their preceding symbol decisions are the same) can be averaged to determine the limiter threshold.

[0055] As previously mentioned, the level finder can be used to determine each of these target levels, which, when subtracted from the equalized signal, produce a linearized equalization error applicable to the adaptation filter coefficients, timing recovery, and / or gain control. To break the cyclic dependency between the target levels and gain control, or to otherwise limit drift in the target levels and limiter thresholds, the target levels can be "anchored" to predetermined values ​​of the linear coefficients f0, f1. These predetermined values ​​are denoted below using tilde notation, i.e., denoted as f0, f1, f1, f2, f3, f4, f5, f6, f1, f6, f1, f1, f2, f3, f4, f5, f6, f6, f1, f6, f1, f6, f1, f6, f1, f2, f3, f6, f1, f1, f2, f3 ... , Such anchoring can take the form of first determining coefficient values ​​that represent the best linear fit to the target level determined by the level finder in equation (1). The best-fit coefficient values ​​are denoted below using caret, i.e., denoted as , The controller uses linear fitting coefficients and predetermined coefficients to determine the offset for each target level, producing an anchored target level: (2) (3)

[0056] The predetermined coefficient value can be temperature-dependent to account for anticipated variations in the characteristics of the received channel, which cause a loss in the impulse response relative to its width. As the transceiver temperature increases, the received signal envelope decreases, necessitating adjustments to the signal gain and / or limiter threshold to maintain a good bit error rate. To address this issue, this paper proposes a controller that monitors the signal envelope and adjusts the target level to compensate for such temperature effects. (Preset coefficient) The value can be adapted based on the signal envelope, gradually increasing when the signal envelope is below a lower threshold and gradually decreasing when the signal envelope is above an upper threshold. (Pre-signed coefficient) These predetermined coefficient values ​​can be kept fixed to provide a balance between ISI elimination capability and error propagation. , The best fitting coefficient value with the current target level , The values ​​are compared, and if they differ, the adjustment of the anchoring equation (2) is applied to the current target level. The adaptation based on the obtained equalization error will cause the signal envelope to converge within the desired range.

[0057] However, it should be noted that the target level is approximately... (That is, the nonlinearity is relatively small), for The least significant bit (LSB) increment results in a change with the external symbol (A). kThe target level offset of ±3 is three times this amount, leading to a potentially significant shift in the equalization error and an associated increase in the BER, until the signal gain and limiter threshold each converge to their new levels. One possible mitigation method is to use a "virtual" equalization level with a higher bit resolution (or some other form of higher precision, including floating-point representation) than the target level. The coefficient value allows the predetermined coefficient value to be incremented by a fraction of the target level LSB. If The coefficient can be incremented (and decremented) by, for example, 1 / 3 or 1 / 4 of the target level LSB, so that the target level of the external symbol will be offset by no more than 1 LSB at a time. In the internal symbol (A k =±1) The target level offset will be incremented multiple times before it is offset, but this more gradual change makes it possible to track better through adaptation techniques.

[0058] This method can be followed as follows Figure 7 The flowchart shown illustrates this. The equalizer receives the digital received signal in block 702. In block 704, the equalizer uses an FFE filter and optionally a feedback signal to provide the equalized signal to the decision element. In block 706, the decision element operates on the equalized signal to form a symbol decision. The equalized signal and symbol decision are combined in block 708 to calculate the equalization error (or at least the error polarity signal). In block 710, the equalizer uses the equalization error to adapt the filter coefficients, adjust the signal gain, and / or derive the signal sampling clock.

[0059] In block 712, the controller uses a level finder or some other form of envelope detector to measure the signal envelope. In block 714, the controller adjusts predetermined coefficient values ​​as needed to drive the signal envelope into a desired range and linearly expands the adjustment to apply the corresponding offset to each target level in the target range.

[0060] In block 716, the controller uses a level finder to locate the optimal target level as previously described. In block 718, these optimal levels are adjusted to anchor them to predetermined filter coefficient values ​​when the target level module is updated. In block 720, the controller can then use the level finder to adapt the limiter threshold as described in U.S. Patent 11,018,656 (“A Multi-FunctionSignal Measurement Circuit for ADC-based SerDes”). Alternatively, the limiter threshold can be derived from the optimal target level.

[0061] For ease of explanation, Figure 7The operations are shown and described sequentially. However, in practice, these operations are expected to be executed concurrently using pipelines or other forms of parallelization, and may be distributed across various hardware components or firmware modules.

[0062] Once fully understanding the above disclosure, numerous alternatives, equivalents, and modifications will become apparent to those skilled in the art. For example, DFE is used to provide context, but the disclosed principles also apply to other types of equalizers, including linear equalizers, partial response equalizers, and peak detectors. Furthermore, the specific examples provided herein assume the use of PAM4 signaling, but these principles are readily applicable to larger signal constellation sizes. The claims are intended to be construed as covering all such alternatives, equivalents, and modifications contained within the scope of the appended claims.

Claims

1. A receiver, comprising: An equalizer provides an equalized signal to one or more symbol decision elements, each of which uses multiple decision thresholds to represent symbol decisions; An equalization error calculator, which determines the equalization error signal by subtracting the target level corresponding to the symbol decision from the equalized signal; An adaptation module uses the equalization error signal to adapt to at least one of the following: received signal gain, filter coefficients of the equalizer, and sampling clock phase; An envelope detector that measures the envelope of the equalized signal; as well as A controller that determines equalization parameter adjustments based on the envelope and determines a gain-adjusted target level by applying the equalization parameter adjustments in proportion to the associated sign of the target level.

2. The receiver according to claim 1, wherein, The target level is determined independently to take into account the nonlinearity in the equalized signal.

3. The receiver according to claim 1, wherein, The equalization parameter adjustment has an amplitude smaller than that corresponding to the least significant bit of each target level as represented in the equalization error calculator, and wherein the controller uses a higher bit resolution than the equalization error calculator to represent each target level.

4. The receiver of claim 1, further comprising a level finder, the level finder being configurable to determine the median signal level for each symbol, wherein, The controller uses the level finder to determine a refined version of the gain-adjusted target level.

5. The receiver according to claim 4, wherein, The level finder further operates as the envelope detector.

6. The receiver according to claim 4, wherein, The equalizer is a decision feedback equalizer, which includes: A pre-compensation unit uses one or more symbol decision elements to generate provisional symbol decisions. Each symbol decision element uses a comparator configured to compare the equalized signal with a plurality of decision thresholds that take into account the channel response to a set of speculative symbols, including speculative current symbols and speculative prior symbols, which are different for different decision elements. Registers, configured to track prior symbolic decisions of the decision feedback equalizer; and A multiplexer configured to supply a current symbol decision, selected from the provisional symbol decision, to the register based on the prior symbol decision.

7. The receiver according to claim 6, wherein, The target level used by the equalization error calculator includes an independent target level for each combination of the current symbol decision and the previous symbol decision.

8. The receiver according to claim 7, wherein, After determining the refined version, the controller determines an adjustment to the refined version of the target level to anchor the target level to the gain-adjusted target level.

9. A receiving method, comprising: The equalized signal is provided to one or more symbol decision elements, each of which uses multiple decision thresholds to present symbol decisions. The equalization error signal is determined by subtracting the target level corresponding to the symbol decision from the equalized signal. Use equalization error to adapt to at least one of the following: received signal gain, filter coefficients, and sampling clock phase; Measure the envelope of the equalized signal; as well as The equalization parameters are adjusted based on the envelope. as well as The gain-adjusted target level is calculated by applying the equalization parameters in proportion to the associated sign of the target level.

10. The receiving method according to claim 9, wherein, The target level is determined independently to take into account the nonlinearity in the equalized signal.

11. The receiving method according to claim 9, wherein, The equalization parameter adjustment has an amplitude smaller than that corresponding to the least significant bit of each target level as represented in the equalization error calculator, and wherein the calculation uses a higher bit resolution than the equalization error calculator to represent each target level.

12. The receiving method of claim 9, further comprising using a level finder to determine a median signal level for each symbol, the median signal level serving as a refined version of the gain-adjusted target level.

13. The receiving method according to claim 12, wherein, The provision is performed by a decision feedback equalizer, which includes: A pre-compensation unit uses one or more symbol decision elements to generate provisional symbol decisions. Each symbol decision element uses a comparator configured to compare the equalized signal with a plurality of decision thresholds that take into account the channel response to a set of speculative symbols, including speculative current symbols and speculative prior symbols, which are different for different decision elements. Registers, configured to track prior symbolic decisions of the decision feedback equalizer; and A multiplexer configured to supply a current symbol decision, selected from the provisional symbol decision, to the register based on the prior symbol decision.

14. The receiving method according to claim 13, wherein, The target level used to determine the equalization error signal includes an independent target level for each combination of the current symbol decision and the previous symbol decision.

15. The receiving method according to claim 14, further comprising: After determining the refined version, the refined version of the target level is adjusted to anchor the target level to the gain-adjusted target level.

16. A non-transitory information storage medium having a semiconductor intellectual property core for generating a receiver circuit system, the receiver circuit system comprising: An equalizer provides an equalized signal to one or more symbol decision elements, each of which uses multiple decision thresholds to represent symbol decisions; An equalization error calculator, which determines the equalization error signal by subtracting the target level corresponding to the symbol decision from the equalized signal; An adaptation module uses the equalization error signal to adapt to at least one of the following: received signal gain, filter coefficients of the equalizer, and sampling clock phase; An envelope detector that measures the envelope of the equalized signal; as well as A controller that determines equalization parameter adjustments based on the envelope and determines a target level for gain adjustment by applying the equalization parameter adjustments in proportion to the associated sign of the target level.

17. The non-transient information storage medium according to claim 16, wherein, The target level is determined independently to take into account the nonlinearity in the equalized signal.

18. The non-transient information storage medium according to claim 16, wherein, The equalization parameter adjustment has an amplitude smaller than that corresponding to the least significant bit of each target level as represented in the equalization error calculator, and wherein the controller uses a higher bit resolution than the equalization error calculator to represent each target level.

19. The non-transient information storage medium according to claim 16, wherein, The receiver circuitry further includes a level finder configured to determine the median signal level for each symbol, wherein the controller uses the level finder to determine a refined version of the gain-adjusted target level.

20. The non-transient information storage medium according to claim 19, wherein, The equalizer is a decision feedback equalizer, which includes: A pre-compensation unit uses one or more symbol decision elements to generate provisional symbol decisions. Each symbol decision element uses a comparator configured to compare the equalized signal with a plurality of decision thresholds that take into account the channel response to a set of speculative symbols, including speculative current symbols and speculative prior symbols, which are different for different decision elements. Registers, configured to track prior symbolic decisions of the decision feedback equalizer; and A multiplexer configured to supply a current symbol decision, selected from the provisional symbol decision, to the register based on the prior symbol decision, and The target level used by the equalization error calculator includes an independent target level for each combination of the current symbol decision and the previous symbol decision.

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