Fpga implementation method and system of full pipelined channel estimation and channel equalization for mimo-ofdm system

Abstract

The application discloses a kind of MIMO-OFDM system full pipelined channel estimation and channel equalization FPGA implementation method and system, belong to MIMO-OFDM communication technical field.The method of the present application is first by constructing the coupled calculation model of channel estimation and equalization, the LS estimation result is directly substituted into ZF equalization;Then by analytic inversion algorithm based on adjoint matrix, realize full pipelined single-precision floating-point matrix multiplication and inversion;Finally, by data stream control antenna configuration mode under the condition of not increasing additional hardware logic resources using the feature of block matrix.In the FPGA device of the system, pilot cache module, intermediate result calculation and cache module and equalization result calculation module are designed, to solve the FPGA device resource consumption caused by matrix operation in the multi-antenna communication MIMO-OFDM system, while ensuring high precision and low processing delay, the maximum reuse of hardware resources is realized, and the comprehensive performance of MIMO-OFDM receiving end equipment on FPGA platform is significantly improved.

Description

Technical Field

[0001] This invention relates to an efficient implementation method for channel estimation and channel equalization in MIMO-OFDM systems based on FPGA. This method is applicable to high-speed wireless communication scenarios with strict limitations on delay, accuracy, and hardware resources, and belongs to the field of channel estimation technology for MIMO-OFDM systems.

[0002] MIMO, Multiple Input Multiple Output communications.

[0003] OFDM, Orthogonal Frequency Division Multiplexing. Background Technology

[0004] Currently, MIMO-OFDM technology utilizes multiple antennas at both the transmitting and receiving ends to transmit multiple signals in the same frequency band and time. It also leverages OFDM technology to convert frequency-selective fading channels into multiple flat fading sub-channels, significantly improving spectral efficiency and channel capacity. MIMO technology is defined by the IEEE 802.11n standard.

[0005] Channel estimation is used to obtain the channel's frequency response characteristics (i.e., channel state information, CSI), while channel equalization eliminates channel effects based on the channel estimation results and recovers the original transmitted symbols. The accuracy of channel estimation and channel equalization directly determines the bit error rate performance, making them the most computationally intensive and real-time-critical components in MIMO-OFDM receiver equipment.

[0006] The Field-Programmable Gate Array (FPGA) embedded digital signal processing (DSP) unit is chosen for computation. With its strong parallel computing capabilities, fast real-time response speed, and good reconfigurability, it has become the preferred hardware implementation carrier for MIMO-OFDM systems. In multi-antenna configuration scenarios, the parallel architecture of FPGA can effectively handle the large number of matrix operations required in the channel estimation and equalization process, meeting the system's strict real-time requirements.

[0007] Currently, FPGA implementations of matrix inversion for MIMO systems mainly rely on methods such as QR decomposition and Cholesky decomposition. These decomposition algorithms transform complex matrix inversion into solving triangular matrix equations. However, these decomposition-based methods are difficult to implement in a fully pipelined design on FPGAs, resulting in typically high latency, especially with a high number of subcarriers. When deploying MIMO-OFDM algorithms on FPGAs, the computational accuracy of hardware resources must also be considered. While traditional fixed-point arithmetic saves resources, it is prone to precision overflow or underflow during matrix inversion due to insufficient dynamic range, severely impacting demodulation performance at high signal-to-noise ratios.

[0008] In terms of multi-antenna adaptation, existing FPGA implementations are typically designed specifically for a fixed number of antennas. When the MIMO-OFDM receiver needs to adapt to a scenario with fewer antennas than designed, the properties of the block matrix cannot be fully utilized for resource optimization, resulting in wasted hardware resources. Furthermore, in existing solutions, least squares (LS) channel estimation and ZF channel equalization each have independent matrix multiplication resources, which cannot be shared, further increasing hardware resource overhead. Simultaneously, existing solutions employ a separate design of sequential "LS estimation, output channel matrix H, ZF inversion, and equalization calculation," failing to consider the coupling relationship between the two. The channel matrix H and its inverse must be explicitly calculated, leading to high overall computational complexity and making it difficult to simultaneously meet the comprehensive requirements of low latency, high accuracy, and low resource overhead.

[0009] To address the aforementioned issues, this invention considers the coupled design of channel estimation and equalization, and proposes an FPGA implementation method for fully pipelined channel estimation and channel equalization in MIMO-OFDM systems. Summary of the Invention

[0010] To address the technical challenges of low computational accuracy, high latency, and excessive hardware resource consumption in traditional MIMO-OFDM receivers during channel estimation and equalization, this invention proposes a fully pipelined FPGA implementation method and system for channel estimation and equalization, considering the coupled design of channel estimation and equalization. Specifically, this invention significantly reduces computational complexity through the coupled design of channel estimation and equalization. Simultaneously, it designs a pipelined inversion module based on the adjoint matrix and combines it with pipelined matrix multiplication to achieve high resource reuse of FPGA devices. Furthermore, to meet the needs of different antenna configurations, this invention utilizes block matrix technology to enable the matrix multiplication method in the coupled model of channel estimation and equalization to support scenarios with arbitrarily fewer than four antennas without adding extra control logic and hardware resources. Through this method, while maintaining high-precision floating-point arithmetic performance, the resource consumption of FPGA device logic units and DSP computing units can be significantly reduced, and low-latency data stream processing can be achieved.

[0011] See Figure 1 As shown, the FPGA implementation method for fully pipelined channel estimation and channel equalization in the MIMO-OFDM system of the present invention includes the following steps:

[0012] Step 1: Construct a coupled model for channel estimation and channel equalization;

[0013] The LS channel estimation results are coupled with ZF channel equalization to obtain a coupled model for channel estimation and channel equalization, denoted as [model name missing]. The aforementioned coupling model of channel estimation and channel equalization is adapted to FPGA-based fully pipelined data stream processing.

[0014] Step 2: FPGA implementation design based on the coupling model;

[0015] In the FPGA software design, a pilot buffer module, an intermediate result calculation and buffer module, and an equalization result calculation module were instantiated to complete the full pipelined data flow operation.

[0016] Pilot buffer module: In the OFDM standard frame structure, physical layer data frames typically consist of a preamble in the frame header, a known sequence of pilot symbols used for channel estimation, and valid data symbols;

[0017] The intermediate result calculation and caching module utilizes full pipelined matrix multiplication and inversion to calculate the intermediate result matrix for each subcarrier in parallel according to the coupling model, and stores it in a pipelined manner in the BRAM group.

[0018] The equalization result calculation module uses the cached intermediate result matrix to perform real-time channel equalization on each input frequency domain data symbol by reusing the full pipeline matrix multiplication module, and outputs the equalized data symbols.

[0019] Step A: Perform pilot sequence caching and dimension transformation;

[0020] The input parallel pilot symbols are stored in multiple BRAMs and their dimensions are transformed to adapt to the input format requirements of subsequent full pipeline matrix operations;

[0021] Step B involves pipelined computation and caching of intermediate results;

[0022] Using the full pipelined matrix multiplication module and the full pipelined matrix inversion module, the intermediate result matrix in the coupling formula is calculated in parallel for each subcarrier, and the calculation results are stored in the BRAM group in the order of subcarriers in a pipelined manner.

[0023] Step C: Calculate the channel equalization results;

[0024] Using the cached intermediate result matrix and the known transmitter pilot data, the input frequency domain data symbols are equalized in real time through the multiplexed full pipeline matrix multiplication module, and the equalized data symbols are output.

[0025] This invention discloses an FPGA implementation system for fully pipelined channel estimation and channel equalization in a MIMO-OFDM system. The system is implemented on an FPGA device.

[0026] A pilot buffer module is used to store the input parallel pilot symbols into multiple BRAMs and perform dimension transformation. The pilot buffer module consists of a pilot buffer controller and BRAMs.

[0027] The intermediate result calculation and caching module is used to utilize the full pipeline matrix multiplication module and the full pipeline matrix inversion module, based on the coupling model. The intermediate result matrix is ​​computed in parallel for each subcarrier and stored in a pipelined manner. The intermediate result computation and caching module consists of a matrix transpose module, a first matrix multiplication module, a pipelined inversion module based on the adjoint matrix, a second matrix multiplication module, a cache control module, and a BRAM.

[0028] The equalization result calculation module is used to perform real-time channel equalization on each input frequency domain data symbol by reusing the full pipeline matrix multiplication module using the cached intermediate result matrix, and output the equalized data symbols.

[0029] Compared with the prior art, the technical advantages of the present invention are as follows:

[0030] (1) This invention proposes a coupled design scheme for the mathematical characteristics of LS channel estimation and ZF channel equalization. The LS estimation result is directly substituted into the ZF formula for simplification, which avoids the explicit solution and storage of the channel matrix H in the traditional method and greatly reduces the computational complexity.

[0031] (2) This invention designs a pipelined inversion module based on the adjoint matrix combined with a pipelined matrix multiplication module, and uses single-precision floating-point numbers for calculation. Compared with traditional inversion schemes, this invention significantly reduces processing latency while ensuring high precision, thus meeting the needs of communication scenarios with extremely high real-time requirements.

[0032] (3) This invention achieves deep reuse and flexible adaptation of core computing resources. Channel estimation and channel equalization are performed using a single set of hardware resources, which greatly saves the computing resources of the FPGA. At the same time, by utilizing the properties of the block matrix, it can seamlessly support any configuration of less than 4 antennas, such as 3×3 and 2×2, without reconfiguring the FPGA or adding computing units, thus enhancing the versatility and compatibility of the system. Attached Figure Description

[0033] Figure 1 This is a flowchart of the FPGA implementation method for the fully pipelined channel estimation and channel equalization of the present invention.

[0034] Figure 2 This is a flowchart illustrating the construction of the coupled computational model for channel estimation and equalization in this invention.

[0035] Figure 3 This is a structural diagram of the FPGA implementation device for the fully pipelined channel estimation and channel equalization of the present invention.

[0036] Figure 4 This is a structural diagram of the intermediate result calculation and caching module of the present invention.

[0037] Figure 5 This is a diagram illustrating the steps of FPGA implementation of the full pipeline matrix inversion method of this invention.

[0038] Figure 6 This is a comparison chart of the fixed-point calculation accuracy and single-precision floating-point calculation accuracy of FPGA with the ideal results in Matlab under different channel correlations.

[0039] Figure 7 This is a comparison chart of the fixed-point calculation accuracy and single-precision floating-point calculation accuracy of FPGA with the ideal results in Matlab under different signal-to-noise ratios. Detailed Implementation

[0040] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. The examples of the parameters listed are merely preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

[0041] This invention employs Verilog programming language supporting IEEE Std 1364-2005 on the FPGA device. BRAM (Block RAM) is a dedicated, hard-core storage resource within the FPGA device. It consists of a series of fixed-size memory blocks used for efficient and reliable data storage within the chip. In MIMO-OFDM communication systems implemented using FPGA software, BRAM is a core internal cache resource ensuring the orderly, synchronous, and high-speed flow of data from multiple antennas.

[0042] This invention designs an instruction interface on an FPGA device using a programming language to implement data initiation, transmission, storage, and write / read operations. For example, it includes instructions for caching data. Cache address interface Cache write enable signal instruction Cache sequence information interface Sequence Extraction Address Interface Handshake status signal command Synchronous pull-up signal command Effective frequency domain data instructions .

[0043] Construct a coupled computational model for channel estimation and equalization.

[0044] This invention proposes a design scheme for mathematically coupling LS channel estimation and ZF channel equalization for MIMO-OFDM systems. This scheme not only avoids the explicit calculation and storage of the channel matrix in traditional methods, but also addresses... For non-square matrix scenarios, a coupled computation model based on generalized inverse expansion is presented to adapt to the full pipeline processing of FPGA software design.

[0045] In a MIMO-OFDM system, assuming the number of transmit antennas is... The number of receiving antennas is (In this embodiment, it is set to maximum support) (Configuration). For the k-th subcarrier, the frequency domain relationship is expressed as... ,in, for The received signal vector, Let be the channel frequency domain response matrix at the k-th frequency point. for The transmitted signal vector, It is an additive white Gaussian noise vector.

[0046] In the channel estimation phase, assume that the transmitter sends a known pilot signal matrix on the k-th subcarrier. , dimension Let be a full-rank square matrix, and let the pilot signal matrix received by the receiver be denoted as . , dimension The estimated value of the channel matrix based on the LS criterion is denoted as... ,and , dimension , Pilot signal matrix The inverse matrix.

[0047] During the channel equalization phase, let the data symbol vector received by the receiver on the k-th subcarrier be denoted as... The transmitted signal was recovered according to the ZF equalization criterion. The generalized inverse of the channel matrix needs to be calculated, i.e., the channel equalization is calculated as follows: , The estimated value of the channel matrix based on the LS criterion. The conjugate transpose of .

[0048] See Figure 2 As shown, in order to reduce the computational complexity of the coupling between channel estimation and equalization, the LS channel estimation results are substituted into... In the middle. Considering the pilot signal matrix transmitted by the k-th subcarrier. When the orthogonal pilots are known, the coupling relationship between channel estimation and equalization can be expressed as follows: Based on the above It includes four matrix multiplication operations and one matrix inversion operation, using a fully pipelined matrix multiplication module and a fully pipelined matrix inversion module as the basic operation units. First, it calculates... It requires two matrix multiplication operations and one matrix inversion operation, and then substituting the intermediate results into... Calculated in This requires two matrix multiplication operations. Therefore, in the FPGA software design, instantiating two matrix multiplication modules and one matrix inversion module can complete the fully pipelining operation. Register instructions were designed on the FPGA device. For example, the instruction to set the initial operation state of the register is Calculate at this time The calculation result is then stored in the BRAM; for example, the instruction for the current operation state of the register is... Calculate at this time .

[0049] This invention proposes a design scheme for MIMO-OFDM systems that couples LS channel estimation with ZF channel equalization, i.e., satisfies... This scheme not only avoids the explicit calculation and storage of the channel matrix in traditional methods, but also... The process also targets For non-square matrix scenarios, a coupled computation model based on generalized inverse expansion is presented to adapt to FPGA full pipeline processing.

[0050] See Figure 3As shown, this invention discloses an FPGA implementation system for a fully pipelined channel estimation and channel equalization (CECE) system in a MIMO-OFDM system (referred to as an FPGA-based fully pipelined CECE system). This invention's FPGA software-designed fully pipelined CECE system adds a pilot buffer module, an intermediate result calculation and buffer module, and a channel equalization result calculation module to the traditional MIMO-OFDM receiver's channel estimation and equalization modules. When the transmitted signal enters the receiver through the wireless channel, the amplitude and phase of the signal change at the receiving end due to channel noise. Therefore, channel estimation and equalization are required to recover the faded transmitted information. The pilot buffer module, intermediate result calculation and buffer module, and channel equalization result calculation module added to the traditional MIMO-OFDM receiver are designed on the FPGA device using a programming language. A design scheme that couples LS channel estimation and ZF channel equalization is adopted, thus satisfying... This scheme not only avoids the explicit calculation and storage of the channel matrix in traditional methods, but also... The process also targets For non-square matrix scenarios, a coupled computation model based on generalized inverse expansion is presented to adapt to FPGA full pipeline processing.

[0051] (1) Pilot buffer module

[0052] A pilot buffer module consisting of a pilot buffer controller and BRAM was built on the FPGA device using programming software.

[0053] In the OFDM standard frame structure, physical layer data frames typically consist of a preamble located in the frame header, used for channel estimation. Composition. The preamble is usually discarded after synchronization, therefore it is used after channel estimation and channel equalization. As a pilot symbol, and the dimension of the pilot symbol is ,in This indicates the number of antennas installed at the transmitting end. Indicates the number of subcarriers. This indicates the number of antennas configured at the receiving end. In this invention, each clock cycle has... Several parallel pilot symbols are input to the pilot buffer controller, requiring transmission. Includes The pilot symbols of each subcarrier consume [amount] One clock cycle.

[0054] In the FPGA software design and implementation, 16 BRAMs are instantiated for pilot sequence buffering. Each BRAM has a depth of h and a data width of 32 bits, consuming the resources of 16 BRAMs. Let the current sampling time be denoted as t, and the sampling times preceding the current sampling time t be denoted as... The sampling time located after the current sampling time t is denoted as The buffered pilot sequence information received by the pilot buffer controller at the current sampling time t is denoted as... The After pilot buffer processing by the pilot buffer controller, the buffer sequence information of the current sampling time t is output and denoted as follows: During a sampling period, data from the first sampling point is stored in parallel in the BRAM. to Each cached sequence of information. When the matrix transpose module needs to perform calculations, it retrieves the information from the BRAM in parallel. The buffer sequence information is processed in a pipelined manner. The BRAM designed in this invention is used to receive the buffer sequence information output by the pilot buffer controller on one hand, and to output the buffer sequence information stored in parallel on the other hand. The third aspect is receiving the sequence extraction address provided by the matrix transpose module. .

[0055] The pilot buffer module in the FPGA software design consumed a total of 16 buffer resources and a small amount of FPGA logic resources. Ignoring minor timing and state machine overhead, the total processing latency of the FPGA device is approximately... One clock cycle.

[0056] (2) Intermediate result calculation and caching module

[0057] An intermediate result calculation and caching module was constructed on an FPGA device using programming software. This module utilizes fully pipelined matrix multiplication and matrix inversion, and performs parallel calculations and real-time caching of intermediate matrices for each subcarrier based on a coupled model of channel estimation and channel equalization. See also... Figure 4 The intermediate result calculation and caching module of this invention, as shown, consists of a matrix transpose module, matrix multiplication module A, a pipelined inversion module based on the adjoint matrix, matrix multiplication module B, a cache control module, and a BRAM. Matrix multiplication module A and matrix multiplication module B each consist of two modules. Multiplier structure for scale matrix.

[0058] (3) Matrix transpose module

[0059] The matrix transpose module of this invention converts cached sequence information into a linear data arrangement format.

[0060] (4) Matrix multiplication module A

[0061] Because this invention supports physical layer technology for fully pipelined channel estimation and channel equalization of MIMO-OFDM systems on FPGA devices, it supports a maximum of [missing information - likely related to FPGA technology]. Given the antenna size, the left block matrix form in the matrix multiplication module A of the full pipeline matrix multiplication is therefore represented as: The column vectors of the block matrix C represents a complex number; the left expansion matrix form in matrix multiplication module A is expressed as: any element of the expanded matrix The subscript i is the row identifier of the row array, and the subscript j is the column identifier of the matrix.

[0062] (5) Matrix multiplication module B

[0063] The right-block matrix form in the matrix multiplication module B of the full-flow matrix multiplication is represented as follows: The column vectors of the block matrix , C represents a complex number; the expanded matrix form in the matrix multiplication module B is expressed as follows: Any element of the right expansion matrix , The subscript i is the row identifier of the row array, and the subscript j is the column identifier of the matrix.

[0064] The output column vector matrix after matrix multiplication module B is denoted as ,and .in Sixteen matrix multiplications are required. One complex multiplication operation requires four real multiplication operations and two real addition operations. Considering the timing stability of the FPGA and the characteristics of the IP core, let's assume that each floating-point real multiplication operation requires... 1 clock cycle, floating-point real number addition operation requires One clock cycle. Therefore, one complex matrix multiplication operation can be decomposed into one clock cycle. A multi-stage production line is required. One clock cycle completes. In the previous The clock cycle calculates all real number multiplications, then To perform real number addition in one clock cycle, four real number multipliers and two real number adders are required. Therefore, The calculation is also as follows The pipeline requires a total of 64 real number multipliers and 32 real number adders. In the input At that time Addition pipeline, front Calculate per clock cycle and ,back Calculate per clock cycle Since all additions are complex numbers, a total of 6 real number adders are needed. Therefore, the 4th order matrix multiplication is: A multi-stage production line is required. It takes one clock cycle and consumes 64 real multipliers and 38 real adders. Assume each real multiplier requires [a certain amount of time / cost]. Each DSP calculator resource requires a certain amount of resources; each real number adder consumes [amount / resources]. For each DSP calculator resource, a 4th order matrix multiplier would require a total of [amount missing]. DSP calculator resources.

[0065] This represents the number of clock cycles required for a single-precision floating-point real number multiplication operation.

[0066] This represents the number of clock cycles required for a single-precision floating-point real number addition operation.

[0067] (6) Pipeline inversion module based on adjoint matrix

[0068] A pipelined adjoint matrix inversion module was constructed on an FPGA device using programming software. This module is used for signal decoupling during channel estimation. If the dimension of the input matrix currently received by the pipelined adjoint matrix inversion module is less than 4, the properties of block matrices can be utilized for calculation.

[0069] In the pipelined inversion module based on the adjoint matrix, the matrix to be inverted is denoted as... ,and The The inverse matrix is ​​denoted as Then the analytical expression of the inverse matrix is: ,in, Let be the determinant of the matrix whose inverse is to be found. Let be the adjoint matrix of the matrix to be inverted. It is the transpose of a cofactor matrix, and its matrix representation is: Any element in this matrix is ​​a The determinant of a matrix.

[0070] In this invention, the clock-level fully pipelining inversion calculation process is divided into four stages, such as... Figure 5 As shown. The clock-level full pipelined architecture refers to inputting a matrix for each clock cycle and outputting an inverse matrix for each clock cycle after a fixed delay.

[0071] (a) Clock-level fully pipelined first computing stage

[0072] The first stage uses a parallel multiplier to calculate all the values ​​in the first two rows and the last two rows of the matrix. The determinant of the submatrix, i.e., solving for the second-order subdeterminant. This is the matrix whose inverse is to be found. Then it is necessary to calculate the inverse matrix of the matrix to be solved. and The subscripts s and r are the column identifiers of different columns in the matrix. There are a total of 12 second-order determinants to be calculated in the process of solving second-order subdeterminants. One second-order determinant calculation requires two complex multiplications and one complex addition. One complex multiplication requires four real multiplications and two real additions. Complex addition includes two real multiplications. Therefore, the delay for one second-order determinant calculation is... One clock cycle, consuming One DSP computing resource, 12 second-order determinants as consumption. One DSP computing resource.

[0073] (ii) Clock-level fully pipelined second calculation stage

[0074] Temporal alignment A is the matrix to be inverted. The matrix is ​​then aligned by shifting and paving.

[0075] Since the floating-point multiplication and addition in the first stage have a fixed delay, the matrix to be inverted cannot be directly multiplied with the second-order determinant output from the first stage. This invention designs a deep data shift register group (in an FPGA device) to achieve timing alignment and to shift the matrix to be inverted step by step in the register. Its delay depth precisely matches the operation time of the first stage. When the second-order determinant result of the first stage is output effectively, the matrix to be inverted is exactly shifted to the input of the multiplier in the second stage, thereby completing the operation of the third-order algebraic cofactor without interruption.

[0076] The second stage uses the results from the first stage to calculate all the 4th-order matrices. Algebraic cofactors, according to the Laplace expansion principle, each The algebraic cofactor can be derived from the aligned matrix and The sum of the products of the subdeterminants constitutes the solution for the third-order subdeterminant. By the Laplace expansion principle, when the value of the second-order determinant is known... The calculation of algebraic cofactors involves three complex multiplications and two complex additions, therefore The delay in calculating algebraic cofactors is One clock cycle, comprising 12 real multiplications and 10 real additions, requires One clock cycle, since the second stage requires a total of 16 calculations. Algebraic cofactors, therefore consume One DSP computing resource.

[0077] (III) Clock-level fully pipelined third computing stage

[0078] The third stage is the second-order subdeterminant calculated in the first stage. Based on the algebraic cofactors, calculate the determinant of the inverse matrix to be found. This involves solving for the fourth-order subdeterminant. According to the Laplace expansion theorem for determinants, the value of a fourth-order determinant is equal to the sum of the products of any row element and its corresponding cofactor. This invention selects the first row element for expansion calculation. This calculation requires four complex multipliers for parallel computation, the product result is summed through a two-stage pipelined addition tree, and requires three complex adders. The calculation includes one complex multiplication delay and two-stage addition delay, with a total delay of [calculation details missing]. It takes one clock cycle, four complex multipliers, and three complex adders to consume a total of [number] clock cycles. One DSP computing resource.

[0079] (iv) Clock-level fully pipelined fourth computing stage

[0080] The timing alignment B is to shift and beat the third-order sub-determinant to obtain the aligned matrix.

[0081] In the fourth stage, the fourth-order subdeterminant is divided element-wise by the aligned matrix of the third-order subdeterminant to obtain the final inverse matrix. Since implementing complex division directly in FPGA devices is extremely resource-intensive and timing convergence is difficult, this invention uses the modular square root method to transform complex inversion into real number operations. This process requires two real number multipliers, one real number adder, and one real number inverter. The total delay of this process is... One clock cycle, consuming One DSP computing resource. Calculate Afterwards, All elements and When performing complex multiplication, since There are 16 elements, and each complex multiplication consumes [amount missing]. The process consumes a total of DSP computing resources. One DSP computing resource, latency is The fourth phase consumes [number] clock cycles. One DSP computing resource, latency is One clock cycle.

[0082] This represents the number of clock cycles required to perform the inverse operation on a single-precision floating-point real number.

[0083] This represents the number of clock cycles required for a single-precision floating-point real number multiplication operation.

[0084] This represents the number of clock cycles required for a single-precision floating-point real number addition operation.

[0085] This represents the DSP computing resources consumed in the inverse operation of a single-precision floating-point real number.

[0086] This represents the DSP computing resources consumed by single-precision floating-point real number multiplication operations.

[0087] This represents the DSP computing resources consumed by single-precision floating-point real number addition operations.

[0088] In this invention, the pipelined inversion module based on the adjoint matrix counts the resource consumption and delay of the four stages, thus obtaining the total resource consumption of the entire pipelined matrix inversion module. One DSP computing resource, latency is Within one clock cycle, this invention employs a pipelined inversion method for the adjoint matrix to achieve low latency and low DSP resource consumption for inversion, thereby improving the efficiency of channel estimation.

[0089] (7) Cache control module

[0090] The cache control module of this invention is used, on the one hand, to receive intermediate results output by the matrix multiplication module B. On the other hand, it transmits cache control interface information (including cache data interface). Cache address interface Interface with cache write enable signal ) to BRAM.

[0091] Whenever an intermediate result When the intermediate results arrive at the cache control module, the cache control module first... Copy and start Interface, then for Increment the interface by 1, then start. The interface pulls the buffer write enable signal high until all intermediate results from all subcarriers are written into the BRAM. Once all intermediate results have been written, the buffer control module will... The interface signal is set to high level to indicate that all intermediate calculation results of the current subcarrier have been buffered.

[0092] (8) BRAM

[0093] In the FPGA device implementation, 16 BRAMs are instantiated to cache intermediate results. Since the total number of subcarriers is 64, the depth of the BRAM is the same as the number of intermediate results and the number of subcarriers, and is also set to 64. The data bit width of each memory cell is 64 bits (32 bits each for I / Q, corresponding to the real part and imaginary part of a single-precision floating-point number, respectively).

[0094] In FPGA device implementation, the BRAM receives cache data, cache address, and cache write enable signal from the cache control module, and then writes intermediate results in a pipelined manner according to the subcarrier index sequence. On the other hand, it receives the read address signal provided by the channel equalization result calculation module, synchronously reads the intermediate result matrix of the corresponding subcarrier index, and outputs it to the subsequent module for channel equalization calculation. If the actual antenna configuration is less than 4 transmit and 4 receive, the BRAM only stores the intermediate result matrix elements corresponding to the valid antenna configuration. The data of invalid channels is automatically padded with zeros when read to adapt to the inherent 4×4 computing capability of the hardware, thereby being compatible with any configuration mode of less than 4 antennas without adding extra hardware logic resources.

[0095] (9) Channel equalization result calculation module

[0096] A channel equalization result calculation module consisting of two matrix multiplications was constructed on an FPGA device using programming software. After completing the calculation and pipelined buffering of intermediate results, the MIMO-OFDM system enters the data symbol equalization processing stage, which uses the buffered intermediate result matrix to perform real-time channel equalization on each input frequency domain data symbol.

[0097] According to channel equalization and intermediate results Once the intermediate results are calculated, they can be read. Data. Matrix multiplication module A is responsible for calculation. When the valid frequency domain data command is triggered The matrix multiplication module A instantiates 16 synchronously read intermediate result matrices from the BRAM based on the subcarrier index of the current data symbol. Since the BRAM read operation has a fixed clock delay, the matrix multiplication module A needs to perform corresponding clock aligning on the input valid data symbols through a shift register chain to ensure that the intermediate result matrices and the corresponding subcarrier data symbols can accurately reach the input of the next-level operation module within the same clock cycle.

[0098] In the channel equalization result calculation, matrix multiplication module A first converts the input parallel complex symbols (16 bits each for I and Q) into single-precision floating-point format, and then performs matrix multiplication with the floating-point intermediate results read from BRAM. If the actual antenna configuration of the current system is less than 4 transmit and 4 receive, matrix multiplication module A will continue to utilize the properties of block matrices to pad the input of invalid data channels with zeros.

[0099] In the calculation of channel equalization results, matrix multiplication module B receives the calculation results output by matrix multiplication module A. , and pre-stored Multiplying yields the final channel equalization result. The matrix multiplication module A outputs the calculation results. For a column vector with dimension (4×1), when actually using the matrix multiplication module for calculation, it is necessary to pad the column vector with zeros to adapt it to the dimension of matrix multiplication module B.

[0100] Finally, the channel equalization results are output through the parallel bus and synchronously pulled high. The signal indicates the validity of the equalization data on the output bus. At this point, the complete MIMO-OFDM full-pipeline channel estimation and channel equalization data stream processing is finished.

[0101] In this invention, the delays of matrix multiplication module A and matrix multiplication module B are equal to the delay of one matrix multiplication operation. One clock cycle.

[0102] Example

[0103] The FPGA implementation method for full pipelined channel estimation and channel equalization of MIMO-OFDM system proposed in this invention is comprehensively evaluated by listing simulation examples, mainly covering the analysis of three dimensions: computational delay, resource consumption, and computational accuracy.

[0104] (A) Computational delay analysis

[0105] The delays in channel estimation and channel equalization mainly arise from three steps: pilot buffering, intermediate result calculation, and equalization result calculation. The pilot buffering time is approximately... One clock cycle; the delay in calculating the intermediate result is the delay of two matrix multiplications and the time for one matrix inversion, totaling [number] clock cycles. The calculation of the equalization result can only begin after all intermediate results have been calculated, which requires [number] clock cycles. One clock cycle; the delay for calculating the equalization result is... One clock cycle, due to the delay required for converting fixed-point to floating-point numbers. Converting a floating-point number to a fixed-point number requires a delay. Therefore, the theoretical delay calculation result is Based on the Vivado IP core, we can conclude that the IP core achieves optimal performance and maximum latency at the following conditions. , , and Therefore, the theoretical delay is calculated to be 675 clock cycles. Taking a 200MHz clock cycle as an example, the delay is... Since the calculation is a fully pipelined process, for classical parameters... and The total completion time is calculated as follows: One clock cycle, specifically the time is Compared to data frame times in milliseconds, this latency is extremely small.

[0106] Due to time overhead such as BRAM access latency and state machine switching, the actual computation latency is slightly higher than the theoretical computation latency, by about tens of clock cycles. In this embodiment, the measured computation latency is about 30 clock cycles higher than the theoretical computation latency.

[0107] (B) Resource Consumption Analysis

[0108] This module mainly consumes 2 Matrix multiplication module resources, 1 The matrix inversion module requires resources equivalent to 16 x 36Kbram units. A single matrix multiplication module consumes... Each DSP resource, consumed by a single matrix inversion module One DSP resource, therefore a total of [number] resources were consumed. One DSP resource. This can be obtained from the Vivado IP core attributes. , and Therefore, a total of 836 DSP resources are consumed, which is less than the DSP resources occupied by a common XCZU47DR RFSoC chip. Experimental results show that the DSP and Bram resource consumption are completely consistent with theoretical calculations.

[0109] (C) Calculation accuracy analysis

[0110] This experiment uses MATLAB to generate multiple random bitstreams, performs QAM (Quadrature Amplitude Modulation) mapping and IFFT (Inverse Fast Fourier Transform) modulation on the bitstreams, adds pilot symbols before the data symbols, and passes the resulting time-domain data through a multipath fading channel with Gaussian white noise added. Subsequently, the received signals are input into a MATLAB ideal calculation model, an FPGA 16-bit fixed-point calculation model, and the FPGA single-precision floating-point calculation model used in this invention, respectively, to complete channel estimation and channel equalization. Finally, using the ideal modulation symbols at the transmitting end as a reference, the EVM of the equalization results obtained by the three calculation methods is calculated to evaluate the error performance of the system demodulation results under different numerical precisions.

[0111] The simulation parameters to be set include: the number of transmitting antennas. Number of receiving antennas QAM modulation order Number of subcarriers Number of data symbols ; Length of the cyclic prefix .

[0112] In MIMO-OFDM systems, channel estimation and equalization involve numerous complex matrix operations, among which multi-antenna matrix inversion and matrix multiplication are highly sensitive to numerical precision. As the spatial correlation of MIMO channels increases, the ill-conditioned nature of the channel matrix typically intensifies, making matrix inversion more prone to amplifying fixed-point quantization and rounding errors, thus affecting the EVM (Error Vector Magnitude) performance of the final equalized symbol. To eliminate the randomness caused by the single generation of stochastic fading channels, this embodiment conducted independent experiments on different channel spatial correlation coefficients at a 20dB signal-to-noise ratio. The EVM results corresponding to MATLAB ideal calculation, FPGA 16-bit fixed-point calculation, and FPGA single-precision floating-point calculation under different channel correlation conditions were statistically analyzed. Figure 6 As shown.

[0113] Furthermore, to examine the impact of three computational accuracies on system performance under different signal-to-noise ratios, this embodiment fixes the MIMO channel spatial correlation coefficient at 0.7 and sets the signal-to-noise ratio to 10dB to 30dB. The EVM of the equalization results obtained from ideal MATLAB calculations, FPGA 16-bit fixed-point calculations, and FPGA single-precision floating-point calculations are statistically analyzed, as follows: Figure 7 As shown.

[0114] Experimental results show that, compared with FPGA fixed-point computation, FPGA single-precision floating-point computation can achieve EVM performance close to that of MATLAB's ideal double-precision computation under different channel correlations and signal-to-noise ratios, while the equalization results of fixed-point computation are significantly worse. This indicates that the single-precision floating-point pipeline structure used in this invention can effectively reduce numerical quantization errors in matrix operations and improve the computational accuracy of MIMO-OFDM channel estimation and channel equalization results.

Claims

1. An FPGA implementation method for fully pipelined channel estimation and channel equalization in a MIMO-OFDM system, characterized in that... The method includes: Step 1: Construct a coupled model for channel estimation and channel equalization; The LS channel estimation results are coupled with ZF channel equalization to obtain the following coupling model for channel estimation and channel equalization: ; This refers to the pilot information from the transmitting end; To cache pilot sequence information; for The complex transpose; The information received by the receiving end; The aforementioned coupling model of channel estimation and channel equalization is adapted to FPGA-based fully pipelined data flow processing; Step 2: FPGA implementation design based on the coupling model; In the FPGA software design, a pilot buffer module, an intermediate result calculation and buffer module, and an equalization result calculation module were instantiated and designed. The pilot buffer module stores the input parallel pilot symbols into multiple BRAMs and performs dimension transformation; The intermediate result calculation and caching module uses the full pipeline matrix multiplication module and the full pipeline matrix inversion module to calculate the intermediate result matrix in parallel for each subcarrier according to the coupling model, and stores it in a pipelined manner into the BRAM group; The equalization result calculation module uses the cached intermediate result matrix to perform real-time channel equalization on each input frequency domain data symbol by reusing the full pipeline matrix multiplication module, and outputs the equalized data symbols.

2. The FPGA implementation method for fully pipelined channel estimation and channel equalization in a MIMO-OFDM system according to claim 1, characterized in that, For the k-th subcarrier, the channel matrix estimate is obtained based on the LS criterion. The channel equalization calculation used to recover the transmitted signal based on the ZF equalization criterion is as follows: .

3. The FPGA implementation method for fully pipelined channel estimation and channel equalization in a MIMO-OFDM system according to claim 1, characterized in that, The fully pipelined matrix inversion module is implemented based on the adjoint matrix. The inversion calculation of the matrix to be inverted is divided into four stages under the clock-level fully pipelined operation: The fully pipelined matrix inversion module described in step two is implemented using an analytical inversion algorithm based on the adjoint matrix, which specifically includes four core stages: The first stage uses a parallel multiplier to calculate the determinants of all second-order submatrices of the input matrix; The second stage uses the results of the first stage to calculate all algebraic cofactors of the input matrix; The third stage calculates the determinant of the input matrix according to the Laplace expansion theorem; the fourth stage uses the modulus square reciprocal method to convert the complex number inversion into real number operations, calculates the reciprocal of the determinant, and multiplies it with the adjoint matrix to obtain the final inverse matrix; the four stages constitute a clock-level full pipeline, with one matrix input per clock cycle and one inverse matrix output per clock cycle after a fixed delay.

4. The FPGA implementation method for fully pipelined channel estimation and channel equalization in a MIMO-OFDM system according to claim 3, characterized in that, Both the second and fourth stages include a timing alignment step, which uses a deep data shift register group to shift and time the input data to precisely match the time consumption of other operation stages and ensure that the data flow is uninterrupted.

5. The FPGA implementation method for fully pipelined channel estimation and channel equalization in a MIMO-OFDM system according to claim 3, characterized in that, The full pipeline matrix multiplication module and the full pipeline matrix inversion module perform operations using single-precision floating-point format.

6. The FPGA implementation method for fully pipelined channel estimation and channel equalization in a MIMO-OFDM system according to claim 1, characterized in that, The method further includes an antenna configuration adaptation step: when the actual antenna configuration is less than 4 transmit and 4 receive, the intermediate result calculation and caching module and the equalization result calculation module utilize the block matrix property to calculate and store only the matrix elements corresponding to the valid antenna configuration. The data of the invalid channel is automatically padded with zeros when read, so as to be compatible with any configuration mode of less than 4 antennas.

7. An FPGA implementation system for fully pipelined channel estimation and channel equalization in a MIMO-OFDM system, characterized in that, The system is implemented on an FPGA device: A pilot buffer module is used to store the input parallel pilot symbols into multiple BRAMs and perform dimension transformation. The pilot buffer module consists of a pilot buffer controller and BRAMs. The intermediate result calculation and caching module is used to utilize the full pipeline matrix multiplication module and the full pipeline matrix inversion module, based on the coupling model. The intermediate result matrix is ​​computed in parallel for each subcarrier and stored in a pipelined manner. The intermediate result computation and caching module consists of a matrix transpose module, a first matrix multiplication module, a pipelined inversion module based on the adjoint matrix, a second matrix multiplication module, a cache control module, and a BRAM. The equalization result calculation module is used to perform real-time channel equalization on each input frequency domain data symbol by reusing the full pipeline matrix multiplication module using the cached intermediate result matrix, and output the equalized data symbols.

8. The system according to claim 7, characterized in that, The adjoint matrix-based pipelined inversion module divides the inversion calculation into four clock-level fully pipelined stages: In the first stage, calculate the determinants of all second-order submatrices in the first two rows and the last two rows of the inverse matrix to be found; In the second stage, all third-order algebraic cofactors of the inverse matrix to be found are calculated using the results of the first stage. In the third stage, based on the third-order algebraic cofactor, the determinant value of the matrix to be inverted is calculated. In the fourth stage, the matrix is ​​divided element by element based on the third-order algebraic cofactor and the determinant value to obtain the final inverse matrix.

9. The system according to claim 7, characterized in that, The pipelined inversion module based on the adjoint matrix also includes a depth data shift register group, which is used to perform timing alignment of the input data in the second and fourth stages.

10. The system according to claim 7, characterized in that, Both the first matrix multiplication module and the second matrix multiplication module have two components. The system has a multiplier structure for the scaling matrix and supports a maximum configuration of 4 transmit and 4 receive antennas.

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