A full-digital half-baud rate clock recovery method and system based on FTN assistance

Abstract

The application relates to the field of optical communication systems and high-speed optical signal processing, and more particularly to a full-digital single baud rate clock recovery method and system based on FTN assistance. The 3Sign-TED algorithm is used to realize low-complexity timing error extraction under the condition of single baud rate, the spectrum compression characteristic of the FTN technology is used, and equivalent oversampling characteristics are constructed under the condition of single baud rate sampling, so that the digital interpolation filter in the clock recovery loop can work under the condition of single baud rate, and finally the oversampling rate required by the entire clock recovery module is reduced to single baud rate. In addition, in order to solve the ISI caused by spectrum compression, the application utilizes the THP precoding technology based on the transmitting end, and proposes an equalizer combined with phase tracking to realize low-complexity recovery of the FTN signal.

Description

Technical Field

[0001] This application relates to the fields of optical communication systems and high-speed optical signal processing technology, and more specifically, to a method and system for recovering a fully digital single baud rate clock based on FTN assistance. Background Technology

[0002] To meet the urgent need for capacity expansion and upgrades in short-distance optical interconnect transmission systems for intelligent computing centers, coherent technology, with its rich modulation dimensions, is considered a key technology with great potential to overcome the bottlenecks of future short-distance optical interconnects. However, traditional coherent optical communication technology relies on complex oversampling digital signal processing (DSP) algorithms to ensure reliable signal recovery, resulting in high power consumption and making it difficult to meet the stringent power consumption requirements of intelligent computing centers. Therefore, it is necessary to simplify the coherent DSP algorithm. According to the power consumption distribution of coherent optical modules, the power consumption generated by the DSP is dominant. Since the power consumption generated by the DSP is proportional to the oversampling rate, reducing the oversampling rate required by the coherent DSP to one baud rate will be the most direct and effective way to reduce power consumption. However, the clock recovery module in traditional coherent systems is highly dependent on the digital oversampling rate. Classic timing error detection (TED) algorithms, such as the Gardner and Godard algorithms, all require at least two times oversampling. The Mueller & Müller (MM) algorithm, a classic single-baud-rate TED algorithm widely used in intensity-modulated direct detection systems, is highly sensitive to impairments such as frequency offset, phase noise, and dispersion in coherent systems. It requires embedding a corresponding compensation module in the clock recovery loop, thus introducing a significant loop delay. Another single-baud-rate TED algorithm, the Absolute Phase Detection (ABSPD) algorithm, is more robust to frequency offset and phase noise, but it still involves excessive multiplication operations when extracting timing errors, resulting in high computational complexity. Although the ABSPD algorithm can extract timing errors under single-baud-rate conditions, the digital interpolation filter in the clock recovery loop still relies on oversampled data samples to reconstruct the signal at the optimal sampling time, thus not achieving single-baud-rate operation for the entire clock recovery loop.

[0003] In summary, clock recovery schemes based on commonly used TED algorithms, such as the classic time-domain Gardner algorithm and the frequency-domain Godard algorithm, are highly dependent on the receiver's oversampling rate, extracting timing errors under at least double oversampling conditions, resulting in high computational complexity. In single-baud-rate clock recovery schemes based on the MM algorithm, the MM algorithm is highly sensitive to frequency offset, phase noise, and dispersion in coherent systems, requiring the embedding of corresponding compensation modules in the loop, thus introducing significant loop delays and making it unsuitable for coherent systems. In existing clock recovery schemes based on the ABSPD algorithm, although the TED module in the loop can operate at single baud rate, the digital interpolation filter in the clock recovery loop still needs to utilize oversampled data samples to reconstruct the signal at the optimal sampling time, failing to reduce the oversampling rate required for the entire clock recovery loop to single baud rate. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of existing clock recovery algorithms, such as high computational complexity and the need for oversampling in some steps. It provides a fully digital single-baud-rate clock recovery method and system based on FTN assistance, which effectively reduces computational complexity and achieves fully digital single-baud-rate clock recovery.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: A fully digital single-baud-rate clock recovery method based on FTN (Faster-than-Nyquist) assistance is provided, comprising the following steps: S1. Map the generated pseudo-random bit sequence to QAM symbols, and perform THP (Tomlinson-Harashima Precoding) precoding on the QAM symbols; S2. The THP precoded signal is compressed and shaped using an FTN root raised cosine filter. S3. Resample the signal to one baud rate and perform dispersion compensation; S4. Timing synchronization is performed through a fully digital single-baud-rate clock recovery loop based on the 3Sign-TED algorithm, and clock recovery is completed at single baud rate.

[0006] This invention discloses an all-digital single-baud-rate clock recovery method based on FTN assistance. By utilizing the spectral compression characteristics of FTN technology, an equivalent oversampling characteristic is constructed under single-baud-rate sampling conditions. This enables the digital interpolation filter to reconstruct the FTN signal at the optimal sampling time under single-baud-rate conditions, thereby realizing an all-digital single-baud-rate clock recovery loop. This reduces the oversampling rate required by the clock recovery module to single-baud rate, thus reducing the complexity of the receiver DSP. Since spectral compression introduces severe inter-symbol interference (ISI), this invention employs a transmitter-based THP precoding method to achieve low-complexity recovery of the FTN signal.

[0007] Further, in step S1, the THP precoding of the QAM symbols includes: (1) (2) In the formula, Represents the original data. The results after introducing ISI, This is the final output after THP precoding. M The modulation order, These are the tap coefficients of the feedback equalizer. N This refers to the tap length; Based on the above formulas (1) and (2), the output of THP precoding is expressed as: (3) In the formula, n Represents an integer.

[0008] Further, in step S4, the all-digital clock recovery loop includes an interpolation filter, a timing error detector, a loop filter, and a numerically controlled oscillator. When calculating the timing error, the timing error detector uses sign judgment instead of numerical multiplication. After calculating the timing error, the timing error is input into the loop filter for noise filtering to obtain a control word. Then, the control word is used to control the numerically controlled oscillator, and the fractional interval is calculated from the output of the numerically controlled oscillator and the control word. The received signal is interpolated in the interpolation filter using the integer sign and the calculated fractional interval, thereby calculating the correctly timed data.

[0009] Furthermore, the timing error detector calculates the timing error based on the 3Sign-TED algorithm. : (4) In the formula, and These are the real and imaginary parts of the received signal, respectively.k Indicates a time index. This indicates the length of the data block used in each calculation of the timing error. This indicates symbolic operation.

[0010] This invention also provides an FTN-assisted all-digital single-baud-rate clock recovery system, comprising: THP precoding module: used to map the generated pseudo-random bit sequence to QAM symbols and perform THP precoding on the QAM symbols; FTN spectrum compression module: used to perform spectrum compression and shaping on the pre-coded signal using FTN raised cosine filters; Dispersion compensation module: used to perform dispersion compensation on signals resampled to one baud rate; All-digital clock recovery module: Used for timing synchronization through an all-digital single-baud-rate clock recovery loop based on the 3Sign-TED algorithm, and completes clock recovery at single baud rate.

[0011] Furthermore, the THP precoding module performs THP precoding in the following manner: (1) (2) In the formula, Represents the original data. The results after introducing ISI, This is the final output after THP precoding. M The modulation order, These are the tap coefficients of the feedback equalizer. N This refers to the tap length; Based on the above formulas (1) and (2), the output of THP precoding is expressed as: (3) In the formula, n Represents an integer.

[0012] Furthermore, in the all-digital clock recovery module, the all-digital clock recovery loop includes an interpolation filter, a timing error detector, a loop filter, and a numerically controlled oscillator. When calculating the timing error, the timing error detector uses sign judgment to replace numerical multiplication. After calculating the timing error, the timing error is input into the loop filter for noise filtering to obtain a control word. Then, the control word is used to control the numerically controlled oscillator, and the fractional interval is calculated from the output of the numerically controlled oscillator and the control word. The received signal is interpolated in the interpolation filter using the integer sign and the calculated fractional interval, thereby calculating the correctly timed data.

[0013] Furthermore, the timing error detector extracts timing errors based on the 3Sign-TED algorithm. : (4) In the formula, and These are the real and imaginary parts of the received signal, respectively. k Indicates a time index. This indicates the length of the data block used in each calculation of the timing error. This indicates symbolic operation.

[0014] The present invention also provides an optical communication method, comprising: Transmitter digital signal processing: First, the pseudo-random bit sequence is mapped to QAM symbols. Then, the QAM is precoded using the THP precoding method described above. Next, the precoded signal is spectral compressed and shaped using an FTN root raised cosine filter. Finally, the signal is resampled. Digital signal processing at the receiver: First, the signal is resampled to single baud rate. Then, after dispersion compensation, a fully digital single baud rate clock recovery loop based on the 3Sign-TED algorithm is used for timing synchronization. Subsequently, after synchronization and frequency offset compensation, an equalizer combined with phase noise tracking is used to achieve equalization and phase noise compensation. Finally, the equalized signal is subjected to modulo operation to achieve THP decoding, and the bit error rate is calculated.

[0015] This invention provides an optical communication method that utilizes the spectral compression characteristics of FTN technology to ensure that the obtained FTN signal possesses inherent oversampling characteristics under single baud rate sampling conditions. This facilitates the reconstruction of the optimal sampling time of the FTN signal by a digital interpolation filter under single baud rate sampling. However, spectral compression introduces severe inter-symbol interference (ISI). To achieve low-complexity recovery of the FTN signal, this invention employs a transmitter-based Tomlinson-Harashima precoding (THP) technique and proposes an equalizer combined with phase tracking to achieve equalization and phase noise compensation of the FTN signal.

[0016] Furthermore, the equalization process performed by the equalizer in conjunction with phase noise tracking includes: (5) In the formula, , and , These represent the input and output of the equalizer, respectively. , , , These represent the tap coefficients of the equalizer.p The phase factor representing a single tap; The update process for tap coefficients and phase factors includes: (6) (7) In the formula, and These represent the step sizes for updating the equalizer tap coefficients and phase factors, respectively. * indicates the conjugate operation. and The error signals representing X-polarization and Y-polarization are calculated as follows: (8) In the formula, and This represents the standard extended signal after the ideal training sequence or decision.

[0017] Compared with the prior art, the beneficial effects of the present invention are: This invention discloses an all-digital single-baud-rate clock recovery method and system based on FTN assistance. It not only utilizes the 3Sign-TED algorithm to achieve low-complexity timing error extraction under single-baud-rate conditions, but also leverages the spectral compression characteristics of FTN technology to construct equivalent oversampling characteristics under single-baud-rate sampling conditions. This allows the digital interpolation filter in the clock recovery loop to operate under single-baud-rate conditions, ultimately reducing the oversampling rate required by the entire clock recovery module to single-baud-rate. Furthermore, to address ISI caused by spectral compression, this invention employs THP precoding technology based on the transmitter and proposes an equalizer combined with phase tracking to achieve low-complexity recovery of FTN signals. Attached Figure Description

[0018] Figure 1 This is a flowchart illustrating an FTN-assisted all-digital single-baud-rate clock recovery method. Figure 2 This is a schematic diagram illustrating the implementation principle of THP precoding in one embodiment; Figure 3 This is a schematic diagram illustrating the implementation principle of the 3Sign-TED algorithm in one embodiment; Figure 4 This is a schematic diagram of an equalizer architecture incorporating phase tracking in another embodiment; Figure 5 This is a schematic diagram of the experimental system apparatus in Example 4; Figure 6 This is a schematic diagram comparing the performance of uncompressed signal and FTN signal in Example 4; Figure 7This is a schematic diagram of the bit error rate performance curves under different sampling frequency offset conditions in Example 4; Figure 8 This is a schematic diagram of the bit error rate curves under different oversampling rate conditions in Example 4. Detailed Implementation

[0019] The present invention will be further described below with reference to specific embodiments. The accompanying drawings are for illustrative purposes only, representing schematic diagrams rather than actual physical objects, and should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some components in the drawings may be omitted, enlarged, or reduced, and do not represent the actual dimensions of the product. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0020] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0021] Example 1 This embodiment is an example of an FTN-assisted all-digital single-baud-rate clock recovery method, such as... Figure 1 As shown, it includes the following steps: Step S1. Map the generated pseudo-random bit sequence to QAM symbols, and perform THP precoding on the QAM symbols; such as Figure 2 The diagram shown illustrates the implementation principle of THP precoding. The THP precoding process includes: (1) (2) In the formula, Represents the original data. The results after introducing ISI, This is the final output after THP precoding. M The modulation order, These are the tap coefficients of the feedback equalizer. N This refers to the tap length; Based on the above formulas (1) and (2), the output of THP precoding is expressed as: (3) In the formula, n Represents an integer. From formula (3), the extended signal can be obtained. :

[0022] The extended signal is the equalization target of the receiver equalizer. After equalization, the extended signal can be used to recover the original signal through analog-to-digital conversion.

[0023] Step S2. Use an FTN root raised cosine filter to perform spectral compression and shaping on the THP precoded signal.

[0024] Step S3. Resample the signal to one baud rate and perform dispersion compensation; Step S4. Timing synchronization is performed using a fully digital single-baud-rate clock recovery loop based on the 3Sign-TED algorithm, completing clock recovery at single baud rate. For example... Figure 3 The diagram shown is a schematic of the 3Sign-TED algorithm implementation.

[0025] In this embodiment, the all-digital clock recovery loop includes an interpolation filter, a timing error detector, a loop filter, and a numerically controlled oscillator (CNC). When calculating the timing error, the timing error detector uses sign judgment instead of numerical multiplication. After calculating the timing error, the timing error is input into the loop filter for noise filtering to obtain a control word. The control word is then used to control the CNC, and the output of the CNC and the control word are used to calculate a fractional interval. The received signal is interpolated in the interpolation filter using the integer sign and the calculated fractional interval to obtain correctly timed data.

[0026] The timing error detector calculates the timing error using the following method. : (4) In the formula, and These are the real and imaginary parts of the received signal, respectively. k Indicates a time index. This indicates the length of the data block used in each calculation of the timing error. This indicates symbolic operation.

[0027] This embodiment presents an all-digital single-baud-rate clock recovery method based on FTN assistance. By utilizing the spectral compression characteristics of FTN technology, an equivalent oversampling characteristic is constructed under single-baud-rate sampling conditions. This allows the digital interpolation filter to reconstruct the FTN signal at the optimal sampling time under single-baud-rate conditions, thereby realizing an all-digital single-baud-rate clock recovery loop. This reduces the oversampling rate required by the clock recovery module to single-baud rate, thus reducing the complexity of the receiver's DSP. Since spectral compression introduces severe inter-symbol interference (ISI), this invention employs a transmitter-based THP precoding method to achieve low-complexity recovery of the FTN signal.

[0028] Example 2 This embodiment is an example of an FTN-assisted all-digital single-baud-rate clock recovery system, including: The THP precoding module maps the generated pseudo-random bit sequence to QAM symbols and performs THP precoding on the QAM symbols. The THP precoding module performs THP precoding as follows: (1) (2) In the formula, Represents the original data. The results after introducing ISI, This is the final output after THP precoding. M The modulation order, These are the tap coefficients of the feedback equalizer. N This refers to the tap length; Based on the above formulas (1) and (2), the output of THP precoding is expressed as: (3) In the formula, n Represents an integer.

[0029] FTN spectrum compression module: used to perform spectrum compression and shaping on the pre-coded signal using FTN raised cosine filters.

[0030] Dispersion compensation module: used to perform dispersion compensation on signals resampled to one baud rate; All-digital clock recovery module: used for timing synchronization through an all-digital single-baud-rate clock recovery loop, and completes clock recovery at single baud rate.

[0031] The all-digital clock recovery loop includes an interpolation filter, a timing error detector, a loop filter, and a numerically controlled oscillator (CNC). The timing error detector uses sign judgment instead of numerical multiplication when calculating the timing error. After calculating the timing error, the timing error is input to the loop filter for noise filtering to obtain a control word. The control word is then used to control the CNC, and the output of the CNC and the control word are used to calculate a fractional interval. The received signal is interpolated in the interpolation filter using the integer sign marker and the calculated fractional interval to obtain correctly timed data.

[0032] The timing error detector extracts timing errors based on the 3Sign-TED algorithm. : (4) In the formula, and These are the real and imaginary parts of the received signal, respectively. k Indicates a time index. This indicates the length of the data block used in each calculation of the timing error. This indicates symbolic operation.

[0033] The working principle and beneficial effects of this embodiment are similar to those of Embodiment 1, and will not be repeated here.

[0034] Example 3 This embodiment is an example of an optical communication method, including: Transmitter digital signal processing: First, the pseudo-random bit sequence is mapped to QAM symbols. Then, the QAM is precoded using the THP precoding described in Example 1. Next, the precoded signal is spectral compressed and shaped using an FTN root raised cosine filter. Finally, the signal is resampled. Digital signal processing at the receiver: First, the signal is resampled to single baud rate. Then, after dispersion compensation, a fully digital single baud rate clock recovery loop based on the 3Sign-TED algorithm is used for timing synchronization. Subsequently, after synchronization and frequency offset compensation, an equalizer combined with phase noise tracking is used to achieve equalization and phase noise compensation. Finally, the equalized signal is subjected to modulo operation to achieve THP decoding, and the bit error rate is calculated.

[0035] In this embodiment, as Figure 4 The diagram shown is a schematic of an equalization architecture combining phase tracking proposed in this embodiment. The equalization process is represented as follows: (5) In the formula, , and , These represent the input and output of the equalizer, respectively. , , , These represent the tap coefficients of the equalizer. p The phase factor representing a single tap; The update process for tap coefficients and phase factors includes: (6) (7) In the formula, and These represent the step sizes for updating the equalizer tap coefficients and phase factors, respectively. * indicates the conjugate operation. and The error signals representing X-polarization and Y-polarization are calculated as follows: (8) In the formula, and This represents the standard extended signal after the ideal training sequence or decision.

[0036] This embodiment provides an optical communication method that utilizes the spectral compression characteristics of FTN technology to ensure that the obtained FTN signal possesses inherent oversampling characteristics under single baud rate sampling conditions. This facilitates the reconstruction of the optimal sampling time of the FTN signal by the digital interpolation filter under single baud rate sampling. However, spectral compression introduces severe inter-symbol interference (ISI). To achieve low-complexity recovery of the FTN signal, this invention employs the transmitter-based Tomlinson-Harashima precoding (THP) technique and proposes an equalizer combined with phase tracking to achieve equalization and phase noise compensation of the FTN signal.

[0037] Example 4 This embodiment provides a specific implementation scheme based on the method of Embodiment 3, and analyzes and verifies the method of the present invention through experiments.

[0038] The effectiveness was verified in a dual-polarization 35Gbaud FTN 16QAM coherent optical communication system. Figure 5A schematic diagram of the experimental system setup for this invention is provided. At the transmitting end, the offline-generated signal is fed into a digital-to-analog converter (DAC) with a sampling rate of 80 GSa / s. The output of the DAC is then input into a dual-polarization IQ modulator (DP-IQM) for electro-optical conversion. The optical carrier is provided by an external cavity laser with a linewidth less than 100 kHz and an output optical power of 16 dBm. The modulated signal is amplified by an optical amplifier and then injected into an 80 km long optical fiber for transmission. At the receiving end, an adjustable optical attenuator adjusts the received optical power of the signal. Then, a local oscillator laser (LO) with an output optical power of 16 dBm is input along with the signal to an integrated coherent receiver for coherent detection. The detected signal is acquired by an analog-to-digital converter (ADC) with a sampling rate of 80 GSa / s, and the final acquired signal is processed by an offline DSP.

[0039] (1) Transmitter DSP: In the transmitter DSP, a pseudo-random bit sequence is first mapped to 16QAM symbols to generate two 35Gbaud 16QAM signals; then, the 16QAM symbols are precoded using THP; next, the encoded signal is spectrally compressed and shaped using an FTN root raised cosine filter with a roll-off factor of 0; finally, the signal is resampled.

[0040] (2) Receiver DSP: In the receiver DSP, the signal is first resampled to a single baud rate. Then, after dispersion compensation, a proposed all-digital single baud rate clock recovery loop based on the 3Sign-TED algorithm is used for timing synchronization. Subsequently, after synchronization and frequency offset compensation, the proposed equalizer combined with phase noise tracking is used to achieve equalization and phase noise compensation. Finally, the equalized signal is subjected to modulo operation to achieve THP decoding, and the bit error rate is calculated.

[0041] Results analysis: based on Figure 5 The experimental setup first presents the bit error rate curves of traditional uncompressed 16QAM signals and FTN signals (spectral compression factor = 0.95) after transmission through 80 kilometers of optical fiber under the condition of a sampling frequency offset of 15ppm and the use of a fully digital single baud rate clock recovery loop. Figure 6 As shown, the signal performance without sampling frequency offset is also given as a reference. For uncompressed signals, performance degrades significantly when a fully digital single-baud-rate clock recovery loop is used. In contrast, the bit error rate curve of the FTN signal recovered using a fully digital single-baud-rate clock is very close to that without sampling frequency offset. This confirms that the digital interpolation filter under single-baud-rate conditions can reconstruct the FTN signal at the optimal sampling time.

[0042] like Figure 7 As shown, the relationship between the bit error rate (BER) of the FTN signal and the received optical power under different sampling frequency offsets is presented. The experimental results show that, despite the sampling frequency offset varying from 15ppm to 60ppm, this all-digital single-baud-rate clock recovery loop can effectively eliminate timing errors; its BER curves almost overlap and approach the condition of no timing error.

[0043] like Figure 8 As shown, the bit error rate (BER) curves are presented under different oversampling rates. The BER performance of uncompressed 16QAM and FTN signals under different oversampling conditions is further discussed when the received optical power is -14 dBm. Figure 8 As shown, for uncompressed signals, a significant performance improvement can be observed when the oversampling rate increases from 1 to 1.2, indicating that oversampling is essential for digital interpolation filters. However, by employing FTN technology, the bit error rate curve remains flat under different oversampling conditions, demonstrating that the all-digital single-baud-rate clock recovery loop can effectively solve the clock asynchrony problem with the assistance of FTN technology.

[0044] In the specific implementation of the above embodiments, the technical features can be combined in any non-contradictory way. For the sake of brevity, not all possible combinations of the above technical features are described. However, as long as the combination of these technical features is not contradictory, it should be considered to be within the scope of this specification.

[0045] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively describe all embodiments here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A fully digital single-baud-rate clock recovery method based on FTN assistance, characterized in that, Includes the following steps: S1. Map the generated pseudo-random bit sequence to QAM symbols, and perform THP precoding on the QAM symbols; S2. The THP precoded signal is compressed and shaped using an FTN root raised cosine filter. S3. Resample the signal to one baud rate and perform dispersion compensation; S4. Timing synchronization is performed through a fully digital single-baud-rate clock recovery loop based on the 3Sign-TED algorithm, and clock recovery is completed at single baud rate.

2. The FTN-assisted all-digital single-baud-rate clock recovery method according to claim 1, characterized in that, In step S1, the THP precoding of the QAM symbols includes: （1） （2） In the formula, Represents the original data. The results after introducing ISI, This is the final output after THP precoding. M The modulation order, These are the tap coefficients of the feedback equalizer. N This refers to the tap length; Based on the above formulas (1) and (2), the output of THP precoding is expressed as: （3） In the formula, n Represents an integer.

3. The FTN-assisted all-digital single-baud-rate clock recovery method according to claim 2, characterized in that, In step S4, the all-digital clock recovery loop includes an interpolation filter, a timing error detector, a loop filter, and a numerically controlled oscillator; the timing error detector uses sign judgment to replace numerical multiplication when calculating the timing error. After the timing error is calculated by the timing error detector, the timing error is input into the loop filter for noise filtering to obtain the control word; then the control word is used to control the numerically controlled oscillator, and the fractional interval is calculated from the output of the numerically controlled oscillator and the control word; the received signal is interpolated in the interpolation filter using the integer marking of the sign and the calculated fractional interval, thereby calculating the data with correct timing.

4. The FTN-assisted all-digital single-baud-rate clock recovery method according to claim 3, characterized in that, The timing error detector calculates the timing error using the following method. : （4） In the formula, and These are the real and imaginary parts of the received signal, respectively. k Indicates a time index. This indicates the length of the data block used in each calculation of the timing error. This indicates symbolic operation.

5. A fully digital single-baud-rate clock recovery system based on FTN assistance, characterized in that, include: THP precoding module: used to map the generated pseudo-random bit sequence to QAM symbols and perform THP precoding on the QAM symbols; FTN spectrum compression module: used to perform spectrum compression and shaping on the pre-coded signal using FTN raised cosine filters; Dispersion compensation module: used to perform dispersion compensation on signals resampled to one baud rate; All-digital clock recovery module: Used for timing synchronization through an all-digital single-baud-rate clock recovery loop based on the 3Sign-TED algorithm, and completes clock recovery at single baud rate.

6. The FTN-assisted all-digital single-baud-rate clock recovery system according to claim 5, characterized in that, The THP precoding module performs THP precoding in the following manner: （1） （2） In the formula, Represents the original data. The results after introducing ISI, This is the final output after THP precoding. M The modulation order, These are the tap coefficients of the feedback equalizer. N This refers to the tap length; Based on the above formulas (1) and (2), the output of THP precoding is expressed as: （3） In the formula, n Represents an integer.

7. The FTN-assisted all-digital single-baud-rate clock recovery system according to claim 6, characterized in that, In the all-digital clock recovery module, the all-digital clock recovery loop includes an interpolation filter, a timing error detector, a loop filter, and a numerically controlled oscillator; the timing error detector uses sign judgment to replace numerical multiplication operations when calculating the timing error. After the timing error is calculated by the timing error detector, the timing error is input into the loop filter for noise filtering to obtain the control word; then the control word is used to control the numerically controlled oscillator, and the fractional interval is calculated from the output of the numerically controlled oscillator and the control word; the received signal is interpolated in the interpolation filter using the integer marking of the sign and the calculated fractional interval, thereby calculating the data with correct timing.

8. The FTN-assisted all-digital single-baud-rate clock recovery system according to claim 7, characterized in that, The timing error detector extracts timing errors based on the 3Sign-TED algorithm. : （4） In the formula, and These are the real and imaginary parts of the received signal, respectively. k Indicates a time index. This indicates the length of the data block used in each calculation of the timing error. This indicates symbolic operation.

9. An optical communication method, characterized in that, include: Transmitter digital signal processing: First, the pseudo-random bit sequence is mapped to QAM symbols. Then, the QAM is precoded using the THP precoding method described in claim 2. Next, the precoded signal is spectral compressed and shaped using an FTN root raised cosine filter. Finally, the signal is resampled. Digital signal processing at the receiver: First, the signal is resampled to single baud rate. Then, after dispersion compensation, a fully digital single baud rate clock recovery loop based on the 3Sign-TED algorithm is used for timing synchronization. Subsequently, after synchronization and frequency offset compensation, an equalizer combined with phase noise tracking is used to achieve equalization and phase noise compensation. Finally, the equalized signal is subjected to modulo operation to achieve THP decoding, and the bit error rate is calculated.

10. The optical communication method according to claim 9, characterized in that, The equalizer combined with phase noise tracking performs the equalization process including: （5） In the formula, , and , These represent the input and output of the equalizer, respectively. , , , These represent the tap coefficients of the equalizer. p The phase factor representing a single tap; The update process for tap coefficients and phase factors includes: （6） （7） In the formula, and These represent the step sizes for updating the equalizer tap coefficients and phase factors, respectively. * indicates the conjugate operation. and The error signals representing X-polarization and Y-polarization are calculated as follows: （8） In the formula, and This represents the standard extended signal after the ideal training sequence or decision.

Images