A carrier synchronization device suitable for deep space communication

Abstract

The application discloses a carrier synchronization device suitable for deep space communication and relates to communication signal receiving and demodulation technology. The device is composed of AD, two-stage digital down-conversion unit, half-band filtering, digital resampling, matching filtering, coherent / non-coherent digital AGC, carrier phase error compensation, equalization, carrier / timing error calculation, integral cleaning, low-pass filtering, two-stage Q square unit, two-stage Doppler frequency offset estimation unit, two-stage control word mapping unit, carrier synchronization automatic reset, loop filtering and control word conversion unit. The device adopts two-stage carrier phase error feedback structure, compensates to the phase compensation unit and the digital down-conversion unit respectively, improves loop bandwidth and reduces filtering damage; adopts two-stage Doppler frequency offset estimation and compensation in stages, improves frequency offset adaptation range and estimation precision. The application is suitable for high-reliability carrier synchronization under the condition of multiple modulation systems and symbol rates in deep space communication.

Description

Technical Field

[0001] This invention relates to the field of communication and data transmission, and is particularly applicable to demodulation signal processing and carrier synchronization used as receiving devices in communication systems. Background Technology

[0002] In deep space communication applications, carrier synchronization devices need to meet the carrier synchronization requirements of signals with different symbol rates and multiple modulation schemes. As the signal transmission distance increases, the signal transmission path itself or the signal relay transmission process will affect the instantaneous fluctuation of the signal carrier phase, thereby affecting the carrier synchronization effect.

[0003] In satellite-to-ground communication, carrier synchronization mainly consists of three parts: carrier phase synchronization, carrier Doppler frequency offset estimation, and carrier synchronization status determination and automatic reset. For traditional satellite-to-ground communication, there are three main methods for achieving carrier phase synchronization: The first method involves the device performing analog or digital quadrature downconversion by real-time feedback of the input carrier phase error to achieve carrier phase synchronization. This carrier phase error is generated through signal processing after filtering and timing synchronization at various stages. This method achieves carrier phase synchronization at the initial stage of signal demodulation, so subsequent filters in the demodulation process are not damaged by Doppler frequency offset in the signal itself, and the noise immunity of the extracted carrier phase error is also good. However, this method introduces a significant time delay in the carrier synchronization loop feedback process, resulting in a smaller loop bandwidth and ultimately reducing the device's adaptability range for carrier frequency offset change rate during carrier phase tracking. Therefore, during signal generation and transmission, large instantaneous fluctuations in the carrier phase can cause the carrier phase synchronization loop to lose lock, affecting the device's operational stability. Considering the above, this method is suitable for applications with low symbol rates under various modulation schemes.

[0004] The second method involves the device first performing carrier phase error compensation calculations on the signal after filtering and timing synchronization at each stage, then calculating the carrier phase error on the processed signal, and finally directly feeding the generated carrier phase error value back to the carrier phase error compensation unit. This method utilizes the real-time generated carrier phase error to directly achieve carrier phase synchronization through the carrier phase error compensation loop. Therefore, the processing delay of the corresponding carrier synchronization loop is relatively small, effectively improving the loop bandwidth of the device's carrier phase synchronization. Ultimately, this increases the adaptability range of the carrier frequency offset rate during carrier phase tracking. In addition, this method also improves the device's noise immunity and reduces the carrier synchronization lock-in time. However, when the signal has a large Doppler frequency offset, the filters at each stage of demodulation processing will damage the signal itself, and the lower the symbol rate, the more obvious the damage, leading to a decrease in signal reception quality or even signal reception failure. Considering the above, this method is suitable for applications with high symbol rates under various modulation schemes.

[0005] The third method involves the device first performing carrier phase synchronization, followed by various stages of filtering and timing synchronization. This method completes carrier phase synchronization at the initial stage of signal demodulation, preventing damage to subsequent filters due to Doppler frequency offset. Furthermore, the carrier phase synchronization loop processing delay is relatively small, effectively increasing the loop bandwidth and ultimately improving the device's adaptability to carrier frequency offset changes during carrier phase tracking. However, this method extracts carrier phase errors before timing synchronization. When the transmitted signal uses a high-order modulation scheme, the extraction process fails to effectively utilize the peak points of the transmitted symbols, resulting in poor carrier phase error extraction performance. Therefore, this method is suitable for applications with low-order modulation schemes and varying symbol rates.

[0006] For traditional satellite-to-ground communication, there are two main methods for carrier Doppler frequency offset estimation: The first method involves directly estimating the carrier Doppler frequency offset of the down-converted signal before timing synchronization and feeding the estimated value back to the down-conversion unit, thus achieving carrier Doppler frequency offset compensation. This method completes carrier Doppler frequency offset estimation and compensation in the early stages of signal demodulation, preventing damage to subsequent filters due to the initial Doppler frequency offset of the signal itself. Furthermore, for signals with low symbol rates, this method can effectively estimate larger Doppler frequency offset values, thereby improving the receiving performance of the device. However, because this method estimates the carrier Doppler frequency offset before timing synchronization, when the transmitted signal uses a high-order modulation scheme, the extraction process does not effectively utilize the peak points of the transmitted symbols, leading to interference from various spurious peaks and potentially causing errors in the estimation results. Considering all these factors, this method is suitable for applications with low-order modulation schemes and various symbol rates.

[0007] The second method involves estimating the carrier Doppler frequency offset using the peak point of the transmitted symbol after the signal has undergone various stages of filtering and timing synchronization. This Doppler frequency offset estimate is then fed back to the down-conversion unit or the carrier phase error compensation unit, thereby achieving carrier Doppler frequency offset compensation. However, when the symbol rate of the processed signal is low, if the signal itself has a large initial Doppler frequency offset, the various filtering processes before Doppler frequency offset estimation will damage the signal itself, reducing the accuracy of the Doppler frequency offset estimation and consequently reducing the device performance. Considering all these factors, this method is suitable for high symbol rate applications under various modulation schemes.

[0008] For traditional satellite-to-ground communication, the carrier Doppler frequency offset estimate after carrier synchronization is typically used to determine the current carrier synchronization status. Therefore, the carrier synchronization status determination module and the carrier Doppler frequency offset estimation module are time-division multiplexed. Before carrier synchronization, the frequency offset output by the carrier Doppler frequency offset estimation module is not zero; the estimated frequency offset is used for carrier Doppler frequency offset compensation. After carrier synchronization, the frequency offset output by the carrier Doppler frequency offset estimation module should be zero. If the frequency offset output by the carrier Doppler frequency offset estimation module is not zero after carrier synchronization, it indicates that the carrier synchronization state has become a lost-lock state. Using this module multiplexing method can effectively improve the efficiency of computing resource utilization, but it cannot simultaneously reduce the false alarm probability during carrier synchronization lock determination while effectively reducing the carrier Doppler frequency offset estimation computation time, thus reducing the effectiveness of the device. Summary of the Invention

[0009] The purpose of this invention is to overcome the shortcomings of the aforementioned background technology and provide a carrier synchronization device suitable for deep space communication. This invention also features high reliability, high stability, and low implementation complexity.

[0010] The objective of this invention is achieved as follows: A carrier synchronization device suitable for deep space communication. Analog-to-digital converter (1), first digital down-conversion unit (2-1), second digital down-conversion unit (2-2), half-band filter unit (3), digital resampling unit (4), matched filter unit (5), coherent digital automatic gain control unit (6), carrier phase error compensation unit (7), equalization unit (8), carrier phase error calculation unit (9), timing error calculation unit (10), integral cleaning unit (11), low-pass filter unit (12), incoherent digital automatic gain control unit (13), first Q-power unit (14-1), second Q-power unit (14-2), first Doppler frequency offset estimation unit (15-1), second Doppler frequency offset estimation unit (15-2), first control word mapping unit (16-1), second control word mapping unit (16-2), carrier synchronization automatic reset unit (17), loop filter unit (18), and control word conversion unit (19); The analog-to-digital converter (1) is used to perform analog-to-digital conversion on the input intermediate frequency analog signal to generate a digital intermediate frequency signal, and outputs the digital intermediate frequency signal to the first digital down-conversion unit (2-1) and the second digital down-conversion unit (2-2) respectively. The first digital downconversion unit (2-1) performs digital downconversion processing on the digital intermediate frequency signal to generate a first I / Q quadrature baseband signal; The integral cleaning unit (11), low-pass filtering unit (12), incoherent digital automatic gain control unit (13), first Q-power unit (14-1), first Doppler frequency offset estimation unit (15-1) and first control word mapping unit (16-1) process the first I / Q quadrature baseband signal in sequence to generate the first NCO accumulation step signal and output it to the second digital down-conversion unit (2-2). The second digital downconversion unit (2-2) receives the first NCO accumulation step signal and the second NCO accumulation step signal output by the control word conversion unit (19), and adds them to the internal initial NCO accumulation step value to generate an NCO accumulation step control signal. The NCO accumulation step control signal is used to perform digital downconversion processing on the digital intermediate frequency signal to generate a second I / Q quadrature baseband signal. The half-band filtering unit (3), digital resampling unit (4), matched filtering unit (5), and coherent digital automatic gain control unit (6) sequentially process the second I / Q quadrature baseband signal and output the processed signal to the carrier phase error compensation unit (7). The carrier phase error compensation unit (7) performs carrier phase error compensation processing on the input signal and outputs the compensated I / Q quadrature baseband signal. The compensated I / Q quadrature baseband signal is output to the carrier phase error calculation unit (9), the timing error calculation unit (10), the equalization unit (8), and the second Q power unit (14-2). The carrier phase error calculation unit (9) calculates the carrier phase error according to the input modulation scheme setting parameters and outputs it to the loop filter unit (18). The timing error calculation unit (10) calculates the timing error and outputs it to the digital resampling unit (4). The equalization unit (8) performs equalization processing and outputs the result for use by other modules; The second Q-power unit (14-2), the second Doppler frequency offset estimation unit (15-2), and the second control word mapping unit (16-2) process the compensated I / Q quadrature baseband signal in sequence to generate the third NCO accumulation step signal and output it to the carrier phase error compensation unit (7). The loop filter unit (18) performs split processing on the input carrier phase error signal to generate an integral term carrier phase error and a direct term carrier phase error. A portion of the integral term carrier phase error is output to the control word conversion unit (19), and the other portion is added to the direct term carrier phase error and output to the carrier phase error compensation unit (7). The control word conversion unit (19) performs differential operation on the integral term carrier phase error and converts it into the second NCO accumulation step signal, which is then output to the second digital downconversion unit (2-2). The carrier synchronization automatic reset unit (17) receives the Doppler frequency offset judgment lock signals output by the first Doppler frequency offset estimation unit (15-1) and the second Doppler frequency offset estimation unit (15-2), respectively. It generates a carrier synchronization automatic reset pulse signal and a carrier synchronization indication signal according to the preset judgment logic. The carrier synchronization automatic reset pulse signal is output to the loop filter unit (18), the first Doppler frequency offset estimation unit (15-1) and the second Doppler frequency offset estimation unit (15-2) respectively. The carrier synchronization indication signal is output to the first Doppler frequency offset estimation unit (15-1) and the second Doppler frequency offset estimation unit (15-2) respectively and is used as the device output.

[0011] Furthermore, the first Doppler frequency offset estimation unit (15-1) and the second Doppler frequency offset estimation unit (15-2) both include: an FFT unit (20), a modulus calculation unit (21), a delay unit (22), an addition unit (23), a RAM unit (24), an output control unit (25), a loop counting unit (26), a circular convolution unit (27), a maximum value search unit (28), and a signal receiving and holding unit (29). The FFT unit (20) performs buffering and FFT operation on the input I / Q quadrature baseband signal according to the FFT period operation control pulse output by the cycle counting unit (26), and outputs the complex signal after operation to the modulus calculation unit (21). The modulus calculation unit (21) performs modulus calculation on the complex signal to generate a modulus signal and a corresponding modulus position number; The RAM unit (24) uses the modulus position number as the read address and outputs the cached accumulated modulus signal to the addition unit (23). The delay unit (22) delays the modulus signal and outputs it to the addition unit (23). The addition unit (23) performs an addition operation on the accumulated modulus signal output by the RAM unit (24) and the modulus signal output by the delay unit (22) to generate a new accumulated modulus signal and the corresponding accumulated modulus position number, and writes them into the RAM unit (24) and outputs them to the output control unit (25). The output control unit (25) outputs the latest modulus accumulation signal to the circular convolution unit (27) according to the FFT period output control pulse output by the circular counting unit (26). The circular convolution unit (27) performs a circular convolution operation on the input modulus accumulation signal and extracts the effective signal, which is then output to the maximum value search unit (28). The maximum value search unit (28) searches for the maximum value in a frame of valid modulus signals, outputs the receiving number corresponding to the maximum value, and outputs the receiving number as a Doppler frequency offset judgment lock signal to the carrier synchronization automatic reset unit (17) and to the signal receiving and holding unit (29). The signal receiving and holding unit (29) outputs the first received maximum modulus receiving number as a Doppler frequency offset compensation signal according to the carrier synchronization automatic reset pulse signal.

[0012] Furthermore, the circular convolution unit (27) performs a circular convolution operation on the input modulus accumulation signal in the form of a second-order low-pass filter, and truncates the output signal starting from the second bit after the operation, with the truncation length being equal to the length of the input signal.

[0013] Furthermore, the cycle counting unit (26) dynamically adjusts the internal cycle counter setting value according to the carrier synchronization indication signal: when the carrier synchronization indication signal is high, the setting value is increased to increase the generation period of the FFT period operation control pulse and the FFT period output control pulse; when the carrier synchronization indication signal is low, the setting value is decreased to decrease the generation period.

[0014] Furthermore, the determination logic of the carrier synchronization automatic reset unit (17) is as follows: In the initial state or after reset, the Doppler frequency offset judgment and locking signal output by the second Doppler frequency offset estimation unit (15-2) is periodically sampled first; When three consecutive sampling cycles indicate that the current Doppler frequency offset is not 0, the carrier synchronization automatic reset pulse signal is output. After outputting the reset pulse, the detection of the second Doppler frequency offset estimation unit (15-2) is stopped, and the Doppler frequency offset judgment lock signal output by the first Doppler frequency offset estimation unit (15-1) is detected instead; When the first valid Doppler frequency offset estimation unit (15-1) outputs the first valid Doppler frequency offset judgment lock signal, the detection of the first Doppler frequency offset estimation unit (15-1) is stopped, and the periodic sampling and detection of the second Doppler frequency offset estimation unit (15-2) is resumed. When the Doppler frequency offset determination lock signal output by the second Doppler frequency offset estimation unit (15-2) indicates that the current Doppler frequency offset is 0, the carrier synchronization is determined to be locked, and the carrier synchronization indication signal is high level; When the Doppler frequency offset detection lock signal detected in three consecutive sampling cycles indicates that the Doppler frequency offset is not 0, the carrier synchronization automatic reset pulse signal is output again, and the carrier synchronization indicator signal becomes low.

[0015] Furthermore, after receiving the carrier synchronization automatic reset pulse signal, the loop filter unit (18) forcibly resets the accumulated value used to generate the integral term carrier phase error to the initial value of 0.

[0016] Furthermore, the first Q-power unit (14-1) and the second Q-power unit (14-2) determine the exponent Q of the Q-power operation according to the input modulation scheme setting parameters.

[0017] Furthermore, the first control word mapping unit (16-1) and the second control word mapping unit (16-2) convert the corresponding Doppler frequency offset compensation signal into the corresponding NCO accumulating step signal according to the input modulation scheme setting parameters.

[0018] Compared with the prior art, the present invention has the following advantages: 1. This device employs a two-stage carrier phase error feedback and processing structure to achieve carrier tracking of the received signal. The first-stage carrier phase error is fed back to the carrier phase error compensation unit for processing, reducing the processing delay of the carrier synchronization loop and thus increasing the bandwidth of the carrier synchronization loop. This, in turn, improves the carrier rate of change adaptation range of the device during carrier tracking. The second-stage carrier phase error is fed back to the digital down-conversion unit for processing, reducing the carrier frequency offset of the signal itself during low-pass filtering and matched filtering. This reduces the damage to the received signal caused by each stage of the filter and further improves the carrier frequency offset adaptation range of the device during carrier tracking.

[0019] 2. This device employs a two-stage carrier Doppler frequency offset estimation and compensation structure to achieve carrier acquisition of the received signal. In the initial signal reception stage, the first-stage carrier Doppler frequency offset estimation result is directly obtained from the digital intermediate frequency signal output by the AD converter through processing. This eliminates the problem of carrier acquisition failure caused by damage to the signal carrying the initial Doppler frequency offset during each stage of demodulation processing, thereby improving the Doppler frequency offset adaptability range of the device. The second-stage carrier Doppler frequency offset estimation and compensation process is performed after the signal has completed each stage of filtering and timing synchronization. The above processing improves the accuracy of carrier Doppler frequency offset estimation and enhances its noise immunity.

[0020] 3. In performing two-stage carrier Doppler frequency offset estimation, this device employs multi-stage equivalent filtering to improve the noise immunity of the Doppler frequency offset estimation. Specifically, it first uses FFT operations to replace filter bank operations, dividing the signal into frequency sub-bands and performing sub-band filtering. Then, it utilizes a RAM module to accumulate the signals within each sub-band, thereby achieving equivalent low-pass filtering. Furthermore, this device uses circular convolution to accumulate the magnitudes of adjacent subcarriers, reducing the amplitude drop of the main peak caused by the main peak expansion in carrier Doppler frequency offset estimation, further improving the noise immunity of the carrier Doppler frequency offset estimation.

[0021] 4. This device optimizes the two-stage carrier Doppler frequency offset estimation process through a carrier synchronization automatic reset unit. That is, by dynamically adjusting the internal working period and internal accumulation period of carrier Doppler frequency offset estimation through the carrier synchronization status, it reduces the carrier synchronization processing time and the probability of carrier lock-up false alarm caused by fluctuations such as signal phase noise after carrier synchronization, thereby improving the working stability of the device. Attached Figure Description

[0022] Figure 1 This is a block diagram illustrating the principle of the present invention.

[0023] Figure 2 This is a circuit diagram of the Doppler frequency offset estimation unit of the present invention. Detailed Implementation

[0024] Reference Figures 1 to 2 The present invention comprises an AD (1), a digital downconversion unit (2-1) and a digital downconversion unit (2-2), a half-band filter unit (3), a digital resampling unit (4), a matched filter unit (5), a coherent digital AGC unit (6), a carrier phase error compensation unit (7), an equalization unit (8), a carrier phase error calculation unit (9), a timing error calculation unit (10), an integral cleaning unit (11), a low-pass filter unit (12), an incoherent digital AGC unit (13), a Q-power unit (14-1) and a Q-power unit (14-2), a Doppler frequency offset estimation unit (15-1) and a Doppler frequency offset estimation unit (15-2), a control word mapping unit (16-1) and a control word mapping unit (16-2), a carrier synchronization automatic reset unit (17), a loop filter unit (18), and a control word conversion unit (19).

[0025] The device first performs analog-to-digital conversion on the input intermediate frequency analog signal using AD (1), generates and outputs a digital intermediate frequency signal, and the digital intermediate frequency signal output by AD (1) is then transmitted to the digital downconversion unit (2-1) and the digital downconversion unit (2-2) respectively via a splitter. The digital downconversion unit (2-1) performs digital downconversion processing on the digital intermediate frequency signal output by AD (1) to generate and output I / Q quadrature baseband signal; The integral cleaning unit (11) performs integral cleaning processing on the I / Q quadrature baseband signal output by the digital downconverter unit (2-1) and transmits the processed signal to the low-pass filter unit (12). The low-pass filter unit (12) performs low-pass filtering on the input I / Q quadrature baseband signal and transmits the processed signal to the incoherent digital AGC unit (13); The incoherent digital AGC unit (13) performs power adjustment on the input I / Q quadrature baseband signal and transmits the processed signal to the Q power unit (14-1). The Q-power unit (14-1) performs Q-power operations on the input I / Q quadrature baseband signal according to the input modulation scheme setting parameters, and transmits the calculated signal to the Doppler frequency offset estimation unit (15-1). The Doppler frequency offset estimation unit (15-1) processes the input I / Q quadrature baseband signal to generate a Doppler frequency offset compensation signal and a Doppler frequency offset judgment lock signal, and transmits the generated Doppler frequency offset compensation signal and Doppler frequency offset judgment lock signal to the control word mapping unit (16-1) and the carrier synchronization automatic reset unit (17), respectively. The control word mapping unit (16-1) converts the input Doppler frequency offset compensation signal into an NCO accumulating step signal according to the input modulation scheme setting parameters, and transmits the generated NCO accumulating step signal to the digital downconverter unit (2-2). The digital downconverter unit (2-2) receives the NCO accumulation step signal output by the control word mapping unit (16-1) and the control word conversion unit (19), respectively, and performs an addition operation with the initial NCO accumulation step value inside to generate the NCO accumulation step control signal. The digital downconverter unit (2-2) uses the generated NCO accumulation step control signal to perform digital downconversion processing on the digital intermediate frequency signal output by AD (1) to generate and output the I / Q quadrature baseband signal. The half-band filtering unit (3) performs half-band low-pass filtering on the I / Q quadrature baseband signal output by the digital down-conversion unit (2-2) and transmits the processed signal to the digital resampling unit (4). The digital resampling unit (4) receives the timing error signal output by the timing error calculation unit (10), performs digital resampling processing on the input I / Q quadrature baseband signal, and transmits the processed signal to the matched filter unit (5). The matched filtering unit (5) performs matched filtering on the input I / Q quadrature baseband signal and transmits the processed signal to the coherent digital AGC unit (6). The coherent digital AGC unit (6) performs power adjustment on the input I / Q quadrature baseband signal and transmits the processed signal to the carrier phase error compensation unit (7). The carrier phase error compensation unit (7) performs carrier phase error compensation processing on the input I / Q quadrature baseband signal and outputs the processed signal. The I / Q quadrature baseband signal output by the carrier phase error compensation unit (7) is then transmitted to the carrier phase error calculation unit (9), timing error calculation unit (10), equalization unit (8) and Q power unit (14-2) respectively via a splitter. Among them, the carrier phase error calculation unit (9) calculates the carrier phase error of the input I / Q quadrature baseband signal according to the input modulation scheme setting parameters, and transmits the calculated carrier phase error signal to the loop filter unit (18); the timing error calculation unit (10) calculates the timing error of the input I / Q quadrature baseband signal, and transmits the calculated timing error signal to the digital resampling unit (4); the equalization unit (8) performs equalization processing on the input I / Q quadrature baseband signal, and outputs the processed signal for use by other modules; the Q-power unit (14-2) performs Q-power operation on the input I / Q quadrature baseband signal according to the input modulation scheme setting parameters, and transmits the calculated signal to the Doppler frequency offset estimation unit (15-2). The Doppler frequency offset estimation unit (15-2) processes the input I / Q quadrature baseband signal to generate a Doppler frequency offset compensation signal and a Doppler frequency offset judgment lock signal, and transmits the generated Doppler frequency offset compensation signal and Doppler frequency offset judgment lock signal to the control word mapping unit (16-2) and the carrier synchronization automatic reset unit (17), respectively. The control word mapping unit (16-2) converts the input Doppler frequency offset compensation signal into an NCO accumulating step signal according to the input modulation scheme setting parameters, and transmits the generated NCO accumulating step signal to the carrier phase error compensation unit (7). The loop filter unit (18) internally splits the input carrier phase error signal to generate two carrier phase error signals. The first signal is weighted and accumulated to generate an integral term carrier phase error, and the second signal is weighted to generate a direct term carrier phase error. The loop filter unit (18) splits the internally generated integral term carrier phase error signal to generate two sets of signals. The first set of signals is output to the control word conversion unit (19), and the second set of signals is added to the corresponding direct term carrier phase error. The calculated signal is then transmitted to the carrier phase error compensation unit (7). The wave unit (18) receives the carrier synchronization automatic reset pulse signal output by the carrier synchronization automatic reset unit (17). When the loop filter unit (18) receives the valid carrier synchronization automatic reset pulse signal, the loop filter unit (18) forces the accumulated value used to generate the integral term carrier phase error to the initial value 0. The control word conversion unit (19) performs differential operation on the integral term carrier phase error output by the loop filter unit (18), and then converts the operation signal into an NCO accumulation step signal, and transmits the generated NCO accumulation step signal to the digital downconverter unit (2-2). The carrier synchronization automatic reset unit (17) first periodically samples the Doppler frequency offset judgment lock signal output by the Doppler frequency offset estimation unit (15-2). When the Doppler frequency offset judgment lock signal obtained in three consecutive sampling periods indicates that the current Doppler frequency offset is not 0, the carrier synchronization automatic reset pulse signal is output. After the carrier synchronization automatic reset unit (17) outputs the carrier synchronization automatic reset pulse signal, the carrier synchronization automatic reset unit (17) stops detecting the Doppler frequency offset judgment lock signal output by the Doppler frequency offset estimation unit (15-2) and starts detecting the Doppler frequency offset judgment lock signal output by the Doppler frequency offset estimation unit (15-1). When the carrier synchronization automatic reset unit (17) detects the first valid Doppler frequency offset judgment lock signal output by the Doppler frequency offset estimation unit (15-1), the carrier synchronization automatic reset unit (17) stops detecting the Doppler frequency offset judgment lock signal output by the Doppler frequency offset estimation unit (15-1). 5-1) The output Doppler frequency offset judgment lock signal is detected, and the Doppler frequency offset judgment lock signal output by the Doppler frequency offset estimation unit (15-2) is periodically sampled and detected. When the Doppler frequency offset judgment lock signal output by the Doppler frequency offset estimation unit (15-2) indicates that the current Doppler frequency offset is 0, it is determined that the current carrier synchronization is locked. At this time, the carrier synchronization indication signal output by the carrier synchronization automatic reset unit (17) is high level. When the Doppler frequency offset judgment lock signal obtained by three consecutive sampling cycles indicates that the current Doppler frequency offset is not 0, the carrier synchronization automatic reset pulse signal is output, and the carrier synchronization indication signal output is low level. The carrier synchronization automatic reset unit (17) transmits the generated carrier synchronization automatic reset pulse signal to the loop filter unit (18), the Doppler frequency offset estimation unit (15-1), and the Doppler frequency offset estimation unit (15-2) through the branch circuit. The carrier synchronization automatic reset unit (17) transmits the generated carrier synchronization indication signal to the Doppler frequency offset estimation unit (15-1) and the Doppler frequency offset estimation unit (15-2) respectively via a split path. At the same time, it is used as the device output for other modules. The carrier synchronization automatic reset unit (17) continuously detects and processes the carrier synchronization status according to the above principle.

[0026] In the example, the digital downconversion unit (2-1) and digital downconversion unit (2-2), half-band filter unit (3), digital resampling unit (4), matched filter unit (5), coherent digital AGC unit (6), carrier phase error compensation unit (7), equalization unit (8), carrier phase error calculation unit (9), timing error calculation unit (10), integral cleaning unit (11), low-pass filter unit (12), incoherent digital AGC unit (13), Q-power unit (14-1) and Q-power unit (14-2), Doppler frequency offset estimation unit (15-1) and Doppler frequency offset estimation unit (15-2), control word mapping unit (16-1) and control word mapping unit (16-2), carrier synchronization automatic reset unit (17), loop filter unit (18) and control word conversion unit (19) are all implemented using FPGA.

[0027] Figure 2 This is a block diagram illustrating the principle of a Doppler frequency offset estimation unit. An example is shown below. Figure 2 The connecting lines include a Doppler frequency offset estimation unit (15-1) comprising an FFT unit (20), a modulus calculation unit (21), a delay unit (22), an addition unit (23), a RAM unit (24), an output control unit (25), a loop counting unit (26), a loop convolution unit (27), a maximum value search unit (28), and a signal receiving and holding unit (29).

[0028] The FFT unit (20) receives the I / Q quadrature baseband signal output by the Q power unit (14-1) and the FFT period operation control pulse output by the cycle counting unit (26). When the FFT unit (20) receives a valid FFT period operation control pulse, it continuously buffers the input I / Q quadrature baseband signal according to the FFT operation data length and performs FFT operation on the buffered signal. The FFT unit (20) transmits the complex signal after FFT operation to the modulus calculation unit (21). Modulus calculation unit (21) performs modulus calculation on the input complex signal, generates and outputs the modulus signal, and counts the complex signal to generate a modulus position number. The RAM unit (24) receives the modulus position number output by the modulus calculation unit (21), and uses the received modulus position number as the data read address to read the corresponding cached data in the RAM unit (24), and transmits the read signal to the addition unit (23). The delay unit (22) receives the modulus signal output by the modulus calculation unit (21), performs delay processing on the input signal according to the data reading time period of the RAM unit (24), and transmits the delayed signal to the addition unit (23). The addition unit (23) performs addition operations on the data output by the RAM unit (24) and the modulus signal output by the delay unit, and counts the modulus signal being operated on, generating and outputting the modulus accumulation signal and the accumulated modulus position number respectively. The modulus accumulation signal output by the addition unit (23) is then transmitted to the RAM unit (24) and the output control unit (25) via a branch. The RAM unit (24) uses the position number of the input accumulated modulus value as the address and uses the corresponding input modulus value accumulation signal as new cache data for corresponding cache. The output control unit (25) receives the FFT periodic output control pulse from the cyclic calculation unit (26). When the output control unit (25) receives a valid FFT periodic output control pulse, it outputs the latest received modulus accumulation signal. After the output control unit (25) outputs a valid signal, the cyclic convolution unit (27) performs cyclic convolution on the input modulus accumulation signal in the form of a second-order low-pass filter. According to the length of the input signal, starting from the second bit of the output signal after the operation, the cyclic convolution unit (27) truncates the output signal after the operation. The cyclic convolution unit (27) transmits the truncated modulus signal to the maximum value search unit (28). The maximum value search unit (28) receives the cyclic convolution unit's signal in sequence. (27) Output a frame of valid modulus signal and determine the reception number of each received data through the data receiving counter. The maximum value search unit (28) compares the received modulus signals in sequence to determine the maximum value of the received signal and outputs the reception number corresponding to the maximum value. When there are multiple maximum values ​​with the same value in the frame of valid modulus signal received by the maximum value search unit (28), the reception number corresponding to the first maximum value is output. The maximum modulus reception number output by the maximum value search unit (28) is then split into two signals. The first signal is transmitted to the signal receiving and holding unit (29), and the second signal is transmitted to the carrier synchronization automatic reset unit (17) as a Doppler frequency offset judgment lock signal. The signal receiving and holding unit (29) receives the carrier synchronization automatic reset pulse signal output by the carrier synchronization automatic reset unit (17). When the signal receiving and holding unit (29) receives a valid carrier synchronization automatic reset pulse signal, the signal receiving and holding unit (29) outputs the maximum modulus received number received for the first time after receiving the carrier synchronization automatic reset pulse signal as a Doppler frequency offset compensation signal to the control word mapping unit (16-1), and keeps the above output state unchanged. The loop counter unit (26) dynamically adjusts the internal loop counter setting value according to the carrier synchronization indication signal output by the carrier synchronization automatic reset unit (17). When the carrier synchronization indication signal is high, the internal loop counter setting value is increased, thereby increasing the period of generating and outputting the FFT period operation control pulse and the FFT period output control pulse. When the carrier synchronization indication signal is low, the internal loop counter setting value is decreased, thereby decreasing the period of generating and outputting the FFT period operation control pulse and the FFT period output control pulse.

[0029] The basic working principle of this invention is as follows: When a carrier synchronization device suitable for deep space communication is working, the AD (1) first performs analog-to-digital conversion on the input intermediate frequency analog signal to generate and output a digital intermediate frequency signal. The digital intermediate frequency signal output by the AD (1) is then transmitted to the digital downconversion unit (2-1) and the digital downconversion unit (2-2) respectively through a branch. The digital downconversion unit (2-1) performs digital downconversion processing on the digital intermediate frequency signal output by the AD (1) to generate and output an I / Q quadrature baseband signal. The integration cleaning unit (11) performs integration cleaning processing on the I / Q quadrature baseband signal output by the digital downconversion unit (2-1) and transmits the processed signal to the low-pass filter unit (12). The low-pass filter unit (12) performs low-pass filtering processing on the input I / Q quadrature baseband signal and transmits the processed signal to the incoherent digital AGC unit (13).

[0030] The incoherent digital AGC unit (13) performs power adjustment on the input I / Q quadrature baseband signal and transmits the processed signal to the Q-power unit (14-1). The Q-power unit (14-1) performs Q-power operation on the input I / Q quadrature baseband signal according to the input modulation scheme setting parameters and transmits the processed signal to the Doppler frequency offset estimation unit (15-1). The Doppler frequency offset estimation unit (15-1) processes the input I / Q quadrature baseband signal to generate a Doppler frequency offset compensation signal and a Doppler frequency offset judgment lock signal, and transmits the generated Doppler frequency offset compensation signal and Doppler frequency offset judgment lock signal to the control word mapping unit (16-1) and the carrier synchronization automatic reset unit (17), respectively. The control word mapping unit (16-1) sets the parameters of the input modulation scheme, converts the input Doppler frequency offset compensation signal into an NCO accumulation step signal, and transmits the generated NCO accumulation step signal to the digital downconversion unit (2-2). The digital downconversion unit (2-2) receives the NCO accumulation step signal output by the control word mapping unit (16-1) and the control word conversion unit (19), respectively, and performs addition operation with its internal initial NCO accumulation step value to generate an NCO accumulation step control signal. The digital downconversion unit (2-2) uses the generated NCO accumulation step control signal to perform digital downconversion processing on the digital intermediate frequency signal output by AD (1), and generates and outputs the I / Q quadrature baseband signal.

[0031] The half-band filtering unit (3) performs half-band low-pass filtering on the I / Q quadrature baseband signal output by the digital down-conversion unit (2-2) and transmits the processed signal to the digital resampling unit (4). The digital resampling unit (4) receives the timing error signal output by the timing error calculation unit (10), performs digital resampling on the input I / Q quadrature baseband signal, and transmits the processed signal to the matched filtering unit (5). The matched filtering unit (5) performs matched filtering on the input I / Q quadrature baseband signal and transmits the processed signal to the coherent digital AGC unit (6). The coherent digital AGC unit (6) performs power adjustment on the input I / Q quadrature baseband signal and transmits the processed signal to the carrier phase error compensation unit (7). The carrier phase error compensation unit (7) performs carrier phase error adjustment on the input I / Q quadrature baseband signal. Phase error compensation processing is performed, and the processed signal is output. The I / Q quadrature baseband signal output by the carrier phase error compensation unit (7) is then transmitted to the carrier phase error calculation unit (9), timing error calculation unit (10), equalization unit (8) and Q-power unit (14-2) respectively via a splitter. The carrier phase error calculation unit (9) performs carrier phase error calculation on the input I / Q quadrature baseband signal according to the input modulation scheme setting parameters, and transmits the calculated carrier phase error signal to the loop filter unit (18). The timing error calculation unit (10) performs timing error calculation on the input I / Q quadrature baseband signal, and transmits the calculated timing error signal to the digital resampling unit (4). The equalization unit (8) performs equalization processing on the input I / Q quadrature baseband signal, and outputs the processed signal for use by other modules.

[0032] The Q-power unit (14-2) performs Q-power operations on the input I / Q quadrature baseband signal according to the input modulation scheme setting parameters, and transmits the processed signal to the Doppler frequency offset estimation unit (15-2). The Doppler frequency offset estimation unit (15-2) processes the input I / Q quadrature baseband signal to generate a Doppler frequency offset compensation signal and a Doppler frequency offset judgment lock signal, and transmits the generated Doppler frequency offset compensation signal and Doppler frequency offset judgment lock signal to the control word mapping unit (16-2) and the carrier synchronization automatic reset unit (17), respectively. The control word mapping unit (16-2) converts the input Doppler frequency offset compensation signal into an NCO accumulation step signal according to the input modulation scheme setting parameters, and transmits the generated NCO accumulation step signal to the carrier phase error compensation unit (7).

[0033] The loop filter unit (18) internally splits the input carrier phase error signal to generate two carrier phase error signals. The first signal is weighted and accumulated to generate an integral term carrier phase error, and the second signal is weighted to generate a direct term carrier phase error. The loop filter unit (18) splits the internally generated integral term carrier phase error signal to generate two sets of signals. The first set of signals is output to the control word conversion unit (19), and the second set of signals is added to the corresponding direct term carrier phase error. The calculated signal is then transmitted to the carrier phase error compensation unit (7). The wave unit (18) receives the carrier synchronization automatic reset pulse signal output by the carrier synchronization automatic reset unit (17). When the loop filter unit (18) receives the valid carrier synchronization automatic reset pulse signal, the loop filter unit (18) forces the accumulated value used to generate the integral term carrier phase error to the initial value 0. The control word conversion unit (19) performs differential operation on the integral term carrier phase error output by the loop filter unit (18), and then converts the operation signal into an NCO accumulation step signal, and transmits the generated NCO accumulation step signal to the digital downconversion unit (2-2).

[0034] The carrier synchronization automatic reset unit (17) first periodically samples the Doppler frequency offset judgment and lock signal output by the Doppler frequency offset estimation unit (15-2). When the Doppler frequency offset judgment and lock signal obtained in three consecutive sampling periods all indicate that the current Doppler frequency offset is not 0, the carrier synchronization automatic reset pulse signal is output. After the carrier synchronization automatic reset unit (17) outputs the carrier synchronization automatic reset pulse signal, the carrier synchronization automatic reset unit (17) stops detecting the Doppler frequency offset judgment and lock signal output by the Doppler frequency offset estimation unit (15-2). Simultaneously, the Doppler frequency offset estimation unit (15-1) begins to detect the Doppler frequency offset lock signal output by the carrier synchronization automatic reset unit (17). When the carrier synchronization automatic reset unit (17) detects the first valid Doppler frequency offset lock signal output by the Doppler frequency offset estimation unit (15-1), the carrier synchronization automatic reset unit (17) stops detecting the Doppler frequency offset lock signal output by the Doppler frequency offset estimation unit (15-1) and simultaneously begins to periodically sample and detect the Doppler frequency offset lock signal output by the Doppler frequency offset estimation unit (15-2). When the Doppler frequency offset judgment lock signal output by the Doppler frequency offset estimation unit (15-2) indicates that the current Doppler frequency offset is 0, it is determined that the current carrier synchronization is locked. At this time, the carrier synchronization indication signal output by the carrier synchronization automatic reset unit (17) is high. When the Doppler frequency offset judgment lock signal obtained for three consecutive sampling periods indicates that the current Doppler frequency offset is not 0, the carrier synchronization automatic reset pulse signal is output, and the output carrier synchronization indication signal is low. The carrier synchronization automatic reset unit (17) will generate the carrier... The automatic reset pulse signal is transmitted to the loop filter unit (18), the Doppler frequency offset estimation unit (15-1), and the Doppler frequency offset estimation unit (15-2) via a split path. The carrier synchronization automatic reset unit (17) transmits the generated carrier synchronization indication signal to the Doppler frequency offset estimation unit (15-1) and the Doppler frequency offset estimation unit (15-2) via a split path. At the same time, it is used as the device output for use by other modules. The carrier synchronization automatic reset unit (17) continuously detects and processes the carrier synchronization status according to the above principle.

Claims

1. A carrier synchronization device suitable for deep space communication, characterized in that, Analog-to-digital converter (1), first digital down-conversion unit (2-1), second digital down-conversion unit (2-2), half-band filter unit (3), digital resampling unit (4), matched filter unit (5), coherent digital automatic gain control unit (6), carrier phase error compensation unit (7), equalization unit (8), carrier phase error calculation unit (9), timing error calculation unit (10), integral cleaning unit (11), low-pass filter unit (12), incoherent digital automatic gain control unit (13), first Q-power unit (14-1), second Q-power unit (14-2), first Doppler frequency offset estimation unit (15-1), second Doppler frequency offset estimation unit (15-2), first control word mapping unit (16-1), second control word mapping unit (16-2), carrier synchronization automatic reset unit (17), loop filter unit (18), and control word conversion unit (19); The analog-to-digital converter (1) is used to perform analog-to-digital conversion on the input intermediate frequency analog signal to generate a digital intermediate frequency signal, and outputs the digital intermediate frequency signal to the first digital down-conversion unit (2-1) and the second digital down-conversion unit (2-2) respectively. The first digital downconversion unit (2-1) performs digital downconversion processing on the digital intermediate frequency signal to generate a first I / Q quadrature baseband signal; The integral cleaning unit (11), low-pass filtering unit (12), incoherent digital automatic gain control unit (13), first Q-power unit (14-1), first Doppler frequency offset estimation unit (15-1) and first control word mapping unit (16-1) process the first I / Q quadrature baseband signal in sequence to generate the first NCO accumulation step signal and output it to the second digital down-conversion unit (2-2). The second digital downconversion unit (2-2) receives the first NCO accumulation step signal and the second NCO accumulation step signal output by the control word conversion unit (19), and adds them to the internal initial NCO accumulation step value to generate an NCO accumulation step control signal. The NCO accumulation step control signal is used to perform digital downconversion processing on the digital intermediate frequency signal to generate a second I / Q quadrature baseband signal. The half-band filtering unit (3), digital resampling unit (4), matched filtering unit (5), and coherent digital automatic gain control unit (6) sequentially process the second I / Q quadrature baseband signal and output the processed signal to the carrier phase error compensation unit (7). The carrier phase error compensation unit (7) performs carrier phase error compensation processing on the input signal and outputs the compensated I / Q quadrature baseband signal. The compensated I / Q quadrature baseband signal is output to the carrier phase error calculation unit (9), the timing error calculation unit (10), the equalization unit (8), and the second Q power unit (14-2). The carrier phase error calculation unit (9) calculates the carrier phase error according to the input modulation scheme setting parameters and outputs it to the loop filter unit (18). The timing error calculation unit (10) calculates the timing error and outputs it to the digital resampling unit (4). The equalization unit (8) performs equalization processing and outputs the result for use by other modules; The second Q-power unit (14-2), the second Doppler frequency offset estimation unit (15-2), and the second control word mapping unit (16-2) process the compensated I / Q quadrature baseband signal in sequence to generate the third NCO accumulation step signal and output it to the carrier phase error compensation unit (7). The loop filter unit (18) performs split processing on the input carrier phase error signal to generate an integral term carrier phase error and a direct term carrier phase error. A portion of the integral term carrier phase error is output to the control word conversion unit (19), and the other portion is added to the direct term carrier phase error and output to the carrier phase error compensation unit (7). The control word conversion unit (19) performs differential operation on the integral term carrier phase error and converts it into the second NCO accumulation step signal, which is then output to the second digital downconversion unit (2-2). The carrier synchronization automatic reset unit (17) receives the Doppler frequency offset judgment lock signals output by the first Doppler frequency offset estimation unit (15-1) and the second Doppler frequency offset estimation unit (15-2), respectively. It generates a carrier synchronization automatic reset pulse signal and a carrier synchronization indication signal according to the preset judgment logic. The carrier synchronization automatic reset pulse signal is output to the loop filter unit (18), the first Doppler frequency offset estimation unit (15-1) and the second Doppler frequency offset estimation unit (15-2) respectively. The carrier synchronization indication signal is output to the first Doppler frequency offset estimation unit (15-1) and the second Doppler frequency offset estimation unit (15-2) respectively and is used as the device output.

2. A carrier synchronization device suitable for deep space communication according to claim 1, characterized in that, The first Doppler frequency offset estimation unit (15-1) and the second Doppler frequency offset estimation unit (15-2) both include: an FFT unit (20), a modulus calculation unit (21), a delay unit (22), an addition unit (23), a RAM unit (24), an output control unit (25), a loop counting unit (26), a loop convolution unit (27), a maximum value search unit (28), and a signal receiving and holding unit (29); The FFT unit (20) performs buffering and FFT operation on the input I / Q quadrature baseband signal according to the FFT period operation control pulse output by the cycle counting unit (26), and outputs the complex signal after operation to the modulus calculation unit (21). The modulus calculation unit (21) performs modulus calculation on the complex signal to generate a modulus signal and a corresponding modulus position number; The RAM unit (24) uses the modulus position number as the read address and outputs the cached accumulated modulus signal to the addition unit (23). The delay unit (22) delays the modulus signal and outputs it to the addition unit (23). The addition unit (23) performs an addition operation on the accumulated modulus signal output by the RAM unit (24) and the modulus signal output by the delay unit (22) to generate a new accumulated modulus signal and the corresponding accumulated modulus position number, and writes them into the RAM unit (24) and outputs them to the output control unit (25). The output control unit (25) outputs the latest modulus accumulation signal to the circular convolution unit (27) according to the FFT period output control pulse output by the circular counting unit (26). The circular convolution unit (27) performs a circular convolution operation on the input modulus accumulation signal and extracts the effective signal, which is then output to the maximum value search unit (28). The maximum value search unit (28) searches for the maximum value in a frame of valid modulus signals, outputs the receiving number corresponding to the maximum value, and outputs the receiving number as a Doppler frequency offset judgment lock signal to the carrier synchronization automatic reset unit (17) and to the signal receiving and holding unit (29). The signal receiving and holding unit (29) outputs the first received maximum modulus receiving number as a Doppler frequency offset compensation signal according to the carrier synchronization automatic reset pulse signal.

3. A carrier synchronization device suitable for deep space communication according to claim 2, characterized in that, The circular convolution unit (27) performs a circular convolution operation on the input modulus accumulation signal in the form of a second-order low-pass filter, and truncates the output signal starting from the second bit after the operation, with the truncation length being equal to the length of the input signal.

4. A carrier synchronization device suitable for deep space communication according to claim 2, characterized in that, The cycle counting unit (26) dynamically adjusts the internal cycle counter setting value according to the carrier synchronization indication signal: when the carrier synchronization indication signal is high, the setting value is increased to increase the generation period of the FFT period operation control pulse and the FFT period output control pulse; when the carrier synchronization indication signal is low, the setting value is decreased to decrease the generation period.

5. A carrier synchronization device suitable for deep space communication according to claim 1, characterized in that, The determination logic of the carrier synchronization automatic reset unit (17) is as follows: In the initial state or after reset, the Doppler frequency offset judgment and lock signal output by the second Doppler frequency offset estimation unit (15-2) is periodically sampled first; When three consecutive sampling cycles indicate that the current Doppler frequency offset is not 0, the carrier synchronization automatic reset pulse signal is output. After outputting the reset pulse, the detection of the second Doppler frequency offset estimation unit (15-2) is stopped, and the Doppler frequency offset judgment lock signal output by the first Doppler frequency offset estimation unit (15-1) is detected instead; When the first valid Doppler frequency offset estimation unit (15-1) outputs the first valid Doppler frequency offset judgment lock signal, the detection of the first Doppler frequency offset estimation unit (15-1) is stopped, and the periodic sampling and detection of the second Doppler frequency offset estimation unit (15-2) is resumed. When the Doppler frequency offset determination lock signal output by the second Doppler frequency offset estimation unit (15-2) indicates that the current Doppler frequency offset is 0, the carrier synchronization is determined to be locked, and the carrier synchronization indication signal is high level; When the Doppler frequency offset detection lock signal detected in three consecutive sampling cycles indicates that the Doppler frequency offset is not 0, the carrier synchronization automatic reset pulse signal is output again, and the carrier synchronization indicator signal becomes low.

6. A carrier synchronization device suitable for deep space communication according to claim 1, characterized in that, After receiving the carrier synchronization automatic reset pulse signal, the loop filter unit (18) forcibly resets the accumulated value used to generate the integral term carrier phase error to the initial value of 0.

7. A carrier synchronization device suitable for deep space communication according to claim 1, characterized in that, The first Q-power unit (14-1) and the second Q-power unit (14-2) determine the exponent Q of the Q-power operation according to the input modulation scheme setting parameters.

8. A carrier synchronization device suitable for deep space communication according to claim 1, characterized in that, The first control word mapping unit (16-1) and the second control word mapping unit (16-2) convert the corresponding Doppler frequency offset compensation signal into the corresponding NCO accumulating step signal according to the input modulation scheme setting parameters.

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