Communication method and communication apparatus

Abstract

A communication method and a communication device, the method involves scrambling a first bit sequence, and selecting different scrambling modes for scrambling according to conditions met by bit values in the first bit sequence, so as to improve the probability of occurrence of low-energy symbols and improve the performance of probability shaping.

Description

Technical Field

[0001] This application relates to the field of wireless communication technology, and more specifically, to a communication method and a communication device. Background Technology

[0002] Higher-order modulation refers to mapping multiple bits to the same modulation symbol, which can improve spectral efficiency. Common higher-order modulation schemes include quadrature amplitude modulation (QAM), such as 16QAM and 64QAM. Different modulation symbols in higher-order modulation may have different energies; by transmitting more low-energy modulation symbols and fewer high-energy modulation symbols, average energy can be saved. Theoretical analysis shows that for a Gaussian white noise channel, the greatest energy saving occurs when the transmitted symbol distribution follows a Gaussian distribution. Compared to a uniform distribution, up to 1.53 dB of transmit power can be saved.

[0003] Probabilistic shaping (PS) is a common "shaping" technique. It involves cascading a precoder before the encoder to map ("shape") the information bits into a sequence following a specific distribution (the precoder is also called a distribution matcher (DM), or some kind of transformation). Then, during channel coding, systematic coding is used, ensuring that the aforementioned sequence satisfying the specific distribution ultimately appears directly in the coded sequence, thus shaping the final modulated symbol. Probabilistic shaping can increase the probability of low-energy symbols appearing compared to high-energy symbols. However, implementing this symbol-level shaping is currently quite complex. Summary of the Invention

[0004] This application provides a communication method and a communication device that achieves symbol-level shaping effects through bit-level shaping, thereby improving the performance of probability shaping.

[0005] In a first aspect, a communication method is provided, which can be executed by a transmitting device or a module applied to the transmitting device (e.g., a processor, chip, circuit, etc., or a logic module, hardware, and / or software capable of implementing all or part of the functions of the transmitting device). The transmitting device is also referred to as an encoding device.

[0006] The method may include: the transmitting device acquiring a first bit sequence; the transmitting device selecting a first scrambling method or a second scrambling method to scramble the first bit sequence according to the conditions satisfied by the bit values ​​in the first bit sequence, to obtain a second bit sequence.

[0007] One possible implementation is that the first bit sequence mentioned above is obtained through distribution matching.

[0008] It should be understood that the distribution matching in this application may also be referred to as precoding.

[0009] The method provided in this application can select a scrambling method according to the bit values ​​in a bit sequence. That is, different bit values ​​may be scrambled using different scrambling methods, thereby specifically increasing the probability of low-energy symbols appearing and improving the performance of probability shaping.

[0010] In conjunction with the first aspect, in some implementations of the first aspect, the first bit sequence comprises m first subsequences, each of which has a length of N; the second bit sequence comprises m second subsequences, each of which has a length of N, wherein N is less than or equal to 2N. re N re Indicates the number of resource units or the number of symbols in a modulation symbol sequence, m, N, N re It is a positive integer.

[0011] The method provided in this application can perform bit-level distribution matching on a bit sequence of length m*N to obtain a first bit sequence of length m*N. It is simple to implement and only requires configuring a distribution matching code rate, which simplifies code rate configuration.

[0012] In conjunction with the first aspect, in some implementations of the first aspect, the aforementioned transmitting device selects a first scrambling method or a second scrambling method to scramble the first bit sequence according to the conditions satisfied by the bit values ​​in the first bit sequence, including: selecting a first scrambling method or a second scrambling method to scramble the first bit sequence according to the conditions satisfied by the bit values ​​of the i-th first subsequence among m first subsequences and the bit values ​​of one or more first subsequences other than the i-th first subsequence among m first subsequences, where 1≤i≤m.

[0013] The method provided in this application can combine multiple first subsequences for shaping, which can obtain long code gain. Furthermore, the scrambling method takes into account the bit values ​​of each first subsequence in the multiple first subsequences, thereby improving the shaping effect.

[0014] In conjunction with the first aspect, in some implementations of the first aspect, the aforementioned transmitting device selects a first scrambling method or a second scrambling method to scramble the first bit sequence according to the conditions satisfied by the bit values ​​in the first bit sequence, including: the transmitting device selects a first scrambling method or a second scrambling method to scramble the first bit sequence according to the conditions satisfied by the bit values ​​of the i-th first sub-sequence and the (i-1)-th first sub-sequence among m first sub-sequences, where 2≤i≤m.

[0015] The method provided in this application can scramble two first subsequences together, and the scrambling method takes into account the bit values ​​of each of the two first subsequences, which can obtain a certain degree of long code gain and reduce the processing complexity.

[0016] In conjunction with the first aspect, in some implementations of the first aspect, the aforementioned transmitting device selects a first scrambling method or a second scrambling method to scramble the first bit sequence based on the conditions satisfied by the bit values ​​in the first bit sequence, including: selecting the first scrambling method to scramble the first bit sequence when the bit values ​​of the i-th first subsequence and the (i-1)-th first subsequence satisfy a first condition; wherein, the first condition is: there are more 0s than 1s in the i-th first subsequence and the (i-1)-th first subsequence, or, there are more 1s than 0s in the i-th first subsequence and the (i-1)-th first subsequence; the first scrambling method is: the i-th first subsequence, the (i-1)-th first subsequence, and 1 are XORed to obtain the i-th second subsequence.

[0017] In conjunction with the first aspect, in certain implementations of the first aspect, the aforementioned transmitting device selects a first scrambling method or a second scrambling method to scramble the first bit sequence based on the conditions satisfied by the bit values ​​in the first bit sequence, including: when the bit values ​​of the i-th first subsequence and the (i-1)-th first subsequence in the first bit sequence satisfy a second condition, the second scrambling method is selected to scramble the first bit sequence; wherein, the second condition is: there are more 0s than 1s in the i-th first subsequence and more 1s than 0s in the (i-1)-th first subsequence, or, there are more 1s than 0s in the i-th first subsequence and more 0s than 1s in the (i-1)-th first subsequence; the second scrambling method is to obtain the i-th second subsequence by XORing the i-th first subsequence and the (i-1)-th first subsequence.

[0018] For example, the second bit sequence described above can be carried in the amplitude bits of the modulation symbol.

[0019] The method provided in this application selects different scrambling methods to obtain the i-th second subsequence under different bit values ​​in the i-th and (i-1)-th first subsequences. This can specifically increase the probability of low-energy symbols appearing and improve the performance of probability shaping. In addition, the scrambled second bit sequence can be carried in the amplitude bits of the modulation symbol, which can realize amplitude bit shaping.

[0020] In conjunction with the first aspect, in some implementations of the first aspect, the aforementioned transmitting device selects a first scrambling method or a second scrambling method to scramble the first bit sequence based on the conditions satisfied by the bit values ​​in the first bit sequence, including: selecting the first scrambling method to scramble the first bit sequence when the bit value of the first first subsequence in the first bit sequence satisfies a third condition; wherein, the third condition is: there are more 0s than 1s in the first first subsequence; the first scrambling method is: the first first subsequence is the same as the first second subsequence among m second subsequences.

[0021] In conjunction with the first aspect, in some implementations of the first aspect, the aforementioned transmitting device selects a first scrambling method or a second scrambling method to scramble the first bit sequence according to the conditions satisfied by the bit values ​​in the first bit sequence, including: when the bit value of the first first subsequence in the first bit sequence satisfies a fourth condition, the second scrambling method is selected to scramble the first bit sequence; wherein, the fourth condition is: there are more 1s than 0s in the first first subsequence; the second scrambling method is: the first first subsequence and 1 are XORed to obtain the first second subsequence among m second subsequences.

[0022] The method provided in this application selects different scrambling methods to obtain the first second subsequence under different conditions of bit values ​​in the first subsequence, which reduces the processing complexity to a certain extent.

[0023] In conjunction with the first aspect, in some implementations of the first aspect, the aforementioned transmitting device selects a first scrambling method or a second scrambling method to scramble the first bit sequence based on the conditions satisfied by the bit values ​​in the first bit sequence, including: when the bit value of the i-th first subsequence among m first subsequences satisfies a first condition, the first scrambling method is selected to scramble the first bit sequence; wherein, the first condition is: there are more 0s than 1s in the i-th first subsequence; the first scrambling method is: the i-th first subsequence, the third bit sequence, and 1 are XORed to obtain the i-th second subsequence among m second subsequences.

[0024] The length of the third bit sequence mentioned above is N.

[0025] For example, the third bit sequence mentioned above could be a payload bit.

[0026] For example, the third bit sequence mentioned above can be carried on the sign bit of the modulation symbol.

[0027] In conjunction with the first aspect, in some implementations of the first aspect, the aforementioned transmitting device selects a first scrambling method or a second scrambling method to scramble the first bit sequence based on the conditions satisfied by the bit values ​​in the first bit sequence, including: when the bit value of the i-th first subsequence among the m first subsequences satisfies a second condition, the second scrambling method is selected to scramble the first bit sequence; wherein, the second condition is: there are more 1s than 0s in the i-th first subsequence; the second scrambling method is: the i-th first subsequence and the third bit sequence are XORed to obtain the i-th second subsequence among the m second subsequences.

[0028] The method provided in this application selects different scrambling methods to obtain the i-th second subsequence under different conditions where the bit values ​​in the i-th first subsequence satisfy different conditions. The i-th first subsequence is obtained by performing operations with payload bits of the same length to obtain the scrambled i-th second subsequence. This process only needs to determine the ratio of 0s and 1s in the i-th first subsequence, which reduces the processing complexity to a certain extent. In addition, the scrambled second bit sequence can be carried in the amplitude bits of the modulation symbol, and the third bit sequence participating in the scrambling process can be carried in the sign bits of the modulation symbol, which can realize the joint shaping of the sign bits and amplitude bits.

[0029] In conjunction with the first aspect, in some implementations of the first aspect, the aforementioned transmitting device selects a first scrambling method or a second scrambling method to scramble the first bit sequence based on the conditions satisfied by the bit values ​​in the first bit sequence, including: selecting the first scrambling method to scramble the first bit sequence when the bit values ​​of the i-th first sub-sequence and the bit values ​​of the seventh bit sequence satisfy a first condition; wherein, the first condition is: there are more 0s than 1s in the i-th first sub-sequence and the seventh bit sequence, or, there are more 1s than 0s in the i-th first sub-sequence and the seventh bit sequence; the first scrambling method is: the i-th first sub-sequence, the seventh bit sequence, and 1 are XORed to obtain the i-th second sub-sequence.

[0030] For example, the seventh bit sequence can be predefined, preconfigured, pre-stored, or specified by the protocol.

[0031] For example, the seventh bit sequence above has more 0s than 1s, or the seventh bit sequence above has more 1s than 0s.

[0032] In conjunction with the first aspect, in certain implementations of the first aspect, the aforementioned transmitting device selects a first scrambling method or a second scrambling method to scramble the first bit sequence based on the conditions satisfied by the bit values ​​in the first bit sequence, including: when the bit values ​​of the i-th first subsequence and the bit values ​​of the seventh bit sequence in the first bit sequence satisfy a second condition, the second scrambling method is selected to scramble the first bit sequence; wherein, the second condition is: there are more 0s than 1s in the i-th first subsequence and more 1s than 0s in the seventh bit sequence, or, there are more 1s than 0s in the i-th first subsequence and more 0s than 1s in the seventh bit sequence; the second scrambling method is to obtain the i-th second subsequence by XORing the i-th first subsequence and the seventh bit sequence.

[0033] The method provided in this application can scramble the i-th first subsequence using a preset bit sequence, which can not only simplify the operation logic and reduce the processing complexity, but also improve the probability of low-energy symbols appearing by flexibly designing the bit values ​​of the seventh bit sequence, thereby improving the performance of probability shaping.

[0034] One possible implementation involves storing two seventh-bit sequences, where one sequence has more 0s than 1s and the other has more 1s than 0s. In practical applications, one of these seven-bit sequences can be selected based on the ratio of 0s to 1s in the i-th first subsequence, thus ensuring that the scrambling method is fixed and simplifying the scrambling process.

[0035] In conjunction with the first aspect, in some implementations of the first aspect, obtaining the first bit sequence includes: the transmitting device obtaining a payload bit sequence of length K, wherein the payload bit sequence of length K includes a fourth bit sequence and a fifth bit sequence, and K is a positive integer.

[0036] For example, the fourth bit sequence mentioned above can be obtained by distribution matching to obtain the first bit sequence mentioned above.

[0037] For example, the fifth bit sequence mentioned above includes the third bit sequence mentioned above.

[0038] In conjunction with the first aspect, in some implementations of the first aspect, the above method further includes: the transmitting device encoding the second bit sequence to obtain an encoded bit sequence.

[0039] Alternatively, the transmitting device may encode the second bit sequence and the fifth bit sequence to obtain the encoded bit sequence.

[0040] For example, low-density parity check (LDPC) codes or other types of encoding methods can be used.

[0041] In conjunction with the first aspect, in some implementations of the first aspect, the above method further includes: modulating the encoded bit sequence according to the first modulation scheme to obtain a modulation symbol sequence, the modulation symbol sequence including multiple modulation symbols, each modulation symbol including one or more amplitude bits, the i-th second subsequence among the above m second subsequences being located at the i-th amplitude bit among the one or more amplitude bits, the i-th amplitude bit being the i-th amplitude bit after the one or more amplitude bits are sorted from highest to lowest reliability.

[0042] That is, the above m second subsequences are located on the m amplitude bits with the highest reliability among the above one or more amplitude bits.

[0043] The methods described above in this application can improve the results of plastic surgery.

[0044] Secondly, a communication method is provided, which can be executed by a receiving device or a module applied to the receiving device (e.g., a processor, chip, circuit, etc., or a logic module, hardware, and / or software capable of implementing all or part of the functions of the receiving device). The receiving device is also referred to as a decoding device.

[0045] The method includes: a receiving device obtaining a decoded bit sequence, the decoded bit sequence including a second bit sequence; the receiving device selecting a first descrambling method or a second descrambling method to descramble the second bit sequence according to the conditions satisfied by the bit values ​​in the first bit sequence, to obtain the first bit sequence.

[0046] It should be understood that the second aspect corresponds to the first aspect above, and supplementary explanations and technical effects can be found in the description of the first aspect above.

[0047] In conjunction with the second aspect, in some implementations of the second aspect, the first bit sequence comprises m first subsequences, each of which has a length of N; the second bit sequence comprises m second subsequences, each of which has a length of N, wherein N is less than or equal to 2N. re N re Indicates the number of resource units or the number of symbols in a modulation symbol sequence, m, N, N re It is a positive integer.

[0048] In conjunction with the second aspect, in some implementations of the second aspect, the receiving device selects a first descrambling method or a second descrambling method to descramble the second bit sequence based on the conditions satisfied by the bit values ​​in the first bit sequence, including: the receiving device selects a first descrambling method or a second descrambling method to descramble the second bit sequence based on the conditions satisfied by the bit values ​​of the i-th first subsequence among m first subsequences and the bit values ​​of one or more first subsequences other than the i-th first subsequence among m first subsequences, where 1≤i≤m.

[0049] In conjunction with the second aspect, in some implementations of the second aspect, the receiving device selects a first descrambling method or a second descrambling method to descramble the second bit sequence according to the conditions satisfied by the bit values ​​in the first bit sequence, including: the receiving device selects a first descrambling method or a second descrambling method to descramble the second bit sequence according to the conditions satisfied by the bit values ​​of the i-th first sub-sequence and the (i-1)-th first sub-sequence in m first sub-sequences, where 2≤i≤m.

[0050] In conjunction with the second aspect, in some implementations of the second aspect, the receiving device selects a first descrambling method or a second descrambling method to descramble the second bit sequence based on the conditions satisfied by the bit values ​​in the first bit sequence, including: selecting the first descrambling method to descramble the second bit sequence when the bit values ​​of the i-th first subsequence and the (i-1)-th first subsequence satisfy a first condition; wherein, the first condition is: there are more 0s than 1s in the i-th first subsequence and the (i-1)-th first subsequence, or, there are more 1s than 0s in the i-th first subsequence and the (i-1)-th first subsequence; the first descrambling method is: the i-th second subsequence, the (i-1)-th first subsequence, and 1 are XORed to obtain the i-th first subsequence.

[0051] In conjunction with the second aspect, in some implementations of the second aspect, the receiving device selects a first descrambling method or a second descrambling method to descramble the second bit sequence based on the conditions satisfied by the bit values ​​in the first bit sequence. This includes: selecting the second descrambling method to descramble the second bit sequence when the bit values ​​of the i-th first subsequence and the (i-1)-th first subsequence satisfy a second condition; wherein the second condition is: the i-th first subsequence has more 0s than 1s and the (i-1)-th first subsequence has more 1s than 0s, or the i-th first subsequence has more 1s than 0s and the (i-1)-th first subsequence has more 0s than 1s; the second descrambling method is to obtain the i-th first subsequence by XORing the i-th second subsequence and the (i-1)-th first subsequence.

[0052] In conjunction with the second aspect, in some implementations of the second aspect, the receiving device selects a first descrambling method or a second descrambling method to descramble the second bit sequence based on the conditions satisfied by the bit values ​​in the first bit sequence, including: when the bit value of the first first subsequence in the first bit sequence satisfies a third condition, the first descrambling method is selected to descramble the second bit sequence; wherein, the third condition is: there are more 0s than 1s in the first first subsequence; the first descrambling method is: the first second subsequence in m second subsequences is the same as the first first subsequence.

[0053] In conjunction with the second aspect, in some implementations of the second aspect, the receiving device selects a first descrambling method or a second descrambling method to descramble the second bit sequence based on the conditions satisfied by the bit values ​​in the first bit sequence, including: when the bit value of the first first subsequence in the first bit sequence satisfies a fourth condition, the second descrambling method is selected to descramble the second bit sequence; wherein, the fourth condition is: there are more 1s than 0s in the first first subsequence; the second descrambling method is: the first second subsequence and 1 are XORed to obtain the first first subsequence among m first subsequences.

[0054] In conjunction with the second aspect, in some implementations of the second aspect, the receiving device selects a first descrambling method or a second descrambling method to descramble the second bit sequence based on the conditions satisfied by the bit values ​​in the first bit sequence, including: when the bit value of the i-th first subsequence among m first subsequences satisfies a first condition, the first descrambling method is selected to descramble the second bit sequence; wherein, the first condition is: there are more 0s than 1s in the i-th first subsequence; the first descrambling method is: the i-th second subsequence, the third bit sequence, and 1 are XORed to obtain the i-th first subsequence.

[0055] In conjunction with the second aspect, in some implementations of the second aspect, the receiving device selects a first descrambling method or a second descrambling method to descramble the second bit sequence based on the conditions satisfied by the bit values ​​in the first bit sequence, including: when the bit value of the i-th first sub-sequence among the m first sub-sequences satisfies the second condition, the second descrambling method is selected to descramble the second bit sequence; wherein, the second condition is: there are more 1s than 0s in the i-th first sub-sequence; the second descrambling method is: the i-th second sub-sequence and the third bit sequence are XORed to obtain the i-th first sub-sequence.

[0056] In conjunction with the second aspect, in some implementations of the second aspect, the receiving device selects a first descrambling method or a second descrambling method to descramble the second bit sequence based on the conditions satisfied by the bit values ​​in the first bit sequence, including: selecting the first descrambling method to descramble the second bit sequence when the bit values ​​of the i-th first sub-sequence and the bit values ​​of the seventh bit sequence satisfy a first condition; wherein, the first condition is: there are more 0s than 1s in the i-th first sub-sequence and the seventh bit sequence, or, there are more 1s than 0s in the i-th first sub-sequence and the seventh bit sequence; the first descrambling method is: the i-th second sub-sequence, the seventh bit sequence, and 1 are XORed to obtain the i-th first sub-sequence.

[0057] In conjunction with the second aspect, in some implementations of the second aspect, the receiving device selects a first descrambling method or a second descrambling method to descramble the second bit sequence based on the conditions satisfied by the bit values ​​in the first bit sequence. This includes: selecting the second descrambling method to scramble the second bit sequence when the bit values ​​of the i-th first subsequence and the bit values ​​of the seventh bit sequence satisfy a second condition; wherein the second condition is: the i-th first subsequence has more 0s than 1s and the seventh bit sequence has more 1s than 0s, or the i-th first subsequence has more 1s than 0s and the seventh bit sequence has more 0s than 1s; the second descrambling method is to obtain the i-th first subsequence by XORing the i-th second subsequence and the seventh bit sequence.

[0058] In conjunction with the second aspect, in some implementations of the second aspect, the above method further includes: the receiving device acquiring the information to be decoded; the receiving device decoding the information to be decoded to obtain the decoded bit sequence.

[0059] In conjunction with the second aspect, in some implementations of the second aspect, the above method further includes: the receiving device obtaining the information to be demodulated; the receiving device modulating the information to be demodulated according to the first modulation method to obtain a modulation symbol sequence, the modulation symbol sequence including multiple modulation symbols, each modulation symbol including one or more amplitude bits, the i-th second subsequence among the above m second subsequences being located at the i-th amplitude bit among the one or more amplitude bits, the i-th amplitude bit being the i-th amplitude bit after the one or more amplitude bits are sorted from highest to lowest reliability.

[0060] Thirdly, a communication device is provided, which has the function of implementing the method in the first aspect or any possible implementation of the first aspect. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above-described function.

[0061] Fourthly, a communication device is provided, which has the function of implementing the method in the second aspect or any possible implementation of the second aspect. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above-described function.

[0062] Fifthly, a communication device is provided, comprising at least one processor configured to cause the communication device to execute the method of the first aspect or any possible implementation thereof; or to execute the method of the second aspect or any possible implementation thereof. Optionally, the at least one processor is coupled to at least one memory for storing computer programs or instructions, and the at least one processor is configured to call and run the computer program or instructions from the at least one memory, causing the communication device to execute the method of the first aspect or any possible implementation thereof; or to execute the method of the second aspect or any possible implementation thereof. Optionally, the at least one processor may be included in the communication device or may be configured outside the communication device. Optionally, the communication device further includes the at least one memory. Optionally, the communication device further includes at least one communication interface. As an example, the communication interface may include an input interface and / or an output interface, or may be an interface circuit.

[0063] Sixthly, a communication device is provided, comprising a communication interface and a circuit. The communication interface is configured to receive a signal to be processed and transmit the signal to the circuit. The circuit is configured to process the signal to perform a method as described in the first aspect or any possible implementation thereof; or to perform a method as described in the second aspect or any possible implementation thereof. Optionally, the communication interface is further configured to output a signal processed by the circuit. Optionally, the signal may include information and / or data. Optionally, the communication device may be a chip (e.g., a baseband chip) or a chip system.

[0064] A seventh aspect provides a computer-readable storage medium storing computer program code or instructions that, when executed on a computer, cause the method of the first aspect or any possible implementation thereof to be implemented; or, the method of the second aspect or any possible implementation thereof to be implemented.

[0065] Eighthly, a computer program product is provided, the computer program product comprising computer program code or instructions, which, when executed on a computer, cause the method in the first aspect or any possible implementation thereof to be implemented; or, as in the second aspect or any possible implementation thereof, the method to be implemented.

[0066] A ninth aspect provides a wireless communication system, including a communication device as described in the third aspect and a communication device as described in the fourth aspect. Attached Figure Description

[0067] Figure 1 This is an example of a communication system applicable to the technical solutions of this application.

[0068] Figure 2 This is a schematic diagram of the basic process of wireless communication.

[0069] Figure 3 This is a flowchart of a plastic surgery technique.

[0070] Figure 4 This is a schematic diagram of a modulation symbol distribution.

[0071] Figure 5 This is a schematic flowchart of a communication method provided in an embodiment of this application.

[0072] Figure 6 A schematic structural diagram of a communication device provided in this application.

[0073] Figure 7 A schematic structural diagram of another communication device provided in this application.

[0074] Figure 8 A schematic structural diagram of the chip provided in this application. Detailed Implementation

[0075] The technical solutions of this application can be applied to various existing and future communication systems, including but not limited to: satellite communication systems, fifth-generation (5G) systems or new radio (NR) systems, long-term evolution (LTE) systems, LTE frequency division duplex (FDD) systems, LTE time division duplex (TDD) systems, and future communication systems. Furthermore, they can also be applied to sidelink (SL) communication, vehicle-to-everything (V2X) communication, machine-to-machine (M2M) communication, machine-type communication (MTC), and Internet of Things (IoT) communication systems, or other communication systems, etc., which are not limited herein.

[0076] Figure 1 This is an example of a communication system applicable to the technical solution of this application. For example... Figure 1 The communication system may include one or more transmitting devices and one or more receiving devices. Optionally, one of the transmitting and receiving devices may be a terminal device, and the other may be a network device. The communication method provided in this application is applicable to... Figure 1 The communication between the network device and the terminal device shown is either uplink or downlink communication. For example, in downlink communication, the sending device in this embodiment is a network device, and the receiving device is a terminal device; in uplink communication, the sending device in this embodiment is a terminal device, and the receiving device is a network device.

[0077] For example, a terminal device may also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, wireless communication device, user agent, or user apparatus. In the embodiments of this application, the terminal device may be a device that provides voice and / or data connectivity to a user, and can be used to connect people, objects, and machines, such as a handheld device with wireless connectivity, in-vehicle equipment, etc. The terminal device in the embodiments of this application may be a mobile phone, tablet computer, laptop computer, PDA, mobile internet device (MID), wearable device, virtual reality (VR) device, augmented reality (AR) device, wireless terminal in industrial control, wireless terminal in self-driving, wireless terminal in remote medical surgery, wireless terminal in smart grid, wireless terminal in transportation safety, wireless terminal in smart city, wireless terminal in smart home, etc. Optionally, the UE may be used to act as a base station. For example, the UE may act as a scheduling entity, providing sidelink signals between UEs in V2X or SL, etc.

[0078] In this embodiment, the device for implementing the functions of the terminal device can be the terminal device itself, or any device capable of supporting the terminal device in implementing the corresponding functions, such as a chip, processor, circuit, hardware, and / or software combination. This device can be configured in the terminal device or used in conjunction with the terminal device. A chip system can consist of chips or include chips and other discrete components. In this embodiment, the terminal device is used as an example to illustrate the device for implementing the corresponding functions of the terminal device.

[0079] The network device in this application embodiment may include a device for communicating with a terminal device. This network device may include an access network device or a radio access network device; for example, the network device may be a base station. In this application embodiment, the access network device may refer to a radio access network (RAN) node (or device) that connects the terminal device to the wireless network. A base station can broadly encompass, or be replaced by, various names such as: NodeB, evolved NodeB (eNB), next-generation NodeB (gNB), relay station, access point, transmitting and receiving point (TRP), transmitting point (TP), master station, auxiliary station, motor slide retainer (MSR) node, home base station, network controller, access node, wireless node, access point (AP), transmission node, transceiver node, baseband unit (BBU), remote radio unit (RRU), active antenna unit (AAU), remote radio head (RRH), central unit (CU), distributed unit (DU), radio unit (RU), positioning node, etc. A base station can be a macro base station, micro base station, relay node, donor node, or a combination thereof. A base station can also refer to a communication module, modem, or chip installed within the aforementioned equipment or apparatus. A base station can also be a mobile switching center, a device performing base station functions in D2D, V2X, and M2M communications, a network device (e.g., a base station) in a future communication network, or a device performing network device functions. A base station can support networks using the same or different access technologies. Optionally, a RAN node can also be a server, wearable device, vehicle, or in-vehicle equipment. For example, the access network equipment in vehicle-to-everything (V2X) technology can be a roadside unit (RSU). The embodiments of this application do not limit the specific technology or device form used in the network equipment.

[0080] Base stations can be fixed or mobile. For example, a helicopter or drone can be configured to act as a mobile base station, and one or more cells can move depending on the location of the mobile base station. In other examples, a helicopter or drone can be configured as a device to communicate with another base station.

[0081] The network equipment described in this application can also be applied to non-terrestrial network (NTN) systems such as inter-satellite communication and satellite communication. As an example, the network equipment can be deployed on non-terrestrial equipment such as drones, hot air balloons, low-Earth orbit satellites, medium-Earth orbit satellites, and high-Earth orbit satellites.

[0082] In some deployments, the network device in this application embodiment may be a device including a CU, or a DU, or a device including both CU and DU, or a control plane CU node (central unit-control plane (CU-CP)) and a user plane CU node (central unit-user plane (CU-UP)) and a DU node. For example, the network device may include gNB-CU-CP, gNB-CU-UP, and gNB-DU.

[0083] In some deployments, multiple RAN nodes collaborate to assist terminals in achieving wireless access, with different RAN nodes each implementing some of the base station's functions. For example, RAN nodes can be CUs, DUs, CU-CPs, CU-UPs, or RUs. CUs and DUs can be configured separately or included in the same network element, such as a BBU. RUs can be included in radio frequency equipment or radio frequency units, such as RRUs, AAUs, or RRHs.

[0084] In different systems, CU (or CU-CP and CU-UP), DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an open radio access network (ORAN / O-RAN) system, CU can also be called an open CU (open CU, O-CU), and DU can also be called an open DU (open DU, O-DU). CU-CP can also be called O-CU-CP, CU-UP can also be called O-CU-UP, and RU can also be called O-RU. Any of the units among CU (or CU-CP, CU-UP), DU, and RU in this application can be implemented through software modules, hardware modules, or a combination of software modules and hardware modules.

[0085] In this embodiment, the apparatus for implementing the functions of a network device can be a network device itself; it can also be an apparatus capable of supporting the network device in implementing the corresponding functions, such as a chip, processor, circuit, hardware, and / or software combination. This apparatus can be configured within the network device or used in conjunction with the network device. In this embodiment, only the network device itself is used as an example to illustrate the implementation of the corresponding functions of the network device.

[0086] Figure 2 This is a schematic diagram of the basic process of wireless communication. For example... Figure 2 As shown, at the signal transmitting device, the signal source is transmitted after sequentially undergoing source coding, channel coding, and digital modulation. At the signal receiving device, the received signal is sequentially processed through digital demodulation, channel decoding, and source decoding before being output to the destination.

[0087] The communication method provided in this application can be used in dedicated network devices or general-purpose devices, and can be applied to the various network devices (e.g., base stations) and terminal devices mentioned above. Specifically, channel coding is mainly implemented by channel coding units (e.g., encoders or devices that support coding devices to perform corresponding functions) in these devices; channel decoding is mainly implemented by channel decoding units (e.g., decoders or devices that support decoding devices to perform corresponding functions) in these devices.

[0088] Optionally, the functions of the encoding or decoding device can be implemented by application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or by software (e.g., program code in memory), or by a combination of both, without limitation.

[0089] To facilitate understanding of the embodiments provided in this application, several concepts or terms involved in the embodiments of this application are briefly described. The concepts or terms described below are based on the concepts or terms specified in the agreement, but do not mean that the embodiments of this application can only be applied to existing systems. The concepts or terms involved in the embodiments of this application can be applied to future systems. Furthermore, the specific names of the concepts or terms (e.g., concepts or terms involving functional descriptions) can be adjusted as the system develops in the future.

[0090] 1. Modulation and demodulation

[0091] In combination with the above Figure 2 As shown, the transmitting device can also map the encoded bit sequence to a modulation symbol sequence, and then transmit the modulation symbol sequence; correspondingly, the receiving device can receive the modulation symbol sequence and obtain the information to be decoded through demodulation. Modulation refers to the transmitting device mapping the encoded bit sequence to a constellation according to a constellation diagram to obtain the modulation symbol sequence. Demodulation is the reverse process of modulation. Common modulation methods include quadrature amplitude modulation (QAM) and amplitude shift keying (ASK) modulation.

[0092] For example, the encoded bit sequence can be mapped to the modulation symbol sequence by referring to a lookup table or according to a preset rule. Here, only a lookup table is used as an illustration. As shown in Table 1, it is a bit mapping relationship of 8ASK. During the modulation process, the modulation symbol X is determined according to bits b0, b1 and b2, which is used as the modulation symbol to be transmitted.

[0093] Table 1: Mapping between bit values ​​and modulation symbols

[0094]

[0095]

[0096] When using 8ASK modulation, the encoded bit sequence can be mapped to a modulation symbol sequence according to the bit values, referring to Table 1. When using QAM (such as 16QAM, 64QAM, etc.) modulation, the QAM constellation diagram has real and imaginary parts, which can be mapped to the modulation symbol sequence according to Table 1 or other tables, respectively. This application does not elaborate on this further.

[0097] It should be understood that different bits have different functions when mapping the encoded bit sequence to the modulation symbol sequence. For example, in Table 1, bit b0 is used to determine the quadrant of the modulation symbol, so bit b0 is also called the symbol bit. Bits b1 and b2 are used to determine the amplitude of the modulation symbol, so bits b1 and b2 are also called amplitude bits. Furthermore, the transmission reliability of bits b0, b1, and b2 decreases in that order, that is, the transmission reliability satisfies the following relationship: transmission reliability of b0 > transmission reliability of b1 > transmission reliability of b2.

[0098] It should also be understood that the values ​​of the modulation symbols in Table 1 (i.e. the magnitude of X) are only examples. In actual applications, X can be adjusted according to power consumption requirements, such as scaling up or down the multiple X values ​​shown in Table 1 by the same proportion.

[0099] 2. Distribution matching

[0100] Higher-order modulation maps multiple bits to the same modulation symbol, thereby further improving spectral efficiency. Common higher-order modulation methods include 16QAM and 64QAM, without specific limitations. 16QAM maps 4 bits to one modulation symbol, while 64QAM maps 6 bits to one modulation symbol.

[0101] In higher-order modulation, the energy of different modulation symbols may be different. As shown in Table 1 above, the energy of the modulation symbols from high to low is as follows: modulation symbol -7 (modulation symbol 7), modulation symbol -5 (modulation symbol 5), modulation symbol -3 (modulation symbol 3), and modulation symbol -1 (modulation symbol 1). Among them, modulation symbol -7 has the same energy as modulation symbol 7, modulation symbol -5 has the same energy as modulation symbol 5, modulation symbol -3 has the same energy as modulation symbol 3, and modulation symbol -1 has the same energy as modulation symbol 1.

[0102] By transmitting more low-energy modulation symbols and fewer high-energy modulation symbols, average energy can be saved. Theoretical analysis shows that for a Gaussian white noise channel, the information transmitted per unit energy is maximized when the transmitted modulation symbols follow a Gaussian distribution. Compared to a uniform distribution, the Gaussian distribution has the best performance, theoretically offering a performance gain of 1.53 dB.

[0103] Distribution matching, also known as probability shaping or precoding, or simply shaping, is a common shaping technique. A typical flowchart can be found here. Figure 3 . Figure 3 This is a schematic diagram of another processing flow for the information source and the information sink. Figure 3 and Figure 2 The difference is that, Figure 3 The transmitting end device also needs to perform distribution matching, and the receiving end device needs to perform dedistribution matching (or deprobabilistic shaping). For example... Figure 3 As shown, by cascading a precoder before channel coding, information bits are mapped (or "shaped") to a bit sequence that follows a specific distribution. Then, during channel coding, systematic code encoding is used, so that the aforementioned sequence satisfying the specific distribution ultimately appears directly in the coded sequence, thus shaping the final modulation symbols. As an example, the distribution of modulation symbols after "shaping" is as follows... Figure 4 As shown, it can be seen that the probability of low-energy modulation symbols appearing is higher than that of high-energy modulation symbols.

[0104] The current implementation of this symbolic integer method is quite complex.

[0105] This application provides a communication method aimed at improving the performance of probabilistic shaping. The communication method 500 provided in this application is described in detail below.

[0106] Figure 5 A schematic flowchart of the communication method 500 provided in this application. The method includes the following steps.

[0107] It is understood that method 500 can be executed by both the sending device and the receiving device. Unless otherwise specified, "sending device" or "receiving device" can refer to the sending device or receiving device itself, or it can refer to a device that enables the sending device or receiving device to implement this function. For ease of description, the following text will use "sending device" and "receiving device" to describe it. Among them, the sending device can be a terminal device or a network device, and the receiving device can be a terminal device or a network device.

[0108] 510, The sending device acquires the first bit sequence.

[0109] For example, the first bit sequence may include m first subsequences, which are denoted as the 1st first subsequence, the 2nd first subsequence, ..., the mth first subsequence, respectively, and the length of each first subsequence is N.

[0110] Where N is less than or equal to 2N re N re N represents the number of resource units or the number of symbols in a modulation symbol sequence. re The values ​​are predefined or preconfigured, m, N, N re It is a positive integer.

[0111] Before step 510, the above communication method 500 may further include: the transmitting device obtaining a payload bit sequence of length K, where K is a positive integer.

[0112] For example, a payload bit sequence of length K includes a fourth bit sequence and a fifth bit sequence. The first bit sequence mentioned above can be obtained by performing distribution matching on the fourth bit sequence.

[0113] For example, a payload bit sequence of length K can have cyclic redundancy check (CRC) bits added. For example, some or all of the CRC bits can be carried in the fourth bit sequence.

[0114] For example, for 500 payload bits, 100 payload bits (e.g., the fifth bit sequence) are not distributed and matched, while the other 400 payload bits (e.g., the fourth bit sequence) are distributed and matched to obtain a bit sequence that follows a specific distribution, which includes 512 bits; then, channel coding is performed on the 100 information bits and the 512 bits after distribution matching.

[0115] For example, the process of obtaining the first bit sequence by performing distribution matching on the fourth bit sequence can be based on a channel code-based distribution matching method. This channel code can be a polar code, LDPC code, convolutional code, etc. The following explanation uses a polar code-based distribution matching method as an example.

[0116] In one example, after the transmitting device acquires a payload bit sequence of length K, it performs distribution matching on the fourth bit sequence of the payload bit sequence of length K based on the scrambling bit sequence to determine the first bit sequence. The first bit sequence is determined by XORing the scrambling bit sequence and the fourth bit sequence, and the scrambling bit sequence is determined by polar coding of the sixth bit sequence.

[0117] For example, the lengths of the fourth bit sequence, the scrambling bit sequence, and the first bit sequence are all m*N.

[0118] For example, the length of the sixth bit sequence is S, where S = N*(mR) DM ), R DM The bitrate for distribution matching.

[0119] In another example, after the transmitting device obtains a payload bit sequence of length K, it performs distribution matching on the fourth bit sequence within the payload bit sequence of length K to determine the first bit sequence. The first bit sequence is determined by polar code encoding the fourth bit sequence.

[0120] For example, in polar code encoding, the bit sequence to be encoded consists of two parts: one part can be called frozen bits, and the other part can be called auxiliary bits. These auxiliary bits can be used to help shape the first bit sequence. The fourth bit sequence is placed in the set corresponding to the frozen bits during polar code encoding. The bit position.

[0121] For example, the length of the fourth bit sequence is P, and the length of the first bit sequence is m*N, where P = m*N*R. DM P is a positive integer.

[0122] 520. The transmitting device selects either a first scrambling method or a second scrambling method to scramble the first bit sequence according to the conditions satisfied by the bit values ​​in the first bit sequence, thereby obtaining the second bit sequence.

[0123] For example, the second bit sequence may include m second subsequences, which are denoted as the 1st second subsequence, the 2nd second subsequence, ..., the mth second subsequence, respectively, and the length of each second subsequence is N.

[0124] For example, when selecting a first scrambling method or a second scrambling method, the transmitting device may consider the conditions satisfied by the bit values ​​of at least one of the m first subsequences.

[0125] For example, in each of the m first subsequences, the number of 0s is greater than the number of 1s. Or, in each of the m first subsequences, the number of 1s is greater than the number of 0s. Or, in some of the m first subsequences, the number of 0s is greater than the number of 1s, and in another part of the first subsequences, the number of 1s is greater than the number of 0s.

[0126] For example, in the process of obtaining the first bit sequence by distribution matching of the fourth bit sequence, the bit value of each of the m first subsequences can be controlled by setting the log-likelihood ratio (LLR).

[0127] For example, the first scrambling method or the second scrambling method can be selected based on the conditions satisfied by the bit values ​​of the i-th first subsequence among m first subsequences.

[0128] Alternatively, a first scrambling method or a second scrambling method can be selected based on the bit value of the i-th first subsequence among the m first subsequences and the conditions satisfied by at least one first subsequence among the m first subsequences excluding the i-th first subsequence. More specifically, a first scrambling method or a second scrambling method can be selected based on the conditions satisfied by the bit value of the i-th first subsequence among the m first subsequences and the bit value of the (i-1)-th first subsequence. Alternatively, a first scrambling method or a second scrambling method can be selected based on the conditions satisfied by the bit value of the i-th first subsequence, the (i-1)-th first subsequence, and the (i-2)-th first subsequence among the m first subsequences. Alternatively, a first scrambling method or a second scrambling method can be selected based on the conditions satisfied by the bit value of the i-th first subsequence among the m first subsequences and the bit value of the first first subsequence, etc. This application does not limit this.

[0129] The following provides several exemplary methods for selecting the first scrambling method and the second scrambling method.

[0130] Example 1: Select either the first scrambling method or the second scrambling method based on the conditions satisfied by the bit values ​​of the i-th first subsequence and the (i-1)-th first subsequence, where 2≤i≤m.

[0131] For example, when the bit values ​​of the i-th first subsequence and the (i-1)-th first subsequence satisfy the first condition, the first scrambling method is selected to scramble the first bit sequence.

[0132] For example, the first condition mentioned above is: the number of 0s in the i-th first subsequence and the (i-1)-th first subsequence is greater than the number of 1s, or the number of 1s in the i-th first subsequence and the (i-1)-th first subsequence is greater than the number of 0s. Accordingly, the selected first scrambling method can be: the i-th first subsequence, the (i-1)-th first subsequence, and 1 are XORed to obtain the i-th second subsequence.

[0133] It should be understood that the i-th second subsequence is obtained by XORing the i-th first subsequence, the (i-1)-th first subsequence, and a sequence of all 1s of length N. Each bit in the sequence of all 1s of length N has a value of 1.

[0134] For example, the i-th first subsequence can be represented as: The (i-1)th first subsequence can be represented as: A sequence of all 1s of length N can be represented as: 1 0 1 1 1 2 、…、1 N-1 The i-th second subsequence can be represented as Formula 1 can be used to express the first scrambling method for obtaining the second to m-th second subsequences:

[0135]

[0136] Among them, in Formula 1 This represents the XOR operator. This represents the j-th bit in the i-th first subsequence. Represents the j-th bit in the (i-1)-th first subsequence, 1 j This represents the j-th bit in a sequence of all 1s of length N. Let j represent the j-th bit in the i-th second subsequence, where 1 ≤ j ≤ N.

[0137] Alternatively, if the bit values ​​of the i-th first subsequence and the (i-1)-th first subsequence satisfy the second condition, the second scrambling method is selected to scramble the first bit sequence.

[0138] For example, the second condition mentioned above is: the number of 0s in the i-th first subsequence is greater than the number of 1s, and the number of 1s in the (i-1)-th first subsequence is greater than the number of 0s; or, the number of 1s in the i-th first subsequence is greater than the number of 0s, and the number of 0s in the (i-1)-th first subsequence is greater than the number of 1s. Accordingly, the selected second scrambling method can be: the i-th first subsequence and the (i-1)-th first subsequence are XORed to obtain the i-th second subsequence.

[0139] For example, Formula 2 can be used to express the second scrambling method for obtaining the second to m-th second subsequences:

[0140]

[0141] Among them, in formula 2 This represents the XOR operator. This represents the j-th bit in the i-th first subsequence. This represents the j-th bit in the (i-1)-th first subsequence. Let j represent the j-th bit in the i-th second subsequence, where 1 ≤ j ≤ N.

[0142] Additionally, when the bit values ​​of the first subsequence satisfy the third condition, the first scrambling method is selected to scramble the first bit sequence.

[0143] For example, the third condition mentioned above is: the number of 0s in the first subsequence is greater than the number of 1s. Accordingly, the first scrambling method can be: the first subsequence is the same as the first second subsequence.

[0144] For example, Formula 3 can be used to express the first scrambling method for the first second subsequence:

[0145]

[0146] Among them, in formula 3 This represents the XOR operator. This represents the j-th bit in the first subsequence. Let j represent the j-th bit in the first second subsequence, where 1 ≤ j ≤ N.

[0147] Alternatively, if the bit value of the first subsequence satisfies the fourth condition, the second scrambling method is selected to scramble the first bit sequence.

[0148] For example, the fourth condition mentioned above is: the number of 1s in the first subsequence is greater than the number of 0s. Accordingly, the selected second scrambling method can be: the first subsequence and 1 are XORed to obtain the first second subsequence.

[0149] It should be understood that the first second subsequence is obtained by XORing the first first subsequence and a sequence of all 1s of length N, where each bit in the sequence of all 1s of length N has a value of 1.

[0150] For example, Formula 4 can be used to express the second scrambling method for obtaining the first second subsequence:

[0151]

[0152] Among them, in formula 4 This represents the XOR operator. Represents the j-th bit in the first subsequence, 1 j This represents the j-th bit in a sequence of all 1s of length N. Let j represent the j-th bit in the first second subsequence, where 1 ≤ j ≤ N.

[0153] Example 2: Select either the first scrambling method or the second scrambling method based on the conditions satisfied by the bit values ​​of the i-th first subsequence and the bit values ​​of the 1st first subsequence, where 1≤i≤m.

[0154] For example, when the bit values ​​of the i-th first subsequence and the bit values ​​of the 1st first subsequence satisfy the first condition, the first scrambling method is selected to scramble the first bit sequence.

[0155] For example, the first condition mentioned above is: the number of 0s in the i-th first subsequence and the first first subsequence is greater than the number of 1s, or the number of 1s in the i-th first subsequence and the first first subsequence is greater than the number of 0s. Accordingly, the selected first scrambling method can be: the i-th first subsequence, the first first subsequence, and 1 are XORed to obtain the i-th second subsequence.

[0156] It should be understood that the i-th second subsequence is obtained by XORing the i-th first subsequence, the first first subsequence, and a sequence of all 1s of length N. Each bit in the sequence of all 1s of length N has a value of 1.

[0157] For example, the i-th first subsequence can be represented as: The first subsequence can be represented as: A sequence of all 1s of length N can be represented as: 1 0 1 1 1 2 、…、1 N-1 The i-th second subsequence can be represented as Formula 5 can be used to express the first scrambling method for obtaining the first to m-th second subsequences:

[0158]

[0159] Among them, in formula 5 This represents the XOR operator. This represents the j-th bit in the i-th first subsequence. Represents the j-th bit in the first subsequence, 1 j This represents the j-th bit in a sequence of all 1s of length N. Let j represent the j-th bit in the i-th second subsequence, where 1 ≤ j ≤ N.

[0160] Alternatively, if the bit values ​​of the i-th first subsequence and the bit values ​​of the 1st first subsequence satisfy the second condition, the second scrambling method is selected to scramble the first bit sequence.

[0161] For example, the second condition mentioned above is: the number of 0s in the i-th first subsequence is greater than the number of 1s, and the number of 1s in the first subsequence is greater than the number of 0s; or, the number of 1s in the i-th first subsequence is greater than the number of 0s, and the number of 0s in the first subsequence is greater than the number of 1s. Accordingly, the selected second scrambling method can be: the i-th first subsequence and the first subsequence are XORed to obtain the i-th second subsequence.

[0162] For example, Formula 6 can be used to represent the second scrambling method for obtaining the first to m-th second subsequences:

[0163]

[0164] Among them, in formula 6 This represents the XOR operator. This represents the j-th bit in the i-th first subsequence. This represents the j-th bit in the first subsequence. Let j represent the j-th bit in the i-th second subsequence, where 1 ≤ j ≤ N.

[0165] Example 3: Select either the first scrambling method or the second scrambling method based on the conditions satisfied by the bit values ​​of the i-th first subsequence, the (i-1)-th first subsequence, and the (i-2)-th first subsequence, where 3 ≤ i ≤ m.

[0166] For example, when the bit values ​​of the i-th first subsequence, the (i-1)-th first subsequence, and the (i-2)-th first subsequence satisfy the first condition, the first scrambling method is selected to scramble the first bit sequence.

[0167] For example, the first condition mentioned above is: the number of 0s in the i-th first subsequence, the (i-1)-th first subsequence, and the (i-2)-th first subsequence is greater than the number of 1s, or the number of 1s in the i-th first subsequence, the (i-1)-th first subsequence, and the (i-2)-th first subsequence is greater than the number of 0s. Accordingly, the selected first scrambling method can be: the i-th first subsequence, the (i-1)-th first subsequence, the (i-2)-th first subsequence, and 1 are XORed to obtain the i-th second subsequence.

[0168] It should be understood that the i-th second subsequence is obtained by XORing the i-th first subsequence, the (i-1)-th first subsequence, the (i-2)-th first subsequence, and a sequence of all 1s of length N. Each bit in the sequence of all 1s of length N has a value of 1.

[0169] For example, the i-th first subsequence can be represented as: The (i-1)th first subsequence can be represented as:

[0170] The (i-2)th first subsequence can be represented as: A sequence of all 1s of length N can be represented as: 1 0 1 1 1 2 、…、1 N-1 The i-th second subsequence can be represented as The first scrambling method for obtaining the third to m-th second subsequences can be expressed by Equation 7:

[0171]

[0172] Among them, in formula 7 This represents the XOR operator. This represents the j-th bit in the i-th first subsequence. This represents the j-th bit in the (i-1)-th first subsequence. Represents the j-th bit in the (i-2)-th first subsequence, 1 j This represents the j-th bit in a sequence of all 1s of length N. Let j represent the j-th bit in the i-th second subsequence, where 1 ≤ j ≤ N.

[0173] Alternatively, if the bit values ​​of the i-th first subsequence, the (i-1)-th first subsequence, and the (i-2)-th first subsequence satisfy the second condition, the second scrambling method is selected to scramble the first bit sequence.

[0174] For example, the second condition mentioned above is: the number of 0s in at least one of the i-th, (i-1), and (i-2)-th first subsequences is greater than the number of 1s, and the number of 1s in at least one of the i-th, (i-1), and (i-2)-th first subsequences is greater than the number of 0s. Accordingly, the selected second scrambling method can be:

[0175] The i-th first subsequence, the (i-1)-th first subsequence, and the (i-2)-th first subsequence are XORed to obtain the i-th second subsequence.

[0176] For example, Formula 8 can be used to express the second scrambling method for obtaining the third to m-th second subsequences:

[0177]

[0178] Among them, in formula 8 This represents the XOR operator. This represents the j-th bit in the i-th first subsequence. This represents the j-th bit in the (i-1)-th first subsequence. This represents the j-th bit in the (i-2)-th first subsequence. Let j represent the j-th bit in the i-th second subsequence, where 1 ≤ j ≤ N.

[0179] Additionally, when the bit values ​​of the second first subsequence and the bit values ​​of the first first subsequence satisfy the third condition, the first scrambling method is selected to scramble the first bit sequence.

[0180] For example, the third condition mentioned above is: the number of 0s in the second first subsequence and the first first subsequence is greater than the number of 1s, or the number of 1s in the second first subsequence and the first first subsequence is greater than the number of 0s. Accordingly, the selected first scrambling method can be: the second first subsequence, the first first subsequence, and 1 are XORed to obtain the second second subsequence.

[0181] For example, Equation 9 can be used to express the first scrambling method for the second subsequence:

[0182]

[0183] Among them, in formula 9 This represents the XOR operator. This represents the j-th bit in the second first subsequence. Represents the j-th bit in the first subsequence, 1 j This represents the j-th bit in a sequence of all 1s of length N. Let j represent the j-th bit in the second subsequence, where 1 ≤ j ≤ N.

[0184] Alternatively, if the bit values ​​of the second first subsequence and the bit values ​​of the first first subsequence satisfy the fourth condition, the second scrambling method is selected to scramble the first bit sequence.

[0185] For example, the fourth condition mentioned above is: the number of 0s in the second first subsequence is greater than the number of 1s, and the number of 1s in the first first subsequence is greater than the number of 0s; or, the number of 1s in the second first subsequence is greater than the number of 0s, and the number of 0s in the first first subsequence is greater than the number of 1s. Accordingly, the selected second scrambling method can be: the second first subsequence and the first first subsequence are XORed to obtain the second second subsequence.

[0186] For example, Equation 10 can be used to express the second scrambling method for the second subsequence:

[0187]

[0188] Among them, in formula 10 This represents the XOR operator. This represents the j-th bit in the second first subsequence. This represents the j-th bit in the first subsequence. Let j represent the j-th bit in the second subsequence, where 1 ≤ j ≤ N.

[0189] Additionally, when the bit values ​​of the first subsequence satisfy the fifth condition, the first scrambling method is selected to scramble the first bit sequence.

[0190] For example, the fifth condition above is: the number of 0s in the first subsequence is greater than the number of 1s. Accordingly, the first scrambling method can be: the first subsequence is the same as the first second subsequence.

[0191] For example, Equation 11 can be used to express the first scrambling method for obtaining the first second subsequence:

[0192]

[0193] Among them, in formula 11 This represents the XOR operator. This represents the j-th bit in the first subsequence. Let j represent the j-th bit in the first second subsequence, where 1 ≤ j ≤ N.

[0194] Alternatively, if the bit value of the first subsequence satisfies the sixth condition, the second scrambling method is selected to scramble the first bit sequence.

[0195] For example, the sixth condition mentioned above is: the number of 1s in the first subsequence is greater than the number of 0s. Accordingly, the selected second scrambling method can be: the first subsequence and 1 are XORed to obtain the first second subsequence.

[0196] For example, Formula 12 can be used to express the second scrambling method for the first second subsequence:

[0197]

[0198] Among them, in formula 12 This represents the XOR operator. Represents the j-th bit in the first subsequence, 1 j This represents the j-th bit in a sequence of all 1s of length N. Let j represent the j-th bit in the first second subsequence, where 1 ≤ j ≤ N.

[0199] Example 4: Select either the first scrambling method or the second scrambling method based on the bit value of the i-th first subsequence, where 1≤i≤m.

[0200] For example, when the bit value of the i-th first subsequence satisfies the first condition, the first scrambling method is selected to scramble the first bit sequence.

[0201] For example, the first condition mentioned above is: the number of 0s in the i-th first subsequence is greater than the number of 1s. Accordingly, the selected first scrambling method can be: the i-th first subsequence, the third bit sequence, and 1 are XORed to obtain the i-th second subsequence.

[0202] The length of the third bit sequence is N.

[0203] For example, the third bit sequence is either the payload bit in the payload bit sequence of length K, or the third bit sequence belongs to the fifth bit sequence.

[0204] It should be understood that the i-th second subsequence is obtained by XORing the i-th first subsequence, the third bit sequence, and a sequence of all 1s of length N. Each bit in the sequence of all 1s of length N has a value of 1.

[0205] For example, the i-th first subsequence can be represented as: The third bit sequence can be represented as: c 0 c 1 c 2 ..., c N-1 A sequence of all 1s of length N can be represented as: 1 0 1 1 1 2 、…、1 N-1 The i-th second subsequence can be represented as Formula 13 can be used to express the first scrambling method for obtaining the first to m-th second subsequences:

[0206]

[0207] Among them, in formula 13 This represents the XOR operator. c represents the j-th bit in the i-th first subsequence. j Represents the j-th bit in the third bit sequence, 1 j This represents the j-th bit in a sequence of all 1s of length N. Let j represent the j-th bit in the i-th second subsequence, where 1 ≤ j ≤ N.

[0208] Alternatively, when the bit value of the i-th first subsequence satisfies the second condition, the second scrambling method is selected to scramble the first bit sequence.

[0209] For example, the second condition mentioned above is: the number of 1s in the i-th first subsequence is greater than the number of 0s. Accordingly, the selected second scrambling method can be: the i-th first subsequence and the third bit sequence are XORed to obtain the i-th second subsequence.

[0210] For example, Formula 14 can be used to express the second scrambling method for obtaining the first to m-th second subsequences:

[0211]

[0212] Among them, in formula 14 This represents the XOR operator. c represents the j-th bit in the i-th first subsequence. j This represents the j-th bit in the third bit sequence. Let j represent the j-th bit in the i-th second subsequence, where 1 ≤ j ≤ N.

[0213] Example 5: Choose either the first scrambling method or the second scrambling method based on the conditions satisfied by the bit values ​​of the i-th first subsequence and the bit values ​​of the seventh bit sequence, where 1≤i≤m.

[0214] The length of the seventh bit sequence is N.

[0215] For example, the seventh bit sequence can be predefined or preconfigured, and the number of 0s in the seventh bit sequence is greater than the number of 1s, or the number of 1s in the seventh bit sequence is greater than the number of 0s.

[0216] For example, when the bit values ​​of the i-th first subsequence and the bit values ​​of the seventh bit sequence satisfy the first condition, the first scrambling method is selected to scramble the first bit sequence.

[0217] For example, the first condition mentioned above is: the number of 0s in the i-th first subsequence and the seventh bit sequence is greater than the number of 1s, or the number of 1s in the i-th first subsequence and the seventh bit sequence is greater than the number of 0s. Accordingly, the selected first scrambling method can be: the i-th first subsequence, the seventh bit sequence, and 1 are XORed to obtain the i-th second subsequence.

[0218] Alternatively, if the bit values ​​of the i-th first subsequence and the bit values ​​of the seventh bit sequence satisfy the second condition, the second scrambling method is selected to scramble the first bit sequence.

[0219] For example, the second condition mentioned above is: the number of 0s in the i-th first subsequence is greater than the number of 1s and the number of 1s in the seventh bit sequence is greater than the number of 0s, or the number of 1s in the i-th first subsequence is greater than the number of 0s and the number of 0s in the seventh bit sequence is greater than the number of 1s. Accordingly, the selected second scrambling method can be: the i-th first subsequence and the seventh bit sequence are XORed to obtain the i-th second subsequence.

[0220] 530, the transmitting device encodes the second bit sequence to obtain the encoded bit sequence.

[0221] For example, the transmitting device can also encode the second and fifth bit sequences to obtain an encoded bit sequence.

[0222] For example, the encoding method can be polar code, LDPC code, convolutional code, etc., and this application does not limit it.

[0223] Optionally, after step 530, the communication method 500 may further include: the transmitting device performing rate matching on the encoded bit sequence.

[0224] For example, the bit sequence after rate matching can be represented as e0, e1, e2, ... e E-1 .

[0225] Optionally, after step 530, the communication method 500 may further include: the transmitting device performing bit interleaving on the rate-matched bit sequence, wherein the bit interleaving is consistent with Q... m Related, Q m This indicates the modulation order corresponding to the first modulation method.

[0226] For example, the bit sequence after rate matching is e0, e1, e2, ... e E-1 The interleaved bit sequence is f0, f1, f2, ... f E-1 , where f i satisfy:

[0227]

[0228] Where 0≤i≤Q m -1, i and j are both integers, W(i) and Q m Related.

[0229] 540. The transmitting device modulates the encoded bit sequence according to the first modulation method to obtain the modulation symbol sequence.

[0230] For example, the above-mentioned modulation symbol sequence can also be a rate-matched, bit-interleaved, or modulated sequence.

[0231] For example, the first modulation scheme described above can be 8ASK, 16QAM, 64QAM, etc., and this application does not limit it.

[0232] It should be understood that the modulation symbol sequence includes multiple modulation symbols, each of which includes a symbol bit and at least one amplitude bit, with the at least one amplitude bit corresponding to a different transmission reliability.

[0233] For example, the transmitting device can use Gray mapping for modulation, such as using the bit mapping relationships shown in Table 1.

[0234] Alternatively, the transmitting device can use natural mapping for modulation; for example, Table 2 shows the bit mapping relationship of natural mapping for 8ASK.

[0235] Table 2: Mapping between bit values ​​and modulation symbols

[0236]

[0237]

[0238] When using 8ASK modulation, the encoded bit sequence can be mapped to the modulation symbol sequence according to the bit values, referring to Table 2. When using QAM (such as 16QAM, 64QAM, etc.) modulation, the QAM constellation diagram has real and imaginary parts, which can be mapped to the modulation symbol sequence according to Table 2 respectively.

[0239] For example, during modulation, the second bit sequence may be located in at least one amplitude bit included in each modulation symbol. For instance, the i-th second subsequence of m second subsequences included in the second bit sequence may be located in the i-th amplitude bit of at least one amplitude bit, which is the i-th amplitude bit after the at least one amplitude bit is sorted in descending order of reliability.

[0240] It should be understood that the first second subsequence among m second subsequences is located on the amplitude bit with the highest reliability among at least one amplitude bit, the second second subsequence among m second subsequences is located on the amplitude bit with the second highest reliability among at least one amplitude bit, ..., the mth second subsequence among m second subsequences is located on the amplitude bit with the lowest reliability among at least one amplitude bit. Taking 8ASK as an example, 8ASK includes two amplitude bits, b1 and b2, and the transmission reliability of b1 is greater than that of b2. Therefore, the first second subsequence in the second bit sequence is located at b1, and the second second subsequence in the second bit sequence is located at b2.

[0241] For example, Examples 1, 2, and 3 shown in step 520 above can be applied to scrambling before modulation using Gray mapping in the transmitting device.

[0242] For example, Example 4 shown in step 520 above can be applied to the transmitting device to perform scrambling before modulation using natural mapping, where the third bit sequence can be located in the sign bits included in each modulation symbol during modulation.

[0243] 550, The transmitting device sends a sequence of modulation symbols to the receiving device.

[0244] For example, the transmitting device can map a sequence of modulation symbols onto physical resources for transmission.

[0245] Optionally, method 500 may also include processing by the receiving device. This will be explained below in conjunction with methods 560–590.

[0246] 560, The receiving device acquires the information to be demodulated.

[0247] It is understandable that the modulation symbol sequence transmitted by the transmitting device may differ from the modulation symbol sequence received by the receiving device because channel noise signals may be introduced during transmission. This will be illustrated using the example of the receiving device obtaining the demodulated information from the transmitting device.

[0248] 570. The receiving device demodulates the information to be demodulated to obtain the information to be decoded.

[0249] Optionally, after step 570, the communication method 500 may further include: the receiving device performing bit deinterleaving on the information to be decoded, wherein the bit deinterleaving is related to the parameter Q in the modulation order. m Related.

[0250] For example, the demodulated bit sequence is f0, f1, f2, ... f E-1 The deinterleaved bit sequence is e0, e1, e2, ... e E-1 ei satisfy:

[0251]

[0252] Where 0≤i≤Q m -1, i and j are both integers, W(i) and Q m Related, Q m Indicates the modulation order.

[0253] It should be understood that the demodulation process described above can be the inverse operation of the modulation process in step 540 above. By demodulation, the bit information of each modulation symbol can be obtained. Some of the descriptions can be found in step 540 above, and will not be repeated here.

[0254] 580. The receiving device decodes the information to be decoded to obtain the decoded bit sequence.

[0255] For example, the decoded bit sequence can be both bit deinterleaved and the decoded sequence.

[0256] Specifically, the decoded bit sequence includes the second bit sequence, or the decoded bit sequence includes the second bit sequence and the fifth bit sequence.

[0257] It should be understood that the above decoding process can be the reverse operation of the encoding process in step 530 above. Some of the descriptions can be found in step 530 above, and will not be repeated here.

[0258] 590. The receiving device selects either the first descrambling method or the second descrambling method to descramble the second bit sequence based on the conditions satisfied by the bit values ​​in the first bit sequence, thereby obtaining the first bit sequence.

[0259] For example, when selecting a first descrambling method or a second descrambling method, the receiving device may consider the conditions satisfied by the bit values ​​of at least one of the m first subsequences.

[0260] For example, the first descrambling method or the second descrambling method can be selected based on the conditions satisfied by the bit values ​​of the i-th first subsequence among the m first subsequences.

[0261] Alternatively, a first descrambling method or a second descrambling method can be selected based on the bit value of the i-th first subsequence among the m first subsequences and the conditions satisfied by at least one first subsequence among the m first subsequences excluding the i-th first subsequence. More specifically, a first descrambling method or a second descrambling method can be selected based on the conditions satisfied by the bit value of the i-th first subsequence among the m first subsequences and the bit value of the (i-1)-th first subsequence. Alternatively, a first descrambling method or a second descrambling method can be selected based on the conditions satisfied by the bit value of the i-th first subsequence, the (i-1)-th first subsequence, and the (i-2)-th first subsequence among the m first subsequences. Alternatively, a first descrambling method or a second descrambling method can be selected based on the conditions satisfied by the bit value of the i-th first subsequence among the m first subsequences and the bit value of the first first subsequence, etc. This application does not limit this.

[0262] The following provides several exemplary methods for selecting the first descrambling method and the second descrambling method.

[0263] One example is to select either the first descrambling method or the second descrambling method based on the conditions satisfied by the bit values ​​of the i-th first subsequence and the (i-1)-th first subsequence, where 2 ≤ i ≤ m.

[0264] For example, when the bit values ​​of the i-th first subsequence and the (i-1)-th first subsequence satisfy the first condition, the first descrambling method is selected to descramble the second bit sequence.

[0265] For example, the first condition mentioned above is: the number of 0s in the i-th first subsequence and the (i-1)-th first subsequence is greater than the number of 1s, or the number of 1s in the i-th first subsequence and the (i-1)-th first subsequence is greater than the number of 0s. Accordingly, the selected first descrambling method can be: the i-th second subsequence, the (i-1)-th first subsequence, and 1 are XORed to obtain the i-th first subsequence.

[0266] Alternatively, if the bit values ​​of the i-th first subsequence and the (i-1)-th first subsequence satisfy the second condition, the second descrambling method is selected to descramble the second bit sequence.

[0267] For example, the second condition mentioned above is: the number of 0s in the i-th first subsequence is greater than the number of 1s, and the number of 1s in the (i-1)-th first subsequence is greater than the number of 0s; or, the number of 1s in the i-th first subsequence is greater than the number of 0s, and the number of 0s in the (i-1)-th first subsequence is greater than the number of 1s. Accordingly, the selected second descrambling method can be: the i-th second subsequence and the (i-1)-th first subsequence are XORed to obtain the i-th first subsequence.

[0268] Additionally, when the bit values ​​of the first subsequence satisfy the third condition, the first descrambling method is selected to descramble the second bit sequence.

[0269] For example, the third condition mentioned above is: the number of 0s in the first subsequence is greater than the number of 1s. Accordingly, the first descrambling method can be: the first second subsequence is the same as the first first subsequence.

[0270] Alternatively, if the bit value of the first subsequence satisfies the fourth condition, the second descrambling method is selected to descramble the second bit sequence.

[0271] For example, the fourth condition mentioned above is: the number of 1s in the first subsequence is greater than the number of 0s. Accordingly, the selected second descrambling method can be: the first subsequence is obtained by XORing the first second subsequence with 1s.

[0272] It should be understood that the descrambling process described above can correspond to the scrambling process in Example 1 of Step 520 above. Some descriptions can be found in Example 1 of Step 520 above, and will not be repeated here. For example, the first descrambling method described above can be the inverse operation of the first scrambling method shown in Example 1 of Step 520 above, and the second descrambling method described above can be the inverse operation of the second scrambling method shown in Example 1 of Step 520 above.

[0273] Another example is to select either the first descrambling method or the second descrambling method based on the conditions satisfied by the bit values ​​of the i-th first subsequence and the bit values ​​of the 1st first subsequence, where 1≤i≤m.

[0274] For example, when the bit values ​​of the i-th first subsequence and the bit values ​​of the 1st first subsequence satisfy the first condition, the first descrambling method is selected to descramble the second bit sequence.

[0275] For example, the first condition mentioned above is: the number of 0s in the i-th first subsequence and the first first subsequence is greater than the number of 1s, or the number of 1s in the i-th first subsequence and the first first subsequence is greater than the number of 0s. Accordingly, the selected first descrambling method can be: the i-th second subsequence, the first first subsequence, and 1 are XORed to obtain the i-th first subsequence.

[0276] Alternatively, if the bit values ​​of the i-th first subsequence and the bit values ​​of the 1st first subsequence satisfy the second condition, the second descrambling method is selected to descramble the second bit sequence.

[0277] For example, the second condition mentioned above is: the number of 0s in the i-th first subsequence is greater than the number of 1s, and the number of 1s in the first subsequence is greater than the number of 0s; or, the number of 1s in the i-th first subsequence is greater than the number of 0s, and the number of 0s in the first subsequence is greater than the number of 1s. Accordingly, the selected second descrambling method can be: the i-th second subsequence and the first first subsequence are XORed to obtain the i-th first subsequence.

[0278] It should be understood that the descrambling process described above can correspond to the scrambling process in Example 2 of Step 520 above. Some descriptions can be found in Example 2 of Step 520 above, and will not be repeated here. For example, the first descrambling method described above can be the inverse operation of the first scrambling method shown in Example 2 of Step 520 above, and the second descrambling method described above can be the inverse operation of the second scrambling method shown in Example 2 of Step 520 above.

[0279] Another example is to select either the first descrambling method or the second descrambling method based on the conditions satisfied by the bit values ​​of the i-th first subsequence, the (i-1)-th first subsequence, and the (i-2)-th first subsequence, where 3 ≤ i ≤ m.

[0280] For example, when the bit values ​​of the i-th first subsequence, the (i-1)-th first subsequence, and the (i-2)-th first subsequence satisfy the first condition, the first descrambling method is selected to descramble the second bit sequence.

[0281] For example, the first condition mentioned above is: the number of 0s in the i-th first subsequence, the (i-1)-th first subsequence, and the (i-2)-th first subsequence is greater than the number of 1s, or the number of 1s in the i-th first subsequence, the (i-1)-th first subsequence, and the (i-2)-th first subsequence is greater than the number of 0s. Accordingly, the selected first descrambling method can be: the i-th second subsequence, the (i-1)-th first subsequence, the (i-2)-th first subsequence, and 1 are XORed to obtain the i-th first subsequence.

[0282] Alternatively, if the bit values ​​of the i-th first subsequence, the (i-1)-th first subsequence, and the (i-2)-th first subsequence satisfy the second condition, the second descrambling method is selected to descramble the second bit sequence.

[0283] For example, the second condition mentioned above is: the number of 0s in at least one of the i-th, (i-1), and (i-2)-th first subsequences is greater than the number of 1s, and the number of 1s in at least one of the i-th, (i-1), and (i-2)-th first subsequences is greater than the number of 0s. Accordingly, the selected second descrambling method can be: obtaining the i-th first subsequence by XORing the i-th second subsequence, the (i-1)-th first subsequence, and the (i-2)-th first subsequence.

[0284] Additionally, when the bit values ​​of the second first subsequence and the first first subsequence satisfy the third condition, the first descrambling method is selected to descramble the second bit sequence.

[0285] For example, the third condition mentioned above is: the number of 0s in the second first subsequence and the first first subsequence is greater than the number of 1s, or the number of 1s in the second first subsequence and the first first subsequence is greater than the number of 0s. Accordingly, the selected first descrambling method can be: the second second subsequence, the first first subsequence, and 1 are XORed to obtain the second first subsequence.

[0286] Alternatively, if the bit values ​​of the second first subsequence and the bit values ​​of the first first subsequence satisfy the fourth condition, the second descrambling method is selected to descramble the second bit sequence.

[0287] For example, the fourth condition mentioned above is: the number of 0s in the second first subsequence is greater than the number of 1s, and the number of 1s in the first first subsequence is greater than the number of 0s; or, the number of 1s in the second first subsequence is greater than the number of 0s, and the number of 0s in the first first subsequence is greater than the number of 1s. Accordingly, the selected second descrambling method can be: the second second subsequence and the first first subsequence are XORed to obtain the second first subsequence.

[0288] Additionally, when the bit values ​​of the first subsequence satisfy the fifth condition, the first descrambling method is selected to descramble the second bit sequence.

[0289] For example, the fifth condition above is: the number of 0s in the first subsequence is greater than the number of 1s. Accordingly, the first descrambling method can be: the first second subsequence is the same as the first first subsequence.

[0290] Alternatively, if the bit value of the first subsequence satisfies the sixth condition, the second descrambling method is selected to descramble the second bit sequence.

[0291] For example, the sixth condition mentioned above is: the number of 1s in the first subsequence is greater than the number of 0s. Accordingly, the selected second descrambling method can be: the first subsequence is obtained by XORing the first second subsequence with 1s.

[0292] It should be understood that the descrambling process described above can correspond to the scrambling process in Example 3 of Step 520 above. Some descriptions can be found in Example 3 of Step 520 above, and will not be repeated here. For example, the first descrambling method described above can be the inverse operation of the first scrambling method shown in Example 3 of Step 520 above, and the second descrambling method described above can be the inverse operation of the second scrambling method shown in Example 3 of Step 520 above.

[0293] Another example is to select either the first descrambling method or the second descrambling method based on the bit value of the i-th first subsequence, where 1≤i≤m.

[0294] For example, when the bit value of the i-th first subsequence satisfies the first condition, the first descrambling method is selected to descramble the second bit sequence.

[0295] For example, the first condition mentioned above is: the number of 0s in the i-th first subsequence is greater than the number of 1s. Accordingly, the first descrambling method selected can be: the i-th second subsequence, the third bit sequence, and 1 are XORed to obtain the i-th first subsequence.

[0296] Alternatively, when the bit value of the i-th first subsequence satisfies the second condition, the second descrambling method is selected to descramble the second bit sequence.

[0297] For example, the second condition mentioned above is: the number of 1s in the i-th first subsequence is greater than the number of 0s. Accordingly, the selected second descrambling method can be: the i-th second subsequence and the third bit sequence are XORed to obtain the i-th first subsequence.

[0298] It should be understood that the descrambling process described above can correspond to the scrambling process in Example 4 of Step 520 above. Some descriptions can be found in Example 4 of Step 520 above, and will not be repeated here. For example, the first descrambling method described above can be the inverse operation of the first scrambling method shown in Example 4 of Step 520 above, and the second descrambling method described above can be the inverse operation of the second scrambling method shown in Example 4 of Step 520 above.

[0299] Another example is to select either the first descrambling method or the second descrambling method based on the conditions satisfied by the bit values ​​of the i-th first subsequence and the bit values ​​of the seventh bit sequence, where 1≤i≤m.

[0300] For example, when the bit values ​​of the i-th first subsequence and the bit values ​​of the seventh bit sequence satisfy the first condition, the first descrambling method is selected to descramble the second bit sequence.

[0301] For example, the first condition mentioned above is: the number of 0s in the i-th first subsequence and the seventh bit sequence is greater than the number of 1s, or the number of 1s in the i-th first subsequence and the seventh bit sequence is greater than the number of 0s. Accordingly, the selected first descrambling method can be: the i-th second subsequence, the seventh bit sequence, and 1 are XORed to obtain the i-th first subsequence.

[0302] Alternatively, if the bit values ​​of the i-th first subsequence and the bit values ​​of the seventh bit sequence satisfy the second condition, the second descrambling method is selected to descramble the second bit sequence.

[0303] For example, the second condition mentioned above is: the number of 0s in the i-th first subsequence is greater than the number of 1s and the number of 1s in the seventh bit sequence is greater than the number of 0s, or the number of 1s in the i-th first subsequence is greater than the number of 0s and the number of 0s in the seventh bit sequence is greater than the number of 1s. Accordingly, the selected second descrambling method can be: the i-th second subsequence and the seventh bit sequence are XORed to obtain the i-th first subsequence.

[0304] It should be understood that the descrambling process described above can correspond to the scrambling process in Example 5 of Step 520 above. Some descriptions can be found in Example 5 of Step 520 above, and will not be repeated here. For example, the first descrambling method described above can be the inverse operation of the first scrambling method shown in Example 5 of Step 520 above, and the second descrambling method described above can be the inverse operation of the second scrambling method shown in Example 5 of Step 520 above.

[0305] Optionally, after step 590, the communication method 500 may further include: the receiving device performing dedistribution matching on the first bit sequence to obtain the fourth bit sequence.

[0306] Based on the above process, the receiving device can obtain the original payload bit sequence.

[0307] Based on the above Figure 5 The method provided in the embodiment of this application, as shown, considers the bit values ​​in the bit sequence to be scrambled when scrambling the bit sequence before encoding. That is, different scrambling methods can be used for scrambling under different bit values, which can specifically increase the probability of low-energy symbols appearing and improve the probability shaping effect.

[0308] The above is a detailed description of the communication method provided in this application.

[0309] It is understood that the steps in the above figures are merely illustrative and are not intended to be strictly limited. Furthermore, the sequence numbers of the processes described above do not imply a specific order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0310] It is also understood that some optional features in the various embodiments of this application may not depend on other features in some scenarios, or may be combined with other features in some scenarios, without limitation.

[0311] It is also understood that, in the above-described method embodiments, the methods and operations implemented by the device (transmitting device or receiving device) can also be implemented by components of the device (such as chips or circuits), without limitation.

[0312] The communication device provided in this application is described below.

[0313] Figure 6 This is a schematic structural diagram of the communication device 600 provided in this application. The communication device 600 can be a transmitting device, or a device applied to the transmitting device that can realize the corresponding functions of the transmitting device in the method embodiments of this application, such as a chip, processor, or circuit. Alternatively, the communication device 600 can be a receiving device, or a device applied to the receiving device that can realize the corresponding functions of the receiving device in the method embodiments of this application, such as a chip, processor, or circuit.

[0314] Optionally, the communication device 600 includes a processing module 601, which may be a processor, a processing board, a processing unit, or a processing device, etc. When the communication device 600 is a transmitting device or a device applied to a transmitting device, the processing module 601 is used to select a first scrambling method or a second scrambling method to scramble the first bit sequence according to the conditions satisfied by the bit values ​​in the first bit sequence, to encode the second bit sequence, and to modulate the encoded bit sequence according to a first modulation method, etc. Specific processes can be found in the detailed descriptions of the corresponding steps in the method embodiments, and will not be repeated here. When the communication device 600 is a receiving device or a device applied to a receiving device, the processing module 601 is used to demodulate the information to be demodulated, to decode the information to be decoded, and to descramble the second bit sequence according to the conditions satisfied by the bit values ​​in the first bit sequence, using a first descrambling method or a second descrambling method, etc. Specific processes can be found in the detailed descriptions of the corresponding steps in the method embodiments, and will not be repeated here.

[0315] Optionally, the communication device 600 further includes a communication module 602, which may also be referred to as a transceiver module, transceiver, transceiver unit, or transceiver device, etc., for performing receiving (or input) and / or sending (or output) operations. For example, when the communication device 600 is a transmitting device or a device applied to a transmitting device, the communication module 602 can be used to acquire a first bit sequence and transmit the first bit sequence to the processing module 601; and output the modulation symbol sequence obtained by the processing module 601. Similarly, when the communication device 600 is a receiving device or a device applied to a receiving device, the communication module 602 can be used to receive information to be demodulated and transmit the information to be demodulated to the processing module 601; and output the original payload bit sequence obtained by the processing module 601 after descrambling. It should be understood that the aforementioned communication module and / or processing module can be implemented by virtual modules. For example, the processing module can be implemented by a software functional unit or a virtual device, and the communication module can be implemented by a software function or a virtual device. Alternatively, the processing module or communication module can also be implemented by a physical device, such as a chip / circuit (e.g., an integrated circuit or logic circuit). The communication module can be an input / output circuit and / or a communication interface, performing input operations (corresponding to the aforementioned receiving operation) and output operations (corresponding to the aforementioned sending operation); the processing module is an integrated processor, microprocessor, or circuit (e.g., an integrated circuit, logic circuit).

[0316] The module division in this application is illustrative and represents only one logical functional division. In actual implementation, other division methods are possible. Furthermore, the functional modules in the various examples of this application can be integrated into a single processor, exist as separate physical entities, or be integrated into a single module. The integrated modules described above can be implemented in hardware, as software functional modules, or a combination of hardware and software.

[0317] Figure 7This is a schematic structural diagram of another communication device provided in this application. The communication device 700 can be used to implement the functions of any communication device (e.g., a transmitting device or a receiving device) in the communication system described in the foregoing examples. The communication device 700 may include at least one processor 710. Optionally, the processor 710 (or processing device) is coupled to a memory, which may be located within the communication device, integrated with the processor, or located outside the communication device. For example, the communication device 700 may also include at least one memory 720. The memory 720 stores computer programs, instructions, or data necessary for implementing any of the above method embodiments; the processor 710 may execute the computer programs, instructions, or data stored in the memory 720 to perform the corresponding functions of the transmitting device or receiving device in any of the above embodiments.

[0318] Optionally, the communication device 700 may further include a communication interface 730, through which the communication device 700 can interact with other devices. For example, the communication interface 730 may be a transceiver, circuit, bus, module, pin, or other type of communication interface. When the communication device 700 is a chip-based device or circuit, the communication interface 730 may also be an input / output circuit, capable of inputting information (or receiving information) and / or outputting information (or sending information). The processor may be an integrated circuit or logic circuit, etc., and the processor can determine the output information based on the input information.

[0319] The coupling in this application refers to indirect coupling or communication connection between devices, units, or modules, which can be electrical, mechanical, or other forms, used for information exchange between devices, units, or modules. The processor 710 may operate in conjunction with the memory 720 and the communication interface 730. This application does not limit the connection medium between the processor 710, the memory 720, and the communication interface 730.

[0320] Figure 8 This is a schematic structural diagram of the chip provided in this application. Chip 800 includes a circuit 801 and a communication interface 802. Circuit 801 can be a logic circuit, integrated circuit, etc., and communication interface 802 can also be called an input / output circuit, input / output interface, interface circuit, etc., and can input information (or receive information) or output information (or send information). Chip 800 can execute the methods performed by the transmitting or receiving device in the various embodiments of this application.

[0321] In addition, this application also provides a computer-readable storage medium storing computer instructions, which, when executed on a computer, cause the operations and / or processes performed by the sending or receiving device in the various method embodiments of this application to be executed.

[0322] This application also provides a computer program product, which includes computer program code or instructions. When the computer program code or instructions are run on a computer, the operations and / or processes performed by the sending end device or the receiving end device in the various method embodiments of this application are executed.

[0323] Furthermore, this application also provides a chip including a processor. A memory for storing a computer program is provided independently of the chip, and the processor is used to execute the computer program stored in the memory, so that operations and / or processes performed by a transmitting or receiving device in any method embodiment are executed. Further, the chip may also include a communication interface. The communication interface may be an input / output interface or an interface circuit, etc. Further, the chip may also include the memory.

[0324] This application provides a communication system, including the transmitting end device and the receiving end device in the above method embodiments.

[0325] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0326] The processor in this application embodiment has signal processing capabilities and can be a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in this application can be directly implemented by the hardware processor, or implemented by a combination of hardware and software modules within the processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above methods.

[0327] In the embodiments of this application, the memory can be volatile memory or non-volatile memory, or it can include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0328] The technical solutions provided in this application can be implemented in whole or in part through software, hardware, firmware, or any combination thereof. When implemented using software, they can be implemented in whole or in part as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a terminal device, an access network device, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., digital video discs (DVDs)), or semiconductor media, etc.

[0329] In the embodiments of this application, "at least one" refers to one or more items. "More than one" means two or more items. "And / or" is used to describe the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0330] The term "comprising" and any variations thereof used in the embodiments of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the steps or units listed, but may optionally include other steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0331] In this application, examples may reference each other without logical contradiction. For example, methods and / or terms between method embodiments may reference each other, functions and / or terms between device embodiments may reference each other, and functions and / or terms between device examples and method examples may reference each other.

[0332] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0333] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0334] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0335] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0336] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

Claims

1. A communication method, characterized in that, The method includes: Obtain the first bit sequence; Based on the conditions satisfied by the bit values ​​in the first bit sequence, either the first scrambling method or the second scrambling method is selected to scramble the first bit sequence to obtain the second bit sequence.

2. The method according to claim 1, characterized in that, The first bit sequence includes m first subsequences, each of which has a length of N; the second bit sequence includes m second subsequences, each of which has a length of N. Where N is less than or equal to 2N re N re Indicates the number of resource units, m, N, N re It is a positive integer.

3. The method according to claim 2, characterized in that, The step of selecting a first scrambling method or a second scrambling method to scramble the first bit sequence based on the conditions satisfied by the bit values ​​in the first bit sequence includes: selecting the first scrambling method or the second scrambling method to scramble the first bit sequence based on the conditions satisfied by the bit values ​​of the i-th first subsequence among the m first subsequences and the bit values ​​of one or more first subsequences other than the i-th first subsequence among the m first subsequences, where 1≤i≤m.

4. The method according to claim 2 or 3, characterized in that, The step of selecting a first scrambling method or a second scrambling method to scramble the first bit sequence based on the conditions satisfied by the bit values ​​in the first bit sequence includes: selecting the first scrambling method or the second scrambling method to scramble the first bit sequence based on the conditions satisfied by the bit values ​​of the i-th first subsequence and the (i-1)-th first subsequence in the m first subsequences, where 2≤i≤m.

5. The method according to claim 4, characterized in that, The step of selecting a first scrambling method or a second scrambling method to scramble the first bit sequence based on the conditions satisfied by the bit values ​​in the first bit sequence includes: selecting the first scrambling method to scramble the first bit sequence when the bit values ​​of the i-th first sub-sequence and the bit values ​​of the (i-1)-th first sub-sequence satisfy a first condition; Wherein, the first condition is: the number of 0s in the i-th first subsequence and the (i-1)-th first subsequence is greater than the number of 1s, or the number of 1s in the i-th first subsequence and the (i-1)-th first subsequence is greater than the number of 0s; the first scrambling method is: the i-th first subsequence, the (i-1)-th first subsequence, and 1 are XORed to obtain the i-th second subsequence among the m second subsequences.

6. The method according to claim 4, characterized in that, The step of selecting a first scrambling method or a second scrambling method to scramble the first bit sequence based on the conditions satisfied by the bit values ​​in the first bit sequence includes: when the bit value of the i-th first subsequence and the bit value of the (i-1)-th first subsequence in the first bit sequence satisfy a second condition, selecting the second scrambling method to scramble the first bit sequence. The second condition is: the number of 0s in the i-th first subsequence is greater than the number of 1s and the number of 1s in the (i-1)-th first subsequence is greater than the number of 0s, or the number of 1s in the i-th first subsequence is greater than the number of 0s in the (i-1)-th first subsequence is greater than the number of 1s; the second scrambling method is: the i-th first subsequence and the (i-1)-th first subsequence are XORed to obtain the i-th second subsequence among the m second subsequences.

7. The method according to claim 4, characterized in that, The step of selecting a first scrambling method or a second scrambling method to scramble the first bit sequence based on the conditions satisfied by the bit values ​​in the first bit sequence includes: selecting the first scrambling method to scramble the first bit sequence when the bit value of the first first subsequence in the first bit sequence satisfies a third condition; The third condition is that there are more 0s than 1s in the first subsequence; the first scrambling method is that the first subsequence is the same as the first second subsequence among the m second subsequences.

8. The method according to claim 4, characterized in that, The step of selecting a first scrambling method or a second scrambling method to scramble the first bit sequence according to the conditions satisfied by the bit values ​​in the first bit sequence includes: when the bit value of the first subsequence in the first bit sequence satisfies the fourth condition, selecting the second scrambling method to scramble the first bit sequence; The fourth condition is that there are more 1s than 0s in the first subsequence; the second scrambling method is that the first subsequence and 1 are XORed to obtain the first second subsequence among the m second subsequences.

9. The method according to claim 2, characterized in that, The step of selecting a first scrambling method or a second scrambling method to scramble the first bit sequence according to the conditions satisfied by the bit values ​​in the first bit sequence includes: when the bit value of the i-th first subsequence in the m first subsequences satisfies the first condition, selecting the first scrambling method to scramble the first bit sequence; The first condition is that there are more 0s than 1s in the i-th first subsequence; the first scrambling method is that the i-th first subsequence, the third bit sequence, and 1 are XORed to obtain the i-th second subsequence among the m second subsequences. The length of the third bit sequence is N.

10. The method according to claim 2, characterized in that, The step of selecting a first scrambling method or a second scrambling method to scramble the first bit sequence according to the conditions satisfied by the bit values ​​in the first bit sequence includes: when the bit value of the i-th first subsequence in the m first subsequences satisfies the second condition, selecting the second scrambling method to scramble the first bit sequence; The second condition is that there are more 1s than 0s in the i-th first subsequence; the second scrambling method is that the i-th first subsequence and the third bit sequence are XORed to obtain the i-th second subsequence among the m second subsequences. The length of the third bit sequence is N.

11. The method according to any one of claims 2 to 10, characterized in that, The method further includes: The second bit sequence is encoded to obtain the encoded bit sequence; The encoded bit sequence is modulated according to the first modulation method to obtain a modulation symbol sequence. The modulation symbol sequence includes multiple modulation symbols, each of which includes one or more amplitude bits. The i-th second subsequence among the m second subsequences is located at the i-th amplitude bit among the one or more amplitude bits. The i-th amplitude bit is the i-th amplitude bit after the one or more amplitude bits are sorted from highest to lowest reliability.

12. A communication method, characterized in that, The method includes: Obtain the decoded bit sequence, wherein the decoded bit sequence includes a second bit sequence; Based on the conditions satisfied by the bit values ​​in the first bit sequence, either the first descrambling method or the second descrambling method is selected to descramble the second bit sequence to obtain the first bit sequence.

13. The method according to claim 12, characterized in that, The first bit sequence includes m first subsequences, each of which has a length of N; the second bit sequence includes m second subsequences, each of which has a length of N. Where N is less than or equal to 2N re N re Indicates the number of resource units, m, N, N re It is a positive integer.

14. The method according to claim 13, characterized in that, The step of selecting a first descrambling method or a second descrambling method to descramble the second bit sequence based on the conditions satisfied by the bit values ​​in the first bit sequence includes: selecting the first descrambling method or the second descrambling method to descramble the second bit sequence based on the conditions satisfied by the bit values ​​of the i-th first subsequence among the m first subsequences and the bit values ​​of one or more first subsequences other than the i-th first subsequence among the m first subsequences, where 1≤i≤m.

15. The method according to claim 13 or 14, characterized in that, The step of selecting a first descrambling method or a second descrambling method to descramble the second bit sequence based on the conditions satisfied by the bit values ​​in the first bit sequence includes: selecting the first descrambling method or the second descrambling method to descramble the second bit sequence based on the conditions satisfied by the bit values ​​of the i-th first subsequence and the (i-1)-th first subsequence in the m first subsequences, where 2≤i≤m.

16. The method according to claim 15, characterized in that, The step of selecting a first descrambling method or a second descrambling method to descramble the second bit sequence based on the conditions satisfied by the bit values ​​in the first bit sequence includes: selecting the first descrambling method to descramble the second bit sequence when the bit value of the i-th first subsequence and the bit value of the (i-1)-th first subsequence in the first bit sequence satisfy the first condition; Wherein, the first condition is: the number of 0s in the i-th first subsequence and the (i-1)-th first subsequence is greater than the number of 1s, or the number of 1s in the i-th first subsequence and the (i-1)-th first subsequence is greater than the number of 0s; the first descrambling method is: the i-th second subsequence in the m second subsequences, the (i-1)-th first subsequence and 1 are XORed to obtain the i-th first subsequence.

17. The method according to claim 15, characterized in that, The step of selecting a first descrambling method or a second descrambling method to descramble the second bit sequence based on the conditions satisfied by the bit values ​​in the first bit sequence includes: selecting the second descrambling method to descramble the second bit sequence when the bit value of the i-th first subsequence and the bit value of the (i-1)-th first subsequence in the first bit sequence satisfy a second condition; The second condition is: the number of 0s in the i-th first subsequence is greater than the number of 1s and the number of 1s in the (i-1)-th first subsequence is greater than the number of 0s, or the number of 1s in the i-th first subsequence is greater than the number of 0s in the (i-1)-th first subsequence is greater than the number of 1s; the second descrambling method is: the i-th second subsequence and the (i-1)-th first subsequence in the m second subsequences are XORed to obtain the i-th first subsequence.

18. The method according to claim 15, characterized in that, The step of selecting a first descrambling method or a second descrambling method to descramble the second bit sequence based on the conditions satisfied by the bit values ​​in the first bit sequence includes: when the bit value of the first subsequence in the first bit sequence satisfies a third condition, selecting the first descrambling method to descramble the second bit sequence; The third condition is that the first subsequence of the m first subsequences contains more 0s than 1s; the first descrambling method is that the first second subsequence of the m second subsequences is the same as the first first subsequence.

19. The method according to claim 15, characterized in that, The step of selecting a first descrambling method or a second descrambling method to descramble the second bit sequence based on the conditions satisfied by the bit values ​​in the first bit sequence includes: when the bit value of the first subsequence in the first bit sequence satisfies the fourth condition, selecting the second descrambling method to descramble the second bit sequence; The fourth condition is that there are more 1s than 0s in the first subsequence; the second descrambling method is that the first subsequence in the m second subsequences and 1 are XORed to obtain the first subsequence.

20. The method according to claim 13, characterized in that, The step of selecting a first descrambling method or a second descrambling method to descramble the second bit sequence based on the conditions satisfied by the bit values ​​in the first bit sequence includes: when the bit value of the i-th first subsequence in the first bit sequence satisfies the first condition, selecting the first descrambling method to descramble the second bit sequence; The first condition is that there are more 0s than 1s in the i-th first subsequence; the first descrambling method is that the i-th second subsequence, the third bit sequence, and 1 in the m second subsequences are XORed to obtain the i-th first subsequence; The length of the third bit sequence is N.

21. The method according to claim 13, characterized in that, The step of selecting a first descrambling method or a second descrambling method to descramble the second bit sequence based on the conditions satisfied by the bit values ​​in the first bit sequence includes: when the bit value of the i-th first subsequence in the first bit sequence satisfies the second condition, selecting the second descrambling method to descramble the second bit sequence; The second condition is that there are more 1s than 0s in the i-th first subsequence; the second descrambling method is that the i-th second subsequence and the third bit sequence in the m second subsequences are XORed to obtain the i-th first subsequence. The length of the third bit sequence is N.

22. The method according to any one of claims 13 to 21, characterized in that, The method further includes: Obtain the demodulation information, which includes multiple modulation symbols, each modulation symbol including one or more amplitude bits, the i-th second subsequence in the m second subsequences is located in the i-th amplitude bit in the one or more amplitude bits, and the i-th amplitude bit is the i-th amplitude bit after the one or more amplitude bits are sorted from highest to lowest reliability; The information to be demodulated is demodulated according to the first demodulation method to obtain the information to be decoded; Obtaining the decoded bit sequence includes: decoding the information to be decoded to obtain the decoded bit sequence.

23. A communication device, characterized in that, The communication device includes one or more processors, the one or more processors being configured to cause the method of any one of claims 1-11 to be performed by the communication device, or the one or more processors being configured to cause the communication device to perform the method of any one of claims 12-22.

24. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed on a computer, implement the method as described in any one of claims 1-22.

25. A computer program product, characterized in that, The computer program product includes a computer program that, when run on a computer, causes the method as described in any one of claims 1-11 to be performed, or causes the method as described in any one of claims 12-22 to be performed.

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