A multi-core SoC integrated triple-play multi-service terminal remote fault diagnosis system

Abstract

The application relates to the technical field of intelligent operation and maintenance, and discloses a multi-core SoC integrated triple-play multi-service terminal remote fault diagnosis system, which comprises the following: a multi-core SoC processing module that performs service analysis and routing distribution of multi-source signals; a state extraction module that acquires underlying physical core operation parameters and hardware environment temperature data; a cross-layer mapping module that establishes address binding of digital byte streams, target thread identifiers and underlying physical parameters corresponding to three types of services (cable television, network IP and wireless access) by injecting dyeing labels, and generates a cross-layer mapping relationship chain; an abnormality diagnosis interaction module that reports corresponding cross-layer mapping relationship chains when detecting service delay abnormalities; and a remote diagnosis server that locates fault nodes according to the cross-layer mapping relationship chains and issues resource rescheduling instructions to adjust terminal underlying system resources. The application realizes the correlation of software and hardware states, and solves the problems of terminal underlying fault tracing difficulty and resource rescheduling lag.

Description

Technical Field

[0001] This invention relates to the field of intelligent operation and maintenance technology, and in particular to a remote fault diagnosis system for a multi-core SoC integrated triple-network converged multi-service terminal. Background Technology

[0002] With the continuous evolution of triple-play technology, terminal devices need to process heterogeneous data from multiple sources, such as cable TV signals, network IP packets, and wireless access service streams, simultaneously. Multi-core SoC (System on Chip) architecture has become the mainstream hardware platform for this type of terminal due to its powerful concurrent processing capabilities.

[0003] However, in high-concurrency, multi-service scenarios, existing terminal diagnostic systems typically remain at the application software or operating system kernel level, unable to penetrate to the underlying hardware architecture. When a terminal experiences service processing lag, latency anomalies, or packet loss, a severe data gap exists between the upper-layer service flow (such as network sockets, processes, and threads) and the underlying physical core's operational status (such as hardware event counts and bus throughput) and hardware environment (such as die temperature). This lack of cross-layer state mapping makes it difficult for remote diagnostic servers to accurately trace the hardware-level root cause of the fault when receiving error logs, and they are unable to directly issue fine-grained control commands to the terminal's underlying hardware registers.

[0004] Therefore, there is an urgent need for an effective diagnostic mechanism that can connect business logic with the physical underlying layer and achieve closed-loop rescheduling of hardware resources from the cloud to the terminal. Summary of the Invention

[0005] This invention provides a remote fault diagnosis system for multi-core SoC integrated triple-play multi-service terminals. By constructing a cross-layer mapping relationship chain between service flow and micro-physical parameters, it realizes the source tracing of triple-play terminal faults and the closed-loop rescheduling of terminal underlying physical resources.

[0006] This invention provides a multi-core SoC integrated remote fault diagnosis system for triple-network converged multi-service terminals, including a multi-core SoC processing module, a status extraction module, a cross-layer mapping module, an anomaly diagnosis interaction module, and a remote diagnosis server. The multi-core SoC processing module is connected to the status extraction module, the cross-layer mapping module, and the anomaly diagnosis interaction module. The status extraction module is also connected to the cross-layer mapping module and the anomaly diagnosis interaction module. The cross-layer mapping module is also connected to the anomaly diagnosis interaction module. The anomaly diagnosis interaction module is also connected to the remote diagnosis server. The multi-core SoC processing module acquires cable TV signals, network IP data packets, and wireless access service streams, and performs service parsing and routing to output the target service data stream, while recording the output time of the target service data stream; The state extraction module acquires the physical core operating parameters and hardware ambient temperature data generated by the multi-core SoC processing module during the execution of service parsing and routing distribution. The cross-layer mapping module detects the entry timestamp of the digital byte stream corresponding to various services arriving at the multi-core SoC processing module, generates a coloring tag containing the entry timestamp and injects it into the corresponding digital byte stream, extracts and processes at least one target thread identifier corresponding to the digital byte stream, and establishes address binding between the coloring tag, at least one target thread identifier and the physical memory address storing the physical core operating parameters and hardware environment temperature data, thereby generating a cross-layer mapping relationship chain. The abnormal diagnosis interaction module compares the output time with the entry timestamp to obtain the business processing latency. When the business processing latency exceeds the preset safety threshold, it extracts the physical core operating parameters and hardware environment temperature data corresponding to the entry timestamp according to the cross-layer mapping relationship chain, and splices them into a diagnosis request data packet and sends it to the remote diagnosis server. The remote diagnostic server locates the faulty node causing the service processing delay to exceed the limit based on the diagnostic request data packet, generates a low-level system resource control instruction for the system resources bound to the target thread identifier based on the faulty node, and sends it to the abnormal diagnostic interaction module to adjust the system resources of the multi-core SoC processing module.

[0007] Furthermore, the multi-core SoC processing module includes a multi-source signal access parsing unit, a shared memory scheduling unit, a service parsing unit, a status monitoring unit, and a time recording unit; The multi-source signal access parsing unit acquires cable TV signals, network IP data packets, and wireless access service streams through a radio frequency demodulator, an Ethernet physical layer transceiver, and a baseband processing circuit, and converts the cable TV signals, network IP data packets, and wireless access service streams into digital byte streams through analog-to-digital conversion and baseband demodulation. The shared memory scheduling unit allocates contiguous physical page frames in the shared memory pool through the direct memory access controller, mapping the digital byte stream to a specific physical address space; The service parsing unit calls at least one target thread identifier through the physical core to perform deep packet inspection, IP addressing, routing table lookup, demultiplexing and hardware video decoding on the digital byte stream in a specific physical address space, and reassembles the processed data into the target service data stream. The state monitoring unit accumulates the hardware event counter of the physical core through the built-in hardware performance monitoring unit, extracts the instruction retirement rate, bus throughput and cache miss rate to generate the physical core running parameter; reads the resistance value change of the thermistor and digital temperature sensor through the built-in thermodynamic acquisition subsystem to generate the hardware environment temperature data; The time recording unit generates clock ticks through the high-precision event timer when the service analysis unit outputs the target service data stream, intercepts the clock ticks as output time, and binds and stores the output time with the serial number of the target service data stream.

[0008] Further, the state extraction module includes a polling reading unit, a physical quantity analysis unit and a synchronous storage unit; The polling reading unit is in communication connection with the hardware performance monitoring unit and the thermodynamic acquisition subsystem inside the multi-core SoC processing module, sends a read instruction to the hardware performance monitoring unit to obtain a discrete hexadecimal count value, and sends a read instruction to the thermodynamic acquisition subsystem to extract a level sampling value according to a preset clock period; The physical quantity analysis unit performs mask matching and bit shift operations on the discrete hexadecimal count value, separates out a value independently representing the physical core running state to generate the physical core running parameter, and converts the level sampling value into a Celsius value using a preset thermistor resistance-temperature mapping table to generate the hardware environment temperature data; The synchronous storage unit splices the physical core running parameter and the hardware environment temperature data into a physical state snapshot, pre-allocates a ring buffer in the kernel mode safe memory space, pushes the physical state snapshot into the current pointer position of the physical page frame where the ring buffer is located, and outputs the physical page frame head address.

[0009] Further, the cross-layer mapping module includes a label dyeing unit, a thread identifier extraction unit, an address binding unit and a mapping link splicing unit; When the multi-source signal access analysis unit generates digital byte streams of various services and triggers a hardware interrupt, the label dyeing unit reads the current tick value to intercept as an entry timestamp, and inserts a binary sequence with global uniqueness in the protocol packet header or payload gap of the digital byte stream to generate a dyeing label; In the process of executing deep packet detection and demultiplexing processing by the service analysis unit, the thread identifier extraction unit locates a specific process that is currently in a running state and is processing a dyeing label data stream, reads the context register saved value in the memory stack of the specific process, and extracts at least one target thread identifier that executes the analysis task; The address binding unit obtains the starting address of a specific physical page frame of the physical core operating parameters and hardware ambient temperature data. Using the starting address of the specific physical page frame as the underlying physical basis, it performs memory address mapping and parameter binding of the entry timestamp, coloring tag, and target thread identifier with the starting address of the specific physical page frame. The mapping link splicing unit splices and packages the bound entry timestamp, color tag, target thread identifier, physical core operating parameters and hardware environment temperature data into a multi-dimensional mapping structure according to the preset continuous memory alignment rules, so as to generate a cross-layer mapping relationship chain.

[0010] Furthermore, the preset continuous memory alignment rules include: applying 4-byte or 8-byte physical memory boundary alignment operations, and adapting to the burst read mechanism of the underlying processor bus by filling the gaps between data fields with zero-value bytes, while forcibly setting a uniform memory byte order.

[0011] Furthermore, the anomaly diagnosis interaction module includes a mapping data baseline comparison unit, an anomaly feature extraction and encapsulation unit, a diagnosis request reporting unit, and a logic verification feedback unit; The mapping data baseline comparison unit reads the cross-layer mapping relationship chain, and takes the business processing latency exceeding the preset safety threshold as the trigger premise. It performs a difference calculation operation on the physical core operating parameters and the hardware environment temperature data in the cross-layer mapping relationship chain and the business-physical benchmark feature matrix to generate an abnormal trigger signal. The business-physical benchmark feature matrix includes a preset upper limit boundary value and a preset lower limit boundary value corresponding to the normal threshold range. After acquiring the abnormal trigger signal, the abnormal feature extraction and encapsulation unit extracts the cross-layer mapping relationship chain data segment where the abnormality occurred and concatenates and packages it into a diagnostic request data packet. The diagnostic request reporting unit establishes a two-way encrypted data link with the remote diagnostic server and outputs a diagnostic request data packet to the remote diagnostic server. The logic verification feedback unit listens on the local port and receives the underlying system resource control instructions issued by the remote diagnostic server based on the diagnostic request data packet, and initiates a physical write operation through the system bus according to the underlying system resource control instructions.

[0012] Furthermore, the mapping data baseline comparison unit reads the cross-layer mapping relationship chain according to a preset time window, and uses the coloring label and the target thread identifier as a joint primary key; The arithmetic logic unit is invoked to perform numerical comparison operations on the currently sampled physical core operating parameters and the hardware ambient temperature data with the preset upper limit boundary value and preset lower limit boundary value corresponding to the normal threshold interval in the service-physical benchmark feature matrix, respectively. When the result of the numerical comparison operation is that the currently sampled value is greater than the preset upper limit boundary value or less than the preset lower limit boundary value, an abnormal status flag is appended to the end of the memory space of the corresponding mapping structure to generate an abnormal trigger signal.

[0013] Furthermore, the remote diagnostic server includes a diagnostic data parsing unit, a root cause correlation tracing unit, a hardware control strategy mapping unit, and a control instruction encoding unit; The diagnostic data parsing unit receives the diagnostic request data packet and performs an unpacking operation, extracts the entry timestamp, color tag, target thread identifier, and associated physical core operating parameters and hardware ambient temperature data, and stores them; The root cause association tracing unit uses the target thread identifier and coloring label as the retrieval index to extract business processing latency, physical core operating parameters and hardware environment temperature data, performs vector similarity calculation operation and outputs the corresponding hardware-level fault root cause identifier. The hardware control strategy mapping unit determines the corresponding target hardware register and obtains its target hardware register address by querying the register address mapping table based on the hardware-level fault root cause identifier, and calculates and allocates the corresponding correction parameters in combination with the deviation of the physical core operating parameters. The control instruction encoding unit concatenates the target hardware register address and the correction parameters into binary encoding to generate the underlying system resource control instruction, and sends it down through a bidirectional encrypted data link.

[0014] Furthermore, the root cause tracing unit preloads a multi-dimensional fault feature matrix containing a set of historical fault samples and their corresponding hardware-level fault root cause identifiers. The standard fault vector of the multi-dimensional fault feature matrix contains three feature dimensions: business processing latency deviation, physical core operating parameters, and hardware ambient temperature. The physical core operating parameters are divided into three sub-indicators: instruction retirement rate, bus throughput, and cache miss rate. The extracted parameter features are used to construct the current state vector, and a dot product and modulus division operation is performed with each standard fault vector in the multidimensional fault feature matrix to calculate the cosine similarity between the current state vector and the standard fault vector. When the calculated cosine similarity score is higher than the preset judgment threshold, the hardware-level fault root cause identifier with the highest matching degree is output.

[0015] Furthermore, in the hardware control strategy mapping unit, Using the hardware-level fault root cause identifier as the query keyword, the corresponding target hardware register physical base address and offset are determined in the register address mapping table to obtain the target hardware register address. Extract the preset compensation coefficients that are bound to the hardware-level fault root cause identifiers from the multidimensional fault feature matrix, and multiply the deviation of the current physical core operating parameters with the preset compensation coefficients to obtain the final allocated correction parameters.

[0016] The beneficial effects of this invention are as follows: This invention establishes a memory address binding mechanism between business data streams, operating system threads, and micro-hardware operating states at the underlying level, generating a cross-layer mapping chain. This mechanism achieves the retention and synchronous extraction of underlying physical core operating parameters and hardware environmental temperature data without increasing the performance overhead of the operating system application layer. When an anomaly occurs in business processing, the remote server can use the reported structured cross-layer data to perform deep vector calculations to locate the root cause of hardware-level faults and generate control instructions for the underlying hardware registers. Upon receiving the instructions, the terminal initiates a physical write operation on the underlying bus, thereby constructing a closed loop from cross-layer state awareness and precise cloud-based tracing to underlying resource self-healing and rescheduling, improving the reliability and remote operation and maintenance efficiency of multi-service high-concurrency terminals. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the structure of the multi-core SoC integrated triple-network converged multi-service terminal remote fault diagnosis system of the present invention.

[0018] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0019] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0020] The terms used in this invention are defined as follows: Cross-layer mapping relationship chain: refers to a structured association data chain formed by binding memory addresses to entry timestamps, coloring tags, target thread identifiers, physical core operating parameters, and hardware environment temperature data; Low-level system resource control instructions: These are low-level control instructions used to adjust terminal hardware register parameters and kernel thread scheduling configurations, including two categories: hardware resource configuration and software scheduling adjustment. Physical core operating parameters: These are parameters that characterize the operating status of the physical cores of a multi-core SoC, including instruction retirement rate, bus throughput, and cache miss rate. Business processing delay deviation: refers to the ratio of the actual processing delay of the current business to the standard delay benchmark value of the same type of business.

[0021] like Figure 1As shown, the present invention provides a multi-core SoC integrated triple-network converged multi-service terminal remote fault diagnosis system, including a multi-core SoC processing module, a status extraction module, a cross-layer mapping module, an anomaly diagnosis interaction module, and a remote diagnosis server. The multi-core SoC processing module is connected to the status extraction module, the cross-layer mapping module, and the anomaly diagnosis interaction module respectively. The status extraction module is also connected to the cross-layer mapping module and the anomaly diagnosis interaction module respectively. The cross-layer mapping module is also connected to the anomaly diagnosis interaction module. The anomaly diagnosis interaction module is also connected to the remote diagnosis server. The multi-core SoC processing module acquires cable TV signals, network IP data packets, and wireless access service streams, and performs service parsing and routing to output the target service data stream, while recording the output time of the target service data stream; The state extraction module acquires the physical core operating parameters and hardware ambient temperature data generated by the multi-core SoC processing module during the execution of service parsing and routing distribution. The cross-layer mapping module detects the entry timestamp of the digital byte stream corresponding to various services arriving at the multi-core SoC processing module, generates a coloring tag containing the entry timestamp and injects it into the corresponding digital byte stream, extracts and processes at least one target thread identifier corresponding to the digital byte stream, and establishes address binding between the coloring tag, at least one target thread identifier and the physical memory address storing the physical core operating parameters and hardware environment temperature data, thereby generating a cross-layer mapping relationship chain. The abnormal diagnosis interaction module compares the output time with the entry timestamp to obtain the business processing latency. When the business processing latency exceeds the preset safety threshold, it extracts the physical core operating parameters and hardware environment temperature data corresponding to the entry timestamp according to the cross-layer mapping relationship chain, and splices them into a diagnosis request data packet and sends it to the remote diagnosis server. The remote diagnostic server locates the faulty node causing the service processing delay to exceed the limit based on the diagnostic request data packet, generates a low-level system resource control instruction for the system resources bound to the target thread identifier based on the faulty node, and sends it to the abnormal diagnostic interaction module to adjust the system resources of the multi-core SoC processing module.

[0022] (1) Multi-core SoC processing module In a preferred embodiment of the present invention, in order to achieve accurate mapping of the underlying state under high-concurrency services of triple-play convergence, the multi-core SoC processing module adopts a heterogeneous multi-core architecture, which not only integrates a general-purpose processor core, but also directly connects to a dedicated hardware acceleration engine and environmental perception circuit via a bus. Specifically, the multi-core SoC processing module executes system instructions through the following internal units: ①Multi-source signal access analysis unit This unit includes an RF tuner, an Ethernet PHY, and baseband processing circuitry. It receives externally fed cable television signals (such as DVB-C coaxial cable RF signals), network IP packets (such as Ethernet frames input via an RJ45 interface), and wireless access service streams (such as Wi-Fi 6 band RF carriers). Through low-level analog-to-digital conversion and baseband demodulation, it strips the physical layer headers from these three types of heterogeneous physical signals, converting them into a standard digital byte stream recognizable by the system bus. This bypasses multiple data copies in the operating system kernel space, directly initiating an interrupt request to the next-level unit.

[0023] ② Shared memory scheduling unit This unit comprises a Direct Memory Access (DMA) controller and a shared memory pool consisting of Dynamic Random Access Memory (DRAM) chips. Once the aforementioned digital byte stream is generated, the DMA controller allocates contiguous physical page frames in the shared memory pool without intervention from the central processing unit (CPU) core, mapping the byte stream, such as network IP packets, to a specific physical address space (i.e., the physical memory address where the socket buffer resides). This direct physical address write operation provides the physical execution basis for the subsequent cross-layer mapping module to lock a fixed memory pointer.

[0024] ③ Business Analysis Unit This unit comprises multiple physical cores (such as ARM Cortex architecture computing cores) and a microarchitecture instruction scheduler. Once data resides in the specific physical address space, the operating system kernel wakes up the specific process bound to that data. The physical cores of this unit extract instructions from the instruction pipeline, call at least one target thread identifier (TID), perform deep packet inspection (DPI), IP addressing, and routing table lookup on network IP packets in memory, and perform MPEG-TS stream demultiplexing and H.265 hardware video decoding on cable television signals. After calculations and register state inversions by the arithmetic logic unit (ALU) of the aforementioned physical cores, the processed data is finally reassembled into the target service data stream (such as a video memory bitmap output via HDMI or a routed data packet forwarded to the external network) and output to the terminal interface.

[0025] ④ Status monitoring unit This unit is the core underlying circuit supporting the system's low-level diagnostics, consisting of a hardware performance monitoring unit (PMU) and a thermodynamic acquisition subsystem built into the SoC. During the high-frequency data processing by the service parsing unit: On the one hand, the PMU accumulates the hardware event counters of each physical core in real time through the level transition of physical pins, and directly extracts the instruction retirement rate, bus throughput and L2 / L3 cache miss rate within the micro instruction cycle, thereby generating physical core operating parameters.

[0026] On the other hand, the thermodynamic acquisition subsystem uses the I2C bus protocol to read the resistance changes of the thermistors embedded in the silicon die and the digital temperature sensors on key heat dissipation nodes of the terminal motherboard at a millisecond-level polling frequency, converting them from analog to digital data into quantified hardware ambient temperature data. These two types of low-level state data are pushed to the system's cache in real time for the state extraction module to read.

[0027] ⑤ Time recording unit This unit includes a High Precision Event Timer (HPET). The HPET generates a nanosecond-level clock tick the instant the service parsing unit pushes the target service data stream into the transmit ring buffer (Tx RingBuffer) of the network interface controller (NIC) or the frame buffer of the video output controller. This unit extracts this clock tick as the output time, binds it to the sequence number of the target service data stream, and performs a brief local storage operation to ensure that the subsequent anomaly diagnosis interaction module has a definite and tamper-proof physical time scale reference when performing latency comparison.

[0028] (2) Status extraction module In a preferred embodiment of the present invention, to ensure accurate capture of the underlying system state and provide a physical addressing basis for subsequent cross-layer address binding, the state extraction module operates on the entity control logic set of the underlying bus and hardware registers. Specifically, the state extraction module obtains the state through the execution state of the following internal units: ① Polling Reading Unit This unit establishes direct electrical communication connections with the Hardware Performance Monitoring Unit (PMU) and thermodynamic acquisition subsystem within the multi-core SoC processing module via physical buses such as the Advanced Peripheral Bus (APB) and the Internal Integrated Circuit Bus (I2C). Controlled by an independent hardware timer, this unit periodically sends physical read commands to a specific hardware event register address allocated within the PMU according to a preset microsecond clock cycle, directly acquiring the native discrete hexadecimal count value within the corresponding instruction cycle. Simultaneously, it sends read commands to the analog-to-digital conversion register address of the thermodynamic acquisition subsystem to extract continuously fluctuating level sampling values. This entire reading process is executed at the underlying bus level, bypassing the operating system's high-level application programming interface (API) calls, thereby avoiding interference from higher-level software fluctuations on data real-time performance.

[0029] ②Analysis Unit of Physical Quantities Since the data read from the underlying bus is a raw bitstream, this unit is responsible for performing physical-reference-based decoding and conversion on the received discrete hexadecimal count values ​​and level sample values. Specifically, this unit performs mask matching and shift operations on the hexadecimal count values, decomposing and separating them into values ​​that independently characterize the physical core's operating status (such as instruction retirement rate, bus throughput, and cache miss rate), generating standardized physical core operating parameters. At the same time, using the system's pre-built thermistor-temperature mapping table, the level sample values ​​are directly converted into quantized Celsius values ​​through a lookup algorithm, thereby generating hardware ambient temperature data.

[0030] ③ Synchronous storage unit To provide a stable addressing target for establishing an extremely accurate "cross-layer mapping relationship chain" for subsequent cross-layer mapping modules, this unit concatenates and encapsulates the parsed and normalized physical core operating parameters and hardware ambient temperature data into a fixed-length physical state snapshot. This unit pre-allocates a circular buffer of a specific length in the system's reserved kernel-mode safe memory space and pushes the physical state snapshot into the current pointer position of this circular buffer through atomic write operations, thereby completing the storage of state data. This operation not only assigns a unique and definite physical page frame starting address to each state extraction but also enables the evolution of the system state to form a traceable, continuous time slice on the physical storage medium.

[0031] (3) Cross-layer mapping module In a preferred embodiment of the present invention, in order to break down the state disconnect between application layer business flows and underlying multi-core SoC physical hardware and achieve accurate fault tracing, the cross-layer mapping module establishes an associated mapping logic of "entry timestamp - coloring tag - thread identifier - physical state parameter" through the physical action of splicing underlying pointer references with memory structures. Specifically, the cross-layer mapping module includes the following internal units: ① Label coloring unit When the multi-source signal access parsing unit generates a digital byte stream and triggers a hardware interrupt, the unit intercepts the interrupt request signal (IRQ) of the system bus. In operating system kernel mode, the unit reads the current tick value of the high-precision system clock register and extracts it as the entry timestamp. Simultaneously, the unit inserts coloring tags into the reserved fields of the corresponding protocol frames for digital byte streams of different service types. For network IP packets, insert into optional fields in the IP header or in the payload gap; For cable TV MPEG-TS streams, insert the reserved space in the adaptive field of the TS packet; For wireless access service flows, reserved bits are inserted in the MAC frame header.

[0032] The coloring label is a globally unique binary sequence that provides micro-level marking of the three types of business data at the physical data stream level, ensuring that cross-layer mapping relationships can be established for all business data.

[0033] ② Thread Identifier Extraction Unit During the deep packet inspection and demultiplexing process performed by the business parsing unit, the unit locates a specific process currently in the running state that is processing the data stream with the aforementioned coloring tags by accessing the Task Control Block (TCB) memory linked list of the operating system kernel. Subsequently, the unit reads the value stored in the context register in the process's memory stack and extracts at least one target thread identifier (TID) for executing the specific parsing task.

[0034] ③ Address Binding Unit This unit is responsible for establishing the physical connection path between the software logic identifier and the underlying hardware state. This unit reads the current pointer position of the ring buffer pre-allocated in the kernel-mode secure memory space by the state extraction module, and obtains the starting address of a specific physical page frame storing the latest and corresponding physical core operating parameters and hardware ambient temperature data. Using this physical page frame starting address as the underlying physical basis, this unit performs memory address mapping and parameter binding with the generated entry timestamp, coloring tag, and target thread identifier.

[0035] ④ Mapping Link Splicing Unit This unit will complete the binding of the entry timestamp, coloring tag, target thread identifier, and physical core operating parameters and hardware ambient temperature data retrieved through the physical page frame's first address. Following a preset continuous memory alignment rule (including applying 4-byte or 8-byte physical memory boundary alignment operations, padding data field gaps with zero-value bytes to adapt to the underlying processor bus's burst read mechanism, and forcibly setting a uniform memory byte order), this data will be assembled and packaged into a formatted multi-dimensional mapping structure. This generates a cross-layer mapping relationship chain in the kernel memory space, with clear timing and physical pointer association characteristics. Subsequently, this unit will store the multi-dimensional mapping structure and the resulting cross-layer mapping relationship chain via a database interface or file system write instruction. This achieves physical solidification of the hardware and software status data, providing a data source for subsequent anomaly diagnosis interaction modules.

[0036] (4) Anomaly Diagnosis Interaction Module In a preferred embodiment of the present invention, in order to accurately capture the local underlying fault state and form a closed-loop control mechanism for resource scheduling with external control nodes, the anomaly diagnosis interaction module receives the cross-layer mapping relationship chain, and completes the physical action flow from "anomaly detection" to "closed-loop repair" by comparing underlying data, encapsulating and reporting it, and receiving and executing scheduling instructions. Specifically, the anomaly diagnosis interaction module includes the following internal units: ① Mapping data baseline comparison unit This unit reads the cross-layer mapping relationship chain according to a preset time window. First, using the coloring label as an index, it matches the entry timestamp and output time of the corresponding business data stream to calculate the single-packet business processing latency. When the business processing latency exceeds a preset safety threshold, it uses the coloring label and the target thread identifier as a combined primary key to call the arithmetic logic unit to perform numerical comparison operations on the currently sampled physical core operating parameters and hardware ambient temperature data with the preset upper limit boundary value and preset lower limit boundary value corresponding to the normal threshold interval in the business-physical benchmark feature matrix, respectively.

[0037] When the result of the numerical comparison operation is that the current sampled value is greater than the preset upper limit boundary value or less than the preset lower limit boundary value, an abnormal status flag is appended to the end of the memory space of the corresponding mapping structure to generate an abnormal trigger signal; if the latency exceeds the standard but the physical parameters are all within the normal range, it is marked as a software scheduling type abnormality and synchronously reported to the remote diagnostic server.

[0038] ② Anomaly Feature Extraction and Encapsulation Unit Upon receiving the anomaly trigger signal, the unit, based on the feedback information from the memory address pointer at the end of the mapping structure carried by the anomaly trigger signal, extracts the cross-layer mapping relationship chain data segment where the anomaly occurred through pointer offset operations. The unit precisely extracts the entry timestamp, color tag, target thread identifier, and associated physical core operating parameters and hardware ambient temperature data, which contain the anomaly status flag. Following a preset Remote Procedure Call (RPC) protocol format, it fills the payload area with the extracted physical and logical feature values ​​(i.e., the aforementioned extracted entry timestamp, color tag, target thread identifier, and associated physical core operating parameters and hardware ambient temperature data), and then concatenates and packages them into a diagnostic request data packet containing a snapshot of the underlying physical structure.

[0039] ③ Diagnostic request reporting unit This unit establishes a bidirectional encrypted data link with the remote diagnostic server by calling the socket interface of the operating system's network protocol stack. After successful handshake verification, the unit pushes the diagnostic request data packet into the network interface controller's (NIC) transmit ring buffer, triggering the NIC's physical transmission action to output the diagnostic request data packet to the remote diagnostic server. The remote diagnostic server then uses the feature data contained in the diagnostic request data packet to execute global logic and root cause diagnosis algorithms for underlying hardware faults, and generates control commands containing targeted repair strategies accordingly.

[0040] ④ Logic verification feedback unit This unit continuously listens on the local port and receives resource rescheduling and control instructions issued by the remote diagnostic server based on diagnostic request data packets. The unit parses the opcode and operands in the control instructions (specifically, it extracts the opcode field of a specified width from the instruction frame header using a bit operation mask to determine the hardware execution type, and extracts operands from the data payload field for numerical decoding). Based on the target hardware register address and correction parameters contained in the instruction (the target hardware register address and correction parameters are obtained by decoding and mapping the operands extracted from the payload field), it initiates a physical write operation via the system bus. On one hand, it adjusts the hardware register parameters such as the frequency configuration register, thermal management control register, and bus bandwidth configuration register of the corresponding physical core; on the other hand, it adjusts the CPU affinity and scheduling priority of the target thread through kernel-mode system calls, completing fault isolation and resource rescheduling from two dimensions: hardware resource allocation and software scheduling configuration.

[0041] (5) Remote diagnostic server In a preferred embodiment of the present invention, in order to form a complete "end-to-cloud" linkage control loop with the underlying hardware status of the local terminal device, the remote diagnostic server receives diagnostic request data packets reported by the abnormal diagnostic interaction module, and generates instructions to intervene in the underlying hardware of the terminal by performing deep feature analysis and strategy matching in the cloud. Specifically, the remote diagnostic server includes the following internal units: ① Diagnostic data parsing unit This unit receives the diagnostic request data packet transmitted via the socket interface through the server-side Network Interface Controller (NIC). The unit unpacks the diagnostic request data packet according to a preset remote procedure call protocol, sequentially stripping the network header and protocol checksum, and extracting the entry timestamp, color tag, target thread identifier, and associated physical core operating parameters and hardware ambient temperature data from the payload area. After completing data extraction and integrity verification, the unit calls the database interface to directly write the extracted physical and logical characteristic values ​​into a cloud-based distributed relational database in the form of structured records, completing the storage of historical operating data for the subsequent establishment of long-term device health records.

[0042] ② Root Cause Association Source Tracing Unit This unit pre-loads a multi-dimensional fault feature matrix into memory, which contains a set of historical fault samples and their corresponding hardware-level fault root cause identifiers. It extracts the physical and logical feature values ​​stored in the database via the system bus, using the target thread identifier and coloring label as search indexes to extract physical core operating parameters (such as the continuous decline in cache hit rate) and hardware ambient temperature data (such as the abnormal temperature rise slope in a specific kernel range). Subsequently, it performs a vector cosine similarity calculation, constructing a current state vector from the currently extracted business processing latency, physical core operating parameters, and hardware ambient temperature data, and performing a dot product and modulus division operation with each standard fault vector in the multi-dimensional fault feature matrix. Each standard fault vector in the multi-dimensional fault feature matrix contains five subdivided feature dimensions: business processing latency deviation, instruction retirement rate, bus throughput, cache miss rate, and core temperature, ensuring consistency between fault triggering conditions and root cause matching features.

[0043] Cosine similarity calculation involves calculating the dot product of the current state vector and the standard fault vector, and then dividing it by the product of the Euclidean moduli of the two vectors. When the calculated similarity score is higher than a preset judgment threshold, the unit outputs the corresponding hardware-level fault root cause identifier with the highest matching degree (e.g., thread starvation caused by hot throttling, or memory leak caused by illegal address access). Using business processing latency deviation as a feature dimension can eliminate the latency baseline differences between different business types, avoid misjudgments of faults due to different business types, and improve the accuracy of root cause matching.

[0044] ③ Hardware control strategy mapping unit This unit receives the hardware-level fault root cause identifier output by the root cause correlation and tracing unit, and searches for the underlying repair strategy required to intervene in the hardware-level fault root cause identifier based on the register address mapping table stored locally on the server. Specific actions include: using the hardware-level fault root cause identifier as the query keyword, the unit locks the corresponding target hardware register physical base address and offset (i.e., the aforementioned target hardware register address) in the register address mapping table, and calculates and allocates corresponding correction parameters based on the deviation of the current physical core operating parameters (the specific execution process is: the unit extracts the preset compensation coefficient bound to the hardware-level fault root cause identifier from the multidimensional fault feature matrix, multiplies the deviation by the preset compensation coefficient, and uses the product of the multiplication as the final allocated correction parameter, for example: reducing the value of the task scheduling priority register from high priority to low priority, or calculating the adjustment step size of the PWM fan duty cycle).

[0045] ④ Control command encoding unit To enable the local multi-core SoC terminal to directly parse and execute physical actions, this unit concatenates the target hardware register address and correction parameters generated by the hardware control strategy mapping unit into binary encoding according to a preset hardware control instruction set frame format. Through bit shifting and bitwise OR operations, an opcode field representing hardware execution types such as "register overwrite," "frequency reduction," or "process termination" is filled into a specified bit-width area at the beginning of the instruction frame. The target hardware register address and correction parameters are then encoded and encapsulated into the data payload field to generate the final operand.

[0046] After encoding is completed, the generated control commands are pushed into the server's underlying transmission protocol stack and sent to the terminal's local listening port via a two-way encrypted data link, thereby closing the feedback loop from "cloud diagnosis" to "end-side intervention" at the physical link level.

[0047] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, apparatus, article, or method that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, apparatus, article, or method. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, apparatus, article, or method that includes that element.

[0048] The above description is merely a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A remote fault diagnosis system for multi-core SoC integrated triple-network converged multi-service terminals, characterized in that, It includes a multi-core SoC processing module, a state extraction module, a cross-layer mapping module, an anomaly diagnosis interaction module, and a remote diagnostic server. The multi-core SoC processing module is connected to the state extraction module, the cross-layer mapping module, and the anomaly diagnosis interaction module. The state extraction module is also connected to the cross-layer mapping module and the anomaly diagnosis interaction module. The cross-layer mapping module is also connected to the anomaly diagnosis interaction module. The anomaly diagnosis interaction module is also connected to the remote diagnostic server. The multi-core SoC processing module acquires cable TV signals, network IP data packets, and wireless access service streams, and performs service parsing and routing to output the target service data stream, while recording the output time of the target service data stream; The state extraction module acquires the physical core operating parameters and hardware ambient temperature data generated by the multi-core SoC processing module during the execution of service parsing and routing distribution. The cross-layer mapping module detects the entry timestamp of the digital byte stream corresponding to various services arriving at the multi-core SoC processing module, generates a coloring tag containing the entry timestamp and injects it into the corresponding digital byte stream, extracts and processes at least one target thread identifier corresponding to the digital byte stream, and establishes address binding between the coloring tag, at least one target thread identifier and the physical memory address storing the physical core operating parameters and hardware environment temperature data, thereby generating a cross-layer mapping relationship chain. The abnormal diagnosis interaction module compares the output time with the entry timestamp to obtain the business processing latency. When the business processing latency exceeds the preset safety threshold, it extracts the physical core operating parameters and hardware environment temperature data corresponding to the entry timestamp according to the cross-layer mapping relationship chain, and splices them into a diagnosis request data packet and sends it to the remote diagnosis server. The remote diagnostic server locates the faulty node causing the service processing delay to exceed the limit based on the diagnostic request data packet, generates a low-level system resource control instruction for the system resources bound to the target thread identifier based on the faulty node, and sends it to the abnormal diagnostic interaction module to adjust the system resources of the multi-core SoC processing module.

2. The multi-core SoC integrated triple-network converged multi-service terminal remote fault diagnosis system according to claim 1, characterized in that, The multi-core SoC processing module includes a multi-source signal access parsing unit, a shared memory scheduling unit, a service parsing unit, a status monitoring unit, and a time recording unit; The multi-source signal access parsing unit acquires cable TV signals, network IP data packets, and wireless access service streams through a radio frequency demodulator, an Ethernet physical layer transceiver, and a baseband processing circuit, and converts the cable TV signals, network IP data packets, and wireless access service streams into digital byte streams through analog-to-digital conversion and baseband demodulation. The shared memory scheduling unit allocates contiguous physical page frames in the shared memory pool through the direct memory access controller, mapping the digital byte stream to a specific physical address space; The service parsing unit calls at least one target thread identifier through the physical core to perform deep packet inspection, IP addressing, routing table lookup, demultiplexing and hardware video decoding on the digital byte stream in a specific physical address space, and reassembles the processed data into the target service data stream. The status monitoring unit accumulates the hardware event counter of the physical core through the built-in hardware performance monitoring unit, extracts instruction retirement rate, bus throughput and cache miss rate to generate physical core operating parameters; and reads the resistance changes of the thermistor and digital temperature sensor through the built-in thermodynamic acquisition subsystem to generate hardware ambient temperature data. When the service parsing unit outputs the target service data stream, the time recording unit generates a clock beat through a high-precision event timer, extracts the clock beat as the output time, and binds and stores the output time with the sequence number of the target service data stream.

3. The multi-core SoC integrated triple-network converged multi-service terminal remote fault diagnosis system according to claim 2, characterized in that, The state extraction module includes a polling reading unit, a physical quantity parsing unit, and a synchronization storage unit; The polling reading unit is communicatively connected to the hardware performance monitoring unit and the thermodynamic acquisition subsystem inside the multi-core SoC processing module. According to a preset clock cycle, it sends a read command to the hardware performance monitoring unit to obtain discrete hexadecimal count values, and sends a read command to the thermodynamic acquisition subsystem to extract level sampling values. The physical quantity analysis unit performs mask matching and shifting operations on the discrete hexadecimal count value to separate the values ​​that independently represent the physical core operating state to generate physical core operating parameters; and uses a preset thermistor-temperature mapping table to convert the level sampling value into a Celsius value to generate hardware ambient temperature data. The synchronous storage unit stitches the physical core operating parameters and hardware ambient temperature data into a physical state snapshot, pre-allocates a circular buffer in the kernel-mode safe memory space, pushes the physical state snapshot into the current pointer position of the physical page frame where the circular buffer is located, and outputs the starting address of the physical page frame.

4. The multi-core SoC integrated triple-network converged multi-service terminal remote fault diagnosis system according to claim 3, characterized in that, The cross-layer mapping module includes a label coloring unit, a thread identifier extraction unit, an address binding unit, and a mapping link splicing unit; When the multi-source signal access parsing unit generates digital byte streams for various services and triggers a hardware interrupt, the tag coloring unit reads the current tick value to extract it as the entry timestamp, and inserts a globally unique binary sequence into the protocol packet header or payload gap of the digital byte stream to generate a coloring tag. During the deep packet inspection and demultiplexing process performed by the business parsing unit, the thread identifier extraction unit locates a specific process that is currently running and processing a data stream with coloring labels, reads the value stored in the context register in the memory stack of the specific process, and extracts at least one target thread identifier that is performing the parsing task. The address binding unit obtains the first address of a specific physical page frame of the physical core operating parameters and hardware ambient temperature data. Using the first address of the specific physical page frame as the underlying physical basis, it performs memory address mapping and parameter binding of the entry timestamp, coloring tag, and target thread identifier with the first address of the specific physical page frame. The mapping link splicing unit splices and packages the bound entry timestamp, color tag, target thread identifier, physical core operating parameters and hardware environment temperature data into a multi-dimensional mapping structure according to the preset continuous memory alignment rules, so as to generate a cross-layer mapping relationship chain.

5. The multi-core SoC integrated triple-network converged multi-service terminal remote fault diagnosis system according to claim 4, characterized in that, The preset continuous memory alignment rules include: applying 4-byte or 8-byte physical memory boundary alignment operations, and filling the gaps in the data fields with zero-value bytes to adapt to the burst read mechanism of the underlying processor bus, while forcibly setting a uniform memory byte order.

6. The multi-core SoC integrated triple-network converged multi-service terminal remote fault diagnosis system according to claim 5, characterized in that, The anomaly diagnosis interaction module includes a mapping data baseline comparison unit, an anomaly feature extraction and encapsulation unit, a diagnosis request reporting unit, and a logic verification feedback unit. The mapping data baseline comparison unit reads the cross-layer mapping relationship chain, and takes the business processing latency exceeding the preset safety threshold as the trigger premise. It performs a difference calculation operation on the physical core operating parameters and the hardware environment temperature data in the cross-layer mapping relationship chain and the business-physical benchmark feature matrix to generate an abnormal trigger signal. The business-physical benchmark feature matrix includes a preset upper limit boundary value and a preset lower limit boundary value corresponding to the normal threshold range. After acquiring the abnormal trigger signal, the abnormal feature extraction and encapsulation unit extracts the cross-layer mapping relationship chain data segment where the abnormality occurred and concatenates and packages it into a diagnostic request data packet. The diagnostic request reporting unit establishes a two-way encrypted data link with the remote diagnostic server and outputs a diagnostic request data packet to the remote diagnostic server. The logic verification feedback unit listens on the local port and receives the underlying system resource control instructions issued by the remote diagnostic server based on the diagnostic request data packet, and initiates a physical write operation through the system bus according to the underlying system resource control instructions.

7. The multi-core SoC integrated triple-network converged multi-service terminal remote fault diagnosis system according to claim 6, characterized in that, The mapping data baseline comparison unit reads the cross-layer mapping relationship chain according to a preset time window, and uses the coloring label and the target thread identifier as a joint primary key; The arithmetic logic unit is invoked to perform numerical comparison operations on the currently sampled physical core operating parameters and the hardware ambient temperature data with the preset upper limit boundary value and preset lower limit boundary value corresponding to the normal threshold interval in the service-physical benchmark feature matrix, respectively. When the result of the numerical comparison operation is that the currently sampled value is greater than the preset upper limit boundary value or less than the preset lower limit boundary value, an abnormal status flag is appended to the end of the memory space of the corresponding mapping structure to generate an abnormal trigger signal.

8. The multi-core SoC integrated triple-network converged multi-service terminal remote fault diagnosis system according to claim 6, characterized in that, The remote diagnostic server includes a diagnostic data parsing unit, a root cause correlation tracing unit, a hardware control strategy mapping unit, and a control instruction encoding unit. The diagnostic data parsing unit receives the diagnostic request data packet and performs an unpacking operation, extracts the entry timestamp, color tag, target thread identifier, and associated physical core operating parameters and hardware ambient temperature data, and stores them; The root cause association tracing unit uses the target thread identifier and coloring label as retrieval index to extract business processing latency, physical core operating parameters and hardware environment temperature data, performs vector similarity calculation operation and outputs the corresponding hardware-level fault root cause identifier; The hardware control strategy mapping unit determines the corresponding target hardware register and obtains its target hardware register address by querying the register address mapping table based on the hardware-level fault root cause identifier, and calculates and allocates the corresponding correction parameters in combination with the deviation of the physical core operating parameters. The control instruction encoding unit concatenates the target hardware register address and the correction parameters into binary encoding to generate the underlying system resource control instruction, and sends it down through a bidirectional encrypted data link.

9. The multi-core SoC integrated triple-network converged multi-service terminal remote fault diagnosis system according to claim 8, characterized in that, The root cause association tracing unit preloads a multi-dimensional fault feature matrix containing a set of historical fault samples and their corresponding hardware-level fault root cause identifiers. The standard fault vector of the multi-dimensional fault feature matrix includes three feature dimensions: business processing latency deviation, physical core operating parameters, and hardware ambient temperature. Among them, the physical core operating parameters are divided into three sub-indicators: instruction retirement rate, bus throughput, and cache miss rate. The extracted parameter features are used to construct the current state vector, and a dot product and modulus division operation is performed with each standard fault vector in the multidimensional fault feature matrix to calculate the cosine similarity between the current state vector and the standard fault vector. When the calculated cosine similarity score is higher than the preset judgment threshold, the hardware-level fault root cause identifier with the highest matching degree is output.

10. The multi-core SoC integrated triple-network converged multi-service terminal remote fault diagnosis system according to claim 9, characterized in that, In the hardware control strategy mapping unit Using the hardware-level fault root cause identifier as the query keyword, the corresponding target hardware register physical base address and offset are determined in the register address mapping table to obtain the target hardware register address. Extract the preset compensation coefficients that are bound to the hardware-level fault root cause identifiers from the multidimensional fault feature matrix, and multiply the deviation of the current physical core operating parameters with the preset compensation coefficients to obtain the final allocated correction parameters.

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