Routing methods, apparatuses, components, multi-processing chip systems, and devices

Abstract

Embodiments of the present application disclose a routing method, device, component, multi-processing chip system and equipment. Embodiments of the present application pre-register a virtual gateway, and make routing processors located in different processing chips correspond to different gateway ports in the virtual gateway, respectively, set corresponding endpoint identifiers for each gateway port, and establish a mapping relationship between the endpoint identifiers of each gateway port and a same target physical address identifier, and then the routing processors implement the transmission and reception of data packets in a pure hardware mode according to a global routing table. Thus, embodiments of the present application can build a routing network between different processing chips, so that the controlled endpoints of each processing chip can route data packets based on the routing network, thereby realizing cross-chip data packet routing in a multi-processing chip system, improving the throughput in the routing process, and reducing the delay and system power consumption.

Description

Technical Field

[0001] This invention relates to the field of chip design technology, and more specifically to a routing method, apparatus, component, multiprocessor chip system, and device. Background Technology

[0002] In current chip designs, data transmission or command exchange between different communication endpoints is typically achieved by sending data packets to each other. This makes data packet routing capability a critical factor limiting chip communication performance. However, existing routing schemes are generally only applicable to data packet routing within a single processing chip and cannot be directly applied to data packet routing in multi-processor chip systems. Furthermore, existing routing schemes usually require significant software intervention. Due to inherent limitations in software, this leads to decreased throughput, increased latency, and increased system power consumption during the routing process. Summary of the Invention

[0003] In view of this, embodiments of the present invention provide a routing method, apparatus, component, multiprocessor chip system and device to realize cross-chip data packet routing in a multiprocessor chip system, improve throughput during the routing process, and reduce latency and system power consumption.

[0004] In a first aspect, embodiments of the present invention aim to provide a routing component, the routing component being suitable for a multi-processor chip system, the routing component comprising: Multiple routing processors are provided, wherein each routing processor is disposed in a different processing chip, each routing processor has the same target physical address identifier in its respective processing chip, each routing processor corresponds to a different gateway port in the virtual gateway, each gateway port has a corresponding endpoint identifier, and the endpoint identifier of each gateway port is mapped to the target physical address identifier. Each of the aforementioned routing processors is configured to perform the following steps: Receive the data packet to be transmitted; The data packet to be transmitted is parsed to obtain the receiver endpoint identifier; In the global routing table, the receiving physical address identifier of the receiving endpoint and the target port identifier of the target gateway port to which the receiving endpoint is connected are determined by querying based on the receiving endpoint identifier. The global routing table is used to record the mapping relationship between the endpoint identifier and the physical address identifier of the controlled endpoint, and to record the port identifier of the gateway port to which the controlled endpoint is connected. The data packet to be transmitted is updated in the bus transmission header according to the received physical address identifier and the target physical address identifier. The current routing processor and the other routing processors in the routing component correspond to different gateway ports in the virtual gateway. Each gateway port has a corresponding endpoint identifier. The target physical address identifier is also mapped to the endpoint identifier of each gateway port. The data packet to be transmitted is forwarded to the corresponding target routing processor according to the target port identifier, so as to instruct the target routing processor to send the data packet to be transmitted to the receiving endpoint.

[0005] Secondly, embodiments of the present invention aim to provide a routing method, the method being applicable to a routing processor, the method comprising: Receive the data packet to be transmitted; The data packet to be transmitted is parsed to obtain the receiver endpoint identifier; In the global routing table, the receiving physical address identifier of the receiving endpoint and the target port identifier of the target gateway port to which the receiving endpoint is connected are determined by querying based on the receiving endpoint identifier. The global routing table is used to record the mapping relationship between the endpoint identifier and the physical address identifier of the controlled endpoint, and to record the port identifier of the gateway port to which the controlled endpoint is connected. The bus transmission header of the data packet to be transmitted is updated based on the received physical address identifier and the target physical address identifier. The current routing processor and the remaining routing processors in the routing component are respectively located in different processing chips. Each routing processor has the same target physical address identifier in its respective processing chip. Each routing processor corresponds to a different gateway port in the virtual gateway, and each gateway port has a corresponding endpoint identifier. A mapping relationship is established between the endpoint identifier of each gateway port and the target physical address identifier. The data packet to be transmitted is forwarded to the corresponding target routing processor according to the target port identifier, so as to instruct the target routing processor to send the data packet to be transmitted to the receiving endpoint.

[0006] Thirdly, embodiments of the present invention aim to provide a routing device, the device comprising: The receiving unit is used to receive data packets to be transmitted. The parsing unit is used to parse the data packet to be transmitted in order to obtain the receiver endpoint identifier of the receiving endpoint; The query unit is used to query and determine the receiving physical address identifier of the receiving endpoint and the target port identifier of the target gateway port to which the receiving endpoint is connected in the global routing table based on the receiving endpoint identifier. The global routing table is used to record the mapping relationship between the endpoint identifier and the physical address identifier of the controlled endpoint, and to record the port identifier of the gateway port to which the controlled endpoint is connected. The packet header update unit is used to update the bus transmission packet header of the data packet to be transmitted according to the received physical address identifier and the target physical address identifier. The current routing processor and the other routing processors in the routing component are respectively set in different processing chips. Each routing processor has the same target physical address identifier in its respective processing chip. Each routing processor corresponds to a different gateway port in the virtual gateway. Each gateway port has a corresponding endpoint identifier. The endpoint identifier of each gateway port is mapped to the target physical address identifier. The sending unit is configured to forward the data packet to be transmitted to the corresponding target routing processor according to the target port identifier, so as to instruct the target routing processor to send the data packet to be transmitted to the receiving endpoint.

[0007] Fourthly, embodiments of the present invention aim to provide a multi-processor chip system, the system comprising: Multiple processing chips; Multiple controlled endpoints, wherein each of the controlled endpoints is connected to a corresponding processing chip; Interconnect bus, used to enable communication between processing chips, and to enable communication between processing chips and controlled endpoints; The routing component as described in the first aspect.

[0008] Fifthly, embodiments of the present invention aim to provide an electronic device, the device comprising: As described in the fourth aspect, a multi-processor chip system.

[0009] This invention pre-registers virtual gateways and assigns routing processors located in different processing chips to different gateway ports within the virtual gateways. It then assigns corresponding endpoint identifiers to each gateway port and establishes a mapping between these endpoint identifiers and the same target physical address identifier. The routing processors then use a global routing table to send and receive data packets in pure hardware. Therefore, this invention can build a routing network between different processing chips, enabling controlled endpoints on each processing chip to route data packets based on this network. This achieves cross-chip data packet routing in multi-processor chip systems, improves throughput during routing, and reduces latency and system power consumption. Attached Figure Description

[0010] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which: Figure 1 This is a schematic diagram of a multi-processor chip system according to an embodiment of the present invention; Figure 2 This is a schematic diagram of a multi-processor chip system according to an embodiment of the present invention; Figure 3 This is a schematic diagram of a multi-processor chip system according to an embodiment of the present invention; Figure 4 This is a flowchart of the routing method according to an embodiment of the present invention; Figure 5 This is a schematic diagram of a local routing table according to an embodiment of the present invention; Figure 6 This is a schematic diagram of a local routing table according to an embodiment of the present invention; Figure 7 This is a schematic diagram of the routing process according to an embodiment of the present invention; Figure 8 This is a schematic diagram of the data packet structure according to an embodiment of the present invention; Figure 9 This is a flowchart of the data packet parsing method according to an embodiment of the present invention; Figure 10 This is a schematic diagram of the global routing table in an embodiment of the present invention; Figure 11 This is a flowchart of the bus transmission packet header update method according to an embodiment of the present invention; Figure 12 This is a schematic diagram of a routing device according to an embodiment of the present invention. Detailed Implementation

[0011] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the substance of the present application, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0012] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0013] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".

[0014] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0015] The solutions described in this specification and embodiments, if involving the processing of personal information, will be processed only on the premise of having a legal basis (such as obtaining the consent of the personal information subject, or being necessary for the performance of a contract), and will only be processed within the scope stipulated or agreed upon. A user's refusal to process personal information beyond what is necessary for basic functions will not affect the user's use of basic functions.

[0016] The routing component in this embodiment of the invention is applicable to multi-processor chip systems. A multi-processor chip system refers to a system containing multiple processing chips. These chips are interconnected and can operate collaboratively. By placing the routing component within the multi-processor chip system, this embodiment of the invention can establish a routing network between different processing chips within the system. This allows controlled endpoints of each processing chip to route data packets based on this network, thereby achieving cross-chip data packet routing in the multi-processor chip system, improving throughput during routing, and reducing latency and system power consumption.

[0017] Figure 1 This is a schematic diagram of a multiprocessor chip system according to an embodiment of the present invention. Figure 1 The diagram shown can be a schematic representation of a multiprocessor chip system from a hardware perspective. For example... Figure 1 As shown, the multiprocessor chip system 1 includes multiple processing chips 11, multiple controlled endpoints 12, interconnect buses (as indicated by bidirectional arrows between the hardware modules), and routing components.

[0018] The multiple processing chips 11 can be processing chips within a multi-processor chip system 1. Each controlled endpoint 12 can be connected to a corresponding processing chip 11. The multiple controlled endpoints 12 can be logical entities capable of performing specific functions and having communication requirements, such as functional modules, chips, or hardware circuits. An interconnect bus can be connected between the processing chips 11 and between the processing chips 11 and the connected controlled endpoints 12 to enable communication between the processing chips 11 and between each processing chip 11 and the connected controlled endpoints 12.

[0019] It should be noted that, in the embodiments of the present invention, each of the plurality of processing chips 11 can be connected to a corresponding number of controlled endpoints 12, and this application does not impose any limitations on this. Furthermore, as one implementation, each processing chip 11 may have a root complex internally. Specifically, the plurality of controlled endpoints 12 can be connected to the corresponding processing chip through the corresponding root complex.

[0020] Optionally, as one implementation, the processing chip 11 may include a central processing unit (CPU) chip and / or a system-on-chip (SoC). The controlled endpoint 12 may include a graphics processing unit (GPU) chip, a tensor processing unit (TPU) chip, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a vision processing unit (VPU) chip, a data processing unit (DPU) chip, a neural processing unit (NPU) chip, a baseboard management controller (BMC) chip, a clock chip, a voltage regulation module, and / or a network interface card (NIC). The interconnect bus may include a PCIe (Peripheral Component Interconnect Express) bus, an SMBus (System Management Bus) bus, and / or a dedicated interconnect bus. It should be noted that, depending on the different processing chips inside and the different controlled endpoints connected to each processing chip, a multi-processor chip system can be a multi-processor server, an artificial intelligence accelerator card cluster, or other types of chip systems, and this application does not impose any restrictions on this.

[0021] Furthermore, in this embodiment of the invention, multiple processing chips 11 can serve as carriers to carry routing components. The routing components can establish a routing network between different processing chips 11, enabling controlled endpoints 12 of each processing chip 11 to route data packets based on this network. This achieves cross-chip data packet routing in the multi-processor chip system 1, improves throughput during the routing process, and reduces latency and system power consumption.

[0022] Furthermore, the routing component may include multiple routing processors 141. Each of the multiple routing processors 141 may be disposed in a different processing chip 11. Each routing processor 141 may have the same target physical address identifier in its respective processing chip 11. It is worth noting that, in this embodiment of the invention, the multiple routing processors 141 may be regarded by an external object as a unified logical entity with multiple output ports and a single physical address identifier, i.e., a virtual gateway. Each routing processor 141 may correspond to a different gateway port in the virtual gateway. Each gateway port may have a corresponding endpoint identifier. A mapping relationship is established between the endpoint identifier of each gateway port and the target physical address identifier. And, after the multiple routing processors 141 are regarded as a virtual gateway, the external object will no longer distinguish between the individual routing processors 141, but will send data packets to the virtual gateway uniformly. Optionally, as an implementation, each routing processor 141 may be implemented by configuring the corresponding circuits (e.g., the management component transmission protocol controller) inside each processing chip 11. Alternatively, as another implementation, each routing processor 141 can also be implemented by additionally setting corresponding hardware circuits (e.g., field-programmable gate array circuits or application-specific integrated circuits) inside each processing chip 11.

[0023] Specifically, for any controlled endpoint 12, when there is a need for cross-chip communication, the controlled endpoint 12 will directly send the data packet carrying relevant data or instructions to the virtual gateway based on the target physical address identifier. Inside the virtual gateway, for any routing processor 141, the routing processor 141 can receive data packets to be transmitted from the corresponding controlled endpoint 12 (i.e., the controlled endpoint connected to its own processing chip). Furthermore, whenever a data packet to be transmitted is received, the routing processor 141 can parse the data packet to obtain the receiving endpoint identifier, and in the global routing table, query the receiving endpoint identifier to determine the receiving physical address identifier of the receiving endpoint and the target port identifier of the target gateway port to which the receiving endpoint is connected. Then, based on the receiving physical address identifier and the target physical address identifier, the routing processor updates the bus transmission header of the data packet to be transmitted, and then forwards the data packet to be transmitted to the corresponding target routing processor (i.e., the routing processor corresponding to the target gateway port) based on the target port identifier, instructing the target routing processor to send the data packet to the receiving endpoint. The global routing table records the mapping between endpoint identifiers and physical address identifiers of controlled endpoints at the global level, as well as the port identifiers of the gateway ports connected to the controlled endpoints. Therefore, by establishing a routing network between different processing chips, enabling controlled endpoints of each processing chip to route data packets based on this network, this embodiment of the invention can achieve cross-chip data packet routing in a multi-processor chip system, improve throughput during the routing process, and reduce latency and system power consumption.

[0024] Figure 2 This is a schematic diagram of a multiprocessor chip system according to an embodiment of the present invention. Figure 2 The diagram shown can be interpreted as a multiprocessor chip system from a software perspective. It should be understood that... Figure 2 and Figure 1 The multi-processor chip system shown refers to the same multi-processor chip system. Furthermore, in this embodiment of the invention, the bus owner can be a routing component or a backplane management controller chip. Figure 2 The schematic diagram shown can specifically be a software-viewed diagram of a multiprocessor chip system when the baseboard management controller chip is the bus owner. For example... Figure 2 As shown, the multiprocessor chip system 2 includes multiple controlled endpoints 21 and a virtual gateway 22.

[0025] Among them, multiple controlled endpoints 21 are Figure 1 The multiple controlled endpoints 12 in the diagram will not be described again here. It should be noted that, in this implementation, the controlled endpoint a is specifically the backplane management controller chip.

[0026] Virtual gateway 22 is a logical entity that multiple route processors are considered as. Virtual gateway 22 may include multiple gateway ports 221. Each gateway port 221 may correspond to a different route processor. For example, gateway port A' may correspond to route processor A, gateway port B' may correspond to route processor B, gateway port C' may correspond to route processor C, and gateway port D' may correspond to route processor D.

[0027] Furthermore, each gateway port 221 can have a corresponding endpoint identifier. For example, gateway port A' can have a corresponding endpoint identifier 32, gateway port B' can have a corresponding endpoint identifier 33, gateway port C' can have a corresponding endpoint identifier 34, and gateway port D' can have a corresponding endpoint identifier 35. Also, the endpoint identifiers of each gateway port 221 can be mapped to target physical address identifiers. For example, the endpoint identifiers of gateway ports A', B', C', and D' are all mapped to 0:31:0.

[0028] Alternatively, as an implementation, when the baseboard management controller chip is the bus owner, the endpoint identifiers of each gateway port 221 and each controlled endpoint 21 can be assigned by the baseboard management controller.

[0029] Figure 3 This is a schematic diagram of a multi-processor chip system according to an embodiment of the present invention. It is intended to illustrate that... Figure 3 The diagram shown can be interpreted as a multiprocessor chip system from a software perspective. It should be understood that... Figure 3 The diagram shown can specifically be a software-viewed illustration of a multiprocessor chip system when the routing component is the bus owner. For example... Figure 3 As shown, the multiprocessor chip system 3 includes multiple controlled endpoints 31 and a virtual gateway 32.

[0030] Among them, multiple controlled endpoints 31 are Figure 1 The multiple controlled endpoints 12 in the document will not be described again here.

[0031] The virtual gateway 32 is a logical entity that multiple route processors are considered as. The virtual gateway 32 may include multiple gateway ports 321. Each gateway port 321 can correspond to a different route processor. For example, gateway port A' can correspond to route processor A, gateway port B' can correspond to route processor B, gateway port C' can correspond to route processor C, and gateway port D' can correspond to route processor D.

[0032] Furthermore, each gateway port 321 can have a corresponding endpoint identifier. For example, gateway port A' can have a corresponding endpoint identifier 1, gateway port B' can have a corresponding endpoint identifier 2, gateway port C' can have a corresponding endpoint identifier 3, and gateway port D' can have a corresponding endpoint identifier 4, etc. Also, the endpoint identifiers of each gateway port 221 can be mapped to target physical address identifiers. For example, the endpoint identifiers of gateway ports A', B', C', and D' are all mapped to 0:31:0.

[0033] Alternatively, as an implementation, when the routing component is the bus owner, the endpoint identifiers of each gateway port 321 and each controlled endpoint 31 can be assigned by the routing component.

[0034] Optionally, as an implementation, to ensure that each routing processor is assigned the same target physical address identifier in its respective processing chip, so that during the MCTP (Management Component Transport Protocol) initialization phase, the endpoint identifier of each gateway port can be mapped to the target physical address identifier, the target physical address identifier can be pre-assigned to each routing processor before the processing chip performs the enumeration operation. It should be noted that, in this embodiment of the invention, the enumeration operation can specifically be an operation performed by the root complex inside the processing chip after power-on. This operation is used to find and discover external devices and functional modules connected to the processing chip, and to determine a unique physical address identifier for each discovered external device and functional module in the bus, so that the processing chip can distinguish different endpoint devices and functional modules based on the physical address identifier during subsequent operation.

[0035] It should be noted that, in this embodiment of the invention, the physical address identifier (Bus Device Function, BDF) is specifically used to characterize the actual physical location of an external device or functional module in the bus, and includes information such as the bus number, device number, and function number. Furthermore, the endpoint identifier can be a communication port number assigned to an external device or functional module with communication needs during the MCTP protocol initialization phase, after the external device or functional module with communication needs is considered as a communication endpoint. The endpoint identifier is used to point to the corresponding communication endpoint (i.e., the controlled endpoint and the routing processor). It should be understood that, in this embodiment of the invention, the endpoint identifier of each communication endpoint is globally unique, while the physical address identifiers determined by different processing chips for the controlled endpoints they connect to can be duplicated. For example, Figure 2Controlled endpoints d and e in the virtual gateway can have the same physical address identifier. Furthermore, unlike endpoint identifiers used to point to corresponding communication endpoints globally, in this embodiment of the invention, port identifiers are used only to point to corresponding routing ports within the virtual gateway.

[0036] Figure 4 This is a flowchart of a routing method according to an embodiment of the present invention. It is intended to be noted that... Figure 4 The execution entity of the routing method shown can be the routing processor in the above embodiments. By executing, as... Figure 4 The routing method shown allows the route processor to route data packets. For example... Figure 4 As shown, the routing method may specifically include the following steps: Step S100: Receive the data packet to be transmitted.

[0037] Specifically, for any controlled endpoint, when there is a need for cross-chip communication, the controlled endpoint can send a data packet carrying relevant data or instructions to the virtual gateway based on the target physical address identifier. Inside the virtual gateway, the routing processor can receive data packets to be transmitted from the corresponding controlled endpoint (that is, the controlled endpoint connected to its own processing chip).

[0038] Optionally, in this embodiment of the invention, each processing chip may have a corresponding local routing table. The local routing table can be used to record the mapping relationship between the endpoint identifier and physical address identifier of a local controlled endpoint, and to record the mapping relationship between the endpoint identifier and target physical address identifier of a non-local controlled endpoint. For any controlled endpoint, when sending a data packet to be transmitted, the controlled endpoint can generate the corresponding header in the data packet to be transmitted (i.e., the bus transmission header and management component header) according to the local routing table, so that the interconnect bus can transmit the data packet to be transmitted from the controlled endpoint to the virtual gateway according to the corresponding header in the data packet to be transmitted.

[0039] Figure 5 This is a schematic diagram of a local routing table according to an embodiment of the present invention. It is intended to illustrate that... Figure 5 The local routing table shown can be Figure 2 The local routing table of processing chip A corresponding to gateway port A' in the table. For example... Figure 5 As shown, the local routing table 51 can record the mapping relationship between the endpoint identifiers and physical address identifiers of local controlled endpoints a and b, as well as the mapping relationship between the endpoint identifiers and target physical address identifiers of non-local controlled endpoints c, d, and e.

[0040] Figure 6 This is a schematic diagram of a local routing table according to an embodiment of the present invention. It is intended to illustrate that... Figure 6The local routing table shown can be Figure 2 The local routing table of the processing chip D corresponding to the gateway port D' in the table. For example... Figure 6 As shown, the local routing table 61 can record the mapping relationship between the endpoint identifier and physical address identifier of the local controlled endpoint e, as well as the mapping relationship between the endpoint identifier and the target physical address identifier of the non-local controlled endpoints a, b, c and d.

[0041] Figure 7 This is a schematic diagram illustrating the routing process according to an embodiment of the present invention. It is intended to be noted that... Figure 7 The routing process shown may include the routing process between controlled endpoint a and controlled endpoint e when controlled endpoint a sends request data or a request command to controlled endpoint e, and the routing process between controlled endpoint e and controlled endpoint a when controlled endpoint e sends response data or a response command back to controlled endpoint a. Also, for illustrative purposes, Figure 7 The routing information and related changes during the routing process are presented in tabular form. However, it should be understood that in practical applications, routing information is embedded in the corresponding header fields of the data packets to be transmitted. For example... Figure 7 As shown, when controlled endpoint a has a need to send request data or request data to controlled endpoint e, controlled endpoint a can do so according to the local routing table of its own chip (i.e., Figure 5 The local routing table 51 shown generates corresponding headers in the transmission data packets to indicate that the source endpoint identifier is 2 (i.e., the endpoint identifier of controlled endpoint a), the receiving endpoint identifier is 192 (i.e., the endpoint identifier of controlled endpoint e), the requester physical address identifier is 128:1:0 (i.e., the physical address identifier of controlled endpoint a), and the destination physical address identifier is 0:31:0 (i.e., the physical address identifier of the virtual gateway), so that the interconnect bus can transmit the data packet to be transmitted from controlled endpoint a to the virtual gateway according to the corresponding header in the data packet to be transmitted.

[0042] Furthermore, when controlled endpoint e needs to send response data or response commands to controlled endpoint a, controlled endpoint e can also do so according to the local routing table of its own chip (i.e., Figure 6 The local routing table 61 shown generates corresponding headers in the transmission data packets to indicate that the source endpoint identifier is 192 (i.e., the endpoint identifier of the controlled endpoint e), the receiving endpoint identifier is 2 (i.e., the endpoint identifier of the controlled endpoint a), the requester physical address identifier is 141:1:1 (i.e., the physical address identifier of the controlled endpoint e), and the destination physical address identifier is 0:31:0 (i.e., the physical address identifier of the virtual gateway), so that the interconnect bus can transmit the data packet to be transmitted from the controlled endpoint e to the virtual gateway according to the corresponding header in the data packet to be transmitted.

[0043] It should be noted that, in practical applications, the aforementioned source endpoint identifier and receiver endpoint identifier can be embedded in the management component header. The content and format of this management component header can conform to the MCTP (Management Component Transport Protocol) to clearly identify the source and receiver endpoints corresponding to the current data packet. Furthermore, the aforementioned requester physical address identifier and destination physical address identifier can be embedded in the bus transport header. The content and format of this bus transport header can conform to the corresponding bus protocol (e.g., PCIe bus cooperation or SMBUS bus protocol) to instruct the interconnect bus to transmit the current data packet from the requester to the destination. It should be understood that the bus transport header is typically located at the outermost layer of the data packet, the management component header can be located in the middle layer, and the payload is located at the innermost layer.

[0044] Figure 8 This is a schematic diagram of the data packet structure according to an embodiment of the present invention. Figure 8 As shown, a complete data packet may include a bus transmission header 81, a management component header 82, and a payload 83. The bus transmission header 81 is located at the outermost layer of the data packet. The content and format of the bus transmission header 81 conform to the MCTP (Management Component Transport Protocol) to clearly identify the source and receiving endpoints of the current data packet to relevant parties. The management component header 82 is located at the middle layer of the data packet. The content and format of the management component header 82 conform to the corresponding bus protocol (e.g., PCIe bus cooperation or SMBUS bus protocol), and it instructs the interconnect bus to transmit the current data packet from the requester to the destination. The payload 83 may be located at the innermost layer of the data packet. The payload 83 is raw data or raw instructions.

[0045] Step S200: The data packet to be transmitted is parsed to obtain the receiver endpoint identifier.

[0046] Specifically, upon receiving a data packet to be transmitted, the routing processor can parse the data packet to obtain the receiving endpoint identifier. The receiving endpoint can be a controlled endpoint that ultimately needs to receive the data packet. The receiving endpoint identifier can be the endpoint identifier of the receiving endpoint.

[0047] Figure 9 This is a flowchart of a data packet parsing method according to an embodiment of the present invention. It is intended to illustrate that by executing... Figure 9The packet parsing method shown allows the route processor to parse packets and obtain the required receiving endpoint identifier. For example... Figure 9 As shown, the packet parsing method may specifically include the following steps: Step S210: Delete the bus transmission packet header of the data packet to be transmitted to obtain the management component protocol packet to be transmitted.

[0048] Specifically, to parse the data packet to be transmitted, the routing processor can first delete the original bus transmission header (used to instruct the bus to transmit the data packet from the source endpoint to the virtual gateway) of the data packet to be transmitted, in order to obtain the management component protocol packet to be transmitted. The management component protocol packet to be transmitted is the data packet to be transmitted after deleting the outermost bus transmission header. Furthermore, the management component protocol packet to be transmitted may further include a management component header. It should be noted that, depending on the connection bus used, the bus transmission header can be a PCIe bus transmission header or an SMBus / I2C bus transmission header; this application does not impose any limitation on this.

[0049] Step S220: Parse the management component header of the management component protocol packet to be transmitted to obtain the receiving endpoint identifier of the receiving endpoint.

[0050] Specifically, the management component header records the source endpoint identifier of the source endpoint and the receiver endpoint identifier of the receiver endpoint. In this step, after obtaining the management component protocol packet to be transmitted, the routing processor can parse the management component header of the protocol packet to be transmitted to obtain the required receiver endpoint identifier.

[0051] Step S300: In the global routing table, query and determine the receiving physical address identifier of the receiving endpoint and the target port identifier of the target gateway port to which the receiving endpoint is connected, based on the receiving endpoint identifier.

[0052] Specifically, for a virtual gateway, it can maintain a corresponding global routing table. In this step, the routing processor can query the global routing table based on the receiving endpoint identifier to determine the receiving physical address identifier of the receiving endpoint and the target port identifier of the target gateway port to which the receiving endpoint is connected. The global routing table records the mapping relationship between the endpoint identifier and physical address identifier of the controlled endpoint, as well as the port identifier of the gateway port to which the controlled endpoint is connected.

[0053] Figure 10 This is a schematic diagram of the global routing table according to an embodiment of the present invention. It is intended to illustrate that... Figure 10 The global routing table shown can be compared with... Figure 2 This corresponds to the multi-processor chip system shown. For example... Figure 10As shown, the global routing table 101 records the mapping relationship between the endpoint identifiers and physical address identifiers of the controlled endpoints a, b, c, d and e, and can also record the port identifiers of the gateway ports connected to the controlled endpoints a, b, c, d and e.

[0054] like Figure 7 As shown, when a data packet to be transmitted is received from the controlled endpoint a, the routing processor (specifically the routing processor corresponding to gateway port A') can determine the receiving endpoint identifier (i.e., 192) of the receiving endpoint e by parsing the data packet. After determining the receiving endpoint identifier, the routing processor can retrieve the data packet from the global routing table (e.g., ...). Figure 10 In the global routing table 101 shown in the table, the receiving physical address identifier (i.e., 114:1:1) of the receiving endpoint e and the target port identifier (i.e., 3) of the target gateway port to which the receiving endpoint e is connected are determined by querying the receiving endpoint identifier.

[0055] Furthermore, when a data packet to be transmitted is received from the controlled endpoint e, the routing processor (specifically, the routing processor corresponding to gateway port D') can determine the receiving endpoint identifier (i.e., 2) of the receiving endpoint a by parsing the data packet. After determining the receiving endpoint identifier, the routing processor can then access the global routing table (e.g., ...). Figure 10 In the global routing table 101 shown in the table, the receiving physical address identifier (i.e., 128:1:0) of receiving endpoint a and the target port identifier (i.e., 0) of the target gateway port to which receiving endpoint a is connected are determined by querying the receiving endpoint identifier.

[0056] It is worth noting that, in this embodiment of the invention, the port identifier of the gateway port connected to the controlled endpoint, recorded in the global routing table, can be used to indicate the forwarding of data packets between different routing processors. Therefore, in the actual routing process, the routing processor can forward the data packet to be transmitted with its updated bus transmission header to the corresponding target routing processor based on the target port identifier of the target gateway port connected to the receiving endpoint.

[0057] Step S400: Update the bus transmission header of the data packet to be transmitted according to the received physical address identifier and the target physical address identifier.

[0058] Specifically, after determining the receive physical address identifier of the receiving endpoint, the routing processor can update the bus transmission header of the data packet to be transmitted based on the receive physical address identifier and the destination physical address identifier.

[0059] Figure 11 This is a flowchart of a bus transmission packet header update method according to an embodiment of the present invention. It is intended to illustrate that by executing... Figure 11The bus transmission header update method shown allows the routing processor to update the bus transmission header of the data packet to be transmitted. For example... Figure 11 As shown, the bus transmission packet header update method may specifically include the following steps: Step S410: Generate a new bus transmission header based on the received physical address identifier and the target physical address identifier.

[0060] Specifically, the routing processor can generate a new bus transmission packet header based on the received physical address identifier and the destination physical address identifier.

[0061] like Figure 7 As shown, after determining the receive physical address identifier (i.e., 114:1:1) of the receiving endpoint e, the routing processor can generate a new bus transport header to indicate that the requester's physical address identifier is 0:31:0 (i.e., the physical address identifier of the virtual gateway) and the destination's physical address identifier is 141:1:1 (i.e., the physical address identifier of the controlled endpoint e). It should be understood that this new bus transport header can be used to instruct the bus to transmit data packets from the virtual gateway to the receiving endpoint e.

[0062] Furthermore, after determining the receive physical address identifier (i.e., 128:1:0) of receiving endpoint a, the routing processor can generate a new bus transport header indicating that the requester's physical address identifier is 0:31:0 (i.e., the virtual gateway's physical address identifier) ​​and the destination's physical address identifier is 128:1:0 (i.e., the controlled endpoint a's physical address identifier). It should be understood that this new bus transport header can be used to instruct the bus to transmit data packets from the virtual gateway to receiving endpoint a.

[0063] Step S420: Concatenate the protocol packet of the management component to be transmitted with the header of the new bus transmission packet.

[0064] Specifically, the routing processor can concatenate the protocol packets of the management components to be transmitted with the header of the new bus transmission packets.

[0065] Optionally, when parsing the data packet to be transmitted, if the parsing method used by the routing processor in the previous steps is the direct parsing method, then before executing step S420, the routing processor may first delete the bus transmission packet header of the data packet to be transmitted, thereby obtaining the management component protocol packet to be transmitted. This application does not impose any restrictions on this.

[0066] Step S500: Forward the data packet to be transmitted to the corresponding target routing processor according to the target port identifier, so as to instruct the target routing processor to send the data packet to be transmitted to the receiving endpoint.

[0067] Specifically, after updating the bus transmission header of the data packet to be transmitted, the routing processor can forward the data packet to be transmitted to the target routing processor based on the destination port identifier, thereby instructing the target routing processor to send the data packet to the receiving endpoint. It should be understood that within the virtual gateway, the data packet forwarding method between routing processors can be implemented in any way (e.g., data packet forwarding based on inter-chip interconnect bus or data packet forwarding based on memory address mapping, etc.), and this application does not impose any restrictions on this.

[0068] like Figure 7 As shown, for a data packet to be transmitted from the controlled endpoint a, the routing processor corresponding to the gateway port A' can forward the data packet to be transmitted to the target routing processor (i.e., the routing processor corresponding to the gateway port C') according to the target port identifier (i.e., 3), so as to instruct the target routing processor to send the data packet to be transmitted to the receiving endpoint.

[0069] For a data packet to be transmitted from the controlled endpoint e, the routing processor corresponding to the gateway port C' can forward the data packet to be transmitted to the target routing processor (i.e., the routing processor corresponding to the gateway port A') according to the destination port identifier (i.e., 0), so as to instruct the target routing processor to send the data packet to the receiving endpoint.

[0070] Alternatively, as one implementation, packet routing between controlled endpoints connected to the same processing chip can also be implemented by a routing processor. In this implementation, when forwarding a packet to be transmitted, the routing processor can first check whether the destination port identifier matches the port identifier of the gateway port corresponding to the current routing processor in the virtual gateway. If they do not match, the routing processor can forward the packet to be transmitted to the target routing processor based on the destination port identifier, instructing the target routing processor to send the packet to the receiving endpoint. If they match, the routing processor can directly send the packet to the receiving endpoint.

[0071] This invention pre-registers virtual gateways and assigns routing processors located in different processing chips to different gateway ports within the virtual gateways. It then assigns corresponding endpoint identifiers to each gateway port and establishes a mapping between these endpoint identifiers and the same target physical address identifier. The routing processors then use a global routing table to send and receive data packets in pure hardware. Therefore, this invention can build a routing network between different processing chips, enabling controlled endpoints on each processing chip to route data packets based on this network. This achieves cross-chip data packet routing in multi-processor chip systems, improves throughput during routing, and reduces latency and system power consumption.

[0072] Figure 12This is a schematic diagram of a routing device according to an embodiment of the present invention. Figure 12 As shown, the routing device of this embodiment includes a receiving unit 121, a parsing unit 122, a querying unit 123, a packet header updating unit 124, and a sending unit 125.

[0073] Specifically, the receiving unit 121 is used to receive data packets to be transmitted.

[0074] The parsing unit 122 is used to parse the data packet to be transmitted in order to obtain the receiving endpoint identifier of the receiving endpoint.

[0075] The query unit 123 is used to query and determine the receiving physical address identifier of the receiving endpoint and the target port identifier of the target gateway port to which the receiving endpoint is connected in the global routing table, based on the receiving endpoint identifier. The global routing table is used to record the mapping relationship between the endpoint identifier and the physical address identifier of the controlled endpoint, and to record the port identifier of the gateway port to which the controlled endpoint is connected.

[0076] The packet header update unit 124 is used to update the bus transmission packet header of the data packet to be transmitted according to the received physical address identifier and the target physical address identifier. The current routing processor and the other routing processors in the routing component are respectively set in different processing chips. Each routing processor has the same target physical address identifier in its respective processing chip. Each routing processor corresponds to a different gateway port in the virtual gateway. Each gateway port has a corresponding endpoint identifier. The endpoint identifier of each gateway port is mapped to the target physical address identifier.

[0077] The sending unit 125 is used to forward the data packet to be transmitted to the corresponding target routing processor according to the target port identifier, so as to instruct the target routing processor to send the data packet to be transmitted to the receiving endpoint.

[0078] This invention pre-registers virtual gateways and assigns routing processors located in different processing chips to different gateway ports within the virtual gateways. It then assigns corresponding endpoint identifiers to each gateway port and establishes a mapping between these endpoint identifiers and the same target physical address identifier. The routing processors then use a global routing table to send and receive data packets in pure hardware. Therefore, this invention can build a routing network between different processing chips, enabling controlled endpoints on each processing chip to route data packets based on this network. This achieves cross-chip data packet routing in multi-processor chip systems, improves throughput during routing, and reduces latency and system power consumption.

[0079] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A routing component, characterized in that, The routing component is suitable for multi-processor chip systems, and the routing component includes: Multiple routing processors are provided, wherein each routing processor is disposed in a different processing chip, each routing processor has the same target physical address identifier in its respective processing chip, each routing processor corresponds to a different gateway port in the virtual gateway, each gateway port has a corresponding endpoint identifier, and the endpoint identifier of each gateway port is mapped to the target physical address identifier. Each of the aforementioned routing processors is configured to perform the following steps: Receive the data packet to be transmitted; The data packet to be transmitted is parsed to obtain the receiver endpoint identifier. In the global routing table, the receiving physical address identifier of the receiving endpoint and the target port identifier of the target gateway port to which the receiving endpoint is connected are determined by querying based on the receiving endpoint identifier. The global routing table is used to record the mapping relationship between the endpoint identifier and the physical address identifier of the controlled endpoint, and to record the port identifier of the gateway port to which the controlled endpoint is connected. The bus transmission header of the data packet to be transmitted is updated according to the received physical address identifier and the target physical address identifier. The data packet to be transmitted is forwarded to the corresponding target routing processor according to the target port identifier, so as to instruct the target routing processor to send the data packet to be transmitted to the receiving endpoint.

2. The routing component according to claim 1, characterized in that, The routing processor is specifically configured as follows: In response to the detection that the target port identifier is inconsistent with the port identifier of the gateway port corresponding to the current routing processor in the virtual gateway, the data packet to be transmitted is forwarded to the corresponding target routing processor according to the target port identifier, so as to instruct the target routing processor to send the data packet to be transmitted to the receiving endpoint.

3. The routing component according to claim 2, characterized in that, The routing processor is also configured to: In response to the detection that the target port identifier matches the port identifier of the gateway port corresponding to the current routing processor in the virtual gateway, the data packet to be transmitted is sent to the receiving endpoint.

4. The routing component according to claim 1, characterized in that, The target physical address identifier is pre-assigned to each of the routing processors before each of the processing chips performs the enumeration operation.

5. The routing component according to claim 1, characterized in that, The routing processor is specifically configured as follows: Delete the bus transmission packet header of the data packet to be transmitted to obtain the management component protocol packet to be transmitted, wherein the management component protocol packet to be transmitted includes a management component packet header; The management component header of the protocol packet to be transmitted is parsed to obtain the receiving endpoint identifier of the receiving endpoint.

6. The routing component according to claim 5, characterized in that, The routing processor is specifically configured as follows: A new bus transmission packet header is generated based on the received physical address identifier and the target physical address identifier; The protocol packet of the management component to be transmitted is concatenated with the header of the new bus transmission packet.

7. The routing component according to claim 1, characterized in that, The endpoint identifiers of each gateway port and each controlled endpoint are assigned by the routing component, or the endpoint identifiers of each gateway port and each controlled endpoint are assigned by the baseboard management controller.

8. The routing component according to claim 1, characterized in that, Each chip has a corresponding local routing table, which is used to record the mapping relationship between the endpoint identifier and the physical address identifier of the local controlled endpoint, and to record the mapping relationship between the endpoint identifier and the target physical address identifier of the non-local controlled endpoint. The original bus transmission packet header in the data packet to be transmitted is generated by the source endpoint based on the corresponding local routing table.

9. A routing method, characterized in that, The method is applicable to a routing processor, and the method includes: Receive the data packet to be transmitted; The data packet to be transmitted is parsed to obtain the receiver endpoint identifier. In the global routing table, the receiving physical address identifier of the receiving endpoint and the target port identifier of the target gateway port to which the receiving endpoint is connected are determined by querying based on the receiving endpoint identifier. The global routing table is used to record the mapping relationship between the endpoint identifier and the physical address identifier of the controlled endpoint, and to record the port identifier of the gateway port to which the controlled endpoint is connected. The data packet to be transmitted is updated in the bus transmission header according to the received physical address identifier and the target physical address identifier. The current routing processor and the other routing processors in the routing component are respectively set in different processing chips. Each routing processor has the same target physical address identifier in its respective processing chip. Each routing processor corresponds to a different gateway port in the virtual gateway. Each gateway port has a corresponding endpoint identifier. The endpoint identifier of each gateway port is mapped to the target physical address identifier. The data packet to be transmitted is forwarded to the corresponding target routing processor according to the target port identifier, so as to instruct the target routing processor to send the data packet to be transmitted to the receiving endpoint.

10. A routing device, characterized in that, The device includes: The receiving unit is used to receive data packets to be transmitted. The parsing unit is used to parse the data packet to be transmitted in order to obtain the receiver endpoint identifier of the receiving endpoint; The query unit is used to query and determine the receiving physical address identifier of the receiving endpoint and the target port identifier of the target gateway port to which the receiving endpoint is connected in the global routing table based on the receiving endpoint identifier. The global routing table is used to record the mapping relationship between the endpoint identifier and the physical address identifier of the controlled endpoint, and to record the port identifier of the gateway port to which the controlled endpoint is connected. The packet header update unit is used to update the bus transmission packet header of the data packet to be transmitted according to the received physical address identifier and the target physical address identifier. The current routing processor and the other routing processors in the routing component are respectively set in different processing chips. Each routing processor has the same target physical address identifier in its respective processing chip. Each routing processor corresponds to a different gateway port in the virtual gateway. Each gateway port has a corresponding endpoint identifier. The endpoint identifier of each gateway port is mapped to the target physical address identifier. The sending unit is configured to forward the data packet to be transmitted to the corresponding target routing processor according to the target port identifier, so as to instruct the target routing processor to send the data packet to be transmitted to the receiving endpoint.

11. A multiprocessor chip system, characterized in that, The system includes: Multiple processing chips; Multiple controlled endpoints, wherein each of the controlled endpoints is connected to a corresponding processing chip; Interconnect bus, used to enable communication between processing chips, and to enable communication between processing chips and controlled endpoints; The routing component as described in any one of claims 1-8.

12. An electronic device, characterized in that, The device includes: The multiprocessor chip system as described in claim 11.

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