A communication node data forwarding optimization method based on a graph neural network

Abstract

The present application relates to the technical field of communication network routing, in particular to a communication node data forwarding optimization method based on a graph neural network, comprising: collecting the physical link state and the backlog number of the buffer queue of local and one-hop neighbor nodes, generating an event priority distribution histogram and constructing a local heterogeneous graph; comparing the hash fingerprints of the current and historical local heterogeneous graph states, triggering the graph neural network event trigger forward inference when the fingerprints are inconsistent; inputting the distribution histogram as a gating signal into a hybrid expert system to dynamically tilt the optimization weight, synchronously outputting the primary and backup routing binary tuples in a single inference; comparing the extracted original routing logic feature values with the reference judgment threshold representing the current physical channel connection state, implementing a negative infinite punishment on illegal links that exhaust the duty cycle quota, and obtaining the final primary and backup routes. The present application effectively solves the efficient calculation of dual-mode heterogeneous network routing under limited computing power and the high-reliability retransmission of burst flow.

Description

Technical Field

[0001] This invention relates to the field of communication network routing technology, specifically to a method for optimizing data forwarding at communication nodes based on graph neural networks. Background Technology

[0002] In existing dual-mode (power line carrier and low-power wireless) communication networks, routing calculations largely rely on traditional metric algorithms or periodic network-wide flooding. Due to the extremely limited hardware resources of the underlying edge nodes (such as the computing power and SRAM capacity of microcontrollers), highly complex intelligent routing algorithms are difficult to deploy directly. This results in the network being unable to accurately assess the physical link status in real time when facing sudden electromagnetic interference or severe channel fading. Furthermore, existing dual-mode routing often performs media selection at the network layer or hybrid abstraction layer, failing to address the scenario of ACK timeouts for sudden tripping commands in circuit breaker MCUs by pre-embedding backup RF targets as lightweight fields in the MAC transmission buffer and completing the switching in a hardware interrupt. This cross-layer interaction causes transmission latency that significantly reduces the reliability and concurrent response performance of industrial field-level communication.

[0003] To address this, a method for optimizing data forwarding at communication nodes based on graph neural networks is proposed. Summary of the Invention

[0004] This invention aims to provide a data forwarding optimization method for communication nodes based on graph neural networks. Through a state hash triggering mechanism and a hybrid expert system, it achieves accurate routing and scheduling of multiple service flows with extremely low computational overhead, and realizes the switching of heterogeneous backup links through cross-layer hardware interrupts.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A method for optimizing data forwarding in communication nodes based on graph neural networks, the method comprising:

[0007] Collect the physical link status of local and one-hop neighbor nodes, obtain the backlog of leakage trip commands and periodic telemetry data in the circuit breaker memory buffer queue, generate an event priority distribution histogram, and construct a local heterogeneous graph in combination with the physical link status.

[0008] Using the hash generator built into the circuit breaker MCU, the hash fingerprint of the current local heterogeneous graph state is compared with the hash fingerprint of the historical state in SRAM; it is determined whether the hash fingerprint has changed. When it has changed, the graph neural network is triggered to perform event-triggered forward inference to obtain the cost embedding for the candidate route tuple.

[0009] The proportion array of the backlog of each service type in the event priority distribution histogram is used as a gating signal and directly input to the gating network of the hybrid expert system. The gating network generates the hybrid weight coefficients of each expert network accordingly, performs dynamic tilting of the optimization weights, and obtains the preferred primary route tuple that is synchronously output under a single forward inference, as well as the second-best backup route tuple for dealing with electromagnetic pulse interference.

[0010] The extracted original routing logical feature values ​​are compared with the benchmark judgment threshold representing the current physical channel connectivity status. Illegal links that have exhausted their duty cycle quotas are penalized with negative infinity to obtain the final primary and backup route tuples that meet the physical constraints.

[0011] Preferably, the generated event priority distribution histogram includes:

[0012] The system invokes the circuit breaker's built-in high-speed power line carrier and long-range low-power wireless dual-mode communication module and the system's underlying queue manager to collect the physical link status of local and neighboring nodes within one-hop physical coverage area; extracts the instantaneous attenuation of the high-speed power line carrier channel and the received signal strength and spreading factor of the long-range low-power wireless channel from the physical link status; synchronously reads the backlog of leakage trip commands and periodic telemetry data in the circuit breaker's memory buffer queue; and generates an event priority distribution histogram based on the backlog corresponding to different service types.

[0013] Preferably, the step of constructing a local heterogeneous graph by combining the physical link states specifically includes:

[0014] The high-speed power line carrier links between nodes are used as carrier physical medium edges, and the extracted instantaneous attenuation is encapsulated as a unique feature vector of the carrier physical medium edge; the long-distance low-power wireless links between nodes are used as wireless physical medium edges, and the received signal strength and the spreading factor are encapsulated as unique feature vectors of the wireless physical medium edge; in the graph topology, the carrier physical medium edges and the wireless physical medium edges are distinguished as dual heterogeneous edges with independent feature vectors; combined with the event priority distribution histogram, a local heterogeneous graph with the current circuit breaker as the central node is obtained.

[0015] Preferably, obtaining the cost embedding for the candidate route tuple specifically includes:

[0016] Extract the node state features and heterogeneous edge features of the local heterogeneous graph, perform hash calculation through the hash generator built into the circuit breaker MCU, and generate the current hash fingerprint that represents the current network topology and physical link status; read the historical hash fingerprint of the previous routing optimization cycle from the SRAM, and perform a bit-by-bit consistency comparison between the current hash fingerprint and the historical hash fingerprint in the MCU arithmetic logic unit;

[0017] When the current hash fingerprint is inconsistent with the historical hash fingerprint, it is determined that a physical link state change has occurred, and the graph neural network is awakened to perform the event-triggered forward inference; when the current hash fingerprint is consistent with the historical hash fingerprint, the MCU keeps the graph neural network in sleep mode and directly reuses the primary and backup route pairs output by the previous forward inference in the SRAM route output buffer; during the forward propagation process, a preset heterogeneous weight matrix is ​​invoked to perform independent feature projection for the exclusive feature vector of the high-speed power line carrier physical medium and the exclusive feature vector of the long-distance low-power wireless physical medium, respectively, to isolate the dimensions and feature spaces of different physical channels;

[0018] Based on the projected heterogeneous features, the state information of one-hop neighbor nodes is aggregated, the cost embedding for candidate route tuples is calculated, and the historical hash fingerprint in the SRAM is overwritten with the current hash fingerprint.

[0019] Preferably, obtaining the primary route tuple and the backup route tuple specifically includes:

[0020] The distribution ratio of backlogged data in the event priority distribution histogram is mapped to a gating weight vector, which is then input into the hybrid expert system as the gating signal.

[0021] The analysis of the service flow characteristics of the event priority distribution histogram includes: when the histogram indicates the existence of distribution characteristics representing the leakage current tripping command, it is determined that there is a burst service flow in the current network. The weight coefficient of the first expert network in the mixed output is increased by the gating weight vector. The first expert network is configured to select the preferred path where the link stability and transmission hop count meet the delay constraint conditions; when the histogram indicates that there is only a distribution characteristic representing temperature telemetry data in the current network, it is determined that there is only a periodic service flow. The weight coefficient of the second expert network in the mixed output is increased by the gating weight vector. The second expert network is configured to select the load balancing path where the remaining duty cycle and node energy consumption meet the preset threshold.

[0022] The outputs of the first expert network and the second expert network are dynamically weighted and fused using the gated weight vector to achieve dynamic tilting of the optimization weights. Based on the evaluation results after weighted fusion, the preferred primary route pair with the highest probability distribution and the second-best backup route pair with the second-highest probability distribution for dealing with electromagnetic pulse interference are simultaneously calculated under the single forward inference of the graph neural network.

[0023] Preferably, comparing the extracted original routing logical feature values ​​with the benchmark judgment threshold characterizing the current physical channel connectivity status includes:

[0024] The expected airtime of the current data packet to be forwarded on the corresponding communication channel is calculated based on the modulation parameters, coding rate, and payload length. The expected airtime is then compared with the remaining duty cycle quota of the current circuit breaker node to generate a binarized blocking mask matrix. When the expected airtime is greater than the remaining duty cycle quota, the corresponding candidate link is marked as an illegal link that has exhausted its duty cycle quota in the binarized blocking mask matrix.

[0025] Using the binarized blocking mask matrix, by superimposing a negative infinity penalty on the routing tuples corresponding to the illegal links, a mask soft maximization operation is performed on the original routing logic values ​​output by the network, forcing the probability distribution of the illegal links after normalization to converge to zero; illegal links whose probability distributions converge to zero are eliminated, and the final primary routing tuple and backup routing tuple that meet the physical duty cycle constraints are output from the remaining legal links.

[0026] Preferably, the method further includes:

[0027] Obtain the final primary route tuple and backup route tuple, perform protocol assembly of the underlying protocol data unit, map the primary route tuple to the preferred forwarding destination address of the current data packet; hardcode the backup route tuple as a backup routing policy into the extended header field of the Media Access Control (MAC) layer, and send the data packet along the primary high-speed power line carrier (HPLC) link; start the hardware timeout timer of the underlying MAC controller, and listen for the primary HPLC link local acknowledgment (ACK) frame for the data packet;

[0028] When an arcing interference occurs and the local acknowledgment (ACK) frame is not received within a preset time threshold, the hardware timeout interrupt routine of the underlying MAC controller is triggered; the underlying interrupt service routine is entered, and the backup routing strategy is directly extracted from the extended header field of the MAC layer without waking up the upper network layer routing protocol stack.

[0029] Based on the extracted backup routing strategy, the backup RF chip is directly activated in the underlying interrupt service routine, and the data packet is switched to a long-distance low-power wireless physical channel for transmission, resulting in extremely fast retransmission of the heterogeneous backup link.

[0030] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0031] 1. By serializing the state features of all nodes and the heterogeneous edge features of the local heterogeneous graph to generate a hash fingerprint, the graph neural network is only activated to perform forward propagation when the current hash fingerprint does not match the historical hash fingerprint in SRAM bit by bit; when they match, the routing result of the previous cycle is directly reused, skipping all matrix operations. Compared with traditional periodic routing inference, this mechanism effectively avoids redundant computational overhead of the microcontroller under steady-state network conditions, significantly reduces system CPU utilization and dynamic power consumption, and thus better adapts to resource-constrained underlying communication hardware nodes.

[0032] 2. By calculating the expected airtime and remaining duty cycle quota of the data packets to be forwarded, a binary blocking mask matrix is ​​generated. Then, a mask soft maximization operation is combined at the model output to impose a negative infinity penalty on illegal links. This design directly embeds physical constraints into the model's probability distribution layer, converging the probability of links exhausting their duty cycle quota to zero, effectively avoiding excessive resource allocation and ensuring that the output strategy meets the underlying physical constraints.

[0033] 3. Through a collaborative design of service gating bias, single-time synchronous inference, and underlying interrupt response, the hybrid expert system synchronously outputs primary and backup routes during single inference. The system then hardcodes the backup route into the MAC layer header. When the primary link experiences local ACK timeout due to arc interference, the system directly extracts the frame header information and activates the backup RF chip in the hardware interrupt service routine. This collaborative design breaks through the independent barrier between upper-layer route calculation and lower-layer link control, avoids the conventional protocol stack backtracking process, and provides lower-latency heterogeneous channel switching capabilities for bursty high-priority data. Attached Figure Description

[0034] Figure 1 This is a flowchart illustrating the steps of a communication node data forwarding optimization method based on graph neural networks according to the present invention.

[0035] Figure 2 This is a schematic diagram of the hash fingerprint event-driven triggering process of the present invention;

[0036] Figure 3 This is a schematic diagram of the hardware timeout interrupt heterogeneous retransmission process of the present invention. Detailed Implementation

[0037] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0038] Please see Figures 1 to 3This invention provides a method for optimizing data forwarding in communication nodes based on graph neural networks, referring to... Figure 1 Flowchart Figure 2 A flowchart illustrating the event-driven triggering process of hash fingerprinting, and Figure 3 A schematic diagram of the hardware timeout interrupt heterogeneous retransmission process; the technical solution is as follows:

[0039] Collect the physical link status of local and one-hop neighbor nodes, obtain the backlog of leakage trip commands and periodic telemetry data in the circuit breaker memory buffer queue, generate an event priority distribution histogram, and construct a local heterogeneous graph in combination with the physical link status.

[0040] Using the hash generator built into the circuit breaker MCU, the hash fingerprint of the current local heterogeneous graph state is compared with the hash fingerprint of the historical state in SRAM; it is determined whether the hash fingerprint has changed. When it has changed, the graph neural network is triggered to perform event-triggered forward inference to obtain the cost embedding for the candidate route tuple.

[0041] The proportion array of the backlog of each service type in the event priority distribution histogram is used as a gating signal and directly input to the gating network of the hybrid expert system. The gating network generates the hybrid weight coefficients of each expert network accordingly, performs dynamic tilting of the optimization weights, and obtains the preferred primary route tuple that is synchronously output under a single forward inference, as well as the second-best backup route tuple for dealing with electromagnetic pulse interference.

[0042] The extracted original routing logical feature values ​​are compared with the benchmark judgment threshold representing the current physical channel connectivity status. Illegal links that have exhausted their duty cycle quotas are penalized with negative infinity to obtain the final primary and backup route tuples that meet the physical constraints.

[0043] Example 1:

[0044] In a typical deployment environment of a power distribution network, multiple circuit breaker nodes are each equipped with a resource-constrained MCU and a built-in high-speed power line carrier and long-distance low-power wireless dual-mode communication module. Each node maintains a physical connection with neighboring circuit breaker nodes within a one-hop range through two types of heterogeneous physical channels. This embodiment takes a single circuit breaker node as the execution subject and follows a complete process of dual-mode physical link status acquisition and local heterogeneous graph construction, status hash triggering incremental graph neural network inference, hybrid expert system service-aware routing collaborative calculation, physical duty cycle mask constraint verification and underlying hardware interrupt heterogeneous retransmission.

[0045] First, the circuit breaker's built-in high-speed power line carrier and long-range low-power wireless dual-mode communication module and the system's underlying queue manager are invoked to collect the physical link status of local and neighboring nodes within the one-hop physical coverage area; the instantaneous attenuation of the high-speed power line carrier channel and the received signal strength and spreading factor of the long-range low-power wireless channel are extracted from the physical link status; the backlog of leakage trip commands and periodic telemetry data in the circuit breaker's memory buffer queue is read synchronously; and an event priority distribution histogram is generated based on the backlog corresponding to different service types.

[0046] Specifically, the circuit breaker MCU calls the built-in dual-mode communication module driver interface to simultaneously activate the high-speed power line carrier communication physical layer transceiver and the long-distance low-power wireless communication physical layer transceiver, sending status query frames to the local node and all neighboring nodes within the one-hop physical coverage area. Each neighboring node responds by returning the current physical layer measurement report. After the MCU's underlying driver completes the message parsing, it stores the collected physical link status data in the link status buffer of the circuit breaker's on-chip SRAM in the form of a structured array, which serves as the input source for subsequent feature extraction.

[0047] For high-speed power line carrier channels, the MCU reads the high-speed power line carrier physical layer measurement reports of each neighboring node from the link state buffer, extracts the instantaneous attenuation field from the current channel estimation result, and records the degree of amplitude attenuation of the power line channel to the reference carrier at the current moment in decibels. For example, when the instantaneous attenuation of the carrier channel returned by a neighboring node in a certain measurement period is 18 dB, this value is used as the original measurement value of the high-speed power line carrier physical medium edge feature corresponding to that node and written into the link feature temporary storage register.

[0048] For long-range low-power wireless channels, the MCU reads the long-range low-power wireless physical layer measurement reports of each neighboring node in parallel from the link state buffer, and extracts the received signal strength indication field and the spreading factor field. The received signal strength indication represents the received power level of the current wireless channel in decibels and milliwatts, and the spreading factor is an integer value indicating the ratio of the chip rate to the symbol rate used by the current radio frequency link. For example, if a neighboring node currently reports a received signal strength indication of -91 dBmW and a spreading factor of 9, then the above two fields are written together into the original measurement value temporary storage area of ​​the long-range low-power wireless physical medium edge characteristics corresponding to that node.

[0049] After completing the physical link status acquisition, the MCU calls the system's underlying queue manager interface to synchronously read the backlog of data packets of each service type in the current memory buffer queue. The memory buffer queue is divided into two independent sub-queues according to service type: the first sub-queue stores emergency burst control service data packets, which are leakage trip instructions generated in real time by the circuit breaker protection detection unit when a leakage fault event is detected. This type of service has the characteristics of unpredictable trigger frequency, small single data volume, and high sensitivity to transmission delay; the second sub-queue stores periodic acquisition and reporting service data packets, including telemetry parameters such as current sampling values, temperature measurement values, and node online status identifiers reported by the circuit breaker at regular intervals. This type of service has the characteristics of fixed generation period, large single batch data volume, and high tolerance to transmission delay. The MCU reads the current backlog of the two sub-queues respectively and writes the backlog of data packets into the backlog of data packet temporary storage register as an integer count value.

[0050] Based on the backlog of the two types of services mentioned above, the MCU constructs an event priority distribution histogram data structure in SRAM. This data structure uses the service type as the horizontal axis index and the proportion of the backlog of each service type to the total backlog as the vertical axis amplitude. It contains two discrete intervals corresponding to the number of service types. For example, if the first sub-queue currently has 3 backlogged emergency burst control data packets and the second sub-queue has 12 backlogged periodic acquisition and reporting data packets, then the amplitude of the emergency burst control interval in the histogram is 0.2 and the amplitude of the periodic acquisition and reporting interval is 0.8. This histogram is stored in a fixed-point format at a specified address in SRAM as the input data source for the subsequent gating signal generation.

[0051] By synchronously collecting dual-mode physical measurement reports and service queue status, the current link quality distribution and service load composition are fully quantified in the form of structured proportional histograms, providing accurate and real-time driving input for graph neural network gating decisions.

[0052] Furthermore, based on the physical link status, a local heterogeneous graph is constructed, specifically including: treating the high-speed power line carrier links between nodes as carrier physical medium edges, and encapsulating the extracted instantaneous attenuation as a unique feature vector of the carrier physical medium edge; treating the long-distance low-power wireless links between nodes as wireless physical medium edges, and encapsulating the received signal strength and the spreading factor as unique feature vectors of the wireless physical medium edge; in the graph topology, distinguishing the carrier physical medium edge and the wireless physical medium edge as dual heterogeneous edges with independent feature vectors; and combining the event priority distribution histogram to obtain a local heterogeneous graph with the current circuit breaker as the central node.

[0053] Specifically, the MCU reads the instantaneous attenuation of the high-speed power line carrier channel extracted in the previous steps from the link status buffer of the circuit breaker's on-chip SRAM. Taking the current circuit breaker node as the starting node, it maps each link between a local node with a high-speed power line carrier physical connection and its neighboring nodes as a carrier physical medium edge in the graph structure. The instantaneous attenuation reported by the neighboring node is encapsulated as a unique feature vector of the edge in the format of a 1-dimensional fixed-point vector and written into the independent storage partition reserved for the carrier physical medium edge type in the SRAM edge feature buffer. For example, if the local node currently has a high-speed power line carrier physical connection with 3 neighboring nodes, and the corresponding instantaneous attenuation is 18 dB, 23 dB and 31 dB respectively, then 3 carrier physical medium edges are generated in the graph structure. The feature vector dimension of each edge is 1, and the above attenuation values ​​are stored and written into the corresponding storage slots to complete the feature encapsulation of all carrier physical medium edges.

[0054] The MCU reads the received signal strength indication and spreading factor of each neighboring node from the SRAM link state buffer in parallel. It maps each node pair with a long-distance low-power wireless physical connection to a wireless physical medium edge in the graph structure. The received signal strength indication and spreading factor are concatenated into a 2D fixed-point vector in a fixed field order and written as the exclusive feature vector of the edge into a storage partition reserved separately for the wireless physical medium edge type in the SRAM edge feature buffer. For example, if the received signal strength indication currently reported by a neighboring node is -91 dBmW and the spreading factor is 9, then the two fields of the 2D exclusive feature vector corresponding to the edge are written into the corresponding storage slot in sequence. They are stored independently in the SRAM partition along with the carrier physical medium edge feature vector already encapsulated on the same node pair, without field overwriting or aliasing.

[0055] After completing the feature encapsulation of the two types of edges, the MCU constructs a heterogeneous graph data structure in SRAM in the form of an adjacency list. All carrier physical medium edges and wireless physical medium edges are registered to independent edge sets with different edge type identifiers. Each edge record consists of four fields: source node index, target node index, edge type identifier, and a pointer to the storage address of the corresponding feature vector. The two types of edge sets maintain mutually independent index areas in the overall graph data structure, so that when the graph neural network performs categorical feature projection, it can accurately address its own exclusive feature vector storage partition according to the edge type identifier. The dimensional features of different physical channels will not be confused across types before aggregation calculation.

[0056] After the heterogeneous graph topology is constructed, the MCU reads the fixed-point array of the event priority distribution histogram generated in the previous steps from the SRAM histogram storage area, and appends it to the node feature field of the current circuit breaker center node in the heterogeneous graph data structure in the form of node attribute fields. At this point, a complete local heterogeneous graph is formed with the current circuit breaker as the center node, including dual heterogeneous edges of carrier physical medium edge and wireless physical medium edge, and the center node's node feature field carries the current service load distribution information. All data of this local heterogeneous graph resides in the circuit breaker's on-chip SRAM, and is read and processed by the subsequent graph neural network inference process scheduled by the MCU main core.

[0057] By mapping two types of physical channels to heterogeneous edges with independent feature vectors and embedding the service load distribution in the feature domain of the central node, a complete expression of multidimensional heterogeneous physical states within a single graph structure is achieved, providing structurally clear input data for subsequent categorical feature projection of graph neural networks.

[0058] Further, the node state features and heterogeneous edge features of the local heterogeneous graph are extracted, and hash calculation is performed using the hash generator built into the circuit breaker MCU to generate a current hash fingerprint representing the current network topology and physical link state. The historical hash fingerprint from the previous routing optimization cycle is read from the SRAM, and a bit-by-bit consistency comparison is performed between the current hash fingerprint and the historical hash fingerprint in the MCU's arithmetic logic unit. When they are inconsistent, it is determined that a physical link state change has occurred, and the graph neural network is awakened to perform the event-triggered forward inference. When they are consistent, the MCU keeps the graph neural network in sleep mode and directly reuses it. The SRAM routing output buffer contains the primary and backup route pairs that were previously output during the forward inference, ending the current optimization cycle. During the forward propagation process, a preset heterogeneous weight matrix is ​​invoked to perform independent feature projections on the exclusive feature vectors of the high-speed power line carrier physical medium and the exclusive feature vectors of the long-distance low-power wireless physical medium, respectively, isolating the dimensions and feature spaces of different physical channels. Based on the projected heterogeneous features, the state information of one-hop neighbor nodes is aggregated, the cost embedding for the candidate route pairs is calculated and output, and the historical hash fingerprint in the SRAM is overwritten with the current hash fingerprint.

[0059] Specifically, the preset heterogeneous weight matrix is ​​a set of parameters that includes a multi-source heterogeneous historical business dataset, which is iteratively updated multiple times using a backpropagation algorithm combined with a loss such as cross-entropy, and finally solidified and converged; it is used to characterize and quantify the intrinsic mapping relationship between the feature spaces of different modalities or different types of nodes.

[0060] The MCU reads the historical hash fingerprint written in the previous routing optimization cycle from the fixed storage address of the historical hash fingerprint in SRAM. In the MCU's arithmetic logic unit, a bitwise XOR operation is performed between the current hash fingerprint and the historical hash fingerprint. If the XOR result is all zeros, the two are completely consistent. The MCU determines that the physical link state has not changed in the current routing optimization cycle, keeps the graph neural network in sleep mode, and directly reuses the primary and backup route pairs output in the previous forward inference in the SRAM routing output buffer. The current optimization cycle ends. If the XOR result is not all zeros, the two are different. The MCU determines that the physical link has undergone a state change that needs to be re-inferred and continues to wake up the graph neural network to execute the subsequent forward propagation process.

[0061] Specifically, during the system deployment phase, all weight parameters of the graph neural network and the hybrid expert system are independently generated offline by an external computing platform. The training dataset of the graph neural network consists of a large number of historical network state snapshots. Each record contains the state features of each node in the local heterogeneous graph and the physical measurement features of each type of edge, as well as the measured end-to-end transmission cost of the corresponding candidate route (labeled with the weighted values ​​of transmission delay and packet loss rate). The mean square error between the predicted cost scalar and the measured transmission cost label is used as the loss function. The Adam optimizer is used to iteratively update the three sets of weight matrices of the graph neural network until convergence. After convergence, the parameters are quantized into fixed-point numbers and written into the SRAM graph neural network weight fixed storage partition. The first expert network of the hybrid expert system is trained independently with the historical candidate route cost embedding scalar, link attenuation, and transmission hop count as input features and the measured end-to-end route transmission delay satisfaction as the label value. The second expert network is trained independently with the historical candidate route cost embedding scalar, node remaining duty cycle quota, and historical energy consumption statistics as input features and the measured network load balancing satisfaction as the label value. The gated network is trained with the relative difference of prediction errors between the two expert networks in each historical sample as the supervision signal. All parameters are quantized and written into the SRAM expert system parameter storage partition, which is stored independently from the graph neural network weight parameter partition.

[0062] Specifically, the graph neural network consists of a heterogeneous message passing layer and a linear output projection layer connected in series. It is responsible for compressing the topology and physical link states of the local heterogeneous graph into candidate route cost embedding scalars. All its weight parameters (including two sets of heterogeneous edge feature projection matrices and one set of output projection matrices, for a total of three sets) are quantized and written into the SRAM graph neural network weight fixed storage partition after offline training on an external computing platform. These weights are stored independently in the SRAM partitions, separate from the hybrid expert system parameters, without overwriting each other. In terms of inference timing, the graph neural network's forward inference executes before the hybrid expert system: after the graph neural network completes the cost embedding scalar calculation for all candidate route pairs and writes it into the SRAM cost embedding output buffer, each expert network of the hybrid expert system reads the cost embedding scalar from this buffer as one of its input features. This is then concatenated with its required supplementary features (link attenuation, hop count or remaining duty cycle, historical node energy consumption) before performing its own forward inference. The output route score is then used for gated weighted fusion. The graph neural network and the hybrid expert system are activated sequentially within the same event-triggered inference cycle, merging to form a complete single forward inference process.

[0063] The MCU reads all node state features and heterogeneous edge features from the local heterogeneous graph data structure in the on-chip SRAM of the circuit breaker. The node state features are a fixed-point array of a 2D event priority distribution histogram stored in the feature domain of the central node. The heterogeneous edge features include a fixed-point vector of 1D instantaneous attenuation corresponding to each carrier physical medium edge and a fixed-point vector of 2D received signal strength and spreading factor corresponding to each wireless physical medium edge. The MCU concatenates all the above features into a continuous feature byte sequence in the on-chip register according to a preset field concatenation order, sends it to the MCU's built-in hash generator hardware peripheral to perform hash operation, outputs a 32-bit current hash fingerprint and writes it into the current hash fingerprint register area of ​​the SRAM.

[0064] The MCU reads the historical hash fingerprint written in the last routing optimization cycle from the fixed storage address of the historical hash fingerprint in SRAM. In the MCU's arithmetic logic unit, a consistency comparison calculation is performed between the current hash fingerprint and the historical hash fingerprint. If the current hash fingerprint is inconsistent with the historical hash fingerprint, the MCU determines that the physical link has undergone a state change that needs to be re-inferred.

[0065] After the graph neural network inference is activated, the MCU loads a preset heterogeneous weight matrix from the SRAM model weight fixed storage partition. The input dimension of the carrier physical medium edge-specific projection matrix is ​​1, and the output dimension is a preset hidden layer feature dimension (set to 8 in this embodiment, a hyperparameter determined by balancing computational complexity and model inference accuracy through grid search or ablation experiments, taking into account the computational overhead constraints of edge computing nodes / local hardware and the information entropy conservation requirements of feature representation; 8 is chosen in this embodiment to maximize computational and memory compression while ensuring no loss of key business features). The input dimension of the edge-specific projection matrix is ​​2, and the output dimension is 8. The two sets of matrices are stored independently in SRAM. According to the edge type identifier of each edge in the local heterogeneous graph, the MCU sends the 1-dimensional feature vector of each carrier physical medium edge to the carrier-specific projection matrix to perform fixed-point matrix-vector multiplication, and sends the 2-dimensional feature vector of each wireless physical medium edge to the wireless-specific projection matrix to perform independent fixed-point matrix-vector multiplication. The feature projection of the two types of channels is completed in their respective dedicated operation channels. The 8-dimensional fixed-point hidden layer feature vectors after each edge projection are written back to the corresponding independent slots in the SRAM edge projection feature buffer.

[0066] After completing the categorized feature projection, the MCU performs neighbor aggregation calculations on all candidate route pairs in the local heterogeneous graph. For each candidate link contained in each candidate route pair, the MCU reads the 8-dimensional projection feature vector of the corresponding edge from the SRAM edge projection feature buffer and reads the target neighbor node state features. Element-level weighted summation aggregation is performed in the MCU's arithmetic logic unit to obtain an 8-dimensional node aggregation feature vector. This vector is then processed by a preset output projection weight matrix in the SRAM (specifically obtained through backpropagation iteration optimization during model training, with its row and column dimensions corresponding to the preset hidden layer feature dimensions and the target output space, respectively). Strict dimensional matching is achieved; this matrix is ​​used to linearly combine and spatially reduce the high-dimensional abstract hidden feature vectors, and finally project them onto a specific decision classification space or prediction numerical space. The linear projection is compressed into a 1-dimensional cost embedding scalar, which represents the comprehensive forwarding cost of the candidate link. The MCU performs the above calculations sequentially on all candidate route pairs, writes the cost embedding scalar set of each candidate route pair into the SRAM cost embedding output buffer in a fixed-point array format, and after writing, overwrites the current hash fingerprint value to the fixed storage address of the historical hash fingerprint in the SRAM, completing the rolling update of the state fingerprint in this optimization cycle.

[0067] By using an event-driven hash triggering mechanism and a categorized heterogeneous weight matrix projection design, while ensuring the independent isolation of different physical channel feature spaces, the activation condition of the graph neural network forward propagation is limited to a substantial change in the physical link state, effectively reducing the redundant computational overhead of resource-constrained MCUs under network steady state.

[0068] Further, the backlog data distribution ratio in the event priority distribution histogram is mapped to a gating weight vector, which is then input to the hybrid expert system as the gating signal. The analysis of the service flow characteristics of the event priority distribution histogram includes: when the histogram indicates the presence of distribution characteristics representing the leakage current tripping command, it is determined that there is a burst service flow in the current network, and the weight coefficient of the first expert network in the hybrid output is increased through the gating weight vector. The first expert network is configured to select the preferred path where link stability and transmission hop count meet the delay constraint; when the histogram indicates that the current network only has distribution characteristics representing temperature telemetry data, it is determined that when… Previously, only periodic service flows existed. The weight coefficient of the second expert network in the mixed output was increased by the gating weight vector. The second expert network was configured to select a load balancing path whose remaining duty cycle and node energy consumption met a preset threshold. The output results of the first expert network and the second expert network were dynamically weighted and fused using the gating weight vector to complete the dynamic tilting of the optimization weight. Based on the evaluation results after weighted fusion, the preferred primary route tuple with the highest probability distribution and the second-best backup route tuple with the second-highest probability distribution for dealing with electromagnetic pulse interference were simultaneously calculated under the single forward inference of the graph neural network.

[0069] Specifically, the hybrid expert system consists of three sub-modules: a first expert network, a second expert network, and a gating network. The parameters of all three sub-modules are generated offline by an external computing platform and then quantized and written into SRAM. The first expert network is a two-layer multilayer perceptron, with the number of input nodes consistent with the feature dimension concatenated from the candidate route cost embedding scalar, link attenuation, and hop count. It has 16 hidden layer nodes and 1 output node, using link route delay satisfaction as the supervision label, and is trained using the mean squared error loss function and the Adam optimizer. The second expert network is also a two-layer multilayer perceptron, with the number of input nodes consistent with... The candidate route cost embedding scalar, remaining duty cycle, and historical node energy consumption concatenated feature dimensions are consistent. The number of hidden layer nodes is 16, and the number of output nodes is 1. The network load balance satisfaction is used as the supervision label value. The mean squared error loss function and Adam optimizer are used for training. The gated network is a single linear layer with an input dimension of 2 (corresponding to the histogram gated weight vector dimension) and an output dimension of 2 (corresponding to the normalized weight coefficients of the two expert networks). The gated coefficients are output through a normalized exponential activation function with a temperature coefficient. After training, all parameters are quantized into fixed-point numbers and written to the SRAM expert system parameter storage partition.

[0070] The MCU reads the fixed-point array of the event priority distribution histogram generated in the previous steps from the SRAM histogram storage area. This array contains two elements: the first element is the proportion of the backlog of emergency and sudden control services to the total backlog, and the second element is the proportion of the backlog of periodic collection and reporting services to the total backlog. The MCU directly writes this 2D fixed-point array as a gating weight vector into the SRAM gating signal buffer. The gating network reads this vector from the buffer to generate the mixed weight coefficients of the two expert networks.

[0071] The MCU activates the gating network inference by reading a 2D gating weight vector from the SRAM gating signal buffer as the input to the gating network. The linear layer of the gating network performs fixed-point matrix-vector multiplication on the input vector, then normalizes it using a normalized exponential activation function with a temperature coefficient, outputting a 2D gating coefficient vector. The component corresponding to emergency / burst control services is analyzed. When the value of this component exceeds a preset threshold for determining the presence of a burst service, this threshold is specifically determined based on the mean and variance of the throughput of regular service flows in historical network traffic logs, combined with a traffic queuing model (such as a Poisson distribution), to select a probability distribution quantile (e.g., the traffic density or packet arrival rate corresponding to a 95% confidence level) that exceeds the normal traffic fluctuation range. This is used to set a primary filtering condition to trigger subsequent burst traffic deep detection logic. The MCU determines that there is a burst traffic flow in the current network. At this time, the weight coefficient of the first expert network in the gating coefficient vector is higher (0.85 for example) and the weight coefficient of the second expert network is lower (0.15 for example). The MCU reads the cost embedding scalar of each candidate route tuple and the instantaneous link attenuation and transmission hop count features of the corresponding candidate link from the SRAM cost embedding output buffer, splices them into the input feature vector of the first expert network, sends it to the first expert network to perform forward inference, outputs a 1-dimensional score value representing the delay satisfaction of the candidate route and writes it into the first expert slot of the SRAM expert output buffer.

[0072] When the proportion of emergency burst control services in the gating coefficient vector is not greater than the burst service existence judgment threshold and the proportion of periodic collection and reporting services is equal to 1, the MCU determines that there are only periodic service flows in the current network. At this time, the weight coefficient of the second expert network in the gating coefficient vector is higher (0.80 for example) and the weight coefficient of the first expert network is lower (0.20 for example). The MCU reads the remaining duty cycle quota and historical node energy consumption statistics of the candidate link nodes corresponding to each candidate route tuple from the SRAM, concatenates them into the input feature vector of the second expert network, sends it to the second expert network to perform forward inference, outputs a 1-dimensional score value representing the load balance satisfaction of the candidate route and writes it into the second expert slot of the SRAM expert output buffer.

[0073] The MCU reads the fixed-point values ​​of the cost scores for all candidate route pairs from the first expert network and the second expert network respectively from the SRAM expert output buffer. Based on the 2D weight coefficients in the gating coefficient vector, it performs element-wise weighted summation on the two sets of scores to obtain the comprehensive optimization score for each candidate route pair and writes it into the SRAM fusion score buffer, thus completing the dynamic tilting of the optimization weight. For example, if the first expert network score for a candidate route pair is 0.78 and the second expert network score is 0.62, and the current gating coefficients are 0.85 and 0.15 respectively, then the comprehensive optimization score is the sum of 0.85×0.78 and 0.15×0.62 and is written into the corresponding fusion score buffer slot.

[0074] The MCU reads the comprehensive optimization score fixed-point array of all candidate route pairs from the SRAM fusion scoring buffer. Within the same forward propagation cycle of the graph neural network, it performs a sequential scan of the array, extracts the candidate route pair with the highest comprehensive score and marks it as the primary route pair, and extracts the candidate route pair with the second highest comprehensive score and marks it as the secondary backup route pair. The secondary backup route pair prioritizes links with physical channel types different from those used by the primary route pair, so as to ensure that when the high-speed power line carrier primary link is affected by arc interference, the backup route can complete heterogeneous switching through long-distance low-power wireless channels. The node index and physical channel type identifier of both are written into the SRAM route output buffer in structure format for subsequent mask constraint processing.

[0075] By directly mapping the business load ratio histogram to the gating weights of the hybrid expert system and simultaneously completing the primary and backup routing tuple calculations within a single inference, the collaborative completion of business flow type awareness and routing decision output is achieved, avoiding the scheduling delay introduced by triggering additional inferences when a sudden surge in high-priority business arrives.

[0076] Further, the backlog data distribution ratio in the event priority distribution histogram is mapped to a gating weight vector, which is then input to the hybrid expert system as the gating signal. The analysis of the service flow characteristics of the event priority distribution histogram includes: when the histogram indicates the presence of distribution characteristics representing the leakage current tripping command, it is determined that there is a burst service flow in the current network, and the weight coefficient of the first expert network in the hybrid output is increased through the gating weight vector. The first expert network is configured to select the preferred path where link stability and transmission hop count meet the delay constraint; when the histogram indicates that the current network only has distribution characteristics representing temperature telemetry data, it is determined that when… Previously, only periodic service flows existed. The weight coefficient of the second expert network in the mixed output was increased by the gating weight vector. The second expert network was configured to select a load balancing path whose remaining duty cycle and node energy consumption met a preset threshold. The output results of the first expert network and the second expert network were dynamically weighted and fused using the gating weight vector to complete the dynamic tilting of the optimization weight. Based on the evaluation results after weighted fusion, the preferred primary route tuple with the highest probability distribution and the second-best backup route tuple with the second-highest probability distribution for dealing with electromagnetic pulse interference were simultaneously calculated under the single forward inference of the graph neural network.

[0077] Specifically, the hybrid expert system consists of three sub-modules: a gating network, a first expert network, and a second expert network. All parameters are quantized into fixed-point numbers and written to the dedicated SRAM storage partition on the circuit breaker after offline training on an external computing platform. The training dataset consists of historical network operation records. Each sample record includes a histogram of the current service queue distribution, channel measurement characteristics of each candidate route, and corresponding measured route utility label values. The first expert network uses the weighted value of measured end-to-end route transmission utility and transmission hop count as label values, while the second expert network uses the measured network load balancing index and the ratio of node remaining energy consumption as label values. Each of the two expert networks independently iterates and updates the weight parameters until convergence using the mean square error as the loss function and the Adam optimizer. The gating network uses the relative difference in prediction errors between the two expert networks in each historical sample as a supervision signal and is also trained using the Adam optimizer. After the three sub-modules converge, the parameters are uniformly quantized and written to the SRAM expert system parameter storage partition as the source of preset weights that are fixedly loaded during the inference phase.

[0078] The MCU reads the fixed-point array of the event priority distribution histogram generated in the previous steps from the on-chip SRAM histogram storage area of ​​the circuit breaker. This array contains two elements: element one is the proportion of the backlog of emergency emergency control services (leakage trip instructions) to the total backlog, and element two is the proportion of the backlog of periodic acquisition and reporting services (temperature telemetry data) to the total backlog. For example, if there are currently 3 backlog emergency emergency control services and 12 backlog periodic acquisition and reporting services, then the two elements are 0.20 and 0.80, respectively. The MCU directly writes this two-dimensional fixed-point ratio array as a gating weight vector into the SRAM gating signal buffer for the gating network to read from the buffer during the inference phase.

[0079] The MCU reads a 2D gating weight vector from the SRAM gating signal buffer and sends it to the linear fully connected layer of the gating network to perform fixed-point matrix-vector multiplication. After the multiplication result is activated by a normalized exponential function with temperature parameters, a 2D gating coefficient vector is output. The sum of the two components of this vector is 1 and both are non-negative. The two components represent the weight coefficients of the first expert network and the second expert network in this mixed output, respectively. The MCU writes the 2D gating coefficient vector into the SRAM gating coefficient buffer for subsequent weighted fusion steps.

[0080] When the gating coefficient component corresponding to the first expert network in the SRAM gating coefficient buffer exceeds the preset burst service activation threshold, this threshold is specifically set by dynamic feedback adjustment or empirical lookup method, taking into account the available bandwidth resources of the current communication link or network slice, as well as the QoS (Quality of Service) latency tolerance of the service itself. When the detected burst service characteristic value (such as the buffer queue length) exceeds this value, the system immediately activates it at the MAC layer and allocates a dedicated physical resource block to ensure low-latency transmission. The MCU determines that there is a burst service flow in the current network, reads the cost embedding scalar of each candidate route tuple from the SRAM cost embedding output buffer, and retrieves the cost embedding scalar from the SRAM cost embedding output buffer. The link state buffer reads the instantaneous attenuation and hop count of the corresponding candidate link, and concatenates them into the input feature vector of the first expert network according to the preset field order. The first expert network is a two-layer multilayer perceptron. The input layer receives the concatenated feature vector, the hidden layer has 16 nodes and the activation function is a linear rectified function, and the output layer has 1 node and outputs a 1-dimensional route delay satisfaction score scalar. The MCU performs the above forward inference for each candidate route tuple one by one. The first expert network prioritizes candidate routes with low instantaneous attenuation and low hop count to obtain higher scores. The route delay satisfaction scores of each candidate route tuple are written into the first expert slot of the SRAM expert output buffer in sequence.

[0081] When the gating coefficient component corresponding to the first expert network in the SRAM gating coefficient buffer is not greater than the burst service activation threshold, the MCU determines that there is only periodic service flow in the current network. It reads the remaining duty cycle quota and historical node energy consumption statistics of the candidate link nodes corresponding to each candidate route tuple from the SRAM, and concatenates them with the cost embedding scalar in the order of preset fields to form the input feature vector of the second expert network. The topology of the second expert network is the same as that of the first expert network. The input layer receives the above concatenated feature vector, the number of hidden layer nodes is 16, the activation function is a linear rectified function, the number of output layer nodes is 1, and it outputs a 1-dimensional load balance satisfaction score scalar. The second expert network prioritizes the candidate routes with sufficient remaining duty cycle quota and low historical node energy consumption to obtain higher scores. The load balance satisfaction scores of each candidate route tuple are written to the second expert slot of the SRAM expert output buffer in sequence.

[0082] The MCU reads a 2D gating coefficient vector from the SRAM gating coefficient buffer and reads the fixed-point scores of each candidate route tuple in the first and second expert slots from the SRAM expert output buffer. In the MCU's arithmetic logic unit, a weighted summation operation is performed on each candidate route tuple. The product of the first expert score and its corresponding gating coefficient and the product of the second expert score and its corresponding gating coefficient are added to obtain the fixed-point value of the comprehensive optimization score, which is then written into the SRAM fusion score buffer. For example, if a candidate route tuple has a first expert score of 0.78 and a first expert gating coefficient of 0.80, a second expert score of 0.55 and a second expert gating coefficient of 0.20, then the comprehensive optimization score is the sum of 0.78 × 0.80 and 0.55 × 0.20. After the comprehensive optimization scores of all candidate route tuples are written, the SRAM fusion score buffer constitutes the sorting basis for all candidate paths in the current optimization cycle, completing the dynamic tilting of the optimization weight.

[0083] Within the same forward inference cycle of the graph neural network, the MCU sequentially scans the fixed-point array of comprehensive optimization scores for all candidate route pairs in the SRAM fusion scoring buffer. It extracts the candidate route pair with the highest comprehensive score and writes its node index number and physical channel type identifier into the primary route slot of the SRAM route output buffer, marking it as the preferred primary route pair. From the remaining candidate route pairs, it extracts the one with the second highest comprehensive score and prioritizes selecting the candidate route whose physical channel type is different from that used by the preferred primary route pair as the secondary backup route pair. Its node index number and physical channel type identifier are written into the backup route slot of the SRAM route output buffer. This ensures that when the primary high-speed power line carrier link fails due to arc interference, the backup route can complete heterogeneous switching through a long-distance low-power wireless channel. Thus, the two route pairs are synchronously solved within a single forward inference cycle, and the primary and backup slot data in the SRAM route output buffer are read by the subsequent mask constraint processing flow.

[0084] By directly mapping the business load ratio histogram to the gating weights of the hybrid expert system and driving the differentiated scoring of the two expert networks, the business-aware primary and backup routing collaborative solution is completed in a single forward inference. This allows nodes to output differentiated routing strategies without triggering additional inference in scenarios where bursty high-priority services and periodic services coexist, thus avoiding response latency when multiple services are concurrent.

[0085] Further, the expected airtime of the current data packet to be forwarded on the corresponding communication channel is calculated based on the modulation parameters, coding rate, and payload length. The expected airtime is then compared with the remaining duty cycle quota of the current circuit breaker node to generate a binarized blocking mask matrix. When the expected airtime is greater than the remaining duty cycle quota, the corresponding candidate link is marked as an illegal link that has exhausted its duty cycle quota in the binarized blocking mask matrix. Using the binarized blocking mask matrix, a mask soft maximization operation is performed on the original routing logic value output by the network by superimposing a negative infinity penalty on the routing tuple corresponding to the illegal link, forcing the probability distribution of the illegal link after normalization to converge to zero. Illegal links whose probability distribution converges to zero are eliminated, and the final primary routing tuple and backup routing tuple that meet the physical duty cycle constraints are output from the remaining legal links.

[0086] Specifically, before executing routing compliance constraints, the MCU reads the payload byte length of the current data packet from the protocol data unit header field of the data packet to be forwarded, and combines it with the physical channel type identifier pointed to by the candidate route tuples written in the previous steps in the SRAM routing output buffer. Based on the current rate configuration register parameters of the physical channel corresponding to each candidate link, the MCU calculates the expected air time of the current data packet on each candidate link. The expected air time of the high-speed power line carrier candidate link is calculated in the MCU arithmetic logic unit based on the current channel coding rate register value and the data packet payload byte length. The expected airtime of long-range low-power wireless candidate links is calculated in the MCU arithmetic logic unit based on the spreading factor and channel bandwidth parameters in the RF channel configuration register. Specifically, the calculation is combined with the duty cycle supervision period specified by the communication standard (e.g., 1 hour). The transmission duration of long-range low-power wireless is calculated based on the preamble length, payload length, and coding rate. The transmission duration of high-speed power line carrier is calculated based on the payload length and modulation order. The expected airtime calculation results of each candidate link are written sequentially to the corresponding slot of the SRAM airtime temporary storage register in integer time unit format for subsequent quota comparison steps.

[0087] The MCU reads the integer values ​​of the remaining duty cycle quotas independently maintained by the high-speed power line carrier channel and the long-distance low-power wireless channel within the current regulatory period from the duty cycle quota register area of ​​the SRAM on the circuit breaker chip. For each candidate link, the MCU reads the integer value of the expected air time of the link from the SRAM air time temporary storage register and performs an integer comparison with the remaining duty cycle quota value corresponding to the physical channel of the link in the MCU arithmetic logic unit. When the expected air time is greater than the remaining duty cycle quota, the MCU writes the blocking flag value 0 to the corresponding candidate link slot in the SRAM binary blocking mask matrix, marking the candidate link as an illegal link that has exhausted its duty cycle quota. When the expected air time is not greater than the remaining duty cycle quota, the MCU writes the pass flag value 1 to the corresponding slot, marking it as a legal link. For example, if there are currently 4 candidate links and the expected air time of the 2nd candidate link exceeds the remaining duty cycle quota of the corresponding channel, then the mask values ​​corresponding to the 4 candidate links are 1, 0, 1, and 1 respectively, and are completely written into the SRAM mask matrix storage area to represent the current compliance status of each candidate link.

[0088] The MCU reads the fixed-point number array of the comprehensive optimization score of each candidate route tuple output by the preceding hybrid expert system from the SRAM fusion scoring buffer as the original route logic value sequence. Simultaneously, it reads the binary blocking mask matrix integer array from the SRAM mask matrix storage area. In the MCU arithmetic logic unit, the corresponding elements of the two arrays are subjected to mask penalty superposition processing one by one. When the mask bit corresponding to a candidate route tuple is 0, the original route logic value at that position is overwritten as a maximum negative integer in the fixed-point number field (equivalent to a negative infinite penalty within the current fixed-point number representation precision range). When the corresponding mask bit is 1, the original route logic value at that position remains unchanged. After all positions are processed, the logic value array after penalty is completely written into the SRAM mask penalty logic value buffer.

[0089] The MCU reads the fixed-point array of all candidate route binary logic values ​​after penalty superposition processing from the SRAM mask penalty logic value buffer. In the MCU's arithmetic logic unit, a normalized exponential soft maximization operation is performed on this array. The output probability value of the illegal link position, which is overwritten as a very large negative integer, converges to zero within the precision range of the fixed-point number representation after the normalized exponential operation. The probability value of the legal link position is re-normalized and reassigned within the legal candidate set. The sum of the normalized probability values ​​of all candidate positions is 1. After the soft maximization operation is completed, the MCU writes the normalized probability distribution integer array into the SRAM probability distribution output buffer. The probability value of the position corresponding to the illegal link is zero and is no longer included in the subsequent route sorting candidate set.

[0090] The MCU reads the normalized probability distribution array from the SRAM probability distribution output buffer, sequentially scans the probability values ​​corresponding to all candidate route pairs, automatically skips illegal link entries with a probability value of zero, extracts the candidate route pair with the highest probability value from the set of legal candidates with non-zero probability values, and overwrites the primary route slot in the SRAM route output buffer with its node index number and physical channel type identifier in a structure format, as the final primary route pair that satisfies the physical duty cycle constraint. Further, it extracts the candidate route pair with the second highest probability value from the remaining legal candidate set, and prioritizes those whose physical channel type is different from the channel used by the final primary route pair, writing them into the backup route slot in the SRAM route output buffer, as the final backup route pair that satisfies the physical duty cycle constraint. At this point, both final route pairs have completed the duty cycle compliance verification, and the final primary and backup route pair data in the SRAM route output buffer are read by the subsequent protocol assembly process.

[0091] By superimposing a negative infinity penalty onto a binary mask at the model output and jointly performing normalized soft maximization, the physical duty cycle compliance constraint is directly embedded in the probability normalization layer, forcing illegal links to zero in the output probability distribution, thus ensuring that the final routing strategy automatically satisfies the underlying channel regulatory constraints.

[0092] Further, the final primary routing tuple and backup routing tuple are obtained, and protocol assembly of the underlying protocol data unit is performed. The primary routing tuple is mapped to the preferred forwarding destination address of the current data packet. The backup routing tuple is used as a backup routing policy and hard-coded into the extended header field of the Media Access Control (MAC) layer. The data packet is then sent along the primary high-speed power line carrier (HPLC) link. The hardware timeout timer of the underlying MAC controller is started to listen for the local acknowledgment (ACK) frame of the primary HPLC link for the data packet. If arcing occurs and the local acknowledgment (ACK) frame is not received within 30ms, the hardware timeout interrupt routine of the underlying MAC controller is triggered. The underlying interrupt service routine is entered, and the backup routing policy is extracted directly from the extended header field of the MAC layer without waking up the upper network layer routing protocol stack. Based on the extracted backup routing policy, the backup RF chip is directly activated in the underlying interrupt service routine, and the data packet is switched to a long-distance low-power wireless physical channel for transmission, resulting in high-speed retransmission of the heterogeneous backup link. This embodiment superimposes the base delay (5ms) with the arc coherent interference time (25ms), setting the preset time threshold at 30ms. This setting provides a time tolerance range that perfectly covers typical physical arc pulses, enabling the system to silently overcome interference peaks and quickly restore the link state at the first moment of arc energy decay, achieving the optimal technical balance between anti-interference robustness and service real-time performance.

[0093] Specifically, the MCU reads the final primary route tuple and the final backup route tuple structures from the circuit breaker's on-chip SRAM routing output buffer, which have already completed the duty cycle compliance verification in the preceding steps. The final primary route tuple contains the preferred forwarding target node index and the high-speed power line carrier physical channel type identifier, while the final backup route tuple contains the backup forwarding target node index and the long-range low-power wireless physical channel type identifier. The MCU calls the underlying protocol data unit assembly driver to convert the preferred forwarding target node index in the final primary route tuple into a MAC layer target address field value through an address mapping table, and writes it into the MAC layer frame header target address field of the protocol data unit of the current data packet to be forwarded, thus completing the protocol assembly of the primary forwarding target address.

[0094] After completing the primary target address writing, the MCU continues to call the MAC layer extended header field writing interface to concatenate the backup forwarding target node MAC address and the long-range low-power wireless physical channel type identifier of the final backup route tuple into a backup route policy byte sequence according to the preset extended field format. For example, this byte sequence consists of 6 bytes of backup target MAC address and 1 byte of channel type identifier, totaling 7 bytes. It is written into the reserved field area of ​​the MAC layer frame header extended header in a hard-coded manner. This extended header field and the data packet payload are encapsulated together in the same protocol data unit frame body to ensure that the backup route policy is transmitted with the frame throughout the entire data packet lifecycle without relying on additional maintenance by the upper layer protocol stack.

[0095] The MCU sends the assembled protocol data unit frame to the primary forwarding target node via the primary HPLC link through the high-speed power line carrier physical layer transceiver driver interface. At the same time as the data packet sending command is issued to the hardware sending queue of the MAC controller, the MCU simultaneously writes the preset waiting time configuration value to the hardware timeout timer of the underlying MAC controller and starts the timer. This timer runs on the MCU hardware timer peripheral and is independent of the upper-layer software protocol stack scheduling. During the timer period, the MAC controller continuously listens for local acknowledgment (ACK) frames from the primary forwarding target node. If a valid local acknowledgment (ACK) frame is received within the preset waiting time, the MAC controller reports the sending success status to the MCU and clears the timer, and the forwarding process ends normally.

[0096] When an arc discharge interference event occurs in the industrial field, the high-speed power line carrier physical channel is polluted by broadband noise. The primary forwarding target node cannot correctly demodulate and reply with a local acknowledgment (ACK) frame. The MCU's underlying MAC controller hardware timeout timer does not detect a valid ACK frame after the preset waiting time expires. The timer automatically triggers a hardware timeout interrupt signal. After responding to the interrupt signal, the MCU immediately suspends the current main task context and saves the state of the context registers. It then jumps to the entry address of the underlying interrupt service routine pre-registered in the interrupt vector table. The entire interrupt response and entry jump process is completed at the MCU hardware layer without generating any operating system task scheduling or upper-layer network layer routing protocol stack wake-up calls.

[0097] During the execution of the underlying interrupt service routine, the MCU directly accesses the original protocol data unit frame currently stuck in the MAC layer transmit buffer through the MAC controller register interface. It locates and reads the backup routing policy byte sequence from the reserved field area of ​​the frame header extension according to the aforementioned preset format, and parses out the 6-byte backup target MAC address and the 1-byte long-range low-power wireless physical channel type identifier. The backup target MAC address is written into the MAC layer target address field of the backup retransmission frame. The entire extraction and parsing process only involves MCU on-chip register read and write and SRAM direct memory access operations, without calling any upper-layer network layer routing protocol stack routing functions or handshake interfaces, thus avoiding the waiting delay introduced by protocol stack backtracking in the conventional cross-layer retransmission process.

[0098] In the underlying interrupt service routine, the MCU, based on the parsed long-range low-power wireless physical channel type identifier, directly writes an activation command to the backup RF chip via the RF chip select signal line and the serial peripheral interface driver. This switches the backup RF chip from low-power standby to transmit-ready state. Subsequently, the MCU transmits the original protocol data unit frame data in the SRAM transmit buffer to the transmit data register of the backup RF chip via the serial peripheral interface, triggering the backup RF chip to complete the over-the-air transmission of data packets along the long-range low-power wireless physical channel. After transmission is complete, the MCU restores the main task context register state and exits the interrupt service routine. The entire heterogeneous channel switching and retransmission activation process is completed within the underlying hardware interrupt service routine, while the upper network layer routing protocol stack remains suspended throughout, achieving ultra-fast retransmission of the heterogeneous backup link.

[0099] By pre-embedding the backup routing strategy in the MAC layer extended header and directly activating the backup RF chip with the underlying hardware timeout interrupt, the heterogeneous channel switching can be completed without backtracking through the upper layer protocol stack when the primary HPLC link fails due to arc interference. This effectively reduces the retransmission response delay in sudden interference scenarios and improves the data transmission reliability of the dual-mode network in harsh electromagnetic environments.

[0100] In summary, this embodiment fully realizes lightweight intelligent routing decision-making and high-reliability transmission of bursty services in a dual-mode heterogeneous network on a resource-constrained circuit breaker MCU through state hash event-driven triggering, independent projection of heterogeneous edge classification features, service load-aware hybrid expert routing collaborative calculation, physical duty cycle mask constraints, and the full-process collaborative cooperation of high-speed heterogeneous retransmission of underlying hardware interruptions.

[0101] Example 2:

[0102] When a circuit breaker node faces the dual anomalies of concurrent backlog of three types of services and local topology changes within the same routing optimization cycle: the memory buffer queue is simultaneously backed up with leakage trip instructions (emergency control type, highest priority), current over-limit warning instructions (secondary emergency warning type, middle priority), and periodic temperature telemetry data (periodic collection and reporting type, lowest priority), and at the same time, a neighboring circuit breaker node within one hop range is triggered to go offline due to over-temperature protection, resulting in a node-missing structural change in the local graph topology centered on the current node.

[0103] For the three types of concurrent backlog scenarios, the MCU calls the system's underlying queue manager interface to read the current backlog quantity from three independent service sub-queues. The first sub-queue stores leakage trip instructions, the second sub-queue stores current over-limit warning instructions, and the third sub-queue stores periodic temperature telemetry data. The current backlog quantity of the three sub-queues is written sequentially as an integer count to three independent slots of the backlog quantity temporary storage register. For example, the backlog quantities of the three types of services are 2, 5, and 18, respectively, with a total backlog quantity of 25, corresponding to ratios of 0.08, 0.2, and 0.72, respectively. The MCU constructs a fixed-point array of a 3-interval event priority distribution histogram in SRAM, with the three intervals corresponding to the three types of services mentioned above, and the amplitudes written sequentially as 0.08, 0.2, and 0.72. This 3D histogram array is written to the SRAM histogram storage area for use in gating signal generation and additional writing of the feature domain of the central node of the local heterogeneous graph.

[0104] In scenarios involving local topology changes, when the MCU constructs a local heterogeneous graph, it detects an offline node in the set of one-hop neighbor nodes. All original carrier physical medium edges and wireless physical medium edges of this offline node are marked as invalid in the adjacency list and removed from the set of valid edges. The corresponding candidate route tuples are simultaneously set to unavailable in the SRAM candidate route set. The number of valid nodes and valid edges in the updated local heterogeneous graph is structurally reduced. The MCU re-serializes the state features of all nodes and valid heterogeneous edges in the updated local heterogeneous graph and sends them to the MCU's built-in hash generator to generate a new current hash fingerprint. Because the offline neighbor node causes the removal of the corresponding carrier physical medium edges and wireless physical medium edges in the graph structure, the serialized byte sequence is substantially different from the historical version. The result of performing a bitwise XOR operation between the current hash fingerprint output by the hash operation and the historical hash fingerprint stored in SRAM will not be all zeros, thus ensuring that the offline topology node event reliably triggers the graph neural network to perform forward inference for the current event.

[0105] In the three concurrent business scenarios, the hybrid expert system is expanded to a structure containing three expert networks during the offline training phase on the external computing platform: The first expert network maintains the latency-sensitive path optimization configuration, using the weighted value of end-to-end routing transmission utility and transmission hop count as the training label, prioritizing the latency constraint of leakage trip commands; A third expert network is added, using the candidate route cost embedded scalar concatenated with the corresponding channel instantaneous attenuation and historical frame error rate statistics as input features, and using the historical measured link frame error rate cost as the training label, and is configured to prioritize the path with the most stable channel quality when there is a large backlog of current over-limit warning commands. The third expert network is also a two-layer multilayer perceptron, with 16 hidden layer nodes and 1 output node. It is trained with the mean square error loss function and Adam optimizer until convergence, and then quantized and written into the SRAM expert system parameter storage partition; The input dimension and output dimension of the linear layer of the gating network are correspondingly expanded to 3, and the output is a 3-dimensional normalized gating coefficient vector. It is trained with the Adam optimizer using the relative difference of the prediction errors of the three expert networks as the supervision signal, and then synchronously written into SRAM after convergence.

[0106] The MCU sends the fixed-point array of the 3D event priority distribution histogram in the SRAM histogram storage area as a 3D gating weight vector to the gate network. After the linear layer of the gate network performs 3D fixed-point matrix-vector multiplication, it is activated by a normalized exponent with temperature parameters to output a 3D gating coefficient vector. For example, in a scenario where the proportions of the three types of services are 0.08, 0.20, and 0.72, the components of the 3D gating coefficient vector are 0.45, 0.35, and 0.2, respectively. The first expert network has the highest weight to ensure the latency requirement of emergency tripping commands, the third expert network has a middle weight to take into account the transmission reliability of current warning services, and the second expert network has the lowest weight to maintain the load balancing scheduling of periodic telemetry services. The MCU activates the three expert networks according to the 3D gating coefficient vector to perform forward inference on all valid candidate route pairs. The three scores are weighted and summed according to their respective gating coefficients and then written into the SRAM fusion score buffer to complete the dynamic tilting of the optimization weights for the three-way service perception.

[0107] Furthermore, in scenarios with a backlog of concurrent services across three types and a large total number of data packets to be forwarded, the competition for duty cycle quotas is more complex than in single-service scenarios. Before comparing the expected airtime with the remaining duty cycle quota, the MCU reads the remaining total quota for the current regulatory period from the SRAM duty cycle quota register and divides the total quota into three independent quota reservation areas according to a preset hierarchical ratio: an emergency quota reservation area (e.g., accounting for 30% of the total quota, dedicated to the candidate route corresponding to the leakage current trip instruction), and an early warning quota reservation area (e.g., accounting for 30% of the total quota, used for the candidate route corresponding to the current over-limit early warning instruction). The MCU uses a general quota area (40% remaining, for candidate routes corresponding to periodic temperature telemetry data to compete for). For each candidate link, the MCU reads the remaining quota value of the corresponding area from the SRAM hierarchical quota register according to its corresponding service type identifier. After performing an integer comparison with the expected air time of the candidate link in the MCU arithmetic logic unit, the blocking mask identifier is written into the corresponding slot of the SRAM mask matrix. The subsequent mask soft maximization and final route tuple output process are consistent with the first embodiment, ensuring that the quota reservation area of ​​high-priority services is not encroached upon by the over-competition of low-priority services.

[0108] In this embodiment, under the dual complex scenarios of concurrent backlog of three types of services and offline neighbor nodes, the overall coordination of fine quantification of multi-level service load distribution using three-interval histograms, forward inference triggered by reliable activation events driven by topology change, multi-objective differentiated collaborative solution of a three-expert hybrid system, and hierarchical duty cycle quota reservation mechanism improves the routing decision accuracy and channel resource scheduling rationality of edge circuit breaker nodes in multi-source concurrent and volatile environments without increasing additional hardware resources.

[0109] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for optimizing data forwarding in communication nodes based on graph neural networks, characterized in that, include: Collect the physical link status of local and one-hop neighbor nodes, obtain the backlog of leakage trip commands and periodic telemetry data in the circuit breaker memory buffer queue, generate an event priority distribution histogram, and construct a local heterogeneous graph in combination with the physical link status. Using the hash generator built into the circuit breaker MCU, the hash fingerprint of the current local heterogeneous graph state is compared with the hash fingerprint of the historical state in SRAM; it is determined whether the hash fingerprint has changed. When it has changed, the graph neural network is triggered to perform event-triggered forward inference to obtain the cost embedding for the candidate route tuple. The proportion array of the backlog of each service type in the event priority distribution histogram is used as a gating signal and directly input to the gating network of the hybrid expert system. The gating network generates the hybrid weight coefficients of each expert network accordingly, performs dynamic tilting of the optimization weights, and obtains the preferred primary route tuple that is synchronously output under a single forward inference, as well as the second-best backup route tuple for dealing with electromagnetic pulse interference. The extracted original routing logical feature values ​​are compared with the benchmark judgment threshold representing the current physical channel connectivity status. Illegal links that have exhausted their duty cycle quotas are penalized with negative infinity to obtain the final primary and backup route tuples that meet the physical constraints.

2. The communication node data forwarding optimization method based on graph neural networks according to claim 1, characterized in that, The generated event priority distribution histogram includes: The system invokes the circuit breaker's built-in high-speed power line carrier and long-range low-power wireless dual-mode communication module and the system's underlying queue manager to collect the physical link status of local and neighboring nodes within one-hop physical coverage area; extracts the instantaneous attenuation of the high-speed power line carrier channel and the received signal strength and spreading factor of the long-range low-power wireless channel from the physical link status; synchronously reads the backlog of leakage trip commands and periodic telemetry data in the circuit breaker's memory buffer queue; and generates an event priority distribution histogram based on the backlog corresponding to different service types.

3. The communication node data forwarding optimization method based on graph neural networks according to claim 2, characterized in that, The construction of the local heterogeneity graph based on the physical link status specifically includes: The high-speed power line carrier links between nodes are used as carrier physical medium edges, and the extracted instantaneous attenuation is encapsulated as a unique feature vector of the carrier physical medium edge; the long-distance low-power wireless links between nodes are used as wireless physical medium edges, and the received signal strength and the spreading factor are encapsulated as unique feature vectors of the wireless physical medium edge; in the graph topology, the carrier physical medium edges and the wireless physical medium edges are distinguished as dual heterogeneous edges with independent feature vectors; combined with the event priority distribution histogram, a local heterogeneous graph with the current circuit breaker as the central node is obtained.

4. The communication node data forwarding optimization method based on graph neural networks according to claim 1, characterized in that, The process of obtaining the cost embedding for candidate route pairs specifically includes: Extract the node state features and heterogeneous edge features of the local heterogeneous graph, perform hash calculation through the hash generator built into the circuit breaker MCU, and generate the current hash fingerprint that represents the current network topology and physical link status; read the historical hash fingerprint of the previous routing optimization cycle from the SRAM, and perform a bit-by-bit consistency comparison between the current hash fingerprint and the historical hash fingerprint in the MCU arithmetic logic unit; When the current hash fingerprint is inconsistent with the historical hash fingerprint, it is determined that a physical link state change has occurred, and the graph neural network is awakened to perform the event-triggered forward inference; when the current hash fingerprint is consistent with the historical hash fingerprint, the MCU keeps the graph neural network in sleep mode and directly reuses the primary and backup route pairs output by the previous forward inference in the SRAM route output buffer; during the forward propagation process, a preset heterogeneous weight matrix is ​​invoked to perform independent feature projection for the exclusive feature vector of the high-speed power line carrier physical medium and the exclusive feature vector of the long-distance low-power wireless physical medium, respectively, to isolate the dimensions and feature spaces of different physical channels; Based on the projected heterogeneous features, the state information of one-hop neighbor nodes is aggregated, the cost embedding for candidate route tuples is calculated, and the historical hash fingerprint in the SRAM is overwritten with the current hash fingerprint.

5. The communication node data forwarding optimization method based on graph neural networks according to claim 1, characterized in that, Obtaining the primary route tuple and the backup route tuple specifically includes: The distribution ratio of backlogged data in the event priority distribution histogram is mapped to a gating weight vector, which is then input into the hybrid expert system as the gating signal. The analysis of the service flow characteristics of the event priority distribution histogram includes: when the histogram indicates the existence of distribution characteristics representing the leakage current tripping command, it is determined that there is a burst service flow in the current network. The weight coefficient of the first expert network in the mixed output is increased by the gating weight vector. The first expert network is configured to select the preferred path where the link stability and transmission hop count meet the delay constraint conditions; when the histogram indicates that there is only a distribution characteristic representing temperature telemetry data in the current network, it is determined that there is only a periodic service flow. The weight coefficient of the second expert network in the mixed output is increased by the gating weight vector. The second expert network is configured to select the load balancing path where the remaining duty cycle and node energy consumption meet the preset threshold. The outputs of the first expert network and the second expert network are dynamically weighted and fused using the gated weight vector to achieve dynamic tilting of the optimization weights. Based on the evaluation results after weighted fusion, the preferred primary route pair with the highest probability distribution and the second-best backup route pair with the second-highest probability distribution for dealing with electromagnetic pulse interference are simultaneously calculated under the single forward inference of the graph neural network.

6. The communication node data forwarding optimization method based on graph neural networks according to claim 1, characterized in that, The step of comparing the extracted original routing logical feature values ​​with the benchmark judgment threshold characterizing the current physical channel connectivity status includes: The expected airtime of the current data packet to be forwarded on the corresponding communication channel is calculated based on the modulation parameters, coding rate, and payload length. The expected airtime is then compared with the remaining duty cycle quota of the current circuit breaker node to generate a binarized blocking mask matrix. When the expected airtime is greater than the remaining duty cycle quota, the corresponding candidate link is marked as an illegal link that has exhausted its duty cycle quota in the binarized blocking mask matrix. Using the binarized blocking mask matrix, by superimposing a negative infinity penalty on the routing tuples corresponding to the illegal links, a mask soft maximization operation is performed on the original routing logic values ​​output by the network, forcing the probability distribution of the illegal links after normalization to converge to zero; illegal links whose probability distributions converge to zero are eliminated, and the final primary routing tuple and backup routing tuple that meet the physical duty cycle constraints are output from the remaining legal links.

7. The communication node data forwarding optimization method based on graph neural networks according to claim 1, characterized in that, The method further includes: Obtain the final primary route tuple and backup route tuple, perform protocol assembly of the underlying protocol data unit, map the primary route tuple to the preferred forwarding destination address of the current data packet; hardcode the backup route tuple as a backup routing policy into the extended header field of the Media Access Control (MAC) layer, and send the data packet along the primary high-speed power line carrier (HPLC) link; start the hardware timeout timer of the underlying MAC controller, and listen for the primary HPLC link local acknowledgment (ACK) frame for the data packet; When an arcing interference occurs and the local acknowledgment (ACK) frame is not received within a preset time threshold, the hardware timeout interrupt routine of the underlying MAC controller is triggered; the underlying interrupt service routine is entered, and the backup routing strategy is directly extracted from the extended header field of the MAC layer without waking up the upper network layer routing protocol stack. Based on the extracted backup routing strategy, the backup RF chip is directly activated in the underlying interrupt service routine, and the data packet is switched to a long-distance low-power wireless physical channel for transmission, resulting in extremely fast retransmission of the heterogeneous backup link.

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