Weighted network traffic distribution

Abstract

The present disclosure relates to weighted network traffic distribution. Example embodiments provide a network device that includes one or more circuits to receive a network packet. The one or more circuits are to: assign the network packet to one of a plurality of port groups in accordance with a network traffic distribution policy that proportionally apportions the network packet among the plurality of port groups based on a network parameter; and forward the network packet through a port of the one port group. In some aspects, the network traffic distribution policy includes a multi-path data structure that maps different entries to different ones of the plurality of port groups. In some aspects, the one or more circuits are further to: receive network condition information indicative of a change in network capacity. In some aspects, the network condition information is indicative of a decrease in capacity of a network path downstream of the network device.

Description

Technical Field

[0001] This disclosure generally relates to networks, and more specifically, to networked devices and their operating methods. Background Technology

[0002] Network topologies in modern computing environments (especially data center and cloud infrastructure) are becoming increasingly complex to support high-bandwidth, low-latency applications. These networks may employ multi-layered architectures (such as leaf-spine or Clos designs), where multiple paths exist between any two endpoints. In such architectures, efficiently routing traffic across available paths is a challenge for maintaining optimal network performance. Traditional routing methods, such as Equal-Cost Multipath (ECMP), have been adopted to distribute network traffic across multiple paths with the same cost metric, thereby maximizing bandwidth utilization and providing redundancy in the event of failures.

[0003] However, as networks scale and evolve, asymmetry often arises, meaning not all paths offer the same capacity or performance. This asymmetry can be caused by a variety of factors, including partial link failures, heterogeneous hardware deployments, or deliberate design decisions based on service patterns. Some ECMP implementations handle path degradation through binary pruning decisions: either fully utilize the path or completely avoid it. Binary pruning can lead to poor network utilization, especially when a link is partially degraded rather than failed. For example, if a link's capacity decreases from 400 Gbps to 300 Gbps, existing ECMP implementations will either continue sending network traffic to the degraded link at full link capacity (causing congestion) or, alternatively, remove the degraded link from consideration (wasting the remaining 300 Gbps of capacity). Summary of the Invention

[0004] This disclosure relates to systems and methods for weighted adaptive multipath routing in network environments. As networks become more dynamic and complex, there is a growing need for routing methods that can proportionally distribute traffic across multiple paths based on their actual available capacity, thereby maximizing overall network performance without costly hardware upgrades or major infrastructure changes. In one aspect, network devices such as switches include multiple ports organized into port groups and routing circuitry / logic configured to proportionally distribute network packets among the port groups based on network parameters, which may refer to network capacity. Unlike conventional ECMP implementations, where routing decisions are binary (i.e., either fully utilize or completely avoid a particular path), aspects of this method aim to provide non-binary, proportional traffic distribution consistent with actual network conditions. The disclosed methods achieve traffic management through a combination of longest prefix matching (LPM) operations, weighted multipath data structures, and directed congestion control, enabling network devices to dynamically adjust traffic proportions when network links experience partial capacity degradation (rather than complete failure).

[0005] By implementing weighted traffic distribution across multiple paths, network devices can optimize bandwidth utilization in asymmetric topologies or scenarios involving partially degraded links. When receiving information about network conditions (such as a link degrading from 400 Gbps to 300 Gbps) via protocols such as Border Gateway Protocol (BGP), network devices can adjust their multipath data structures to ensure that traffic is distributed proportionally to the actual available capacity. Aspects of this approach minimize congestion, maximize throughput, and maintain network connectivity by avoiding over-pruning that occurs in traditional binary routing decisions. The disclosed aspects can be implemented without hardware upgrades to existing network infrastructure, fully utilizing existing LPM, ECMP, and congestion control capabilities available in current networking devices. By adjusting traffic distribution to match real-time network parameters, the aspects of this disclosure improve network efficiency, provide more predictable performance during partial failures, and enhance network resource utilization in complex data center architectures and high-performance computing environments.

[0006] Various exemplary aspects of this disclosure provide a network device. In some aspects, the network device may include one or more circuits for: receiving network packets; allocating network packets to one of a plurality of port groups according to a network traffic distribution policy (which distributes network packets proportionally among a plurality of port groups based on network parameters); and forwarding network packets through ports of a port group.

[0007] This includes various aspects, such as network service distribution strategies, which involve multi-path data structures that map different entries to different port groups within multiple port groups.

[0008] The multipath data structure includes an ECMP table with multiple entries, where different percentages of these entries are mapped to different port groups in multiple port groups.

[0009] The aspects include one or more of these circuits also being used to: perform LPM operations based on the destination address of network packets to select a multipath data structure from multiple multipath data structures.

[0010] The aspects include that one or more circuits are also used to: calculate a hash value based on information in the network packet; and select an entry from multiple entries in a multipath data structure based on the hash value, wherein the selected entry determines a port group among multiple port groups for the network packet.

[0011] Each entry in the multipath data structure is associated with at least one rule or action that identifies a corresponding port group among multiple port groups.

[0012] This includes aspects such as which ports of the network device are included in the corresponding port group, as indicated by the rule or action.

[0013] All aspects, including the rule or action, are updated based on network asymmetric information received via BGP.

[0014] The aspects include multiple port groups, including at least one port group configured to receive overbooked service load based on network parameters.

[0015] The aspects include: the network parameters include available capacity information for multiple port groups; and based on the available capacity information, the proportion is determined to direct more traffic to another port group than to the at least one port group.

[0016] The aspects include that one or more circuits are also used to: perform congestion control to limit the traffic flow directed through at least one of the multiple port groups.

[0017] The congestion control measures also include: over-booking at least one port in at least one of the multiple port groups to cause controlled congestion; and reducing total traffic throughput by a specific amount corresponding to the capacity reduction in the network.

[0018] The aspects include one or more of the circuits being used to: receive network status information indicating changes in network capacity; and adjust the proportion of network packets distributed among multiple port groups based on the network status information.

[0019] This includes various aspects, such as network status information indicating reduced capacity in the network paths downstream of the network device.

[0020] All aspects include the fact that the network status information is received via a BGP update message indicating at least one of a link failure or link degradation.

[0021] The aspects include port forwarding of network packets through a port group, including: selecting the port from multiple available ports in the port group using at least one of adaptive routing, random selection, round-robin selection, or hash-based forwarding.

[0022] The aspects include network parameters including at least one of the following: available bandwidth of network links; network congestion level; link failure information; quality of service requirements; or management weight assigned to network paths.

[0023] Various exemplary aspects of this disclosure provide a system. In some aspects, the system includes: a first network device; and a second network device connected to the first network device via a plurality of network links; wherein the first network device includes one or more circuits configured to: receive network traffic destined for the second network device; distribute the network traffic among the plurality of network links according to a traffic distribution strategy, the traffic distribution strategy allocating different proportions of network traffic to different subsets of the plurality of network links based on capacity information associated with the plurality of network links; and adjust the different proportions in response to changes in the capacity information.

[0024] Various exemplary aspects of this disclosure provide a network device. In some aspects, the network device includes one or more circuits configured to: receive a network packet stream; distribute the network packets of the network packet stream proportionally among a plurality of port groups based on network parameters; and forward the network packets through ports in the plurality of port groups.

[0025] The various aspects, including one or more of these circuits, are also used to: adjust the proportion of network packets distributed among multiple port groups in response to changes in network parameters.

[0026] This article describes additional features and advantages, which will become apparent from the following detailed description and accompanying figures. Attached Figure Description

[0027] This disclosure is described in conjunction with accompanying drawings, which are not necessarily drawn to scale: Figure 1 This is a block diagram depicting an illustrative configuration of a computing environment including processing devices interconnected by a structure, according to at least some embodiments of the present disclosure; Figure 2A It is a block diagram depicting an illustrative network topology implementing weighted adaptive routing according to at least some embodiments of the present disclosure; Figure 2BThis is a block diagram depicting an illustrative network topology with degraded links according to at least some embodiments of the present disclosure; Figure 3A This is a block diagram depicting an illustrative configuration of an interconnected device implementing weighted adaptive multipath routing, according to at least some embodiments of the present disclosure. Figure 3B This is a block diagram depicting illustrative components of a processing circuitry system for implementing weighted adaptive multipath routing, according to at least some embodiments of the present disclosure. Figure 3C This is a block diagram depicting an illustrative memory component for storing data structures for implementing weighted adaptive multipath routing, according to at least some embodiments of the present disclosure; Figure 4A This is a block diagram depicting an illustrative configuration of a weighted adaptive multipath routing system according to at least some embodiments of the present disclosure; Figure 4B This is a block diagram illustrating an illustrative implementation of a weighted adaptive multipath routing system with balanced traffic distribution, according to at least some embodiments of the present disclosure. Figure 4C This is a block diagram illustrating an illustrative implementation of a weighted adaptive multipath routing system with service distribution for path degradation adjustment, according to at least some embodiments of the present disclosure. Figure 4D This is a block diagram illustrating an illustrative implementation of a weighted adaptive multipath routing system with an asymmetric port group configuration, according to at least some embodiments of the present disclosure. Figure 4E This is a block diagram illustrating an illustrative implementation of a weighted adaptive multipath routing system with an asymmetric port group configuration for path degradation adjustment, according to at least some embodiments of the present disclosure. Figure 5A The flowchart illustrates a method for weighted adaptive multipath routing according to at least some embodiments of the present disclosure. Figure 5B The flowchart illustrates a method for determining a weighted service distribution strategy based on network parameters, according to at least some embodiments of the present disclosure. Figure 5C The flowchart illustrates a method for allocating packets to a weighted adaptive routing group based on a weighted service distribution strategy, according to at least some embodiments of the present disclosure. Figure 5D The flowchart illustrates a method for performing LPM operations according to at least some embodiments of the present disclosure; Figure 5E The flowchart illustrates a method for determining entries within a selected multipath data structure based on grouping-specific criteria, according to at least some embodiments of the present disclosure. Figure 5F This is a flowchart illustrating a method for applying adaptive routing logic to select a specific output port within a selected route group, according to at least some embodiments of the present disclosure. Figure 6 This is a flowchart depicting a method for weighted adaptive multipath routing in a network device according to at least some embodiments of the present disclosure; Figure 7 The figure illustrates a block diagram of a system including a switching circuit system located between a first group of devices and a second group of devices, according to at least one embodiment. Figure 8 A block diagram of an example system according to at least one embodiment is illustrated; Figure 9 An example data center according to at least one embodiment is shown; Figure 10 A processing system according to at least one embodiment is shown; Figure 11 A computer system according to at least one embodiment is shown; Figure 12 A system according to at least one embodiment is shown; Figure 13 An example integrated circuit according to at least one embodiment is shown; Figure 14 A computing system according to at least one embodiment is shown; Figure 15 An APU according to at least one embodiment is shown; Figure 16 A CPU according to at least one embodiment is shown; Figure 17 An example accelerator integration slice according to at least one embodiment is shown; Figures 18A-18B An example graphics processor according to at least one embodiment is shown; Figure 19A A graphics core according to at least one embodiment is shown; Figure 19B A GPGPU according to at least one embodiment is shown; Figure 20A A parallel processor according to at least one embodiment is shown; Figure 20B A processing cluster according to at least one embodiment is shown; Figure 20C A graphics multiprocessor according to at least one embodiment is shown; Figure 21 A graphics processor according to at least one embodiment is shown; Figure 22 A processor according to at least one embodiment is shown; Figure 23 A processor according to at least one embodiment is shown; Figure 24 A graphics processor core according to at least one embodiment is shown; Figure 25 A PPU according to at least one embodiment is shown; Figure 26 A GPC according to at least one embodiment is shown; Figure 27 A streaming multiprocessor according to at least one embodiment is illustrated; Figure 28 A software stack of a programming platform according to at least one embodiment is shown; Figure 29 The illustration shows an embodiment according to at least one of the embodiments. Figure 28 The CUDA implementation of the software stack; Figure 30 The illustration shows an embodiment according to at least one of the embodiments. Figure 28 The ROCm implementation of the software stack; Figure 31 The illustration shows an embodiment according to at least one of the embodiments. Figure 28 The OpenCL implementation of the software stack; Figure 32 Software supported by a programming platform according to at least one embodiment is shown; Figure 33 The illustration shows an embodiment of at least one of the following: Figures 28-31 Compiled code executed on the programming platform; Figure 34 The illustration shows an embodiment of at least one of the following: Figures 28-31 More detailed compiled code executed on the programming platform; Figure 35 This illustrates the transformation of source code before compilation, according to at least one embodiment; Figure 36A A system configured to compile and execute CUDA source code using different types of processing units, according to at least one embodiment, is shown. Figure 36B The diagram illustrates a configuration, according to at least one embodiment, to compile and execute using a CPU and a CUDA-enabled GPU. Figure 36A The system of CUDA source code; Figure 36C The diagram illustrates a configuration, according to at least one embodiment, to compile and execute using a CPU and a GPU with CUDA disabled. Figure 36A The system of CUDA source code; Figure 37 The diagram illustrates a method according to at least one embodiment. Figure 36C Example kernels converted by the CUDA to HIP conversion tool; Figure 38 A more detailed description is provided according to at least one embodiment. Figure 36C GPUs without CUDA enabled; and Figure 39 This illustrates how threads of an example CUDA grid, according to at least one embodiment, are mapped to... Figure 38 Different computing units; and Figure 40 This paper illustrates how to migrate existing CUDA code to data-parallel C++ code according to at least one embodiment.

[0028] In the various figures, the same reference numerals and names indicate the same elements. Detailed Implementation

[0029] The following description provides only examples and is not intended to limit the scope, applicability, or configuration of the claims. Rather, it is intended to provide those skilled in the art with enabling descriptions for implementing the described embodiments. It should be understood that various changes may be made to the function and arrangement of the elements without departing from the spirit and scope of the appended claims.

[0030] It should be understood that, based on the following description and for computational efficiency reasons, the components of the system can be placed at any suitable location within the distributed network of components without affecting the operation of the system.

[0031] Furthermore, it should be understood that the various links connecting the elements can be wired, traced, or wireless links, or any suitable combination thereof, or one or more other suitable known or later-developed elements capable of supplying data to and / or transmitting data from the connected elements. For example, the transmission medium used as a link can be any suitable carrier for electrical signals, including coaxial cables, copper wires and optical fibers, electrical traces on printed circuit boards (PCBs), etc.

[0032] As used in this article, the phrases “at least one,” “one or more,” “or,” and “and / or” are open expressions that function as both conjunctions and adversative conjunctions in action. For example, each of the expressions “at least one of A, B, and C,” “at least one of A, B, or C,” “one or more of A, B, and C,” “one or more of A, B, or C,” “A, B, and / or C,” and “A, B, or C” means A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together.

[0033] The terms “determine,” “calculate,” “operate,” and their variations, as used herein, are used interchangeably and include any appropriate type of method, process, operation, or technique.

[0034] Various aspects of this disclosure are described herein with reference to the accompanying drawings, which are schematic illustrations of idealized configurations. Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that terms such as those defined in common dictionaries shall be interpreted as having the same meaning as they have in the context of the relevant technology and this disclosure.

[0035] Systems and methods for weighted adaptive multipath routing in network environments with asymmetric topology are disclosed. In asymmetric network topologies, each path in the network should be assigned a different traffic capacity to optimize network utilization. Aspects of this disclosure can provide a system comprising LPM, ECMP, congestion control (CC), and BGP that works together to route traffic to each destination in the network in a weighted manner and force each path to receive only the traffic it is capable of routing.

[0036] In network clusters, unbalanced topologies can arise due to various factors such as cable detachment, uneven service distribution, or inherent structural asymmetry. These imbalances can lead to congestion and poor network performance, especially in large-scale clusters. Traditional routing algorithms may struggle to effectively manage services in such scenarios because they typically do not consider potential bottlenecks along the paths.

[0037] Current weighted routing solutions typically require expensive hardware upgrades or major modifications to existing infrastructure. Therefore, there is a need for a more efficient and cost-effective method to implement weighted routing, particularly one that fully utilizes existing hardware and is compatible with previous generations of products. Advantageously, aspects of this disclosure can be implemented without additional hardware and can be implemented in software, thus providing an affordable solution that is backward compatible with existing network infrastructure.

[0038] According to various aspects of this disclosure, the packet flow method for weighted adaptive multipath routing can operate as follows: Packets are initially generated at the host (which may include a network interface controller (NIC) or central processing unit (CPU)) and sent to their destination via a switch. Upon receiving a packet, the switch routes the packet based on its destination IP address and virtual router ID using the LPM algorithm.

[0039] For each destination, an ECMP data structure is configured within the network device. LPM operations use hash functions or linear feedback shift register (LFSR) techniques to distribute packets evenly across the ECMP data structure, ensuring balanced initial distribution.

[0040] According to various aspects of this disclosure, each ECMP entry in the data structure is mapped to a corresponding set of routing rules. More specifically, X ECMP entries may point to a first set of rules (designated as set A), while Y ECMP entries may point to a second set of rules (designated as set B), and so on. This mapping enables proportional service distribution among different set of rules.

[0041] Each rule set may contain different port groups, thus enabling weighted routing between the groups based on the proportion of ECMP entries assigned to each rule set. In some respects, the rule set is configured based on network asymmetric information received via BGP updates.

[0042] Traffic to each port group is controlled by proportional ECMP entry allocation, and traffic flow is managed using congestion control algorithms to efficiently execute traffic to each port according to the required distribution strategy.

[0043] Once a packet is assigned to a specific port group based on the selected ECMP entry and the corresponding set of rules, the network device performs adaptive routing, random selection, round-robin selection, or hash-based forwarding for the given port group. The packet is then forwarded to its next-hop destination via the selected port.

[0044] Now refer to Figures 1 to 6 This disclosure describes various systems and methods for performing weighted adaptive multipath routing in network environments with asymmetric topology or local link failures. Various aspects of this disclosure provide apparatus, methods, processing systems, and computer-readable media for performing weighted adaptive multipath routing in network environments with asymmetric topology or local link failures.

[0045] This disclosure relates to a network routing system capable of fine-grained non-binary service distribution across multiple network paths. When localized capacity degradation occurs on network links, the system can dynamically adjust service ratios using weighted adaptive routing based on real-time network conditions. By combining longest prefix matching, weighted multipath data structures, and directed congestion control, some aspects enable bandwidth management without requiring hardware upgrades to existing network infrastructure.

[0046] In modern data center networks, traditional routing methods face limitations when handling asymmetric topologies or localized link failures. As mentioned earlier, ECMP implementations use binary pruning, either fully including or excluding paths, leading to low bandwidth utilization. When a link degrades to partial capacity (rather than complete failure), existing systems cannot proportionally reduce traffic—such systems either overload the degraded link or completely avoid it, potentially wasting available capacity. Furthermore, conventional adaptive routing can distribute traffic evenly across available ports without considering downstream capacity constraints. This can create congestion hotspots and underutilize healthy network segments.

[0047] Various aspects of this disclosure address these issues by implementing a weighted adaptive routing system that distributes network traffic proportionally based on actual link capacity. In some aspects, the system can perform LMP on incoming packets to select a multipath data structure, where entries are weighted according to network parameters received via routing protocols such as BGP. The system controls traffic distribution by mapping different percentages of multipath table entries to different port groups. For scenarios where traffic reduction is desired, the system can intentionally overbook specific port groups and utilize congestion control mechanisms to manage network throughput. In some aspects, intentionally overbooking specific port groups enables non-binary pruning of network paths, allowing for fine-grained bandwidth adjustment rather than all-or-nothing routing decisions.

[0048] In some respects, at least one technical solution offers several significant advantages. For example, in some respects, service distribution can be scaled up based on available path capacity, thereby improving network utilization in asymmetric topologies. In some respects, the system can allow partial reduction of service along degraded paths (rather than binary pruning), thereby maintaining connectivity while adhering to capacity constraints. In some respects, the system can fully utilize existing LPM, ECMP, and congestion control capabilities in current networking equipment without requiring new hardware or hardware upgrades. In some respects, the system can dynamically adapt to changing network conditions through network capacity updates (e.g., via BGP updates), thereby automatically redistributing services when link capacity changes. By strategically managing congestion through controlled overbooking, the system can provide predictable and stable network performance even in scenarios with localized link degradation.

[0049] like Figure 1As shown, the computing environment 100 described herein may include a network of processing devices 104 interconnected via a structure. As described herein, the structure may include one or more interconnect devices 102 and / or one or more processing devices 104. One or more interconnect devices 102 may communicate with processing devices 104 and one or more other computing systems, such as client devices 106. Such a network, consisting of processing devices 104 and interconnect devices 102, can function in a variety of settings, from data centers and cloud computing infrastructures to AI systems.

[0050] Processing device 104 may be a computing unit (such as a personal computer, server, or other computing device) and may be responsible for executing applications and performing data processing tasks. As described herein, processing device 104 may encompass everything from servers in a data center to desktop computers in a network, and even devices such as Internet of Things (IoT) sensors and smart devices.

[0051] One or more processing devices 104 may include one or more processing circuits (such as GPUs, CPUs, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other circuit systems capable of performing computations), as well as memory and storage resources for running software applications, handling data processing, and performing specific tasks as needed. In some embodiments, processing device 104 may also or alternatively include hardware such as GPUs for handling computationally intensive tasks such as machine learning, artificial intelligence (AI) workloads, or other complex processes.

[0052] For example, processing device 104 can operate as a high-performance computing (HPC) cluster. The cluster of processing device 104 may include many interconnected servers, each equipped with a powerful CPU and / or GPU. Processing device 104 can provide computing power for, for example, training large-scale AI models or running complex scientific simulations. For AI and machine learning tasks, processing device 104 may include one or more GPUs or other processing circuitry systems, which can handle the parallel processing needs of neural networks and other applications.

[0053] As described in more detail herein, interconnect device 102 enables communication between processing device 104 and / or client device 106. Interconnect device 102 may be, for example, a network switch, a network interface card (NIC), or another device capable of receiving and transmitting data, and may act as a central node in the network. Interconnect device 102 may be cabled in a topology, including, for example, a spine switch and a top-of-rack (TOR) switch. Interconnect device 102 may be capable of receiving, processing data (e.g., packets), and forwarding them to appropriate destinations within the network. In some aspects, such destinations may include, but are not limited to, processing device 104 and / or client device 106. In some embodiments, as described herein, interconnect device 102 may be included in a switch chassis, platform, or enclosure that can accommodate one or more interconnect devices 102 and one or more power supply devices.

[0054] In some implementations, one or more processing devices 104 may be connected via network cables to one or more ports of one or more interconnecting devices 102. In some aspects, one or more processing devices 104 may be wirelessly connected to one or more ports of one or more interconnecting devices 102. Processes such as applications executed by processing devices 104 may involve transmitting data to nodes in the network, such as to other processing devices 104 and / or client devices 106. Data may flow through the network of processing devices 104 and interconnecting devices 102 using one or more protocols, such as Transmission Control Protocol (TCP), User Datagram Protocol (UDP), or Internet Protocol (IP). Upon receiving data from processing device 104 or another interconnecting device 102, one or more interconnecting devices 102 may examine the data to identify its destination and route the data over the network.

[0055] As described herein, client device 106 can refer to a computing device that performs AI-related, research-related, and / or other processor-intensive tasks. To manage the significant computational load and data throughput required by such applications, client device 106 may utilize one or more processing devices 104. Examples of client devices 106 include, but are not limited to, workstations and personal computers used by researchers, data scientists, and / or professionals to develop, test, and / or execute AI models and research simulations. While client device 106 may be equipped with one or more CPUs and / or GPUs, one or more client devices 106 may require additional computing resources to efficiently perform complex tasks. By interacting with processing device 104, client device 106 can be enabled to perform a variety of functions, such as training machine learning models, performing data processing, running simulations, analyzing large datasets, and / or performing complex data processing tasks (such as data mining, pattern recognition, and / or predictive modeling).

[0056] Now for reference Figure 2A An exemplary network topology 200a is illustrated as an implementation of aspects of a weighted adaptive routing system according to aspects of this disclosure. In some aspects, network topology 200a may represent a multi-layered Clos network architecture comprising multiple interconnected network devices arranged in a hierarchical design to facilitate data communication between various host devices. In some aspects, a Clos network architecture may refer to a class of non-blocking, multi-stage switched networks characterized by multi-stage switches arranged in a specific pattern, allowing arbitrary inputs to connect to arbitrary outputs, thereby providing high bandwidth and fault tolerance. In some data center networks, a Clos topology may include three layers of switches (leaf, spine, and core) organized in a manner that creates multiple equivalent paths between any two endpoints, making it well-suited for implementing ECMP routing techniques and weighted adaptive routing methods according to aspects described herein. Although Figure 2A The diagram illustrates the Clos network, but other network topologies are also considered for implementing weighted adaptive routing techniques.

[0057] In some aspects, network topology 200a may include a first group of hosts 202 and a second group of hosts 204 connected to leaf switches on a first side of the topology. A third group of hosts 254 and a fourth group of hosts 260 may be connected to leaf switches on a second side of the topology. These host groups (e.g., the first group of hosts 202, the second group of hosts 204, the third group of hosts 254, and the fourth group of hosts 260) may include computing devices (such as servers, processors, storage systems, or other network-connected devices) that generate or consume network traffic. In some aspects, network topology 200a enables communication between these different host groups through the network structure. In some respects, network architecture can refer to the interconnected set of leaf switches (e.g., leaf switch (L6) 206, leaf switch (L7) 212, leaf switch (L0) 252 and leaf switch (L1) 258), spine switches (e.g., spine switch (S6) 210, spine switch (S7) 216, spine switch (S0) 240 and spine switch (S1) 246), core switches (e.g., core switch (C0) 224, core switch (C1) 228, core switch (C2) 236 and core switch (C3) 232) and their connecting links (e.g., links 208, 214, 218, 220, 222, 226, 234, 230, 238, 242, 244, 248, 250, 256, 262 and 264), which together provide multiple paths for data transmission between any two endpoints in the network.

[0058] In some respects, leaf switch (L6) 206 represents a network switching device that provides connectivity between the first group of hosts 202 and the network structure. In various implementations, leaf switch (L6) 206 may be a top-of-rack (ToR) switch that connects server racks or other computing devices to the network. Leaf switch (L6) 206 may include circuitry configured to receive network packets, inspect their headers, determine appropriate forwarding paths based on destination addresses, and route packets accordingly. Leaf switch (L6) 206 may implement weighted adaptive routing techniques, including performing LPM operations on packet destination addresses, maintaining multipath data structures (such as ECMP tables), and allocating packets to different port groups according to a network service distribution strategy that distributes traffic based on network parameters.

[0059] In some implementations, the leaf switch (L6) 206 may include memory storing routing tables, port group configurations, and multipath data structures that route traffic to different paths based on current network conditions. The leaf switch (L6) 206 may also include processing circuitry configured to update these tables and structures based on information received via network protocols such as BGP. By implementing weighted adaptive routing at the leaf switch level, the network can optimize traffic distribution from inbound sites, potentially reducing congestion and improving overall network performance.

[0060] Leaf switch (L7) 212 functions similarly to leaf switch (L6) 206, providing connectivity between the second group of hosts 204 and the network structure. Leaf switch (L7) 212 implements similar routing functions and can independently adjust its service distribution based on network parameters.

[0061] The spine switch (S6) 210 represents an intermediate layer device in the network hierarchy that aggregates traffic from multiple leaf switches and routes it to the appropriate core switch. In some respects, the spine switch (S6) 210 connects to leaf switches (L6) 206 and (L7) 212, receives traffic from the first and second groups of hosts, and forwards the traffic to the core switch based on the destination address. In some respects, the spine switch (S6) 210 can implement weighted adaptive routing technology, thereby distributing traffic across multiple uplinks in proportion to available bandwidth or other network parameters.

[0062] The S7 216 spine switch provides functionality similar to the S6 210 spine switch, connecting to leaf switches and core switches to facilitate service flows through the network structure. The S7 216 spine switch can make independent adaptive routing decisions based on local congestion conditions or network-wide parameters.

[0063] In some respects, core switch (C0) 224 represents a top-level network device that interconnects multiple spine switches, thereby allowing traffic to be transmitted from one part of the network to another. For example, core switch (C0) 224 is connected to spine switches (S6) 210 and (S0) 240 via links 222 and 238, respectively, each link comprising four 100 Gbps capacity connections, for a total bandwidth capacity of 400 Gbps per link. Core switch (C0) 224 enables traffic to flow between hosts on opposite sides of the network topology, such as between the first group of hosts 202 and the third group of hosts 254.

[0064] Core switch (C1) 228 functions similarly to core switch (C0) 224, interconnecting spine switches (S6) 210 and (S0) 240 via links 226 and 242. Each of these links comprises four 100 Gbps connections, for a total bandwidth capacity of 400 Gbps per link. Core switches (C2) 236 and (C3) 232 complete the core layer of the network, providing additional paths and redundancy through connections to spine switches (S7) 216 and (S1) 246.

[0065] In some respects, spine switch (S0) 240 connects core switch (C0) 224 and core switch (C1) 228 to leaf switch (L0) 252 via links 238, 242, and 250, respectively. Similarly, spine switch (S1) 246 connects core switch (C2) 236 and core switch (C3) 232 to leaf switch (L1) 258 via links 244, 248, and 256, respectively. These spine switches facilitate service flow from the core layer to the destination side of the network at the leaf layer.

[0066] Leaf switches (L0) 252 and (L1) 258 provide connectivity between the network structure and the third group of hosts 254 and the fourth group of hosts 260, respectively. These leaf switches can function similarly to leaf switches (L6) 206 and (L7) 212, and implement similar routing and service distribution mechanisms.

[0067] Network topology 200a may include numerous links interconnecting various network devices. These links represent physical or logical connections characterized by bandwidth parameters such as 2 × 200 Gbps or 4 × 100 Gbps. These links enable scalable data transfer capabilities between different layers of the switching architecture. In some aspects, link 208 connects leaf switch (L6) 206 to spine switch (S6) 210 and includes two 200 Gbps connections, providing a total bandwidth capacity of 400 Gbps. Similarly, link 214 connects leaf switch (L7) 212 to spine switch (S7) 216, also including two 200 Gbps connections, for a total bandwidth capacity of 400 Gbps. Links 222, 226, 230, 234, 238, 242, 244, and 248 connect the spine switch to the core switch. Each link may include four 100 Gbps connections, with a total bandwidth capacity of 400 Gbps per link. This represents a transition from two 200 Gbps links from the leaf to the spine layer to four 100 Gbps links from the spine to the core layer, thus creating potential asymmetry in the network that could benefit from weighted adaptive routing methods.

[0068] exist Figure 2A In the depicted network topology 200a, links 250, 256, 262, and 264 connect the spine switch to the leaf switch on the destination side of the network. Each link includes two 200 Gbps connections, and the total bandwidth capacity per link is 400 Gbps. The link bandwidths described herein (such as 2 × 200 Gbps and 4 × 100 Gbps) are provided only as examples, and various other link capacities can be implemented according to the weighted adaptive routing techniques of this disclosure. Network topology 200a illustrates a configuration that provides multiple potential paths between any given source host and destination host. For example, a service from a host in the third group of hosts 254 to a host in the first group of hosts 202 may traverse any of several paths through the network structure, including: Path 1: 254→252→250→240→238→224→222→210→208→206→202 Path 2: 254→252→250→240→242→228→226→210→208→206→202 Path 3: 254→252→264→246→248→236→234→216→220→206→202 Path 4: 254→252→264→246→244→232→230→216→220→206→202 In some aspects, such as Figure 2A The described multi-path, multi-layer topology provides the foundation for implementing weighted adaptive routing, which dynamically adjusts service distribution in response to changing network conditions. As described herein, weighted adaptive routing can be implemented at various points in the network, including leaf switches, allowing for optimized service distribution from the ingress points of the network structure.

[0069] Now for reference Figure 2B The diagram illustrates network topology 200b, which describes a network topology 200b involving a degraded link scenario according to various aspects of this disclosure. For example, in... Figure 2B As depicted, link 266 connecting core switch (C0) 224 to spine switch (S0) 240 has been degraded, as shown in symbol 268. Although in Figure 2A The connection consists of four 100 Gbps links (4 × 100 Gbps). Figure 2B The system provides a total bandwidth of 400 Gbps, but the number of connections has been reduced to three 100 Gbps links (3 x 100 Gbps), resulting in a total available bandwidth of 300 Gbps. Such degradation can be caused by a variety of factors, such as hardware failure, environmental conditions, or maintenance operations. It should be understood that this particular degradation pattern is provided as an example, and other degradation scenarios may occur, such as four connections operating at reduced capacity (e.g., 4 x 75 Gbps) or two connections operating at increased but still insufficient capacity (e.g., 2 x 90 Gbps).

[0070] In a traditional ECMP routing scenario, when a host in the third group of hosts 254 sends data destined for a host in the first group of hosts 202, the network traffic will pass through leaf switch (L0) 252, spine switch (S0) 240, and may reach core switch (C0) 224 via degraded link 266. In traditional ECMP, the routing system can make binary decisions regarding link inclusion, including either fully utilizing a link or completely pruning it from consideration. In some respects, this binary decision-making approach can lead to several problems when faced with partially degraded links (such as link 266).

[0071] In other words, in traditional ECMP routing scenarios, when faced with a degraded link (such as link 266, which has been reduced from 4×100 Gbps to 3×100 Gbps), the routing system must choose between two suboptimal options: either continue to treat the link as fully operational and potentially overbook it, or completely remove it from the routing table even though the link still has considerable remaining capacity. This binary decision process fails to account for partial degradation, where the link still maintains significant but reduced bandwidth. Traditional ECMP lacks the granularity to scale traffic according to actual available capacity, which can lead to low network utilization, especially in complex topologies with multiple alternative paths of varying capacities.

[0072] Specifically, traditional ECMP might continue to route the entire service quota through a degraded path, causing congestion at link 266 since this path now only has 75% of its original capacity. Alternatively, traditional ECMP might completely prune this link from a routing perspective, wasting the remaining 300 Gbps of available bandwidth and requiring network traffic to bypass core switch (C0) 224 and instead route to core switch (C1) 228. Neither of these outcomes provides optimal network performance or resource utilization, especially in large-scale networks where efficient service management is crucial.

[0073] Figure 3A A block diagram depicts an interconnect device 102 that can implement weighted adaptive routing technology according to various aspects of this disclosure. In some aspects, the interconnect device 102 may represent a reference... Figure 1 , Figure 2A and / or Figure 2B Any switching equipment described (such as leaf switches, spine switches, or core switches).

[0074] In some aspects, interconnect device 102 may include multiple ports 302a-302n, switching hardware 304, queue monitor 308, multipath data structure 310, buffer 312, adaptive routing engine 324, congestion control manager 316, processing circuitry system 318, and / or memory 320 for implementing one or more weighted adaptive routing methods described herein. Interconnect device 102 may include one or more ports 302a-302n configured to send and receive data in the form of packets, frames, and / or other information units. Ports 302a-302n may be referred to as hardware ports. A “hardware port” may refer to a physical interface (such as an Ethernet or fiber optic port) on a network switching device (also referred to herein as a switch and network switch) through which network packets are transmitted and received over a physical medium. A hardware port may differ from a “logical port,” which may refer to a software-defined endpoint identified by a numerical label for facilitating protocol-specific communication between networked devices at the transport or application layer. Although the aspects discussed primarily concern hardware ports, some aspects of this disclosure can also be applied to logical ports.

[0075] In some respects, each port 302a-302n can support high-speed data transmission over physical cabling (such as copper or fiber optic cables). In other respects, one or more ports 302a-302n can be compatible with one or more wireless transceivers. Ports 302a-302n can be configured to adapt to one or more communication standards and protocols (including Ethernet, InfiniBand, and / or proprietary link layer protocols), enabling flexible deployment in diverse network environments. Each port 302a–302n can dynamically switch between ingress and egress functions, or operate in dedicated ingress or egress modes, depending on the overall configuration and management policies configured, such as software or firmware.

[0076] In some aspects, each port 302a-302n may include a physical layer device (PHY) and / or logic that performs signal encoding / decoding, clocking and data recovery, and other low-level operations. Such PHY components may be circuitically integrated within a substrate (e.g., within an ASIC, FPGA) or otherwise disposed on a separate module. In some implementations, one or more ports 302a-302n may also include on-chip or external memory elements for temporary storage of incoming or outgoing data. The on-chip or external memory elements may work in conjunction with larger shared resources (such as buffer 312) to provide efficient traffic queuing and management. The configuration and operational status of each port 302a-302n (such as speed, duplex setting, or active / inactive state) may be monitored by the processing circuitry system 318. Furthermore, ports 302a-302n may provide status indicators or counters (e.g., for transmitted or discarded packets) that can be accessed by higher-level software for analysis or troubleshooting. Ports 302a-302n may provide one or more interface points that connect interconnect device 102 to external devices to enable one or more service management, congestion management and / or load balancing technologies described herein.

[0077] In some aspects, switching hardware 304 may include one or more integrated circuits, multiplexers, crossbar switches, or other data forwarding components arranged to route incoming data from ports (e.g., one or more ports 302a-302n) to one or more destination ports based on switching logic for Layer 2 forwarding and / or routing logic for Layer 3 processing. In some implementations, switching hardware 304 may operate at line rate (e.g., processing packets at the maximum theoretical speed of the network interface) to ensure minimal latency while maintaining reliable throughput. Switching hardware 304 may include dedicated forwarding tables or pipes for analyzing header information (such as Media Access Control (MAC) addresses for Layer 2 switching, Virtual LAN (VLAN) tags, or network layer identifiers (such as Internet Protocol (IP) addresses) for Layer 3 routing) to determine how to forward each data unit within interconnect device 102. Furthermore, the switching hardware 304 can utilize programmable match-action phases (e.g., processing pipeline phases that compare incoming packet fields with predefined patterns and execute corresponding actions) to adapt to evolving network requirements through software-defined updates. For example, users can reconfigure the switching hardware 304 to implement different flow control policies, weighted adaptive routing methods that can dynamically adjust to changing network conditions, advanced monitoring capabilities, or security filters without redesigning the switching hardware 304.

[0078] In some respects, link 322a represents a physical or logical connection between port 302a and another network device. Links 322b, 322c, and 322n similarly represent connections from other ports to external network elements. Links 322a-322n can represent physical or logical connections characterized by bandwidth parameters (e.g., 2 × 200 Gbps or 4 × 100 Gbps). In some respects, links 322a-322n can provide data transfer capabilities between different layers of the switching architecture, as discussed earlier. Figure 1-2B As described above. In some aspects, port group 323 (e.g., port groups 323a and 323b) may include one or more ports associated with one or more links 322a-322n, wherein the port group provides aggregated connectivity between interconnecting device 102 and other devices in the network.

[0079] In some aspects, the switching hardware 304 can implement a weighted adaptive routing method by coordinating the operations between queues 306a-306n, queue monitor 308, buffer 312, adaptive routing engine 314, and congestion control manager 316. Queue 306a may be associated with a port (such as port 302a) and can be used as a temporary storage area for network packets waiting to be transmitted through that port. In some aspects, queues 306b, 306c, and 306n are similar buffer structures associated with ports 302b, 302c, and 302n, respectively. Each queue can operate independently to manage traffic flow through its respective port. In some aspects, all queues (e.g., queues 306a-306n) can operate under the coordinated control of the switching hardware and associated traffic management components, as further described herein.

[0080] Queue monitor 308 represents components within switching hardware 304 that observe and track the status of each queue 306a-306n. Queue monitor 308 can collect various metrics, such as current queue depth, input rate, output rate, packet drop statistics, and congestion indicators. The collected metrics can be input to adaptive routing engine 314 and congestion control manager 316, enabling them to make informed decisions regarding traffic distribution and flow control. Multipath data structure 310 implements weighted adaptive routing functionality. Multipath data structure 310 (which can be implemented as one or more tables in memory, such as memory 320) can include entries mapping between destination addresses and port groups. When implementing a weighted adaptive routing approach, in some respects, multipath data structure 310 can assign different proportions of traffic to different port groups based on network parameters such as available bandwidth, congestion level, or link failures. For example, if the link capacity in the network has decreased from 400 Gbps to 300 Gbps (e.g., due to the failure of a 100 Gbps link in a 4×100 Gbps configuration), the multipath data structure 310 can allocate 75% of the traffic that normally passes through that link, while redirecting the remaining 25% of the traffic to an alternative path. This non-binary approach allows for finer-grained traffic management than traditional routing methods, which either continue sending 100% of the traffic through the degraded link (causing congestion) or completely prune that link (wasting the remaining 300 Gbps capacity). The multipath data structure 310 can be dynamically updated based on network condition information received via network protocols such as BGP, enabling the switch to continuously optimize traffic distribution on available paths as network conditions change.

[0081] Buffer 312 can represent memory space within switching hardware 304 for temporary storage of packets during processing operations. Buffer 312 can provide additional storage for data packets during transient congestion events, such as when multiple ports 302a-302n simultaneously switch from idle to active, and in some cases, when one or more queues 306a-306n of interconnect device 102 become congested. For example, in scenarios where the network experiences micro-burst traffic patterns (e.g., brief, dense data bursts), buffer 312 can absorb temporary traffic spikes from multiple ingress ports without packet loss. When implementing weighted adaptive routing, buffer 312 can assist in managing oversubscribed port groups. For example, in… Figure 2BIf link 266 between core switch (C0) 224 and spine switch (S0) 240 has been downgraded from 4×100 Gbps to 3×100 Gbps, and multipath data structure 310 has proportionally allocated traffic, then during periods when traffic temporarily exceeds the capacity of the downgraded link, buffer 312 can temporarily store excess packets until congestion subsides or until a congestion control manager (e.g., congestion control manager 316) instructs controlled packet dropping to occur. Therefore, buffering can work in conjunction with adaptive routing engine 314 to ensure that traffic distribution between port groups remains at the desired level. Furthermore, buffering provides resilience to accommodate normal traffic fluctuations that might otherwise trigger unnecessary rerouting decisions.

[0082] In some respects, the adaptive routing engine 314 can select specific ports for packet forwarding based on real-time network conditions. For example, the adaptive routing engine 314 can receive input from the queue monitor 308. Using the input from the queue monitor 308, the adaptive routing engine 314 can dynamically adjust routing decisions to optimize traffic flow on the network. In some respects, adaptive routing can refer to a network routing method that dynamically selects the optimal path for data packets based on current network conditions, rather than relying solely on static routing tables. Unlike traditional routing methods that use fixed paths determined at configuration time, adaptive routing can evaluate network metrics such as congestion level, queue depth, link utilization, and latency to make intelligent data forwarding decisions.

[0083] Within interconnect device 102, adaptive routing engine 314 can implement adaptive routing by analyzing data from queue monitor 308 to identify the least congested or most efficient path within an assigned port group. Therefore, when packets are assigned to a specific port group (e.g., port group 323a) by multipath data structure 310, adaptive routing engine 314 can select a specific port within that port group for packet transmission. For example, if port group 323a contains ports 302a, 302b, and 302c, and queue monitor 308 indicates that queue 306b has a significantly lower occupancy rate than queues 306a and 306c, then adaptive routing engine 314 can prioritize routing packets through port 302b to balance network traffic load.

[0084] The adaptive routing engine 314 can employ various selection algorithms, including round-robin distribution, random selection, weighted selection based on queue occupancy, or other algorithms that consider historical performance metrics. By operating within the context of port groups already assigned by the weighted distribution policy, the adaptive routing engine 314 can provide a second layer of service optimization that works in conjunction with a broader network-wide service distribution policy implemented via the multipath data structure 310.

[0085] In some respects, the congestion control manager 316 can work in conjunction with the adaptive routing engine 314 to manage network traffic during congestion. The congestion control manager 316 can function to regulate traffic flow when network conditions indicate that certain paths or ports are experiencing high utilization or approaching capacity limits. In some respects, the congestion control manager 316 can operate to prevent network congestion from degrading overall performance and supports weighted adaptive routing. Even when certain paths experience reduced capacity or increased load, the congestion control manager 316 can employ various strategies to maintain optimal network throughput.

[0086] In some respects, when implementing weighted adaptive routing, the congestion control manager 316 can manage intentional overbooking scenarios. For example, in network configurations with link degradation (such as... Figure 2B Link 266 (degraded from 400 Gbps to 300 Gbps) in the network, and congestion control manager 316 can intentionally allow controlled congestion on specific port groups to achieve desired traffic shaping results. Congestion control manager 316 does not completely avoid the degraded path, but rather allows a calculated amount of network traffic to be directed to that path, recognizing that a portion of the network traffic will experience controlled packet dropping or delay. Congestion control manager 316 can employ various techniques, including but not limited to: explicit congestion notification (ECN) marking of packets approaching congestion thresholds; sending selective backpressure signals to upstream devices; employing intelligent queue management algorithms such as random early detection (RED); rate limiting per port or per flow; and / or employing credit-based flow control to manage bandwidth allocation between port groups.

[0087] For example, when the multipath data structure 310 has already allocated traffic among port groups in a specific ratio (e.g., 75% to one path and 25% to another), the congestion control manager 316 can enforce these ratios by adjusting the actual throughput, potentially dropping excess packets, or signaling upstream devices to temporarily reduce the transmission rate. Controlled congestion methods enable finer-grained traffic management than traditional binary routing decisions, allowing the network to make fuller use of available bandwidth while avoiding uncontrolled congestion events.

[0088] In some aspects, the processing circuitry 318 may represent one or more computing elements of the interconnect device 102, handling control plane operations, management functions, and software processing. The processing circuitry 318 may include one or more processors, microcontrollers, digital signal processors (DSPs), or dedicated ASIC blocks configured to manage system-level operations of the interconnect device 102. In some embodiments, the processing circuitry 318 may execute firmware stored in memory 320 to maintain routing tables, manage port configuration parameters (e.g., enabling or disabling specific ports 302a-302n), and apply quality of service policies. In a weighted adaptive routing implementation, the processing circuitry 318 may be responsible for processing BGP updates or other network state information, calculating appropriate traffic distribution weights, and programming the multipath data structure 310 accordingly. Furthermore, the processing circuitry 318 may directly coordinate with the queue monitor 308 to collect metrics about queue occupancy, data throughput, and errors, such as generating congestion notification packets or adjusting load balancing algorithms. Furthermore, the processing circuitry 318 can interact with higher-level management tools, such as network orchestration platforms or cloud-based controllers, to deliver telemetry data or receive updated service distribution policy rules in real time. By offloading some decision-making to the switching hardware 304, the processing circuitry 318 remains available for more complex tasks, including congestion analysis, device configuration, and other diagnostic tasks (e.g., performing debugging of flow control counters or verifying compliance with service level agreements). Therefore, the interconnect device 102 can maintain a high level of throughput while providing congestion management and adaptive routing capabilities.

[0089] In some respects, memory 320 can provide storage for the operating system, configuration data, routing tables, and other information required for the operation of interconnected devices. Memory 320 can utilize one or more storage technologies, such as DRAM, SRAM, TCAM, or flash memory. In some respects, DRAM can store large routing tables or buffered data, SRAM can serve as a high-speed temporary storage for real-time operation, and TCAM can facilitate fast lookups of routing or security rules. Regardless of the specific technology used, memory 320 can be used to make configuration parameters, firmware images, and runtime data structures easily accessible to the processing circuitry system 318.

[0090] In the context of weighted adaptive routing, memory 320 can store historical data on network parameters, port group configurations, traffic distribution policies, and notification adaptive decisions. In some aspects, memory 320 can maintain a multipath data structure 310, which may contain a weighted ECMP table determining the traffic distribution ratio between different port groups. When network conditions change (such as when a link degrades from 400 Gbps to 300 Gbps), processing circuitry 318 can update these multipath data structures in memory 320 to reflect the new expected traffic distribution ratio. Memory 320 can also store multiple versions of these structures for different destination prefixes, thereby allowing for destination-specific routing policies.

[0091] In some aspects, memory 320 may store and / or otherwise maintain a service distribution policy that manages how packets are distributed among different port groups. In some aspects, the service distribution policy may be defined as a set of rules for proportionally allocating network services based on current network parameters and may provide a basis for a weighted adaptive routing system. The service distribution policy stored in memory 320 may include port group definitions, proportional allocation ratios, blocking ratios for oversubscribed links (and, in some cases, undersubscribed links), and conditional logic adapting to specific network events. In some aspects, when processing circuitry 318 receives network parameter updates (such as capacity changes via BGP), processing circuitry 318 may query the service distribution policy to determine how network services should be distributed among port groups.

[0092] In some respects, the memory 320 may include a lightweight operating system or embedded software stack that manages hardware resources and provides interfaces for remote configuration and updates. Furthermore, the memory 320 may enable virtualization capabilities, allowing multiple logical partitions (or “slices”) of the device to operate independently. This can be useful in large data center or cloud environments where different tenants or workloads may require isolated resources and custom flow control settings. In some respects, the memory 320 may maintain the relationship between LPM (Longest Prefix Match) results and the corresponding multipath data structures, ensuring that packets with the same destination are processed according to the current network distribution policy. When the processing circuitry 318 receives a BGP update indicating a change in link capacity or availability, it can perform calculations to determine optimal service distribution and update the relevant multipath data structures in the memory 320, enabling the switching hardware 304 to forward services based on the new weighted adaptive routing parameters.

[0093] Figure 3BA block diagram illustrating additional details of the illustrated processing circuitry system 318 includes one or more components that implement weighted adaptive routing functionality according to various aspects of this disclosure. In some aspects, the processing circuitry system 318 may include software and / or firmware modules that work together to manage service distribution on a network.

[0094] The service distribution controller 330 can operate as a central coordinating component of a weighted adaptive routing system. The service distribution controller 330 can coordinate the activities of various modules to implement service distribution policies on the network. The service distribution controller 330 can receive network state information, consult service distribution policies stored in memory 320, and determine how services should be proportionally distributed among available network paths. In some aspects, when network conditions change (such as when link degradation occurs), the service distribution controller 330 can determine appropriate service redistribution policies and coordinate updates to routing structures (such as ECMP tables or multipath data structures) that map destination addresses to specific forwarding paths or port groups and guide network packets through network devices to their destinations. For example, when... Figure 2B When link 266 in the network is downgraded from 4×100 Gbps to 3×100 Gbps, the service distribution controller 330 can determine that the service should be redistributed at a ratio of 75% / 25% to maintain the desired network utilization without causing uncontrolled congestion.

[0095] In some respects, the network state processor 332 can process network state updates. Network state updates can be received from various protocols, including but not limited to BGP. The network state processor 332 can monitor network state information, extract relevant parameters (such as available bandwidth, link failures, or congestion levels), and transform network state information from raw data into actionable intelligence for other components. The network state processor 332 can identify patterns in network behavior, aggregate relevant notifications, and prioritize updates that may require immediate attention. For example, when a BGP update indicating a local link degradation is received, the network state processor 332 can calculate the capacity reduction and forward this information to the service distribution controller 330 and other components to trigger appropriate routing adjustments.

[0096] Multipath data structure generator 334 can create and maintain weighted ECMP tables and other multipath data structures that can be referenced to determine packet forwarding behavior. Based on input from traffic distribution controller 330 and (in some cases) blocking rate policy generator 344, multipath data structure generator 334 can generate a mapping table that associates destination prefixes with port groups according to their expected traffic allocation proportions. For example, if a particular network path should receive 75% of the traffic and another path should receive 25%, multipath data structure generator 334 can create multipath data structures (such as ECMP tables) where 75% of the entries point to one port group and 25% of the entries point to another port group. The multipath data structures can be stored in memory 320 for use by switching hardware 304 during packet processing.

[0097] In some respects, congestion control configuration / policy component 336 can establish parameters and policies for managing network congestion, for example, in scenarios where controlled congestion is part of a weighted adaptive routing policy. Congestion control configuration / policy component 336 can define thresholds, behaviors, and policies that determine the switching hardware 304 (e.g., Figure 3A The congestion control manager 316 in the congestion control configuration / policy component 336 should respond to various congestion scenarios. The congestion control configuration / policy component 336 can specify different congestion handling methods based on service category, port group, or network conditions. In a weighted adaptive routing implementation where certain paths are intentionally overbooked to achieve desired service distribution, the congestion control configuration / policy component 336 can configure appropriate congestion control mechanisms, such as ECN labeling thresholds, selective packet dropping policies, or sending backpressure signals to upstream devices.

[0098] In some aspects, the processing circuitry 318 may include rate limiting logic 338, which is used to establish parameters for traffic shaping and define bandwidth allocation for different service flows or port groups. Rate limiting logic 338 can translate advanced service distribution strategies into specific rate control mechanisms that can be implemented by the switching hardware 304. Rate limiting logic 338 can define rate limits on a per-port, per-flow, or per-service-class basis to ensure that the actual service volume matches the expected allocation determined by the service distribution controller 330.

[0099] In some respects, queue monitoring configuration 340 can be used for switching hardware 304 (e.g., Figure 3AThe queue monitor 308 in the configuration defines one or more parameters, including congestion detection threshold, sampling interval, and metric collection strategy. The queue monitor configuration 340 enables the adaptive routing engine 314 to make informed decisions about port selection within a specified port group based on real-time queue status information. The queue monitor configuration 340 can specify different monitoring methods for different port groups or service categories, thereby achieving customized adaptive routing behavior based on different performance requirements.

[0100] In some respects, the port group manager 342 defines and maintains port groups based on network topology and routing requirements. The port group manager 342 can determine which physical ports (e.g., Figure 3A The port group manager 342 defines which logical port groups (ports 302a-302n) of the interconnected device 102 belong to, thus establishing boundaries for making adaptive routing decisions within them. The port group manager 342 can dynamically adjust port group memberships based on changes in network topology, link status, or management policies. In some respects, port group definitions can be used to implement weighted distribution strategies because they define the set of ports on which services are distributed proportionally.

[0101] In some aspects, the processing circuitry 318 may include a congestion rate policy generator 344 that calculates a traffic distribution ratio based on network capacity information. For example, when a network link undergoes partial degradation, the congestion rate policy generator 344 can determine how much network traffic should be allocated to each available path. Compared to conventional binary pruning methods, the congestion rate policy generator 344 enables non-binary traffic distribution decisions that utilize available bandwidth more efficiently. For example, when a link degrades to 75% of its original capacity, the congestion rate policy generator 344 can determine that traffic should be distributed between two alternative paths at a ratio of 75% / 25%, thereby allowing the network to maintain optimal utilization while avoiding congestion.

[0102] The congestion rate policy generator 344 can generate a congestion rate as the relationship between overbooked network traffic and the amount of data that can be transmitted through a port group. For example, when a capacity reduction occurs, reducing network capacity to 7 / 8 of its original capacity, the congestion rate can be represented as 8 / 7 if paths are intentionally overbooked; if paths are underbooked, the congestion rate can be represented as 7 / 8. In some cases, when overbooking occurs, the congestion control module can be responsible for further reducing traffic. Alternatively or additionally, the congestion rate can be defined as the traffic volume relative to path capacity (e.g., 133.3 Gbps / 100 Gbps, indicating that 133.3 Gbps of traffic is routed to a 100 Gbps path, where such paths are intentionally overbooked). In some cases, the congestion rate can also indicate underbooked lines (e.g., 266.6 Gbps / 300 Gbps, where such paths have been degraded but are not fully utilized). The blocking rate can be used as a parameter to guide the expected overbooking / underbooking level in the business distribution strategy, or as a calculation result reflecting the actual overbooking / underbooking level achieved by the system.

[0103] Figure 3C The diagram illustrates a block diagram of a memory 320, according to at least one aspect of this disclosure, storing data structures and configuration information for implementing weighted adaptive multipath routing. The memory 320 may reside in a network device (such as a reference cipher). Figure 1-3B Within the interconnect device 102. Memory 320 may include one or more types of computer-readable storage media, including but not limited to dynamic random access memory (DRAM), static random access memory (SRAM), ternary content-addressable memory (TCAM), or flash memory. In some aspects, memory 320 may include dedicated memory cells for specific functions within the network device, such as high-speed table lookup or packet buffering.

[0104] like Figure 3C As shown, memory 320 may include multipath data structure 346, port group configuration 348, service distribution policy 350, blocking rate 352, and network parameters 354. These components collectively enable network devices to implement weighted adaptive routing, thereby distributing network packets across port groups in proportion to the current network conditions.

[0105] In some aspects, the multipath data structure 346 includes one or more tables or other data structures that map packet destinations to specific routing actions. In some aspects, the multipath data structure 346 can be implemented as an ECMP table with multiple entries. Each entry in the multipath data structure 346 can be associated with a rule or action that identifies a corresponding port group among multiple port groups. When a packet's destination address undergoes an LPM operation, the result can point to the multipath data structure 346, which can then be used to determine the routing behavior for the packet.

[0106] The multipath data structure 346 enables network service distribution strategies that proportionally distribute network packets across multiple port groups based on network parameters. More specifically, the multipath data structure 346 can map different entries to different port groups within the multiple port groups. In some aspects, the multipath data structure 346 may include an Equal Cost Multipath (ECMP) table with multiple entries, where different percentages of these entries are mapped to different port groups within the multiple port groups. This weighted distribution allows services to be allocated proportionally according to network parameters. For example, if a network path degrades to 75% of its original capacity due to a link failure, the multipath data structure 346 can be configured to direct 75% of its entries to one port group and 25% of its entries to another port group, thereby ensuring that the service load is distributed proportionally across available capacity.

[0107] In some respects, each entry in the multipath data structure 346 may be associated with at least one rule or action that identifies a corresponding port group among multiple port groups, wherein the rule or action indicates which ports of the network device are included in the corresponding port group. For example, a rule might specify that port group A includes ports 0, 1, and 2, while port group B includes only port 3. In addition to port membership specification, rules or actions may include more complex routing behaviors, such as, but not limited to: conditional routing logic that considers packet attributes (like DSCP values ​​or flow identifiers) when selecting specific ports within the group; service classification rules that prioritize specific types of traffic within a port group for priority handling during congestion; time-based routing policies that apply different port selection algorithms at different times of day or under different load conditions; specifying relatively weighted bandwidth allocation parameters among ports within the same group; and congestion thresholds that trigger adaptive behavior within a port group, such as initiating alternative routes when the queue depth exceeds a certain value. Furthermore, rules may specify monitoring requirements, reporting thresholds, or tagging behaviors to be applied to packets routed to a specific port group. In some respects, rules or actions can be updated based on network asymmetric information received via BGP, enabling the system to dynamically adapt to changing network conditions.

[0108] In some respects, the multipath data structure 346 can be implemented as a hash table, where incoming packets are hashed (based on header information such as source / destination addresses and ports) to select a specific entry. The selected entry can point to the corresponding port group used for packet forwarding. By changing the distribution of entries pointing to different port groups, network devices can obtain a desired traffic allocation ratio.

[0109] It should be noted that while multipath data structure 346 represents one implementation of a network service distribution strategy that distributes network packets among port groups based on network parameters, similar weighted distribution can be achieved using other algorithms or functions. For example, a credit-based allocation system can assign different credit pools to different port groups and deduct credits when packets are forwarded; a larger credit pool results in a proportionally larger service allocation. Alternatively, a percentage-based forwarding algorithm can directly calculate the forwarding decision for each packet based on the target distribution percentage, without using a table-based approach. These alternative implementations achieve the core functionality of distributing network packets proportionally among multiple port groups based on network parameters such as network capacity.

[0110] In some aspects, port group configuration 348 can define logical groupsing of physical ports within a network device. Each port group may include one or more ports sharing common characteristics, such as connectivity to a specific network path or next-hop device. Port group configuration 348 may include data structures mapping physical port identifiers to logical group identifiers, as well as metadata about each group, such as, but not limited to, aggregated bandwidth capacity and / or operational status. In some aspects, port group configuration 348 can define asymmetric port groups, where a first port group includes a single port and a second port group includes at least two ports. Alternatively, port groups may be configured with varying numbers of ports based on network topology and routing requirements. Port group configuration 348 can establish boundaries within which adaptive routing decisions can be made and can provide a framework for implementing proportional traffic distribution, for example, provided by multipath data structure 346.

[0111] In some aspects, service distribution policy 350 includes rules and / or parameters that guide how to distribute network packets among different port groups based on network conditions. In some aspects, service distribution policy 350 may include algorithmic definitions that translate network parameters (such as available bandwidth, link state, or congestion level) into service distribution ratios. These policies can be implemented as executable code, lookup tables, or rule sets that the processing circuitry queries when determining routing behavior. In some aspects, service distribution policy 350 may specify different distribution policies for different service categories, destinations, or network scenarios. For example, service distribution policy 350 may specify that high-priority services follow one distribution pattern, while low-priority services follow another. Service distribution policy 350 may also define thresholds that trigger redistribution calculations and minimum bandwidth guarantees for some paths.

[0112] In some aspects, the congestion rate 352 stores parameters defining the relationship between the assigned traffic load and the actual path capacity for each port group. The congestion rate 352 can specify intentional over- or under-booking levels for different port groups. For example, the congestion rate 352 can instruct a particular port group to receive traffic at 133% of its actual capacity, recognizing that congestion control mechanisms will manage the excess traffic. In some aspects, the congestion rate parameter can be expressed in various formats, such as ratios (e.g., 8 / 7 indicates that the assigned traffic is 8 / 7 times the capacity), percentages, or absolute bandwidth values. Therefore, the congestion rate 352 provides the ability to leverage a fine-grained approach to traffic management beyond the binary "use / not use" decisions of traditional routing methods. In some aspects, at least one port group can be configured to receive over-booked traffic loads based on network parameters stored in the congestion rate 352, thereby generating controlled congestion that reduces overall traffic throughput by a specific amount corresponding to a reduction in network capacity.

[0113] In some respects, network parameter 354 may store information about the current network conditions that affect routing decisions. Network parameter 354 may include data structures that maintain current information about available bandwidth, congestion levels, link failures, quality of service requirements, or management weights assigned to specific network paths. The information in network parameter 354 may originate from BGP updates, direct measurements, internal telemetry, or management configurations. In some respects, network parameter 354 may store link capacity information received via BGP update messages indicating link degradation or failure. For example, when the link capacity in the network degrades from 400 Gbps to 300 Gbps, this change may be reflected in network parameter 354, which may provide a basis for adjusting multipath data structure 346 and congestion rate 352.

[0114] In some respects, BGP provides indications of network path degradation and capacity information through several extensions and mechanisms. While the underlying BGP protocol may not directly convey path quality metrics, BGP extensions can handle additional capacity-related information in various ways. For example, the BGP Link State (BGP-LS) extension allows BGP to distribute link-state information collected by Interior Gateway Protocols (IGPs) such as Open Shortest Path First (OSPF) or Intermediate System to Intermediate System (IS-IS), including metrics on link bandwidth, utilization, and latency. Furthermore, one or more BGP attributes, such as Multi-Exit Discriminators (MEDs) and communities (both standard and extended), can convey performance information.

[0115] Other BGP-related mechanisms that can provide network parameter information include: BGP Monitoring Protocol (BMP), which provides a method for monitoring BGP sessions and collecting routing information for analysis; FlowSpec, which can be used to route services based on performance considerations; and Performance Routing (PfR) or Optimized Edge Routing (OER), which can use BGP to reroute services based on performance metrics such as latency, jitter, and packet loss.

[0116] In some respects, network parameters (e.g., network parameter 354) can be updated as conditions change, providing real-time input for service distribution calculations. In other respects, network parameter 354 can include various types of information that influence routing decisions. Available bandwidth information can indicate the current capacity of various network links or paths, enabling network devices to distribute services proportionally. Congestion levels can be measured at various points in the network, enabling devices to route services out of congested areas. Link failure information can indicate that network links are fully or partially degraded, requiring service redistribution. Quality of service requirements can specify minimum performance guarantees for different traffic categories, affecting how traffic is distributed across available paths. Management weights can be assigned to specific network paths based on policy considerations such as cost, security, or performance preferences.

[0117] Therefore, when a network device receives information indicating a change in network capacity (e.g., via BGP update), this information is stored in network parameter 354. The processing circuitry (e.g., Figure 3A and Figure 3BThe processing circuitry 318 can query the service distribution policy 350 to determine how services should be redistributed based on updated network parameters. The processing circuitry 318 can then calculate the appropriate service allocation ratio and update the multipath data structure 346. Port group configuration 348 and congestion rate 352 can inform these calculations by providing information about available port groups and expected overbooking levels. By maintaining current information about network status, port grouping, and service distribution policies, the memory 320 enables network devices to make intelligent routing decisions that optimize bandwidth utilization while avoiding uncontrolled congestion in complex, asymmetric network topologies.

[0118] In some respects, memory 320 can also store historical data about network performance, which can be used to inform predictive routing decisions. Memory 320 can also maintain multiple versions of the multipath data structure for different destination prefixes, allowing for destination-specific routing strategies. Furthermore, memory 320 can store configuration parameters for a congestion control mechanism that works in conjunction with weighted adaptive routing to manage traffic flows during controlled overbooking scenarios.

[0119] Now for reference Figure 4A Examples of a weighted adaptive multipath routing system 400a are illustrated according to various aspects of this disclosure. In some aspects, the weighted adaptive multipath routing system 400a can implement non-binary traffic distribution and congestion management methods that overcome the limitations associated with traditional ECMP routing systems. The weighted adaptive multipath routing system 400a may include multiple functional components capable of proportionally distributing traffic among port groups based on network parameters. In some aspects, the weighted adaptive multipath routing system 400a can, for example... Figures 3A-3C The described interconnect device is implemented within the device.

[0120] In some aspects, inbound network traffic 404 includes data packets arriving at the network device via one or more ingress ports. Inbound network traffic 404 can originate from various hosts, NICs, or upstream network switches, and may include multiple traffic flows destined for different network addresses or prefixes. The weighted adaptive multipath routing system 400a may include a traffic distribution controller 406 configured to coordinate the allocation of inbound network packets among multiple candidate paths or port groups. In some aspects, the traffic distribution controller 406 implements control plane functions that process network parameters and adjust traffic distribution to optimize network utilization, especially in scenarios involving network link degradation or partial failures. Instead of implementing a binary pruning decision of either fully utilizing or completely avoiding a particular link, the traffic distribution controller 406 can enable partial, proportional traffic distribution, thus efficiently utilizing available network capacity.

[0121] In some aspects, service distribution policy 408 provides rules and configurations to guide service distribution controller 406 in allocating services among different port groups. Service distribution policy 408 can define target proportions, minimum bandwidth guarantees, overbooking parameters, or weighting factors for each port group. In some implementations, service distribution policy 408 can be stored in memory (such as...). Figure 3C The service distribution policy 408 can be periodically updated based on detected or announced changes in network capacity, as shown in memory 320.

[0122] The weighted adaptive multipath routing system 400a may include network parameters 410 representing real-time information about the current state of the network. Network parameters 410 may include, but are not limited to, information about link and / or path bandwidth, link and / or path failures, congestion levels, or administrative weights assigned to specific paths. In some respects, network parameters 410 may originate from external routing protocols (such as border gateway protocols), internal telemetry systems, or direct measurements. The weighted adaptive multipath routing system 400a can utilize network parameters 410 to modify the weighted assignment among various paths, thereby ensuring that traffic allocation is consistent with the actual available capacity of each route.

[0123] In some respects, the path capacity indicator 412 provides information about the available or reduced bandwidth on a particular network path. For example, the path capacity indicator 412 may indicate that a link has been reduced from full capacity (e.g., 4 × 100 Gbps) to partial capacity (e.g., reduced to 3 × 100 Gbps due to a single link failure). The path capacity indicator 412 enables the service distribution controller 406 to make proportional service reduction decisions, rather than binary pruning decisions.

[0124] In some respects, the weighted adaptive multipath routing system 400a may include multiple weighted traffic groups 414a-414n, where each group corresponds to a set of egress ports available for packet forwarding. Unlike traditional equal-cost multipath routing methods that distribute traffic evenly across all potential paths, each weighted traffic group (e.g., 414a) may be allocated a portion of network traffic in proportion to its capacity or other policy constraints.

[0125] like Figure 4A As shown, weighted traffic group 414a has a port configuration represented as [X, X, 0, N], indicating which ports within the port group are active. Weighted traffic group 414n has a configuration of [0, 0, Y, N], representing a different set of active ports. This notation indicates that different physical ports can be included in different port groups, thereby allowing flexible traffic allocation among the available ports of the network device.

[0126] In some respects, the group bandwidth and congestion rate parameters 416a-416n define the service allocation characteristics for each weighted service group 414a-414n, including how much service each group should carry and whether the group is intentionally over-booked. For example, the first port group might be configured to receive more service than its physical capacity can handle, thus creating a controlled congestion scenario. By intentionally over-booking some port groups while under-booking others, the system can adhere to global bandwidth usage consistent with actual network conditions.

[0127] The weighted adaptive multipath routing system 400a may include a congestion control module 418 configured to manage traffic flows through over-subscribed ports or groups of ports. When a group of ports receives traffic exceeding its physical transmission capacity, the congestion control module 418 may apply one or more congestion management techniques to ensure appropriate restraint of the excess traffic. Such techniques may include, but are not limited to, explicit congestion notification (ECN) marking, controlled packet dropping, and queue depth threshold management. These mechanisms ensure partial, non-binary throughput reduction on paths that have lost some capacity, rather than completely disabling such paths.

[0128] In some aspects, the congestion-based rate adjustment parameter 420 can provide real-time or near-real-time signals that inform dynamic service distribution adjustments. These signals may include credit-based flow control metrics, ECN feedback, queue depth indicators, or other congestion measures that enable the congestion control module 418 and the service distribution controller 406 to fine-tune service allocation in response to actual network conditions. In some implementations, these parameters may be fed back into the service distribution policy 408 to create a dynamic control loop that continuously optimizes service distribution.

[0129] In some respects, the weighted adaptive multipath routing system 400a also includes an adaptive routing engine 422, which is configured to select a specific physical port for packet forwarding once a packet is assigned to a port group. The adaptive routing engine 422 can implement various selection algorithms, including but not limited to hashing, round-robin distribution, or real-time queue occupancy evaluation, for distributing traffic among ports within a single port group. Figure 4A As shown, the adaptive routing engine 422 routes packets designated as PX through the appropriate physical port associated with the assigned port group, and similarly routes packets designated as PY through the physical port associated with their respective port groups.

[0130] In some respects, outgoing network traffic 424 represents data flowing from network devices to downstream switches or the final destination after allocation and congestion control. When network packets reach this stage, the forwarding path has already been determined and shaped according to the weighted routing method described herein. In some respects, the bandwidth utilization of outgoing traffic can be optimized without being limited by binary pruning decisions.

[0131] During operation, the weighted adaptive multipath routing system 400a processes incoming network traffic 404 with reference to both service distribution policy 408 and network parameters 410 to determine packet distribution among multiple candidate paths. Service distribution controller 406 can allocate service flows among weighted service packets 414a-414n. In some aspects, service distribution controller 406 can allocate service flows among weighted service packets 414a-414n based on associated group bandwidth and congestion rate parameters 416a-416n. When the path capacity indicator 412 associated with network parameter 410 indicates local link degradation, congestion control module 418 can ensure that traffic overbooked on paths is properly managed. In some aspects, when congestion control is executed and / or configured according to one or more congestion control policies, congestion control module 418 can consider congestion-based rate adjustment parameters 420. In some respects, the adaptive routing engine 422 can select a specific egress port within each assigned port group, thereby generating outgoing network service 424 that utilizes available bandwidth. In other respects, the adaptive routing engine 422 can select a specific egress port within each assigned port group, thereby generating outgoing network service 424 that optimally utilizes available bandwidth without requiring binary link pruning.

[0132] In some respects, the weighted adaptive multipath routing system 400a can be implemented as a combination of hardware components (such as ASICs, FPGAs, or other integrated circuits), firmware, and / or software executing on one or more processing circuits. The functionality described herein can be distributed across network devices (such as reference ciphers). Figures 3A-3C On multiple components of the described interconnected device.

[0133] Now for reference Figure 4B According to various aspects of this disclosure, an exemplary embodiment of a weighted adaptive multipath routing system 400b is illustrated. Figure 4B This describes the configuration of a weighted adaptive multipath routing system 400a when path degradation is absent in the network, illustrating the balanced distribution of network traffic among multiple port groups with equal capacity. In some aspects, as previously referenced... Figure 4AAs stated above, incoming network service 404 enters the network device. Network parameter 410 indicates the current network status, which in this example indicates that all paths can operate at full capacity (path 0 = 400 Gbps, path 1 = 400 Gbps), as indicated by path capacity indicator 412. Therefore, network parameter 410 indicates a network status in which there is no degradation or local link failure.

[0134] The service distribution controller 406 implements a service distribution policy 408b, which leverages multiple data structures to determine how incoming packets should be forwarded. In some aspects, the service distribution policy 408b includes an LPM module 426, a multipath data structure 428, and an adaptive routing group assignment data structure 432. The LPM module 426 can be configured to perform a prefix-based lookup based on the packet's destination address. When a packet enters the network device, the LPM module 426 identifies the most specific network prefix that matches the packet's destination IP address. This LPM operation provides results pointing to the multipath data structure, enabling subsequent routing decisions.

[0135] The multipath data structure 428 may include entries (rule / action_0, rule / action_1, ..., rule / action_N) defining specific forwarding actions associated with each potential result of an ECMP table lookup. Each rule or action may identify a corresponding port group configuration and may include information about which physical ports belong to each group, quality of service parameters, or other forwarding attributes.

[0136] In some respects, the multipath data structure 428 is implemented as an ECMP table 430, which includes multiple entries, as further illustrated in ECMP table 430b. Each entry in ECMP table 430 may include an entry identifier (e.g., 0, 1, 2, 3) and a corresponding path identifier (e.g., path...). A ,path B The associated port group is specified (e.g., group 0, group 1). As shown in ECMP Table 430b, entries 0 and 1 map to paths. A Group 0, while entries 2 and 3 are mapped to paths. B Therefore, two entries (representing approximately 50% of the traffic) are routed to Group 0, while two entries (representing approximately 50% of the traffic) are routed to Group 1. This distribution can be predetermined based on network topology, management policies, or other factors, and can be dynamically adjusted as network conditions change.

[0137] In some respects, the adaptive routing group assignment data structure 432 maps selected rules / actions to specific port groups (AR_group_0, AR_group_1, ..., AR_group_N). This mapping creates logical packets for physical ports, serving as candidates for packet forwarding. As shown in the figure, AR_group_0 corresponds to a port configuration of [1, 1, 0, 0], indicating that ports P0 and P1 are included in this group, while AR_group_1 corresponds to a configuration of [0, 0, 1, 1], indicating that ports P2 and P3 are included in this group. After adaptive routing group assignment, packets are directed to specific weighted traffic packets 414a and 414n. Figure 4B As depicted, the port configuration of group 0 (414a) is [1,1,0,0], and the combined bandwidth capacity is 400 Gbps, while the port configuration of group 1 (414n) is [0,0,1,1], and the bandwidth capacity is also 400 Gbps.

[0138] Once a packet is assigned to a specific port group, the adaptive routing engine 422 selects a specific port within that group for packet forwarding. As shown in 424, the network device includes four (or more) physical ports (P0: 200 Gbps, P1: 200 Gbps, P2: 200 Gbps, P3: 200 Gbps), each with a capacity of 200 Gbps, for a total forwarding bandwidth of 800 Gbps across all ports.

[0139] In some aspects, when a packet arrives, its destination address is looked up via LPM module 426, generating a pointer to ECMP table 430b. An entry in ECMP table 430b can be selected (e.g., based on a hash of the packet's header field), determining whether the packet will be forwarded through group 0 or group 1. In this path-degradation-free balanced configuration, approximately 50% of traffic is routed to group 0 (using ports P0 and P1), and approximately 50% is routed to group 1 (using ports P2 and P3). This balanced distribution among equal-capacity port groups demonstrates the operation of the weighted adaptive multipath routing system 400b under optimal network conditions. When network conditions change (e.g., when path degradation occurs), the weighted adaptive multipath routing system 400b can dynamically redistribute traffic by modifying selected entries in ECMP table 430b and adjusting the proportion of entries allocated to each port group to reflect actual available capacity, as previously referenced. Figure 4A As stated above. It should be understood that, although Figure 4B The illustration shows a specific configuration with four ECMP entries and two port groups (each port group containing two physical ports), but the principles described herein can be applied to configurations with different numbers of ECMP entries, port groups, or physical ports without departing from the scope of this disclosure.

[0140] Now for reference Figure 4C According to various aspects of this disclosure, exemplary embodiments of a weighted adaptive multipath routing system 400c are illustrated. Figure 4C The configuration of the weighted adaptive multipath routing system 400a is described when path degradation exists in the network. Therefore, as Figure 4C As described, the weighted adaptive multipath routing system 400c can adaptively redistribute network services to accommodate capacity reduction on one or more network paths.

[0141] In some cases, incoming network services return a 404 error to the network device, as previously mentioned in the reference. Figure 4A and Figure 4B The network parameter 410 indicates the current network condition, which in this example indicates that path degradation has occurred. Specifically, as shown in the path capacity indicator 412, the path... B Maintain its full capacity of 400 Gbps, while the path A It has dropped to 300 Gbps. This indicates a network state where a local link failure or capacity reduction has affected one path but not another.

[0142] The service distribution controller 406 can implement the service distribution policy 408c, which utilizes multiple data structures to determine how to forward incoming packets when path degradation is detected. Figure 4B The configuration shown is similar. Service distribution policy 408c may include LPM module 426, multipath data structure 428 implemented as ECMP table 430c, and adaptive route group assignment data structure 432 for adaptive route group assignment.

[0143] LPM module 426 performs a prefix-based lookup of the packet destination address as previously described. However, in response to detected path degradation, the entries in the resulting ECMP table 430c are reconfigured to take path degradation into account. A Reduced capacity weighted distribution. As shown in ECMP Table 430c, ECMP Table 430c now includes eight entries, where entries 0, 1, and 2 (representing approximately 37.5% of the traffic) are mapped to paths. A Group 0, and entries 3, 4, 5, 6, and 7 (representing approximately 62.5% of the business) are mapped to paths. B And group 1. This means from Figure 4B The balanced configuration shown is a proportional adjustment, with 50% of the traffic being routed to group 0. The redistribution reflects the path... A (300 Gbps) and path BThe ratio of available bandwidth between (400 Gbps) is approximately 3:5, or 62.5% to 37.5%. This illustrates the system's ability to implement non-binary, proportional service distribution in response to partial path degradation.

[0144] In some respects, the multipath data structure 428 is functionally similar to... Figure 4B The description remains similar, although the specific actions taken can be updated to reflect the current network conditions. The adaptive routing group assignment data structure 432 maintains the mapping between the selected rules / actions and the specific adaptive routing groups (AR_group_0, AR_group_1, ..., AR_group_N).

[0145] Following adaptive routing group assignment, packets can be routed to specific weighted traffic packets 414a and 414n. In this example reflecting path degradation, group 0 (414a) maintains its port configuration of [1,1,0,0] but operates at a reduced capacity (with a combined bandwidth capacity of 300 Gbps), as reflected in the "Percentage of Bandwidth Sent to Group 0 (% BW to Group0)" and "Blocking Rate of Group 0" identifiers 416a. Similarly, group 1 (414n) maintains its port configuration of [0,0,1,1], which is now intentionally overbooked, as shown in the "Percentage of Bandwidth Sent to Group 1 (% BW to Group1)" and "Blocking Rate of Group 1" identifiers 416n, for example, in Figure 4C In the example depicted, the "percentage of bandwidth sent to Group 0 (% BW to Group 0)" might be equal to 37.5% (e.g., 800 Gbps × 37.5% = 300 Gbps), and the "percentage of bandwidth sent to Group 1 (% BW to Group 1)" might be equal to 62.5% (e.g., 800 Gbps × 62.5% = 500 Gbps). Therefore, port group 1 could be intentionally overbooked, and the congestion rate could be equal to 500 Gbps / 400 Gbps, or 5 / 4. Alternatively or additionally, the congestion rate of port group 0 could be equal to 300 Gbps / 400 Gbps, or 3 / 4.

[0146] In response to path degradation, congestion control module 418 can proactively manage traffic flows. Working in conjunction with congestion-based rate adjustment parameters 420, congestion control module 418 ensures that traffic allocated to each path remains within the actual capacity of that path, despite intentional overbooking imposed on group 1. As shown in 424, the physical ports of the network devices now reflect the path degradation status. Ports P0 and P1 each maintain a capacity of 150 Gbps in group 0 (total 300 Gbps), while ports P2 and P3 each maintain a capacity of 200 Gbps in group 1 (total 400 Gbps). Therefore, due to path degradation, the total system capacity (based on ports P0-P3) decreases from 800 Gbps to 700 Gbps.

[0147] During operation, when packets arrive under these degraded network conditions, their destination addresses are looked up via LPM module 426, generating pointers to the reconfigured ECMP table 430c. Specific entries in the ECMP table are selected to determine whether the packet will be forwarded through group 0 or group 1. In the weighted configuration adjusted for path degradation, approximately 37.5% of traffic is routed to group 0 (using ports P0 and P1), while approximately 62.5% of traffic is routed to group 1 (using ports P2 and P3). The reconfigured distribution ensures that traffic is allocated proportionally based on the actual available path capacity. Congestion control module 418 further manages any oversubscription, ensuring controlled congestion rather than unpredictable packet loss. This non-binary traffic management approach to path degradation represents an improvement over traditional adaptive routing techniques, which either continue sending excessive traffic to the degraded path (causing uncontrolled congestion) or completely avoid the degraded path (wasting remaining capacity).

[0148] It should be understood that, although Figure 4C The illustration depicts a specific configuration with eight ECMP entries and a specific allocation ratio between two port groups. However, without departing from the scope of this disclosure, the principles described herein can be applied to configurations with varying numbers of ECMP entries, port groups, physical ports, or distribution ratios. The weighted adaptive multipath routing system 400c can dynamically recalculate and implement appropriate traffic distribution ratios based on the specific nature and extent of detected path degradation. As an example, the ECMP table may include seven entries, where entries 0, 1, and 2 (representing approximately 42.9% of traffic) are mapped to paths... A Group 0, while entries 3, 4, 5, and 6 (representing approximately 57.1% of the business) are mapped to paths. B And group 1. This type of redistribution reflects the path A (300Gbps) and path BThe ratio of available bandwidth between (400 Gbps) is approximately 3:4, or 57.1% to 42.9%. The percentage of bandwidth sent to Group 0 (% BW to Group 0) can be equal to 42.9% (e.g., 800 Gbps × 42.9% = 342.9 Gbps), and the percentage of bandwidth sent to Group 1 (% BW to Group 1) can be equal to 57.1% (e.g., 800 Gbps × 7.1% = 457.1 Gbps). Therefore, port groups 0 and 1 can be intentionally over-booked, and the congestion rate of port group 0 can be equal to 342.9 Gbps / 400 Gbps, while the congestion rate of port group 1 can be equal to 457.1 Gbps / 40 Gbps. Therefore, the congestion control module 418 can perform rate limiting on both port groups 0 and 1. Therefore, in some respects, the group bandwidth and blocking rate parameters 416a-416b and the congestion-based rate adjustment parameter 420 may be the result of the service distribution policy 408c, and / or may drive or otherwise guide the service distribution policy 408c, wherein the service distribution policy 408c may be configured based on the group bandwidth and blocking rate parameters 416a-416b and the congestion-based rate adjustment parameter 420.

[0149] Now for reference Figure 4D An exemplary embodiment of a weighted adaptive multipath routing system 400d is illustrated in various aspects of this disclosure. Figure 4D The specific configuration of the weighted adaptive multipath routing system 400a is described, where there is no path degradation in the network, but services are still intentionally distributed asymmetrically among multiple port groups with equal capacity. In some aspects, inbound network services 404 enter the network device, as previously referenced. Figures 4A-4C The network parameter 410 indicates the current network status, which in this example depicts all paths operating at full capacity (paths...). A =400 Gbps, path B =400Gbps), as indicated by path capacity indicator 412. This indicates a network state without degradation or partial link failures, consistent with the reference. Figure 4B Similar to the above.

[0150] The service distribution controller 406 implements a service distribution policy 408d, which utilizes multiple data structures to determine how incoming packets should be forwarded. In the example shown, service distribution policy 408d includes an LPM module, a multipath data structure 428, and an adaptive route group assignment data structure 432 for adaptive route group assignment. Upon receiving a packet, the LPM module 426 performs a prefix-based lookup for the packet's destination address. This LPM operation provides a result pointing to a multipath data structure, which can be implemented as a multipath data architecture 428, an example of which is an ECMP table 430 including multiple entries (as shown in ECMP table 430d).

[0151] and Figure 4B Compared to the balanced configuration shown, ECMP table 430d is configured to achieve intentional asymmetric distribution even when all paths are running at full capacity. As shown in ECMP table 430d, entry 0 maps to path... A Group 0, while entries 1, 2, and 3 are mapped to paths. B It is associated with Group 1. This configuration directs approximately 25% of network traffic to Group 0 and approximately 75% of traffic to Group 1.

[0152] Following the LPM operation, a specific entry in ECMP table 430d is selected (e.g., based on a hash of the packet's header fields), which determines the rule / action to be applied. The selected rule / action can be mapped to a specific adaptive routing group via adaptive routing group assignment data structure 432, which includes entries (AR_group_0, AR_group_1, ..., AR_group_N) defining logical packets for physical ports.

[0153] As shown in the figure, weighted traffic packet 414a corresponds to group 0 with port configuration of [1,0,0,0], indicating that only port P0 is included in this group. This single-port configuration provides a bandwidth capacity of 200 Gbps. Conversely, weighted traffic packet 414n corresponds to group 1 with port configuration of [0,1,1,1], indicating that ports P1, P2, and P3 are included in this group, thus providing a combined bandwidth capacity of 600 Gbps.

[0154] In some respects, the weighted adaptive multipath routing system 400d intentionally allocates approximately 25% of traffic to port groups with 25% of the total port capacity (Group 0, with 200 Gbps out of a total of 800 Gbps), while approximately 75% of traffic is allocated to port groups with 75% of the total port capacity (Group 1, with 600 Gbps out of a total of 800 Gbps). This proportional allocation ensures that each port group receives traffic commensurate with its capacity, thereby achieving balanced utilization across all ports in the case of asymmetric packetization.

[0155] Once a packet is assigned to a specific port group, the adaptive routing engine 422 selects a specific port within that group for packet forwarding. As shown in 424, the network device includes four physical ports (P0: 200 Gbps, P1: 200 Gbps, P2: 200 Gbps, P3: 200 Gbps), each with a capacity of 200 Gbps, for a total forwarding bandwidth of 800 Gbps across all ports.

[0156] During operation, packets destined for Group 0 (via a single entry in ECMP table 430d mapped to Group 0) are forwarded through port P0, while packets destined for Group 1 (via three entries in ECMP table 430d mapped to Group 1) are distributed between ports P1, P2, and P3 according to an adaptive routing algorithm. This configuration demonstrates the flexibility of the Weighted Adaptive Multipath Routing System 400d in implementing various service distribution strategies, even when all network paths are operating at full capacity.

[0157] It should be understood that Figure 4D The configuration shown represents one possible implementation of weighted adaptive multipath routing in a non-degraded network environment. Without departing from the scope of this disclosure, the principles described herein can be applied to configurations with different numbers of ECMP entries, port groups or physical ports, and different service distribution ratios. Furthermore, in response to changing network conditions or management policies, the system can be adapted to different configurations (such as...) Figure 4B , Figure 4C and Figure 4D The configuration shown can be dynamically switched between different configurations.

[0158] Now for reference Figure 4E An exemplary embodiment of the weighted adaptive multipath routing system 400e is illustrated in various aspects of this disclosure. Figure 4E The configuration of the weighted adaptive multipath routing system 400a is depicted, demonstrating its operation in an asymmetric port group configuration with path degradation, and illustrating how the weighted adaptive multipath routing system 400e dynamically adjusts service distribution to accommodate capacity reduction on one or more network paths.

[0159] In some cases, incoming network services return a 404 error to the network device, as previously mentioned in the reference. Figures 4A-4D The network parameter 410 indicates the current network condition, which in this example indicates that path degradation has occurred. Specifically, as indicated by the path capacity indicator 412, the path... A Maintain its full capacity of 200 Gbps, while the path BThe speed has been downgraded to 500 Gbps. This indicates a network condition where a local link failure or capacity reduction has affected one path but not another.

[0160] The service distribution controller 406 implements service distribution policy 408e, which utilizes multiple data structures to determine how incoming packets should be forwarded in the event of detected path degradation and existing asymmetric port group configurations. Figure 4B-4D The configuration shown is similar, with service distribution policy 408e including LPM module 426, multipath data structure 428, and adaptive route group assignment data structure 432 for adaptive route group assignment.

[0161] In response to detected path degradation, the entries in ECMP Table 430e have been reconfigured to take into account asymmetric port group configurations and paths. B Reduced capacity weighted distribution. As shown in ECMP Table 430e, ECMP Table 430e now includes seven entries (0-6), where entry 0 (representing approximately 28.6% of traffic) maps to path 0 and group 0, while entries 2 through 6 (representing approximately 71.4% of traffic) map to path 0. B And various instances of group 1.

[0162] The weighted distribution representative Figure 4D The configuration adjustment shown involves 25% of traffic being routed to group 0 and 75% to group 1. The new distribution ratio is approximately 28.6% to 71.4%, reflecting the system's adaptive response to path degradation, thereby ensuring that traffic allocation is consistent with the actual available capacity between asymmetric port groups. After adaptive routing group assignment, packets are routed to specific weighted traffic packets 414a and 414n. For example, group 0 (414a) maintains its port configuration of [1,0,0,0], corresponding to a bandwidth identifier of 200 Gbps, while group 1 (414n) maintains its port configuration of [0,1,1,1] but now operates at a reduced capacity of 500 Gbps due to path degradation.

[0163] The identifiers 416a, "Percentage of Bandwidth to Group 0 (% BW to Group 0)" and "Blocking Rate of Group 0," indicate how traffic is allocated proportionally to Group 0, while the corresponding identifier 416n for Group 1 reflects its allocation. These parameters demonstrate that despite asymmetric port group configurations and path degradation, traffic distribution remains consistent with actual available capacity. "Percentage of Bandwidth to Group 0 (% BW to Group 0)" can equal 28.6% (e.g., 800 Gbps × 28.6% = 228.8 Gbps), and "Percentage of Bandwidth to Group 1 (% BW to Group 1)" can equal 71.4% (e.g., 800 Gbps × 71.4% = 571.1 Gbps). Therefore, port group 0 can be intentionally over-booked, and the blocking rate of port group 0 can equal 228.8 Gbps / 200 Gbps, while the blocking rate of port group 1 can equal 571.1 Gbps / 600 Gbps. In some respects, the congestion control module 418 can perform rate limiting on both port group 0 and port group 1.

[0164] In response to path degradation, the congestion control module 418 actively participates in managing traffic flow. Working in conjunction with the congestion-based rate adjustment parameter 420, the congestion control module 418 ensures that the traffic allocated to each path remains within the actual capacity of that path.

[0165] As shown in Figure 424, the physical ports of the network devices now reflect both asymmetric configuration and path degradation. Port P0 maintains its 200 Gbps capacity for group 0, while ports P1, P2, and P3 now each operate at 166.66 Gbps (a decrease from their initial 200 Gbps capacity), resulting in a total bandwidth capacity of 500 Gbps in group 1. Therefore, due to path degradation, the total system capacity has decreased from 800 Gbps to 700 Gbps.

[0166] During operation, when a packet arrives under degraded network conditions, its destination address is looked up via LPM module 426 to obtain a pointer to the reconfigured ECMP table 430e. A specific entry in the ECMP table is selected to determine whether the packet will be forwarded through group 0 or group 1. In this weighted configuration that adjusts for path degradation in an asymmetric setup, approximately 28.6% of traffic is routed to group 0 (using port P0), while approximately 71.4% of traffic is routed to group 1 (using ports P1, P2, and P3).

[0167] Once a packet is assigned to a specific port group, the adaptive routing engine 422 selects a specific port within that group for packet forwarding. For packets assigned to group 0, the selection is simple and straightforward since only one port (P0) is available. For packets assigned to group 1, the adaptive routing engine 422 distributes the service among ports P1, P2, and P3 according to an adaptive routing algorithm, while also considering the reduced capacity.

[0168] The reconfigured distribution ensures that services are allocated proportionally based on the actual available path capacity, while maintaining an asymmetric port group configuration. The congestion control module 418 further manages service flows to prevent uncontrolled congestion, thus implementing a non-binary service management approach that represents an improvement over traditional adaptive routing techniques.

[0169] It should be understood that, although Figure 4E The illustration depicts a specific configuration with seven ECMP entries and a specific distribution ratio between two asymmetric port groups under path degradation conditions. However, the principles described herein can be applied to configurations with different numbers of ECMP entries, port groups, physical ports, or distribution ratios without departing from the scope of this disclosure. The weighted adaptive multipath routing system 400e can dynamically recalculate and implement appropriate service distribution ratios based on the specific nature and degree of detected path degradation, while adapting to various port group configurations.

[0170] For example, an ECMP table may include eight entries, where entries 0, 1, and 2 (representing approximately 37.5% of the business) are mapped to paths. A Group 0, while entries 3, 4, 5, 6, and 7 (representing approximately 62.5% of the business) are mapped to paths. B And group 1. This type of redistribution reflects the available bandwidth path. B The ratio (e.g., 500 Gbps) is approximately 5:3, or 62.5% to 37.5%. The "percentage of bandwidth sent to Group 0 (% BW to Group 0)" can be equal to 37.5% (e.g., 800 Gbps × 37.5% = 300 Gbps), and the "percentage of bandwidth sent to Group 1 (% BW to Group 1)" can be equal to 62.5% (e.g., 800 Gbps × 62.5% = 500 Gbps). Therefore, port group 0 can be intentionally over-booked, and the congestion rate of port group 0 can be equal to 300 Gbps / 200 Gbps, while the congestion rate of port group 1 can be equal to 500 Gbps / 600 Gbps. Therefore, the congestion control module 418 can impose rate limiting on port group 0. In some respects, the congestion rate can be associated with the new network capacity and the old network capacity (e.g., 700 Gbps / 800 Gbps = 7 / 8).

[0171] In some respects, group bandwidth and blocking rate parameters 416a-416b and congestion-based rate adjustment parameters 420 may be the result of service distribution policy 408c and / or may drive or otherwise guide service distribution policy 408c, wherein service distribution policy 408c may be configured based on group bandwidth and blocking rate parameters 416a-416b and congestion-based rate adjustment parameters 420.

[0172] Now refer to Appendix Figure 5A-6 The methods according to various aspects of this disclosure are described. Such methods may be derived from, for example, references to... Figure 1 -4 describes one or more circuits for execution. In some examples, one or more circuits include hardware (e.g., processing circuitry, logic, queues, memory) or a combination of hardware and software that implements the weighted adaptive multipath routing functionality described herein. As will be understood, one or more circuits may be included in interconnect device 102 and correspond to or relate to 302, 304, 318 and / or 320.

[0173] Now for reference Figure 5A The flowchart illustrates a method 500 for weighted adaptive multipath routing according to various aspects of this disclosure. Method 500 describes a high-level process for distributing non-binary services among multiple port groups based on network parameters.

[0174] Method 500 begins at the start of box 502, where references Figure 1-3C The described network device (such as interconnect device 102) initializes its routing functionality. In some aspects, this initialization may involve: establishing a data structure for the routing table in memory 320, configuring port groups via port group manager 342, and establishing initial service distribution parameters stored in memory 320 as service distribution policy 350.

[0175] At box 504, the network device receives incoming network traffic. This incoming traffic may include data packets arriving through ports 302a-302n of interconnect device 102. The packets may be destined for various network addresses or prefixes and may enter the switching hardware 304 for initial processing.

[0176] Proceeding to box 506, the network device obtains network parameters indicating path capacity or other network conditions. These parameters may be received via a network protocol (such as BGP) and processed by the network state processor 332 of the processing circuitry system 318. The processed network parameters can then be stored as network parameters 354 in memory 320. In some aspects, the queue monitor 308 may also provide internal telemetry data about congestion levels, which can inform routing decisions.

[0177] At block 508, the network device determines a weighted service distribution strategy based on the obtained network parameters. A portion of block 508 may involve the service distribution controller 330 calculating an appropriate service distribution ratio and querying the blocking rate strategy generator 344 to determine a reasonable service distribution ratio for different port groups. The resulting strategy may be stored as a service distribution strategy 350 in memory 320.

[0178] Moving to box 510, the network device allocates packets to weighted adaptive routing groups based on a weighted traffic distribution strategy. This allocation may involve: switching hardware 304 performing LPM operations on the packet destination address, querying multipath data structures 310 (such as ECMP tables), and routing packets to specific port groups according to a determined distribution ratio. A multipath data structure generator 334 within processing circuitry 318 can update the multipath data structures 346 stored in memory 320 to reflect the current network conditions, thereby ensuring appropriate traffic allocation.

[0179] At box 512, the network device applies adaptive routing logic to select a specific output port within the selected routing group. A portion of box 512 may involve: the adaptive routing engine 314 obtaining port group assignments from the previous box and determining the exact physical port through which each packet will be forwarded. The adaptive routing engine 314 may utilize information from the queue monitor 308 to make informed port selection decisions within the group.

[0180] Proceeding to box 514, the network device forwards outgoing network traffic packets from the selected output port. At this stage, packets leave the network device through physical ports 302a-302n as defined in the preceding boxes. The congestion control manager 316 assists in this process, particularly for port groups experiencing controlled congestion, ensuring appropriate packet handling according to the congestion control configuration defined by the congestion control configuration / policy component 336.

[0181] Method 500 ends at closing box 516. In some aspects, method 500 can continue operating as new packets arrive at the network device. The boxes can be repeated for each packet or group of packets processed by the device, and network parameters and service distribution policies are continuously updated as conditions change.

[0182] By using Figures 3A-3C The components described herein implement method 500, and interconnect device 102 can perform proportional service distribution on multiple paths based on its actual available capacity, thereby providing improvements in network utilization and performance compared to traditional routing methods that make binary include / exclude decisions about available paths.

[0183] Now for reference Figure 5BThe flowchart illustrates method 508 for determining a weighted service distribution strategy based on network parameters, according to various aspects of this disclosure. Method 508 provides... Figure 5A The detailed extension of midframe 508 illustrates the specific operations performed to establish a weighted traffic distribution strategy that optimally distributes network traffic across multiple paths based on their available capacity.

[0184] Method 508 begins at start box 518, which can be initiated when the service distribution controller 330 of the processing circuit system 318 receives an indication that the network conditions have changed and the service distribution parameters need to be recalculated.

[0185] At block 520, the network device receives network parameter updates. At least a portion of block 520 may be executed by a network state processor 332 within the processing circuitry 318, which receives and processes updates from external protocols such as BGP. These updates may indicate changes in network topology, link status, or bandwidth availability. The network state processor 332 may extract relevant information from these updates and format it for use by other components of the system. The processed information may then be stored in memory 320 as updated network parameter 354 data.

[0186] Proceeding to box 522, the network device determines the available capacity of the network path based on the received parameters. Box 522 may involve the service distribution controller 330 and the network state processor 332 analyzing the received network parameters to calculate the current available bandwidth for each potential path in the network. For example, if a BGP update indicates that a link has been downgraded from 400 Gbps to 300 Gbps, the service distribution controller 330 will identify the affected path and its new capacity constraints. This information can be temporarily stored in memory 320 for later calculations.

[0187] At box 524, the network device determines a proportional bandwidth allocation for each available path and corresponding port group based on capacity. Part of box 524 can be performed collaboratively by the traffic distribution controller 330 and the congestion rate policy generator 344. Based on the available capacity determined in the previous boxes, these components calculate an appropriate traffic distribution ratio that optimizes network utilization while avoiding uncontrolled congestion. For example, if one path has an available capacity of 400 Gbps and another path has an available capacity of 300 Gbps, the system might determine a traffic distribution ratio of 4:3 (approximately 57%:43%) between the two paths.

[0188] Proceeding to box 526, the network device determines the congestion rate (target or configuration) of a port group based on network conditions. A portion of box 526 may involve a congestion rate policy generator 344 calculating appropriate oversubscription or undersubscription levels for different port groups. The congestion rate policy generator 344 may determine, for example, that a port group should receive traffic at 120% of its actual capacity, recognizing that congestion control mechanisms will manage excess traffic. These congestion rates may be stored as congestion rates 352 in memory 320 for reference by other components of the system.

[0189] At box 528, the network device generates or updates multipath data structure entries (e.g., an ECMP table) to reflect proportional allocation and congestion rate. Part of box 528 can be performed by a multipath data structure generator 334 of the processing circuitry 318, which creates or modifies entries in a multipath data structure 346 stored in memory 320. The multipath data structure generator 334 adjusts the distribution of entries in the ECMP table to match the determined proportional bandwidth allocation. For example, if a 57%:43% traffic distribution is desired, the multipath data structure generator 334 may allocate four entries to one port group and three entries to another port group in a seven-entry ECMP table.

[0190] Moving to box 530, the network device provides the updated multipath data structure to the appropriate components for implementation. A portion of box 530 may involve processing circuitry 318 programming the updated multipath data structure into switching hardware 304, specifically into the multipath data structure 310 used by the hardware during packet processing. This ensures that subsequent packet forwarding decisions will reflect the newly calculated service distribution strategy.

[0191] This method ends at closing box 532. In some respects, method 508 can be executed periodically, or whenever a significant network change is detected. This is achieved through the use of... Figures 3A-3C The components described herein implement method 508, which allows network devices to dynamically adjust their service distribution strategies to optimize network utilization in the face of changing conditions, thereby achieving non-binary, proportional service management that improves upon traditional routing methods.

[0192] Now for reference Figure 5C The flowchart illustrates method 510 for allocating packets to a weighted adaptive routing group based on a weighted service distribution strategy, according to various aspects of this disclosure. Method 510 provides... Figure 5A The detailed extension of the middle frame 510 illustrates the operation performed when incoming network packets are assigned to the appropriate port groups according to a previously determined weighted distribution strategy.

[0193] Method 510 begins at start box 534, which can be initiated when an incoming packet is ready to be processed according to the weighted adaptive routing method. At box 536, the network device receives the incoming packet. Part of box 536 can be performed by the switching hardware 304 of interconnect device 102, which receives data packets through one or more ports 302a-302n. While awaiting processing, the incoming packet can be temporarily stored in buffer 312. In some embodiments, packets can be organized into queues 306a-306n, corresponding to their ingress ports, before further processing.

[0194] Moving to box 538, the network device performs LPM based on the packet's destination address. Part of box 538 can be performed by an LPM circuitry within switching hardware 304 that compares the destination IP address of each packet with entries in the routing table to identify the most specific matching network prefix. The LPM operation identifies the appropriate next-hop or forwarding action for each packet. In the context of weighted adaptive routing, the LPM result can point to a multipath data structure that will guide further forwarding decisions.

[0195] At box 540, the network device can select a multipath data structure based on the LPM results. A portion of box 540 may involve switching hardware 304 using the results of the LPM operation to identify and access a multipath data structure 310 (such as an ECMP table) associated with the packet's destination. The multipath data structure 310 may be maintained in hardware memory within the switching hardware 304, its contents obtained from a multipath data structure 346 stored in memory 320, and programmed by processing circuitry 318.

[0196] Moving to box 542, the network device determines entries within the selected multipath data structure based on packet-specific criteria. Part of box 542 can be performed by switching hardware 304, which uses additional packet information (such as source / destination IP addresses, port numbers, or protocol identifiers) to calculate a hash value or apply an alternative selection algorithm. The calculated value is then used to select specific entries within multipath data structure 310. The entry selection process efficiently distributes packets across multiple potential forwarding paths according to a weighting ratio established in the multipath data structure, previously configured by the multipath data structure generator 334 to reflect the desired traffic distribution ratio.

[0197] At box 544, the network device assigns packets to adaptive routing groups identified by the determined entries. A portion of box 544 may involve switching hardware 304 mapping selected entries to specific port group configurations defined by port group manager 342. Port group configurations stored as port group configurations 348 in memory 320 define which physical ports belong to each logical group. By assigning packets to specific adaptive routing groups, the network device effectively narrows down the set of egress ports that can be considered for packet forwarding, thereby enabling an earlier-established weighted traffic distribution strategy.

[0198] This method ends at closing box 546. In some respects, method 510 can be performed on each packet processed by the network device. After assigning a packet to an adaptive routing group, the network device can continue to select a specific port within that group (e.g., ...). Figure 5A (as described in middle frame 512), and then finally forward the packet.

[0199] By using Figures 3A-3C The components described herein implement method 510, which allows network devices to efficiently allocate incoming packets to appropriate port groups based on a weighted distribution strategy that reflects the actual network capacity. This approach ensures optimal utilization of available bandwidth while avoiding congestion that may result from binary routing decisions, especially in scenarios involving partially degraded links or asymmetric network topologies.

[0200] Now for reference Figure 5D The flowchart illustrates method 538 for performing LPM operations according to various aspects of this disclosure. Method 538 provides... Figure 5C The detailed extension of middle frame 538 illustrates the specific operations performed when performing LPM operations based on the packet destination address.

[0201] Method 538 begins at start box 548, which can be initiated when a packet requires LPM processing to determine its forwarding path within the weighted adaptive routing system. At box 550, the network device receives a packet with a destination address. This portion of box 550 can be performed by the switching hardware 304 of interconnect device 102, which receives packets from buffer 312 or directly from the ingress port via queues 306a-306n. The packet may have initially been received through one of ports 302a-302n and is queued for processing according to the device's packet handling pipeline.

[0202] Proceeding to box 552, the network device parses the packet header and extracts the destination IP address. Part of box 552 can be performed by packet processing circuitry within switching hardware 304, which examines the packet header structure to locate and extract the destination IP address field. Depending on the specific network protocol used, this may involve: parsing the IPv4 or IPv6 header, possibly navigating through the encapsulation layer, and isolating relevant address information for subsequent matching operations.

[0203] At box 554, the network device performs longest prefix matching on the prefixes stored in the routing table. A portion of box 554 may involve an LPM circuitry within switching hardware 304 that compares the extracted destination IP address with a set of network prefixes stored in high-speed memory, such as TCAM (Ternary Content-Addressable Memory) or other optimized data structures. Routing table entries may be populated and maintained by processing circuitry 318 based on routing protocol updates or management configurations. The LPM operation identifies the most specific (e.g., longest) prefix that matches the destination IP address of the packet, determining the appropriate forwarding behavior.

[0204] Continuing to box 556, the network device identifies the matching prefix and retrieves the associated multipath data structure pointer. Part of box 556 can be performed by switching hardware 304, which, after identifying the longest matching prefix, accesses the corresponding forwarding information. In the context of weighted adaptive routing, each prefix entry in the routing table typically points to a multipath data structure 310 (such as an ECMP table) containing multiple potential forwarding options. The multipath data structure pointer essentially serves as a reference to an appropriate set of weighted entries that will guide subsequent packet forwarding decisions.

[0205] At box 558, the network device returns a pointer to a multipath data structure for use in subsequent boxes. A portion of box 558 may involve switching hardware 304 passing the retrieved pointer to the next stage in the packet processing pipeline, where it will be used to access the multipath data structure 310 identified by LPM operations. This pointer enables the system to locate and utilize the correct set of weighted ECMP entries for the packet's destination, thereby ensuring that traffic is distributed according to the weighting policy established for that particular network prefix.

[0206] Method 538 ends at closing box 560. In some respects, the result of method 538 (a pointer to a multipath data structure) can be used as input for subsequent grouping processing steps (e.g., as...). Figure 5C The selection of multipath data structures is described in detail in box 540.

[0207] By using Figures 3A-3CThe components described in section 538 implement method 538, enabling network devices to efficiently determine the appropriate forwarding path for each packet based on its destination address. LPM operations can guide packets to a multi-path data structure that implements proportional service distribution based on network conditions and management policies. This approach ensures that packets destined for different network prefixes are subject to different weighted distribution schemes, thereby providing fine-grained control over service flows across the entire network.

[0208] Now for reference Figure 5E The flowchart illustrates method 542 for determining entries within a selected multipath data structure based on grouping-specific criteria, according to various aspects of this disclosure. Method 542 provides... Figure 5C The detailed extension of middle frame 542 illustrates the operations performed by selecting the appropriate entry from a multipath data structure, which may be necessary for weighted service distribution across port groups.

[0209] Method 542 begins at start box 562, which can be initiated when packets have undergone LPM processing and a specific multipath data structure has been identified for further processing. At box 564, the network device receives a pointer to the multipath data structure (ECMP table). Part of box 564 can be performed by the switching hardware 304 of interconnect device 102, which receives the data from the previous processing stage (such as...). Figure 5D The LPM module described herein receives this pointer. This pointer identifies a specific multipath data structure 310 within the switching hardware 304, which contains weighted entries for packet forwarding. This multipath data structure may have been pre-configured by the multipath data structure generator 334 and programmed into the switching hardware 304 based on the multipath data structure 346 stored in the memory 320.

[0210] Moving to box 566, the network device generates a packet-specific hash value based on the packet header. Part of box 566 can be performed by a hash circuitry system within the switching hardware 304, which applies a hash function to selected fields from the packet header. These fields may include, but are not limited to: source IP address, destination IP address, source port, destination port, and protocol identifier—often referred to as a "five-tuple" hash. The hash function creates a deterministic but pseudo-random value used to distribute similar packets across different forwarding paths, while ensuring that packets belonging to the same flow (with the same header fields) always choose the same path, thus maintaining flow integrity.

[0211] At box 568, the network device uses a hash value to identify entries within the multipath data structure. A portion of box 568 may involve switching hardware 304 using the generated hash value (or a portion thereof) as an index or selector to identify specific entries within the multipath data structure 310. The previously configured multipath data structure may contain entries mapped proportionally to different port groups, reflecting their expected service allocation, according to a desired service distribution strategy. By using a hash-based selection mechanism, the system ensures that services are distributed among entries based on their relative frequency in the table, thereby implementing the weighted distribution strategy established by the service distribution controller 330.

[0212] Proceeding to box 570, the network device retrieves an adaptive routing group identifier from the selected entry. Part of box 570 can be performed by switching hardware 304, which extracts the port group identifier or adaptive routing group reference associated with the selected multipath data structure entry. Each entry in multipath data structure 310 may correspond to a rule or action that identifies a port group configured by port group manager 342. The retrieved identifier may specify which physical ports' logical packets should be considered during packet forwarding.

[0213] At box 572, the network device returns an adaptive routing group identifier for use in subsequent processing steps. A portion of box 572 may involve the switching hardware 304 passing the retrieved group identifier to the next stage in the packet processing pipeline, where the group identifier can be used to assign packets to a specified port group. This identifier enables the system to correctly associate packets with logically configured ports that receive a specific proportion of network traffic, according to a weighted distribution strategy.

[0214] Method 542 ends at closing box 574. In some respects, the result of method 542 (adaptive routing group identifier) ​​can be used as input for subsequent packet processing steps, particularly for assigning packets to adaptive routing groups, such as... Figure 5C The middle frame is detailed in section 544.

[0215] By using Figures 3A-3C The components described herein implement method 542, enabling network devices to efficiently distribute weighted traffic among port groups. A hash-based entry selection process ensures that packets are distributed statistically according to proportions established in the multipath data structure, which in turn reflects a weighted distribution strategy derived from current network parameters. This approach achieves non-binary traffic management, optimizing bandwidth utilization for partially degraded links or asymmetric network topologies.

[0216] Now for reference Figure 5F The flowchart illustrates method 512 for selecting a specific output port within a selected route group by applying adaptive routing logic according to various aspects of this disclosure. Method 512 provides... Figure 5A The detailed extension of frame 512 illustrates the operation performed to select the appropriate physical egress port from within the assigned adaptive routing group, representing the final routing decision before packet forwarding.

[0217] Method 512 begins at start box 576, which can be initiated when a packet has been assigned to a specific adaptive routing group and is awaiting final port selection for forwarding. At box 578, the network device receives the packet and the adaptive routing group assignment. Part of box 578 can be performed by the adaptive routing engine 314 within the switching hardware 304 of interconnecting device 102, which receives the packet (or a reference to it) and an indication of which adaptive routing group the packet has been assigned to. The adaptive routing group assignment has been determined in previous processing stages, specifically through… Figure 5C-5E The ECMP table selection and entry determination process is described in [the document]. Adaptive routing group assignment can identify logical groups of physical ports configured by port group manager 342, from which a specific egress port must now be selected.

[0218] Moving to box 580, the network device monitors the real-time congestion status (e.g., queue occupancy, packet drop) of each port in the adaptive routing group. Part of box 580 can be performed by a queue monitor 308 within the switching hardware 304, which continuously tracks the status of queues 306a-306n associated with each physical port 302a-302n. The queue monitor 308 can collect various metrics, including current queue depth, buffer utilization, recent packet drop rate, or Explicit Congestion Notification (ECN) flags. These metrics provide real-time insight into the congestion status of each port within the assigned adaptive routing group, enabling informed port selection decisions to avoid or mitigate congestion.

[0219] At box 582, the network device determines congestion-based rate adjustment parameters. A portion of box 582 may involve a congestion control manager 316 within switching hardware 304, which evaluates congestion metrics collected by queue monitor 308 and determines whether any rate adjustment is needed. In some cases, the congestion control manager 316 may query parameters or policies established by congestion control configuration / policy component 336 or rate limiting logic 338 within processing circuitry system 318. These rate adjustment parameters can influence subsequent port selection by identifying ports experiencing severe congestion and which should be temporarily avoided or de-prioritized.

[0220] Moving to box 584, the network device selects a specific egress port within an adaptive routing group based on adaptive logic (e.g., least congested port, random, round-robin, hash-based). Part of box 584 can be performed by adaptive routing engine 314, which can apply selection algorithms or policies to select the most suitable egress port from the available egress ports in the assigned adaptive routing group. Adaptive routing engine 314 may consider congestion-based rate adjustment parameters determined in the previous box, which may favor less congested ports. Depending on the configured policy, selection may employ least congested port logic (actively selecting the port with the shortest queue), round-robin distribution (circling through available ports sequentially), random selection (for simple load balancing), or hash-based methods (for maintaining flow integrity while distributing traffic).

[0221] At box 586, the network device forwards packets to the selected output port. A portion of box 586 may involve switching hardware 304 directing packets from buffer 312 to queues 306a-306n associated with the selected physical ports 302a-302n. The packets are then queued for transmission through the selected port, becoming part of the outgoing network traffic from the device. In scenarios where congestion control is active, the congestion control manager 316 may apply additional processing, such as ECN marking or controlled dropping, based on determined congestion-based rate adjustment parameters.

[0222] This method ends at closing box 588. In some respects, method 512 can be executed for each group assigned to the adaptive routing group. By using Figures 3A-3C The components described herein implement method 512, enabling network devices to make intelligent, congestion-aware port selection decisions within the context of weighted traffic distribution established by the early processing phase. This adaptive routing approach provides an additional layer of traffic optimization, thereby ensuring efficient bandwidth utilization and minimizing congestion even within port groups that may receive different proportions of overall network traffic due to the weighted distribution strategy.

[0223] Figure 6 A method 600 for weighted adaptive multipath routing in a network device according to at least one aspect of this disclosure is described, wherein at least some concepts have been referenced. Figure 1-5F The discussion took place. In one aspect, method 600 can be derived from... Figure 1 and Figure 3A Interconnection devices 102 and / or Figures 3A-3B The processing circuit system 318 is implemented in the middle.

[0224] Method 600 may begin at start box 602 and then flow to box 604 as network packets are received. In some aspects, such as regarding Figure 3AAs described above, incoming network packets can reach one of ports 302a-302n of interconnecting device 102 and enter switching hardware 304 for processing. Furthermore, as... Figure 4A As detailed in the document, an incoming network service 404 error can initiate a weighted adaptive routing process.

[0225] Method 600 can then proceed to box 606, whereby network packets are assigned to one of the multiple port groups according to a network service distribution strategy (which distributes network packets proportionally among multiple port groups based on network parameters). In some aspects, such as Figure 4B-4E The multipath data structures shown (ECMP Tables 430b, 430c, 430d, and 430e) may contain entries pointing to different port groups in proportion to reflect the service distribution strategy. The service distribution strategy may be determined based on network parameters such as available bandwidth, link failures, and / or congestion levels, which may be communicated via network protocols (such as those related to...). Figure 3B and Figure 5B The aforementioned BGP) is received.

[0226] Method 600 can then flow to box 608, forwarding network packets through ports in that port group. In some respects, adaptive routing engine 314 can select specific ports from the assigned port group based on real-time congestion conditions monitored by queue monitor 308. As shown in Figures 4A-4E, once packets have been assigned to a specific port group (e.g., 414a or 414n), adaptive routing engine 422 can select the physical port through which to forward packets, thus completing the routing decision process. In scenarios where port groups are intentionally over-booked, such as regarding... Figure 3A and Figure 4C The congestion control manager 316 can apply congestion control mechanisms to ensure proper business management.

[0227] Method 600 can then end at box 610.

[0228] In some aspects of method 600, the network service distribution strategy includes a multipath data structure that maps different entries to different port groups in multiple port groups.

[0229] In some aspects of method 600, the multipath data structure includes an Equal Multipath (ECMP) table with multiple entries, wherein different percentages of the multiple entries are mapped to different port groups of the multiple port groups.

[0230] In some aspects of method 600, one or more circuits are also used to: perform LPM operations based on the destination address of a network packet to select the multipath data structure from a plurality of multipath data structures.

[0231] In some aspects, method 600 further includes: calculating a hash value based on information in the network packet; and selecting an entry from multiple entries in a multipath data structure based on the hash value, wherein the selected entry determines a port group among multiple port groups of the network packet.

[0232] In some aspects of method 600, each entry in the multipath data structure is associated with at least one of the rules or actions that identify the corresponding port group among the plurality of port groups.

[0233] In some aspects of method 600, the rule or action indicates which ports of the network device are included in the corresponding port group.

[0234] In some aspects of method 600, the rule or action is updated based on network asymmetric information received via BGP.

[0235] In some aspects of method 600, the multiple port groups include at least one port group configured to receive oversubscribed service load based on network parameters.

[0236] In some aspects of method 600, network parameters include available capacity information for multiple port groups; and based on this available capacity information, the proportion is determined to direct more traffic to another port group than to the at least one port group.

[0237] In some respects, method 600 also includes performing congestion control to limit traffic flow directed through at least one of the plurality of port groups.

[0238] In some aspects of method 600, congestion control is also used to: over-book at least one port in at least one of the plurality of port groups to cause controlled congestion; and to reduce total traffic throughput by a specific amount corresponding to a capacity reduction in the network.

[0239] In some aspects, method 600 also includes: receiving network status information indicating changes in network capacity; and adjusting the proportion of network packets distributed among the plurality of port groups based on the network status information.

[0240] In some aspects of method 600, the network condition information indicates a reduction in the capacity of network paths downstream of the network device.

[0241] In some aspects of method 600, network condition information is received via a BGP update message indicating at least one of a link failure or link degradation.

[0242] In some aspects of method 600, forwarding network packets through the port of the port group includes selecting the port from a plurality of available ports in the port group using at least one of adaptive routing, random selection, round-robin selection, or hash-based forwarding.

[0243] In some aspects of method 600, network parameters include at least one of the following: available bandwidth of network links; network congestion level; link failure information; quality of service requirements; or management weights assigned to network paths.

[0244] Method 600 offers beneficial technical effects, such as addressing the binary limitation in traditional routing methods by implementing proportional traffic allocation based on actual link capacity. Unlike traditional ECMP implementations, which either fully utilize specific links or completely avoid them, Method 600 allows for non-binary, granular traffic distribution that reflects actual network conditions. This is particularly relevant in scenarios involving local link degradation (such as when link capacity decreases from 400 Gbps to 300 Gbps). Figure 2B As shown, non-binary, granular service distribution enables the network to fully utilize its remaining network capacity even when links are degraded.

[0245] In some respects, method 600 can optimize bandwidth utilization in asymmetric or partially degraded network topologies by controlling the proportion of traffic sent to each available path. The network parameter-based allocation in step 606 helps ensure that traffic distribution is consistent with actual available capacity, thereby avoiding underutilization of healthy links and congestion on degraded links. This creates a technical solution that maximizes overall network throughput while maintaining predictable performance.

[0246] In some respects, Method 600 may not require hardware upgrades to existing network infrastructure, as it can leverage existing LPM, ECMP, and congestion control capabilities in current networked devices.

[0247] In view of the foregoing, it should be understood that various aspects of this disclosure provide a network device comprising one or more circuits for: receiving a network packet stream; distributing network packets of the network packet stream proportionally among a plurality of port groups based on network parameters; and forwarding the network packets through ports in the plurality of port groups. In some aspects, the one or more circuits are further configured to: adjust the proportion of the network packets distributed among the plurality of port groups in response to changes in the network parameters.

[0248] In view of the foregoing, it should be understood that various aspects of this disclosure provide a system comprising: a first network device; and a second network device connected to the first network device via a plurality of network links, wherein the first network device includes one or more circuits configured to: receive network traffic destined for the second network device; distribute the network traffic among the plurality of network links according to a service distribution strategy, the service distribution strategy allocating different proportions of the network traffic to different subsets of the plurality of network links based on capacity information associated with the plurality of network links; and adjust the different proportions in response to changes in the capacity information.

[0249] Figure 7 The diagram illustrates a block diagram of a system 700 comprising a switching circuitry system 710 (sometimes referred to as the “structure”) located between a first group 712 devices and a second group 714 devices, according to at least one embodiment. As a non-limiting example, system 700 may be implemented as a GPU-to-GPU link system (e.g., an NVLINK® GPU-to-GPU interconnect system), wherein the switching circuitry system 710 may include one or more GPU-to-GPU switches (e.g., one or more NVSWITCH™ switches). System 700 may implement other systems (e.g., be a component of such systems), such as data centers, cloud computing systems, machine learning systems (e.g., utilizing one or more neural networks), autonomous vehicles, medical imaging equipment, etc.

[0250] Each of the first group 712 and the second group 714 can be implemented as a GPU, a parallel processing unit, a central processing unit (“CPU”), a data processing unit (“DPU”), a controller, a switch, a switching circuit system, a memory device, etc. As a non-limiting example, the first group 712 has been illustrated as including several (“M*X”) devices illustrated as devices SD1-1 to SDM-X. However, group 712 can include any number of devices, including a single device. For ease of illustration, in Figure 7In the diagram, devices SD1-1 to SDM-X are illustrated as a two-dimensional array comprising "M" rows and "X" columns. The second group 714 is illustrated as comprising "Y" devices, illustrated as devices T1 to TY, but the second group 714 may include any number of devices, including a single device. Furthermore, one or more devices may be members of both groups 712 and 714. Therefore, groups 712 and 714 are not mutually exclusive and may include one or more of the same devices. Thus, in at least one embodiment, the switching circuit system 710 may allow any device in the first group 712 (SD1-1 to SDM-X) to communicate with any device in the first group 712 (SD1-1 to SDM-X) and / or any device in the second group 714 (T1 to TY). Therefore, in at least one embodiment, the switching circuit system 710 may allow any of the devices T1 to TY in the second group 714 to communicate with any of the devices T1 to TY in the second group 714 and / or any of the devices SD1-1 to SDM-X in the first group 712.

[0251] The switching circuit system 710 may include an “N” number of outbound switches OSW1 to OSWN, a predetermined number of “M*N” internal switches IS1C1 to ISMCN, signal conductors 716, and a routing block 718 for controlling the operation of the internal switches IS1C1 to ISMCN. The routing block 718 has been illustrated to include hardware 720, which may include at least one processor 722, memory 724, and one or more counters 726. In at least one embodiment, each of the one or more processors 722 may be implemented as one or more hardware state machines, one or more microprocessors, one or more microcontrollers, one or more controllers, etc. The memory 724 (e.g., one or more non-transitory processor-readable media) may be implemented, for example, using volatile memory (e.g., dynamic random access memory (“DRAM”) and / or non-volatile memory (e.g., hard disk drives, solid-state devices (“SSDs”), etc.).

[0252] Signal conductors 716 interconnect the first group 712, the second group 714, the internal switches IS1C1 to ISMCN, and the outbound switches OSW1 to OSWN. In the illustrated example, signal conductors 716 may include any number of signal conductors. Each of the signal conductors 716 may be implemented as a wire, a trace, and / or any other type of electrical conductor. As a non-limiting example, one or more of the signal conductors 716 may each be implemented as a wire-based serial short-range communication link. As another non-limiting example, one or more of the signal conductors 716 may each be implemented as a Scalable Link Interface (“SLI”).

[0253] In the illustrated embodiment, signal conductor 716 includes signal conductors 734, 740, and 742. Signal conductor 734 connects devices SD1-1 to SDM-X to internal switches IS1C1 to ISMCN. For ease of illustration, Figure 7 Only the signal conductors 734 connecting each of devices SD1-1 to SD1-X to internal switches IS1C1 to IS1CN are illustrated. In at least one embodiment, internal switches IS1C1 to IS1CN may each include a different port connected via signal conductors 734 to at least a portion of devices SD1-1 to SDM-X (e.g., connected to devices SD1-1 to SD1-X respectively). Similarly, internal switches IS2C1 to IS2CN may each include a different internal port connected via signal conductors 734 to at least a portion of devices SD1-1 to SDM-X (e.g., connected to devices SD2-1 to SD2-X respectively). Further, internal switches ISMC1 to ISMCN may each include a different internal port connected via signal conductors 734 to at least a portion of devices SD1-1 to SDM-X (e.g., connected to devices SDM-1 to SDM-X respectively).

[0254] Signal conductors 742 connect internal switches IS1C1 to ISMCN to outbound switches OSW1 to OSWN. For example, at least one signal conductor in signal conductors 742 connects each internal switch from IS1C1 to ISMC1 to outbound switch OSW1, at least one signal conductor in signal conductors 742 connects each internal switch from IS1C2 to ISMC2 to outbound switch OSW2, and at least one signal conductor in signal conductors 742 connects each internal switch from IS1CN to ISMCN to outbound switch OSWN.

[0255] Signal conductor 740 connects outbound switches OSW1 to OSWN to devices T1 to TY. Outbound switches OSW1 to OSWN may each include different ports, which are connected to at least one device among devices T1 to TY via at least one signal conductor in signal conductor 740.

[0256] Although the switching circuit system 710 has been illustrated as including internal switches IS1C1 to ISMCN, the switching circuit system 710 may include any number of internal switches, including a single internal switch. Further, the internal switches IS1C1 to ISMCN have been illustrated as a two-dimensional array comprising "M" rows and "N" columns. However, this is not required, and the internal switches IS1C1 to ISMCN can be positioned in alternative arrangements to achieve any network topology, including a three-dimensional array. One or more internal switches IS1C1 to ISMCN may be coupled to each other. For example, from the perspective of one internal switch IS1C1 to ISMCN, one or more of the other internal switches IS1C1 to ISMCN may be one of devices T1 to TY. Further, the switching circuit system 710 may be coupled to one or more switches outside the switching circuit system 710 (e.g., a switching circuit system like the switching circuit system 710 itself). For example, one or more of the devices SD1-1 to SDM-X and / or devices T1 to TY can each be implemented as an external switch.

[0257] The routing block 718 can be connected via one or more buses to each of the internal switches IS1C1 to ISMCN and / or at least a portion of the signal conductors 716. For example, one or more processors 722 and memory 724 can be connected to each other via one or more buses 728. One or more buses 728 can also connect one or more processors 722 and memory 724 to each of the internal switches IS1C1 to ISMCN and / or at least a portion of the signal conductors 716. The memory 724 (e.g., a non-transitory processor-readable medium) stores instructions 730, data 732, and firmware 752 executable by one or more processors 722, which can perform monitoring and data manipulation functions. For example, firmware 752 can instruct hardware 720 to transition one or more signal conductors 716 from an active state to an inactive state and vice versa.

[0258] Figure 8A block diagram of an example system 800 according to at least one embodiment is illustrated. In at least one embodiment, system 800 may include one or more CPUs 810 connected to one or more multi-GPU communication systems (e.g., multi-GPU communication system 802) via one or more signal conductors 812. Figure 8 In the embodiment illustrated, one or more CPUs 810 include CPUs 810A and 810B, respectively connected to the multi-GPU communication system 802 via signal conductors 812A and 812B. Figure 8 In the multi-GPU communication system 802, GPUs 808 are interconnected via at least one switch 806 and at least one signal conductor 804. In the illustrated embodiment, one or more switches 806 include switches 806A-806D, GPUs 808 include GPUs 808A-808P, and one or more signal conductors 804 include signal conductors 804A-804E.

[0259] System 800 can be characterized as an example implementation of System 700 (see [link]). Figure 7 For example, one or more CPUs 810 and / or GPUs 808 may be implemented as groups 712 and / or 714. In at least one embodiment, one or more CPUs 810 may be substantially the same as devices SD1-1 to SDM-X and / or devices T1 to TY. In at least one embodiment, GPUs 808 may be substantially the same as devices SD1-1 to SDM-X and / or devices T1 to TY. As another non-limiting example, one or more signal conductors 804 and / or one or more signal conductors 812 may be implemented as signal conductors 716. In at least one embodiment, one or more signal conductors 804 and / or one or more signal conductors 812 may be substantially the same as signal conductors 716. As yet another non-limiting example, one or more switches 806 may be implemented as internal switches IS1C1 to ISMCN and / or outbound switches OSW1 to OSWN. In at least one embodiment, one or more switches 806 may be implemented as switches IS1C1 to ISMCN (see... Figure 7 The outbound switches OSW1 to OSWN are basically the same.

[0260] As a non-limiting example, signal conductor 804 can link GPU 808 to one or more switches 806, and signal conductors 812A and 812B can link at least one of the switches 806 to one or more CPUs 810. Figure 8As illustrated, CPUs 810A and 810B can be connected to switches 806A and 806C respectively via signal conductors 812A and 812B. In at least one embodiment, one or more of the CPUs 810 can be implemented as follows: Figure 16 The CPU 1600 and GPU 808 shown in the illustration can be implemented as one or more GPUs. Figure 14 The illustration shows one or more parallel processors 1412.

[0261] The multi-GPU communication system 802 can be implemented as a mesh network, which can have a local area network topology in which infrastructure nodes or devices can be directly, dynamically, and non-hierarchically connected to other nodes and can cooperate with each other to efficiently route data. Examples of infrastructure devices may include bridges, one or more switches 806, and / or other types of infrastructure devices. The multi-GPU communication system 802 may be referred to as a GPU-to-GPU system. By way of non-limiting example, the multi-GPU communication system 802 can be implemented as a GPU-to-GPU link system (e.g., an NVLINK® GPU-to-GPU interconnect system), in which one or more switches 806 may include one or more GPU-to-GPU switches (e.g., one or more NVSWITCH™ switches).

[0262] Switch 806A is connected to GPUs 808A-808D via signal conductor 804A, switch 806B is connected to GPUs 808E-808H via signal conductor 804B, switch 806C is connected to GPUs 808I-808L via signal conductor 804C, and switch 806D is connected to GPUs 808M-808P via signal conductor 804D. Switches 806A-806D are interconnected via signal conductor 804E. During the duration of the dedicated connection, each of the one or more switches 806 can act as a connection between two endpoints within a router and / or system 800. In at least one embodiment, one or more switches of the one or more switches 806 can be implemented using a node-on-node switch architecture (e.g., one or more NVSWITCH™ switches) that connects processing units (e.g., one or more GPUs, one or more CPUs, and / or one or more other types of processors). System 800 can be used as part of another system (such as a data center) that includes hardware, network, software and / or libraries, and executes applications that perform inference, for example, by executing artificial intelligence (“AI”) or machine learning models.

[0263] The systems and methods described herein can be used, but are not limited to, non-autonomous vehicles, semi-autonomous vehicles (e.g., in one or more adaptive driver assistance systems (ADAS)), manned and unmanned robots or robotic platforms, warehouse vehicles, off-road vehicles, vehicles coupled to one or more trailers, aircraft, boats, shuttles, emergency response vehicles, motorcycles, electric or motorized bicycles, aircraft, engineering vehicles, underwater vehicles, drones, and / or other types of vehicles. The systems and methods described herein can be used in augmented reality, virtual reality, mixed reality, robotics, security and supervision, autonomous or semi-autonomous machine applications, and / or any other technological space where one or more signal conductors may have at least two distinct states consuming different amounts of power.

[0264] The systems and methods described herein can be used, but are not limited to, non-autonomous vehicles, semi-autonomous vehicles (e.g., in one or more adaptive driver assistance systems (ADAS)), manned and unmanned robots or robotic platforms, warehouse vehicles, off-road vehicles, vehicles coupled to one or more trailers, aircraft, boats, shuttles, emergency response vehicles, motorcycles, electric or motorized bicycles, aircraft, engineering vehicles, underwater vehicles, drones, and / or other types of vehicles. Furthermore, the systems and methods described herein can be used for a variety of purposes, by way of example but not limited to, machine control, machine motion, machine driving, synthetic data generation, model training, perception, augmented reality, virtual reality, mixed reality, robotics, safety and supervision, simulation and digital twins, autonomous or semi-autonomous machine applications, deep learning, environmental simulation, object or actor simulation and / or digital twins, data center processing, conversational AI, optical transport simulation (e.g., ray tracing, path tracing, etc.), collaborative content creation for 3D assets, cloud computing, web hosting services or web hosting platforms, and / or any other suitable applications.

[0265] The disclosed embodiments can comprise a variety of different systems, such as automotive systems (e.g., control systems for autonomous or semi-autonomous machines, perception systems for autonomous or semi-autonomous machines), systems implemented using robots, aviation systems, medical systems, boating systems, smart area monitoring systems, systems for performing deep learning operations, systems for performing simulation operations, systems for performing digital twin operations, systems implemented using edge devices, systems containing one or more virtual machines (VMs), systems for performing synthetic data generation operations, systems implemented at least partially in a data center, systems for performing conversational AI operations, systems for performing optical transmission simulations, systems for performing collaborative content creation for 3D assets, systems implemented at least partially using cloud computing resources, systems for implementing web hosting services (e.g., runtime for program optimization) or web hosting platforms (e.g., integrated development environments including program optimization as a service) (as an application programming interface (“API”) between two or more separate applications or systems), and other types of systems.

[0266] Data Center Figure 9 An example data center 900 according to at least one embodiment is shown. In at least one embodiment, the data center 900 includes, but is not limited to, a data center infrastructure layer 910, a framework layer 920, a software layer 930, and an application layer 940.

[0267] In at least one embodiment, such as Figure 9 As shown, the data center infrastructure layer 910 may include a resource coordinator 912, grouped computing resources 914, and node computing resources (“nodes CR”) 916(1)-916(N), where “N” represents any complete positive integer. In at least one embodiment, nodes CR 916(1)-916(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field-programmable gate arrays (“FPGAs”), data processing units (“DPUs”) in network devices, graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid-state drives or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more of nodes CR 916(1)-916(N) may be servers having one or more of the aforementioned computing resources.

[0268] In at least one embodiment, the grouped computing resources 914 may include individual groups (not shown) of node CRs housed in one or more racks, or a plurality of racks (also not shown) housed in data centers in various geographic locations. The individual groups of node CRs within the grouped computing resources 914 may include computing, networking, memory, or storage resources that can be configured or allocated to support groups of one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0269] In at least one embodiment, resource coordinator 912 may be configured or otherwise control one or more nodes CR 916(1)-916(N) and / or grouped computing resources 914. In at least one embodiment, resource coordinator 912 may include a Software Design Infrastructure (“SDI”) management entity for data center 900. In at least one embodiment, resource coordinator 912 may include hardware, software, or some combination thereof.

[0270] In at least one embodiment, such as Figure 9As shown, the framework layer 920 includes, but is not limited to, a job scheduler 932, a configuration manager 934, a resource manager 936, and a distributed file system 938. In at least one embodiment, the framework layer 920 may include a framework of software 952 supporting the software layer 930 and / or one or more applications 942 of the application layer 940. In at least one embodiment, the software 952 or application 942 may respectively include web-based service software or applications, such as services or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 920 may be, but is not limited to, a free and open-source software web application framework, such as Apache Spark™ (hereinafter referred to as "Spark") which can leverage the distributed file system 938 for large-scale data processing (e.g., "big data"). In at least one embodiment, the job scheduler 932 may include a Spark driver to facilitate the scheduling of workloads supported by the various layers of the data center 900. In at least one embodiment, the configuration manager 934 may be able to configure different layers, such as the software layer 930 and the framework layer 920 including Spark and the distributed file system 938 for supporting large-scale data processing. In at least one embodiment, resource manager 936 is capable of managing cluster or group computing resources mapped to or allocated to support distributed file system 938 and job scheduler 932. In at least one embodiment, cluster or group computing resources may include group computing resources 914 on data center infrastructure layer 910. In at least one embodiment, resource manager 936 may coordinate with resource coordinator 912 to manage these mapped or allocated computing resources.

[0271] In at least one embodiment, the software 952 included in the software layer 930 may include software used by at least a portion of the nodes CR 916(1)-916(N), the grouped computing resources 914, and / or the distributed file system 938 of the framework layer 920. One or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0272] In at least one embodiment, one or more applications 942 included in the application layer 940 may include one or more types of applications used by at least a portion of nodes CR 916(1)-916(N), grouped computing resources 914, and / or the distributed file system 938 of the framework layer 920. One or more types of applications may include, but are not limited to, CUDA applications.

[0273] In at least one embodiment, any of the configuration manager 934, resource manager 936, and resource coordinator 912 can implement any number and type of self-modification actions based on any amount and type of data acquired in any technically feasible manner. In at least one embodiment, self-modification actions can mitigate potentially poor configuration decisions by data center operators of data center 900 and can prevent underutilization and / or poor performance of the data center.

[0274] In at least one embodiment, data center 900 can be used to implement system 700 (see...). Figure 7 ) and / or System 800 (see Figure 8 For example, the first group 712 and / or the second group 714 may include one or more groups of computing resources 914 and / or one or more CRs 916(1)-916(N). In at least one embodiment, Figure 9 One or more systems described in the text are used to achieve, for example, combination. Figures 1-8 The description refers to one or more systems and / or processes of the like.

[0275] Computer-based systems The following figures present, but are not limited to, example computer-based systems that can be used to implement at least one embodiment.

[0276] Figure 10 A processing system 1000 according to at least one embodiment is illustrated. In at least one embodiment, the system 1000 includes one or more processors 1002 and one or more graphics processors 1008, and may be a single-processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 1002 or processor cores 1007. In at least one embodiment, the processing system 1000 is a processing platform incorporated within a system-on-a-chip (Sort) integrated circuit for use in mobile, handheld, or embedded devices.

[0277] In at least one embodiment, the processing system 1000 may include or be integrated into a server-based gaming platform, including a game console, mobile game console, handheld game console, or online game console, which are game and media consoles. In at least one embodiment, the processing system 1000 is a mobile phone, smartphone, tablet computing device, or mobile internet device. In at least one embodiment, the processing system 1000 may also include components coupled to or integrated into a wearable device, such as a smartwatch, smart glasses, augmented reality, or virtual reality device. In at least one embodiment, the processing system 1000 is a television or set-top box device having one or more processors 1002 and a graphical interface generated by one or more graphics processors 1008.

[0278] In at least one embodiment, each of the one or more processors 1002 includes one or more processor cores 1007 to process instructions that, when executed, perform operations against the system and user software. In at least one embodiment, each of the one or more processor cores 1007 is configured to process a specific instruction set 1009. In at least one embodiment, the instruction set 1009 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computation via Very Long Instruction Word (VLIW). In at least one embodiment, the plurality of processor cores 1007 may each process a different instruction set 1009, which may include instructions that facilitate the emulation of other instruction sets. In at least one embodiment, the processor cores 1007 may also include other processing devices, such as digital signal processors (DSPs).

[0279] In at least one embodiment, processor 1002 includes cache memory 1004. In at least one embodiment, processor 1002 may have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory is shared among various components of processor 1002. In at least one embodiment, processor 1002 also uses an external cache (e.g., a Level 3 (L3) cache or a last-level cache (LLC)) (not shown), which can be shared among processor cores 1007 using known cache coherence techniques. In at least one embodiment, processor 1002 further includes a register file 1006, which may include different types of registers (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, register file 1006 may include general-purpose registers or other registers.

[0280] In at least one embodiment, one or more processors 1002 are coupled to one or more interface buses 1010 to transmit communication signals, such as address, data, or control signals, between the processor 1002 and other components in the system 1000. In at least one embodiment, the interface bus 1010 may be a processor bus, such as a version of the Direct Media Interface (DMI) bus. In at least one embodiment, the interface bus 1010 is not limited to the DMI bus and may include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), memory buses, or other types of interface buses. In at least one embodiment, the processor 1002 includes an integrated memory controller 1016 and a platform controller hub 1030. In at least one embodiment, the memory controller 1016 facilitates communication between storage devices and other components of the processing system 1000, while the platform controller hub (PCH) 1030 provides connectivity to input / output (I / O) devices via a local I / O bus.

[0281] In at least one embodiment, storage device 1020 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase-change memory device, or a device with suitable performance for use as processor memory. In at least one embodiment, storage device 1020 may be used as system memory of processing system 1000 to store data 1022 and instructions 1021 for use when one or more processors 1002 execute applications or processes. In at least one embodiment, memory controller 1016 is also coupled to an optional external graphics processor 1012, which may communicate with one or more graphics processors 1008 of processor 1002 to perform graph and media operations. In at least one embodiment, display device 1011 may be connected to processor 1002. In at least one embodiment, display device 1011 may include one or more internal display devices, such as those in mobile electronic devices or portable computer devices, or external display devices connected via a display interface (e.g., DisplayPort). In at least one embodiment, the display device 1011 may include a head-mounted display (HMD), such as a stereoscopic display device for virtual reality (VR) or augmented reality (AR) applications.

[0282] In at least one embodiment, the platform controller hub 1030 enables peripheral devices to connect to the storage device 1020 and the processor 1002 via a high-speed I / O bus. In at least one embodiment, the I / O peripheral devices include, but are not limited to, an audio controller 1046, a network controller 1034, a firmware interface 1028, a wireless transceiver 1026, a touch sensor 1025, and a data storage device 1024 (e.g., a hard disk drive, flash memory, etc.). In at least one embodiment, the data storage device 1024 may be connected via a memory interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 1025 may include a touchscreen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 1026 may be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or LTE transceiver. In at least one embodiment, the firmware interface 1028 enables communication with the system firmware and may be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, network controller 1034 may enable network connectivity to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to interface bus 1010. In at least one embodiment, audio controller 1046 is a multi-channel high-definition audio controller. In at least one embodiment, processing system 1000 includes an optional legacy I / O controller 1040 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to processing system 1000. In at least one embodiment, platform controller hub 1030 may also be connected to one or more Universal Serial Bus (USB) controllers 1042 that connect input devices, such as a keyboard and mouse combination 1043, a camera 1044, or other USB input devices.

[0283] In at least one embodiment, instances of the memory controller 1016 and platform controller hub 1030 may be integrated into a discrete external graphics processor, such as external graphics processor 1012. In at least one embodiment, the platform controller hub 1030 and / or the memory controller 1016 may be external to one or more processors 1002. For example, in at least one embodiment, the processing system 1000 may include an external memory controller 1016 and a platform controller hub 1030, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset communicating with the processor 1002.

[0284] In at least one embodiment, the processing system 1000 can be used to implement system 700 (see [link]). Figure 7 ) and / or System 800 (see Figure 8For example, the first group 712 and / or the second group 714 may include one or more processors 1002, one or more processor cores 1007, and / or one or more graphics processors 1008. In at least one embodiment, the interface bus 1010 may be used to implement the switching circuit system 710 (see...). Figure 7 ), bus 728 and / or signal conductors 734 and 740. In at least one embodiment, Figure 10 One or more systems described in the text are used to achieve, for example, combination. Figures 1-8 The description refers to one or more systems and / or processes of the like.

[0285] Figure 11 A computer system 1100 according to at least one embodiment is illustrated. In at least one embodiment, the computer system 1100 may be a system having interconnected devices and components, a System-on-a-Chip (SoC), or some combination thereof. In at least one embodiment, the computer system 1100 is formed by a processor 1102, which may include execution units for executing instructions. In at least one embodiment, the computer system 1100 may include, but is not limited to, components such as the processor 1102, which employs execution units including logic to execute algorithms for process data. In at least one embodiment, the computer system 1100 may include a processor, such as the PENTIUM® processor family, Xeon™, Itanium®, XScale™ and / or StrongARM™, Intel® Core™ or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems (including PCs, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 1100 may execute a version of the Windows operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0286] In at least one embodiment, the computer system 1100 can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor (“DSP”), a system-on-a-chip (SoC), a network computer (“Net PC”), a set-top box, a network hub, a wide area network (“WAN”) switch, or any other system capable of executing one or more instructions according to at least one embodiment.

[0287] In at least one embodiment, computer system 1100 may include, but is not limited to, processor 1102, which may include, but is not limited to, one or more execution units 1108 configured to execute Computing Unified Device Architecture (“CUDA”) programs (CUDA® is developed by NVIDIA Corporation in Santa Clara, California). In at least one embodiment, a CUDA program is at least a portion of a software application written in the CUDA programming language. In at least one embodiment, computer system 1100 is a single-processor desktop or server system. In at least one embodiment, computer system 1100 may be a multiprocessor system. In at least one embodiment, processor 1102 may include, but is not limited to, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor implementing instruction set combinations, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 1102 may be coupled to a processor bus 1110, which can transmit data signals between processor 1102 and other components in computer system 1100.

[0288] In at least one embodiment, processor 1102 may include, but is not limited to, a Level 1 (“L1”) internal cache memory (“cache”) 1104. In at least one embodiment, processor 1102 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to processor 1102. In at least one embodiment, processor 1102 may include a combination of internal and external caches. In at least one embodiment, register file 1106 may store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0289] In at least one embodiment, an execution unit 1108, including but not limited to logic for performing integer and floating-point operations, is also located within the processor 1102. The processor 1102 may also include a microcode (“ucode”) read-only memory (“ROM”) for storing microcode of certain macro instructions. In at least one embodiment, the execution unit 1108 may include logic for processing a packaged instruction set 1109. In at least one embodiment, by including the packaged instruction set 1109 in the instruction set of the general-purpose processor 1102, along with the associated circuitry for executing the instructions, packaged data in the general-purpose processor 1102 can be used to perform operations used by numerous multimedia applications. In at least one embodiment, many multimedia applications can be executed more quickly and efficiently by using the full width of the processor’s data bus to perform operations on the packaged data, which may eliminate the need to transfer smaller data units on the processor’s data bus to perform one or more operations on a data element at a time.

[0290] In at least one embodiment, the execution unit 1108 may also be used in a microcontroller, embedded processor, graphics device, DSP, and other types of logic circuitry. In at least one embodiment, the computer system 1100 may include, but is not limited to, the memory 1120. In at least one embodiment, the memory 1120 may be implemented as a DRAM device, an SRAM device, a flash memory device, or other storage device. The memory 1120 may store instructions 1119 and / or data 1121 represented by data signals that can be executed by the processor 1102.

[0291] In at least one embodiment, the system logic chip may be coupled to processor bus 1110 and memory 1120. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 1116, and processor 1102 may communicate with MCH 1116 via processor bus 1110. In at least one embodiment, MCH 1116 may provide a high-bandwidth memory path 1118 to memory 1120 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, MCH 1116 may initiate data signals between processor 1102, memory 1120, and other components in computer system 1100, and bridge data signals between processor bus 1110, memory 1120, and system I / O 1122. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 1116 can be coupled to memory 1120 via high-bandwidth memory path 1118, and graphics / video card 1112 can be coupled to MCH 1116 via Accelerated Graphics Port (“AGP”) interconnect 1114.

[0292] In at least one embodiment, computer system 1100 may use system I / O 1122 as a proprietary hub interface bus to couple MCH 1116 to I / O controller hub (“ICH”) 1130. In at least one embodiment, ICH 1130 may provide direct connectivity to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to memory 1120, chipset, and processor 1102. Examples may include, but are not limited to, an audio controller 1129, a firmware hub (“Flash BIOS”) 1128, a wireless transceiver 1126, data storage 1124, a conventional I / O controller 1123 and keyboard interface including user input 1125, a serial expansion port 1127 (e.g., USB), and a network controller 1134. Data storage 1124 may include a hard disk drive, floppy disk drive, CD-ROM device, flash memory device, or other mass storage device.

[0293] In at least one embodiment, Figure 11 A system comprising interconnected hardware devices or "chips" is shown. In at least one embodiment, Figure 11 An example SoC can be shown. In at least one embodiment, Figure 11The devices shown can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of system 1100 are interconnected using a compute fast link (CXL) interconnect.

[0294] In at least one embodiment, computer system 1100 can be used to implement system 700 (see [link]). Figure 7 ) and / or System 800 (see Figure 8 For example, the first group 712 and / or the second group 714 may include a processor 1102 and / or a graphics / video card 1112. In at least one embodiment, the processor bus 1110 may be used to implement the switching circuit system 710 (see [link to documentation]). Figure 7 ), bus 728 and / or signal conductors 734 and 740. In at least one embodiment, Figure 11 One or more systems described in the text are used to achieve, for example, combination. Figures 1-8 The description refers to one or more systems and / or processes of the like.

[0295] Figure 12 A system 1200 according to at least one embodiment is illustrated. In at least one embodiment, system 1200 is an electronic device utilizing processor 1210. In at least one embodiment, system 1200 may be, for example, but not limited to, a laptop computer, tower server, rack server, blade server, edge device communicatively coupled to one or more local or cloud service providers, laptop computer, desktop computer, tablet computer, mobile device, telephone, embedded computer, or any other suitable electronic device.

[0296] In at least one embodiment, system 1200 may include, but is not limited to, processor 1210 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, processor 1210 uses a bus or interface coupling, such as an I2C bus, a system management bus (“SMBus”), a low pin count (LPC) bus, a serial peripheral interface (“SPI”), a high-definition audio (“HDA”) bus, a serial advanced technology accessory (“SATA”) bus, a USB (versions 1, 2, and 3) bus, or a universal asynchronous receiver / transmitter (“UART”) bus. In at least one embodiment, Figure 12 A system is illustrated, comprising interconnected hardware devices or "chips". In at least one embodiment, Figure 12 An example SoC can be shown. In at least one embodiment, Figure 12 The device shown can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 12One or more components are interconnected using Computational Fast Link (CXL) interconnects.

[0297] In at least one embodiment, Figure 12 This may include a display 1224, a touchscreen 1225, a touchpad 1230, a near-field communication unit (“NFC”) 1245, a sensor hub 1240, a thermal sensor 1246, a fast chipset (“EC”) 1235, a trusted platform module (“TPM”) 1238, a BIOS / firmware / flash memory (“BIOS, FW Flash”) 1222, a DSP 1260, a solid-state drive (“SSD”) or hard disk drive (“HDD”) 1220, a wireless local area network unit (“WLAN”) 1250, a Bluetooth unit 1252, a wireless wide area network unit (“WWAN”) 1256, a global positioning system (GPS) 1255, a camera (“USB 3.0 camera”) 1254 (e.g., a USB 3.0 camera), or a low-power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1215 implemented in, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0298] In at least one embodiment, other components may be communicatively coupled to processor 1210 via the components discussed above. In at least one embodiment, accelerometer 1241, ambient light sensor (“ALS”) 1242, compass 1243, and gyroscope 1244 may be communicatively coupled to sensor hub 1240. In at least one embodiment, thermal sensor 1239, fan 1237, keyboard 1236, and touchpad 1230 may be communicatively coupled to EC 1235. In at least one embodiment, speaker 1263, earphone 1264, and microphone (“mic”) 1265 may be communicatively coupled to audio unit (“audio codec and Class D amplifier”) 1262, which in turn may be communicatively coupled to DSP 1260. In at least one embodiment, audio unit 1262 may include, for example, but not limited to, audio encoder / decoder (“codec”) and Class D amplifier. In at least one embodiment, SIM card (“SIM”) 1257 may be communicatively coupled to WWAN unit 1256. In at least one embodiment, components such as WLAN unit 1250, Bluetooth unit 1252, and WWAN unit 1256 can be implemented as next-generation form factor (NGFF).

[0299] In at least one embodiment, system 1200 can be used to implement system 700 (see [link]). Figure 7 ) and / or System 800 (see Figure 8 In at least one embodiment, processor 722 (see...) Figure 7This can be implemented using processor 1210. In at least one embodiment, Figure 12 One or more systems described in the text are used to achieve, for example, combination. Figures 1-8 The description refers to one or more systems and / or processes of the like.

[0300] Figure 13 An example integrated circuit 1300 according to at least one embodiment is illustrated. In at least one embodiment, the example integrated circuit 1300 is a SoC (System-on-a-Chip) that can be fabricated using one or more IP cores. In at least one embodiment, the integrated circuit 1300 includes one or more application processors 1305 (e.g., CPU, DPU), at least one graphics processor 1310, and may additionally include an image processor 1315 and / or a video processor 1320, any of which may be a modular IP core. In at least one embodiment, the integrated circuit 1300 includes peripheral or bus logic including a USB controller 1325, a UART controller 1330, an SPI / SDIO controller 1335, and an I2S / I2C controller 1340. In at least one embodiment, the integrated circuit 1300 may include a display device 1345 coupled to one or more of a High Definition Multimedia Interface (HDMI) controller 1350 and a Mobile Industrial Processor Interface (MIPI) display interface 1355. In at least one embodiment, storage may be provided by a flash memory subsystem 1360, including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via memory controller 1365 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1370.

[0301] In at least one embodiment, integrated circuit 1300 can be used to implement system 700 (see [link]). Figure 7 ) and / or System 800 (see Figure 8 In at least one embodiment, the first group 712 and / or the second group 714 may include one or more application processors 1305, one or more graphics processors 1310, image processors 1315, and / or video processors 1320. See also Figure 7 In at least one embodiment, integrated circuit 1300 (see...) Figure 13 The peripheral logic or bus logic can be used to implement the switching circuit system 710 (see [link]). Figure 7 ), bus 728 and / or signal conductors 734 and 740.

[0302] Figure 14A computing system 1400 according to at least one embodiment is illustrated. In at least one embodiment, the computing system 1400 includes a processing subsystem 1401 having one or more processors 1402 and a system memory 1404 communicating via an interconnect path that may include a memory hub 1405. In at least one embodiment, the memory hub 1405 may be a separate component within a chipset assembly or may be integrated within one or more processors 1402. In at least one embodiment, the memory hub 1405 is coupled to an I / O subsystem 1411 via a communication link 1406. In at least one embodiment, the I / O subsystem 1411 includes an I / O hub 1407 that enables the computing system 1400 to receive input from one or more input devices 1408. In at least one embodiment, the I / O hub 1407 may enable a display controller, which is included in one or more processors 1402, for providing output to one or more display devices 1410A. In at least one embodiment, one or more display devices 1410A coupled to the I / O hub 1407 may include local, internal, or embedded display devices.

[0303] In at least one embodiment, the processing subsystem 1401 includes one or more parallel processors 1412 coupled to the memory hub 1405 via a bus or other communication link 1413. In at least one embodiment, the communication link 1413 may be one of many standards-based communication link technologies or protocols, such as, but not limited to, PCIe, or may be a vendor-specific communication interface or communication architecture. In at least one embodiment, the one or more parallel processors 1412 form a computationally concentrated parallel or vector processing system that may include a large number of processing cores and / or processing clusters, such as a multi-core integrated (MIC) processor. In at least one embodiment, the one or more parallel processors 1412 form a graphics processing subsystem capable of outputting pixels to one or more display devices 1410A coupled via an I / O hub 1407. In at least one embodiment, the one or more parallel processors 1412 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 1410B.

[0304] In at least one embodiment, system storage unit 1414 may be connected to I / O hub 1407 to provide a storage mechanism for computing system 1400. In at least one embodiment, I / O switch 1416 may be used to provide an interface mechanism to enable connectivity between I / O hub 1407 and other components, such as network adapter 1418 and / or wireless network adapter 1419 that may be integrated into the platform, and various other devices that may be added via one or more additional devices 1420. In at least one embodiment, network adapter 1418 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 1419 may include one or more Wi-Fi, Bluetooth, NFC, or other network devices comprising one or more radios.

[0305] In at least one embodiment, the computing system 1400 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., and may also be connected to the I / O hub 1407. In at least one embodiment, for Figure 14 The communication paths that interconnect the various components can be implemented using any suitable protocol, such as PCI (Peripheral Component Interconnect) based protocols (e.g., PCIe), or other bus or point-to-point communication interfaces and / or protocols (e.g., NVLink™ high-speed interconnect or interconnect protocols).

[0306] In at least one embodiment, one or more parallel processors 1412 include circuitry optimized for graphics and video processing (including, for example, video output circuitry) and constitute a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 1412 include circuitry optimized for general-purpose processing. In at least one embodiment, components of the computing system 1400 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 1412, memory hub 1405, processor 1402, and I / O hub 1407 may be integrated into a system-on-a-chip (SoC) integrated circuit. In at least one embodiment, components of the computing system 1400 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computing system 1400 may be integrated into a multi-chip module (MCM) that can interconnect with other MCMs to a modular computing system. In at least one embodiment, the I / O subsystem 1411 and display device 1410B are omitted from the computing system 1400.

[0307] In at least one embodiment, computing system 1400 can be used to implement system 700 (see [link]). Figure 7) and / or System 800 (see Figure 8 In at least one embodiment, the first group 712 and / or the second group 714 may include one or more processors 1402 and / or one or more parallel processors 1412. In at least one embodiment, the communication link 1413 may be used to implement the switching circuit system 710 (see [link to documentation]). Figure 7 ), bus 728 and / or signal conductors 734 and 740.

[0308] Processing system The following figures illustrate, but are not limited to, example processing systems that can be used to implement at least one embodiment.

[0309] Figure 15 An accelerated processing unit (“APU”) 1500 according to at least one embodiment is illustrated. In at least one embodiment, the APU 1500 was developed by AMD Inc. of Santa Clara, California. In at least one embodiment, the APU 1500 can be configured to execute applications, such as CUDA programs. In at least one embodiment, the APU 1500 includes, but is not limited to, a core complex 1510, a graphics complex 1540, an architecture 1560, an I / O interface 1570, a memory controller 1580, a display controller 1592, and a multimedia engine 1594. In at least one embodiment, the APU 1500 can be, but is not limited to, any combination of any number of core complexes 1510, any number of graphics complexes 1540, any number of display controllers 1592, and any number of multimedia engines 1594. For illustrative purposes, multiple instances of similar objects are indicated herein by reference numerals, wherein the reference numerals identify the object, and the numbers in parentheses identify the desired instances.

[0310] In at least one embodiment, the core complex 1510 is a CPU, the graphics complex 1540 is a GPU, and the APU 1500 is a processing unit that is not limited to 1510 and 1540 integrated onto a single chip. In at least one embodiment, some tasks may be assigned to the core complex 1510, while other tasks may be assigned to the graphics complex 1540. In at least one embodiment, the core complex 1510 is configured to execute main control software associated with the APU 1500, such as an operating system. In at least one embodiment, the core complex 1510 is the main processor of the APU 1500, which controls and coordinates the operation of other processors. In at least one embodiment, the core complex 1510 issues commands to control the operation of the graphics complex 1540. In at least one embodiment, the core complex 1510 may be configured to execute host executable code derived from CUDA source code, and the graphics complex 1540 may be configured to execute device executable code derived from CUDA source code.

[0311] In at least one embodiment, the core complex 1510 includes, but is not limited to, cores 1520(1)-1520(4) and L3 cache 1530. In at least one embodiment, the core complex 1510 may include, but is not limited to, any combination of any number of cores 1520 and any number and type of cache. In at least one embodiment, the cores 1520 are configured to execute instructions of a specific instruction set architecture (“ISA”). In at least one embodiment, each core 1520 is a CPU core.

[0312] In at least one embodiment, each core 1520 includes, but is not limited to, a fetch / decode unit 1522, an integer execution engine 1524, a floating-point execution engine 1526, and an L2 cache 1528. In at least one embodiment, the fetch / decode unit 1522 fetches instructions, decodes these instructions, generates micro-operations, and dispatches individual micro-instructions to the integer execution engine 1524 and the floating-point execution engine 1526. In at least one embodiment, the fetch / decode unit 1522 may simultaneously dispatch one micro-instruction to the integer execution engine 1524 and another micro-instruction to the floating-point execution engine 1526. In at least one embodiment, the integer execution engine 1524 performs operations not limited to integer and memory operations. In at least one embodiment, the floating-point execution engine 1526 performs operations not limited to floating-point and vector operations. In at least one embodiment, the fetch / decode unit 1522 dispatches micro-instructions to a single execution engine, which replaces both the integer execution engine 1524 and the floating-point execution engine 1526.

[0313] In at least one embodiment, each core 1520(i) can access the L2 cache 1528(i) included in core 1520(i), where i is an integer representing a specific instance of core 1520. In at least one embodiment, each core 1520 included in core complex 1510(j) is connected to other cores 1520 included in core complex 1510(j) via an L3 cache 1530(j) included in core complex 1510(j), where j is an integer representing a specific instance of core complex 1510. In at least one embodiment, a core 1520 included in core complex 1510(j) can access all L3 caches 1530(j) included in core complex 1510(j), where j is an integer representing a specific instance of core complex 1510. In at least one embodiment, the L3 cache 1530 may include, but is not limited to, any number of slices.

[0314] In at least one embodiment, the graphics complex 1540 may be configured to perform computational operations in a highly parallel manner. In at least one embodiment, the graphics complex 1540 is configured to perform graphics pipeline operations, such as drawing commands, pixel operations, geometric calculations, and other operations associated with rendering an image to a display. In at least one embodiment, the graphics complex 1540 is configured to perform graphics-independent operations. In at least one embodiment, the graphics complex 1540 is configured to perform both graphics-related and graphics-independent operations.

[0315] In at least one embodiment, the graphics complex 1540 includes, but is not limited to, any number of computing units 1550 and an L2 cache 1542. In at least one embodiment, the computing units 1550 share the L2 cache 1542. In at least one embodiment, the L2 cache 1542 is partitioned. In at least one embodiment, the graphics complex 1540 includes, but is not limited to, any number of computing units 1550 and any number (including zero) and type of cache. In at least one embodiment, the graphics complex 1540 includes, but is not limited to, any number of dedicated graphics hardware.

[0316] In at least one embodiment, each computing unit 1550 includes, but is not limited to, any number of SIMD units 1552 and shared memory 1554. In at least one embodiment, each SIMD unit 1552 implements a SIMD architecture and is configured to execute operations in parallel. In at least one embodiment, each computing unit 1550 may execute any number of thread blocks, but each thread block executes on a single computing unit 1550. In at least one embodiment, a thread block includes, but is not limited to, any number of execution threads. In at least one embodiment, a workgroup is a thread block. In at least one embodiment, each SIMD unit 1552 executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in the warp belongs to a single thread block and is configured to process different datasets based on a single instruction set. In at least one embodiment, prediction can be used to disable one or more threads in a warp. In at least one embodiment, a channel is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block can be synchronized together and communicate via shared memory 1554.

[0317] In at least one embodiment, structure 1560 is a system interconnect that facilitates data and control transfers across core complex 1510, graphics complex 1540, I / O interface 1570, memory controller 1580, display controller 1592, and multimedia engine 1594. In at least one embodiment, in addition to or instead of structure 1560, APU 1500 may also include, but is not limited to, any number and type of system interconnects that facilitate data and control transfers across any number and type of components that may be directly or indirectly linked, either internally or externally to APU 1500. In at least one embodiment, I / O interface 1570 represents any number and type of I / O interface (e.g., PCI, PCI-Extended (“PCI-X”), PCIe, Gigabit Ethernet (“GBE”), USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 1570. In at least one embodiment, the peripheral device coupled to the I / O interface 1570 may include, but is not limited to, a keyboard, mouse, printer, scanner, joystick or other types of game controllers, media recording devices, external storage devices, network interface cards, etc.

[0318] In at least one embodiment, the display controller AMD92 displays images on one or more display devices (e.g., liquid crystal display (LCD) devices). In at least one embodiment, the multimedia engine 1594 includes, but is not limited to, any number and type of multimedia-related circuitry, such as video decoders, video encoders, image signal processors, etc. In at least one embodiment, the memory controller 1580 facilitates data transfer between the APU 1500 and the unified system memory 1590. In at least one embodiment, the core complex 1510 and the graphics complex 1540 share the unified system memory 1590.

[0319] In at least one embodiment, the APU 1500 implements a memory subsystem, including but not limited to any number and type of memory controllers 1580 and memory devices (e.g., shared memory 1554) that can be dedicated to a single component or shared among multiple components. In at least one embodiment, the APU 1500 implements a cache subsystem, including but not limited to one or more cache memories (e.g., L2 cache 1628, L3 cache 1530, and L2 cache 1542), each cache memory being component-private or shared among any number of components (e.g., core 1520, core complex 1510, SIMD unit 1552, compute unit 1550, and graphics complex 1540).

[0320] In at least one embodiment, the APU 1500 can be used to implement system 700 (see [link]). Figure 7 ) and / or System 800 (see Figure 8 In at least one embodiment, the first group 712 and / or the second group 714 may include one or more components of the core complex 1510 and / or one or more components of the graphic complex 1540. In at least one embodiment, the structure 1560 may be used to implement the switching circuit system 710. In at least one embodiment, Figure 15 One or more systems described in the text are used to achieve, for example, combination. Figures 1-8 The description refers to one or more systems and / or processes of the like.

[0321] Figure 16 A CPU 1600 according to at least one embodiment is illustrated. In at least one embodiment, the CPU 1600 was developed by AMD Inc. of Santa Clara, California. In at least one embodiment, the CPU 1600 can be configured to execute an application. In at least one embodiment, the CPU 1600 is configured to execute host control software, such as an operating system. In at least one embodiment, the CPU 1600 issues commands to control the operation of an external GPU (not shown). In at least one embodiment, the CPU 1600 can be configured to execute host executable code derived from CUDA source code, and the external GPU can be configured to execute device executable code derived from such CUDA source code. In at least one embodiment, the CPU 1600 includes, but is not limited to, any number of core complexes 1610, architectures 1660, I / O interfaces 1670, and memory controllers 1680.

[0322] In at least one embodiment, the core complex 1610 includes, but is not limited to, cores 1620(1)-1620(4) and L3 cache 1630. In at least one embodiment, the core complex 1610 may include, but is not limited to, any combination of any number of cores 1620 and any number and type of cache. In at least one embodiment, the cores 1620 are configured to execute instructions of a specific ISA. In at least one embodiment, each core 1620 is a CPU core.

[0323] In at least one embodiment, each core 1620 includes, but is not limited to, a fetch / decode unit 1622, an integer execution engine 1624, a floating-point execution engine 1626, and an L2 cache 1628. In at least one embodiment, the fetch / decode unit 1622 fetches instructions, decodes these instructions, generates micro-operations, and dispatches individual micro-instructions to the integer execution engine 1624 and the floating-point execution engine 1626. In at least one embodiment, the fetch / decode unit 1622 may simultaneously dispatch one micro-instruction to the integer execution engine 1624 and another micro-instruction to the floating-point execution engine 1626. In at least one embodiment, the integer execution engine 1624 performs operations not limited to integer and memory operations. In at least one embodiment, the floating-point engine 1626 performs operations not limited to floating-point and vector operations. In at least one embodiment, the fetch-decode unit 1622 dispatches micro-instructions to a single execution engine, which replaces both the integer execution engine 1624 and the floating-point execution engine 1626.

[0324] In at least one embodiment, each core 1620(i) can access the L2 cache 1628(i) included in core 1620(i), where i is an integer representing a specific instance of core 1620. In at least one embodiment, each core 1620 included in core complex 1610(j) is connected to other cores 1620 in core complex 1610(j) via an L3 cache 1630(j) included in core complex 1610(j), where j is an integer representing a specific instance of core complex 1610. In at least one embodiment, a core 1620 included in core complex 1610(j) can access all L3 caches 1630(j) included in core complex 1610(j), where j is an integer representing a specific instance of core complex 1610. In at least one embodiment, the L3 cache 1630 may include, but is not limited to, any number of slices.

[0325] In at least one embodiment, structure 1660 is a system interconnect that facilitates data and control transfers across core complexes 1610(1)-1610(N) (where N is a positive integer), I / O interface 1670, and memory controller 1680. In at least one embodiment, in addition to or instead of structure 1660, CPU 1600 may also include, but is not limited to, any number and type of system interconnects that facilitate data and control transfers across any number and type of components that may be directly or indirectly linked, either inside or outside CPU 1600. In at least one embodiment, I / O interface 1670 represents any number and type of I / O interfaces (e.g., PCI, PCI-X, PCIe, GBE, USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 1670. In at least one embodiment, peripheral devices coupled to I / O interface 1670 may include, but are not limited to, displays, keyboards, mice, printers, scanners, joysticks or other types of game controllers, media recording devices, external storage devices, network interface cards, etc.

[0326] In at least one embodiment, memory controller 1680 facilitates data transfer between CPU 1600 and system memory 1690. In at least one embodiment, core complex 1610 and graphics complex 1640 share system memory 1690. In at least one embodiment, CPU 1600 implements a memory subsystem, which includes, but is not limited to, any number and type of memory controllers 1680 and memory devices that may be dedicated to a component or shared among multiple components. In at least one embodiment, CPU 1600 implements a cache subsystem, which includes, but is not limited to, one or more cache memories (e.g., L2 cache 1628 and L3 cache 1630), each cache memory may be component-private or shared among any number of components (e.g., core 1620 and core complex 1610).

[0327] In at least one embodiment, CPU 1600 may be used to implement system 700 (see...) Figure 7 ) and / or System 800 (see Figure 8 In at least one embodiment, the first group 712 and / or the second group 714 may include one or more components of the core composite 1610. In at least one embodiment, the structure 1660 may be used to implement the switching circuit system 110. In at least one embodiment, Figure 16 One or more systems described in the text are used to achieve, for example, combination. Figures 1-8 The description refers to one or more systems and / or processes of the like.

[0328] Figure 17An example accelerator integration slice 1790 according to at least one embodiment is illustrated. As used herein, a "slice" includes a designated portion of the processing resources of an accelerator integrated circuit. In at least one embodiment, the accelerator integrated circuit provides cache management, memory access, environment management, and interrupt management services for multiple graphics processing engines among multiple graphics acceleration modules. Each graphics processing engine may comprise a separate GPU. Optionally, the graphics processing engine may include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In at least one embodiment, a graphics acceleration module may be a GPU having multiple graphics processing engines. In at least one embodiment, the graphics processing engines may be individual GPUs integrated on a general-purpose package, line card, or chip.

[0329] The application's effective address space 1782 within system memory 1714 stores process element 1783. In one embodiment, process element 1783 is stored in response to a GPU call 1781 from an application 1780 executing on processor 1707. Process element 1783 contains the processing state of the corresponding application 1780. A job descriptor (WD) 1784 contained in process element 1783 may be a single job requested by the application or may contain pointers to job queues. In at least one embodiment, WD 1784 is a pointer to a job request queue in the application's effective address space 1782.

[0330] The graphics acceleration module 1746 and / or the various graphics processing engines may be shared by all or some processes in the system. In at least one embodiment, infrastructure may be included for establishing a processing state and sending the WD 1784 to the graphics acceleration module 1746 to begin operation in a virtualized environment.

[0331] In at least one embodiment, a dedicated process programming model is used for implementation. In this model, a single process owns the graphics acceleration module 1746 or an individual graphics processing engine. Since the graphics acceleration module 1746 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owned partition, and the operating system initializes the accelerator integrated circuit for the owned partition when the graphics acceleration module 1746 is allocated.

[0332] During operation, the WD fetch unit 1791 in the accelerator integrated slice 1790 fetches the next WD 1784, which includes instructions for the work to be performed by one or more graphics processing engines of the graphics acceleration module 1746. Data from the WD 1784 can be stored in register 1745 and used by the memory management unit (MMU) 1739, interrupt management circuitry 1747, and / or environment management circuitry 1748, as shown. For example, one embodiment of the MMU 1739 includes segment / page roaming circuitry for accessing segment / page tables 1786 within the OS virtual address space 1785. The interrupt management circuitry 1747 can handle interrupt events (INT) 1792 received from the graphics acceleration module 1746. When performing graph operations, the effective address 1793 generated by the graphics processing engine is translated into an actual address by the MMU 1739.

[0333] In one embodiment, the same register set 1745 is copied for each graphics processing engine and / or graphics acceleration module 1746 and can be initialized by the hypervisor or operating system. Each of these copied registers can be included in the accelerator integration slice 1790. Table 1 shows example registers that can be initialized by the hypervisor.

[0334] Table 1 – Registers for Supervisor Initialization Table 2 shows exemplary registers that can be initialized by the operating system.

[0335] Table 2 – Operating System Initialization Registers In one embodiment, each WD 1784 is specific to a particular graphics acceleration module 1746 and / or a particular graphics processing engine. It contains all the information required for the graphics processing engine to perform its work or to do so, or it may be a pointer to a memory location where the application has established a command queue for the work to be done.

[0336] In at least one embodiment, the accelerator integration slice 1790 can be used to implement system 700 (see [link]). Figure 7 ) and / or System 800 (see Figure 8 In at least one embodiment, the first group 712 and / or the second group 714 may include a processor 1707, a graphics acceleration module 1746, and / or various graphics processing engines. In at least one embodiment, Figure 17 One or more systems described in the text are used to achieve, for example, combination. Figures 1-8 The description refers to one or more systems and / or processes of the like.

[0337] Figures 18A-18BAn example graphics processor according to at least one embodiment of this document is illustrated. In at least one embodiment, any example graphics processor may be manufactured using one or more IP cores. In addition to the illustrations, other logic and circuitry may be included in at least one embodiment, including additional graphics processor / cores, peripheral interface controllers, or general-purpose processor cores. In at least one embodiment, the example graphics processor is used within a System-on-a-Chip (SoC).

[0338] Figure 18A An example graphics processor 1810 of a SoC integrated circuit according to at least one embodiment is shown, which can be manufactured using one or more IP cores. Figure 18B An additional example graphics processor 1840 of a SoC integrated circuit according to at least one embodiment is shown, which can be manufactured using one or more IP cores. In at least one embodiment, Figure 18A The graphics processor 1810 is a low-power graphics processor core. In at least one embodiment, Figure 18B The graphics processor 1840 is a higher-performance graphics processor core. In at least one embodiment, each graphics processor 1810, 1840 may be... Figure 13 A variant of the 1310 graphics processor.

[0339] In at least one embodiment, the graphics processor 1810 includes a vertex processor 1805 and one or more fragment processors 1815A-1815N (e.g., 1815A, 1815B, 1815C, 1815D to 1815N-1 and 1815N). In at least one embodiment, the graphics processor 1810 can execute different shader programs via separate logic, such that the vertex processor 1805 is optimized to perform operations for the vertex shader program, while one or more fragment processors 1815A-1815N perform fragment (e.g., pixel) shading operations for fragments or pixels or shader programs. In at least one embodiment, the vertex processor 1805 performs the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. In at least one embodiment, the fragment processors 1815A-1815N use the primitive and vertex data generated by the vertex processor 1805 to generate framebuffers for display on a display device. In at least one embodiment, the fragment processors 1815A-1815N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform operations similar to those of pixel shader programs provided in the Direct 3D API.

[0340] In at least one embodiment, the graphics processor 1810 additionally includes one or more MMUs 1820A-1820B, caches 1825A-1825B, and circuit interconnects 1830A-1830B. In at least one embodiment, one or more MMUs 1820A-1820B provide a virtual-to-physical address mapping for the graphics processor 1810, including for the vertex processor 1805 and / or fragment processors 1815A-1815N, which can reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in one or more caches 1825A-1825B. In at least one embodiment, one or more MMUs 1820A-1820B can be synchronized with other MMUs within the system, including with... Figure 13 One or more application processors 1305, graphics processors 1315, and / or video processors 1320 are associated with one or more MMUs, enabling each processor 1305-1320 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1830A-1830B enable the graphics processor 1810 to connect to other IP cores within the SoC via the SoC's internal bus or via a direct connection.

[0341] In at least one embodiment, the graphics processor 1840 includes Figure 18A The graphics processor 1810 includes one or more MMUs 1820A-1820B, caches 1825A-1825B, and circuit interconnects 1830A-1830B. In at least one embodiment, the graphics processor 1840 includes one or more shader cores 1855A-1855N (e.g., 1855A, 1855B, 1855C, 1855D, 1855E, 1855F, to 1855N-1 and 1855N) that provide a unified shader core architecture, wherein a single core or type of core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores may vary. In at least one embodiment, the graphics processor 1840 includes an inter-core task manager 1845 that acts as a thread dispatcher to assign execution threads to one or more shader cores 1855A-1855N and a tile unit 1858 to accelerate tile-based rendering operations, wherein rendering operations of a scene are subdivided in image space, for example, to take advantage of local spatial consistency within the scene or to optimize the use of internal caches.

[0342] In at least one embodiment, the first group 712 (see Figure 7 ) and / or Group 2 714 (see Figure 7 The system may include one or more graphics cores 1800 and / or one or more graphics processors 1840. In at least one embodiment, the first group 712 and / or the second group 714 may include vertex processors 1805 and / or one or more fragment processors 1815A-1815N. In at least one embodiment, the first group 712 and / or the second group 714 may include an inter-core task manager 1845 and / or one or more shader cores 1855A-1855N. In at least one embodiment, Figures 18A-18B One or more systems described in the text are used to achieve, for example, combination Figures 1-8 The description refers to one or more systems and / or processes of the like.

[0343] Figure 19A A graphics core 1900 according to at least one embodiment is shown. In at least one embodiment, the graphics core 1900 may include... Figure 13 The graphics processor 1310 is located within it. In at least one embodiment, the graphics core 1900 may be... Figure 18B The graphics core 1900 uses a unified shader core 1855A-1855N. In at least one embodiment, the graphics core 1900 includes a shared instruction cache 1902, texture units 1918, and cache / shared memory 1920, which are common to execution resources within the graphics core 1900. In at least one embodiment, the graphics core 1900 may include multiple slices 1901A-1901N or partitions of each core, and the graphics processor may include multiple instances of the graphics core 1900. Slices 1901A-1901N may include supporting logic including local instruction caches 1904A-1904N, thread schedulers 1906A-1906N, thread dispatchers 1908A-1908N, and a set of registers 1910A-1910N. In at least one embodiment, slices 1901A-1901N may include a set of additional functional units (AFU) 1912A-1912N, floating-point units (FPU) 1914A-1914N, integer arithmetic logic units (ALU) 1916A-1916N, address calculation units (ACU) 1913A-1913N, double-precision floating-point units (DPFPU) 1915A-1915N, and matrix processing units (MPU) 1917A-1917N.

[0344] In one embodiment, the FPU 1914A-1914N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPU 1915A-1915N can perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALU 1916A-1916N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPU 1917A-1917N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPU 1917A-1917N can perform various matrix operations to accelerate CUDA programs, including enabling support for accelerated General Matrix-to-Matrix Multiplication (GEMM). In at least one embodiment, the AFU 1912A-1912N can perform additional logical operations not supported by floating-point or integer units, including trigonometric operations (e.g., Sine, Cosine, etc.).

[0345] Figure 19B A general-purpose graphics processing unit (GPGPU) 1930 is illustrated in at least one embodiment. In at least one embodiment, the GPGPU 1930 is highly parallel and suitable for deployment on a multi-chip module. In at least one embodiment, the GPGPU 1930 can be configured to enable highly parallel computational operations to be performed by a GPU array. In at least one embodiment, the GPGPU 1930 can be directly linked to other instances of the GPGPU 1930 to create a multi-GPU cluster to improve execution time for CUDA programs. In at least one embodiment, the GPGPU 1930 includes a host interface 1932 for connection to a host processor. In at least one embodiment, the host interface 1932 is a PCIe interface. In at least one embodiment, the host interface 1932 can be a vendor-specific communication interface or communication structure. In at least one embodiment, the GPGPU 1930 receives commands from the host processor and uses a global scheduler 1934 to assign execution threads associated with those commands to a set of computational clusters 1936A-1936H. In at least one embodiment, computing clusters 1936A-1936H share cache memory 1938. In at least one embodiment, cache memory 1938 can be used as an advanced cache of cache memory within computing clusters 1936A-1936H.

[0346] In at least one embodiment, the GPGPU 1930 includes memory 1944A-1944B coupled to the computing cluster 1936A-1936H via a set of memory controllers 1942A-1942B. In at least one embodiment, memory 1944A-1944B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0347] In at least one embodiment, computing clusters 1936A-1936H each include a set of graphics cores, such as Figure 19A The graphics core 1900 may include various types of integer and floating-point logic units, capable of performing computational operations at various precisions, including computations suitable for CUDA programs. For example, in at least one embodiment, at least a subset of the floating-point units in each computing cluster 1936A-1936H may be configured to perform 16-bit or 32-bit floating-point operations, while different subsets of the floating-point units may be configured to perform 64-bit floating-point operations.

[0348] In at least one embodiment, multiple instances of GPGPU 1930 can be configured to operate as a computing cluster. Computing clusters 1936A-1936H can implement any technically feasible communication technology for synchronization and data exchange. In at least one embodiment, the multiple instances of GPGPU 1930 communicate via host interface 1932. In at least one embodiment, GPGPU 1930 includes an I / O hub 1939 that couples GPGPU 1930 to GPU link 1940, enabling direct connection to other instances of GPGPU 1930. In at least one embodiment, GPU link 1940 is coupled to a dedicated GPU-to-GPU bridge, enabling communication and synchronization among the multiple instances of GPGPU 1930. In at least one embodiment, GPU link 1940 is coupled to a high-speed interconnect for sending and receiving data to and from other GPGPUs or parallel processors. In at least one embodiment, the multiple instances of GPGPU 1930 reside in a separate data processing system and communicate via a network device accessible via host interface 1932. In at least one embodiment, the GPU link 1940 may be configured to connect to a host processor, supplementing or replacing the host interface 1932. In at least one embodiment, the GPGPU 1930 may be configured to execute CUDA programs.

[0349] In at least one embodiment, Figures 19A-19BThe described system is used to detect and / or predict (e.g., within a multi-GPU system) signals conducted by signal conductors, using various algorithms, formulas, and / or processes (e.g., combining...). Figure 1-8 Those described herein) transition signal conductors between active and inactive states, and / or otherwise perform the operations described herein. In at least one embodiment, the GPU 808 (see...) Figure 8 One or more of these can be implemented using a general-purpose graphics processing unit 1930. In at least one embodiment, Figures 19A-19B The one or more systems described herein are used to implement one or more systems and / or processes, for example, in combination Figures 1-8 Those described.

[0350] Figure 20A A parallel processor 2000 according to at least one embodiment is shown. In at least one embodiment, various components of the parallel processor 2000 may be implemented using one or more integrated circuit devices, such as programmable processors, application-specific integrated circuits (ASICs), or FPGAs.

[0351] In at least one embodiment, the parallel processor 2000 includes a parallel processing unit 2002. In at least one embodiment, the parallel processing unit 2002 includes an I / O unit 2004 that enables communication with other devices, including other instances of the parallel processing unit 2002. In at least one embodiment, the I / O unit 2004 can be directly connected to other devices. In at least one embodiment, the I / O unit 2004 is connected to other devices using a hub or switch interface (e.g., a memory hub 2005). In at least one embodiment, the connection between the memory hub 2005 and the I / O unit 2004 forms a communication link. In at least one embodiment, the I / O unit 2004 is connected to a host interface 2006 and a memory crossbar switch 2016, wherein the host interface 2006 receives commands for performing processing operations, and the memory crossbar switch 2016 receives commands for performing memory operations.

[0352] In at least one embodiment, when host interface 2006 receives a command buffer via I / O unit 2004, host interface 2006 can direct work operations to execute those commands to front end 2008. In at least one embodiment, front end 2008 is coupled to scheduler 2010, which is configured to assign commands or other work items to processing array 2012. In at least one embodiment, scheduler 2010 ensures that processing array 2012 is correctly configured and in an active state before assigning tasks to processing array 2012. In at least one embodiment, scheduler 2010 is implemented via firmware logic executed on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2010 can be configured to perform complex scheduling and work assignment operations at both coarse and fine granular levels, thereby enabling fast preemption and environment switching of threads executing on processing array 2012. In at least one embodiment, host software can demonstrate workloads scheduled on processing array 2012 via one of multiple graphics processing doorbells. In at least one embodiment, the workload can then be automatically distributed on the processing array 2012 by the scheduler 2010 logic within the microcontroller, which includes the scheduler 2010.

[0353] In at least one embodiment, the processing array 2012 may include up to "N" processing clusters (e.g., clusters 2014A, 2014B to 2014N). In at least one embodiment, each cluster 2014A-2014N of the processing array 2012 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 2010 may use various scheduling and / or work allocation algorithms to allocate work to the clusters 2014A-2014N of the processing array 2012, which may vary depending on the workload generated by each type of program or computation. In at least one embodiment, scheduling may be handled dynamically by the scheduler 2010, or may be partially assisted by compiler logic during the compilation of program logic configured to be executed by the processing array 2012. In at least one embodiment, different clusters 2014A-2014N of the processing array 2012 may be assigned to process different types of programs or to perform different types of computations.

[0354] In at least one embodiment, the processing array 2012 may be configured to perform various types of parallel processing operations. In at least one embodiment, the processing array 2012 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, the processing array 2012 may include logic for performing processing tasks, including filtering video and / or audio data, performing modeling operations, including physical operations, and performing data transformations.

[0355] In at least one embodiment, the processing array 2012 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing array 2012 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing array 2012 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2002 may transfer data from system memory via I / O unit 2004 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2022) and then written back to system memory.

[0356] In at least one embodiment, when the parallel processing unit 2002 is used to perform graph processing, the scheduler 2010 may be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations to multiple clusters 2014A-2014N of the processing array 2012. In at least one embodiment, portions of the processing array 2012 may be configured to perform different types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of the clusters 2014A-2014N may be stored in a buffer to allow intermediate data to be transferred between the clusters 2014A-2014N for further processing.

[0357] In at least one embodiment, the processing array 2012 may receive processing tasks to be executed via a scheduler 2010, which receives commands defining the processing tasks from a front end 2008. In at least one embodiment, the processing task may include an index of data to be processed, such as surface (patch) data, raw data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data is processed (e.g., what program to execute). In at least one embodiment, the scheduler 2010 may be configured to acquire an index corresponding to a task, or may receive an index from the front end 2008. In at least one embodiment, the front end 2008 may be configured to ensure that the processing array 2012 is configured to be active before initiating the workload specified by an incoming command buffer (e.g., a batch buffer, push buffer, etc.).

[0358] In at least one embodiment, each of one or more instances of the parallel processing unit 2002 may be coupled to the parallel processor memory 2022. In at least one embodiment, the parallel processor memory 2022 may be accessed via a memory crossbar switch 2016, which may receive memory requests from the processing array 2012 and the I / O unit 2004. In at least one embodiment, the memory crossbar switch 2016 may access the parallel processor memory 2022 via a memory interface 2018. In at least one embodiment, the memory interface 2018 may include a plurality of partition units (e.g., partition units 2020A, 2020B to 2020N), each of which may be coupled to a portion (e.g., a memory cell) of the parallel processor memory 2022. In at least one embodiment, the plurality of partition units 2020A-2020N are configured to be equal to the number of memory units, such that the first partition unit 2020A has a corresponding first memory unit 2024A, the second partition unit 2020B has a corresponding memory unit 2024B, and the Nth partition unit 2020N has a corresponding Nth memory unit 2024N. In at least one embodiment, the number of partition units 2020A-2020N may not be equal to the number of memory devices.

[0359] In at least one embodiment, memory cells 2024A-2024N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory cells 2024A-2024N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, rendering targets such as frame buffers or texture maps may be stored across memory cells 2024A-2024N, allowing partitioning cells 2020A-2020N to write portions of each rendering target in parallel to efficiently utilize the available bandwidth of the parallel processor memory 2022. In at least one embodiment, local instances of the parallel processor memory 2022 may be excluded to facilitate a unified memory design that combines system memory with local cache memory.

[0360] In at least one embodiment, any of the clusters 2014A-2014N of the processing array 2012 can process data to be written to any memory cell 2024A-2024N within the parallel processor memory 2022. In at least one embodiment, the memory crossbar switch 2016 can be configured to transfer the output of each cluster 2014A-2014N to any partition cell 2020A-2020N or another cluster 2014A-2014N, and the clusters 2014A-2014N can perform further processing operations on the output. In at least one embodiment, each cluster 2014A-2014N can communicate with the memory interface 2018 via the memory crossbar switch 2016 to read from or write to various external storage devices. In at least one embodiment, the memory crossbar switch 2016 has a connection to a memory interface 2018 for communication with I / O unit 2004, and a connection to a local instance of parallel processor memory 2022, thereby enabling processing units within different processing clusters 2014A-2014N to communicate with system memory or other memory not local to parallel processing unit 2002. In at least one embodiment, the memory crossbar switch 2016 may use virtual channels to separate traffic flows between clusters 2014A-2014N and partition units 2020A-2020N.

[0361] In at least one embodiment, multiple instances of the parallel processing unit 2002 may be provided on a single insert card, or multiple insert cards may be interconnected. In at least one embodiment, different instances of the parallel processing unit 2002 may be configured to interoperate, even if the different instances have different numbers of processing cores, different numbers of local parallel processor memories, and / or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 2002 may include higher-precision floating-point units relative to other instances. In at least one embodiment, a system combining one or more instances of the parallel processing unit 2002 or the parallel processor 2000 may be implemented in various configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0362] In at least one embodiment, the first group 712 (see Figure 7 ) and / or Group 2 714 (see Figure 7 This may include one or more parallel processors 2000. In at least one embodiment, Figure 20A One or more systems are described as being used to detect and / or predict signals conducted by signal conductors (e.g., within a multi-GPU system), and various algorithms, formulas, and / or processes (such as combining...) are employed. Figures 1 to 8The described ones) cause the signal conductor to transition between an active and inactive state, and / or otherwise perform the operations described herein. In at least one embodiment, Figure 20A One or more systems described in the text are used to achieve, for example, combination Figures 1-8 The description refers to one or more systems and / or processes of the like.

[0363] Figure 20B A processing cluster 2094 according to at least one embodiment is illustrated. In at least one embodiment, the processing cluster 2094 is included within a parallel processing unit. In at least one embodiment, the processing cluster 2094 is... Figure 20A An example of one of the processing clusters 2014A-2014N. In at least one embodiment, the processing cluster 2094 can be configured to execute a number of threads in parallel, wherein the term "thread" refers to an instance of a specific program executing on a particular set of input data. In at least one embodiment, a Single Instruction Multiple Data (SIMD) instruction issuing technique is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, a Single Instruction Multiple Threading (SIMT) technique is used to support the parallel execution of a large number of generally synchronous threads, which uses a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster 2094.

[0364] In at least one embodiment, the operation of the processing cluster 2094 can be controlled by a pipeline manager 2032 that assigns processing tasks to the SIMT parallel processors. In at least one embodiment, the pipeline manager 2032... Figure 20A The scheduler 2010 receives instructions and manages the execution of these instructions via the graphics multiprocessor 2034 and / or texture unit 2036. In at least one embodiment, the graphics multiprocessor 2034 is an example instance of a SIMT parallel processor. However, in at least one embodiment, the processing cluster 2094 may include various types of SIMT parallel processors with different architectures. In at least one embodiment, the processing cluster 2094 may include one or more instances of the graphics multiprocessor 2034. In at least one embodiment, the graphics multiprocessor 2034 can process data, and the data crossover switch 2040 can be used to distribute the processed data to one of several possible destinations, including other shader units. In at least one embodiment, the pipeline manager 2032 can facilitate the distribution of processed data by specifying the destination of the processed data to be distributed via the data crossover switch 2040.

[0365] In at least one embodiment, each graphics multiprocessor 2034 within the processing cluster 2094 may include the same set of functional execution logic (e.g., arithmetic logic units, load-memory units (LSUs), etc.). In at least one embodiment, the functional execution logic may be configured in a pipelined manner, wherein new instructions may be issued before previous instructions complete. In at least one embodiment, the functional execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, shift operations, and computation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be used to perform different operations, and any combination of functional units may exist.

[0366] In at least one embodiment, instructions transmitted to the processing cluster 2094 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, the thread group executes programs on different input data. In at least one embodiment, each thread within the thread group may be assigned to a different processing engine within the graphics multiprocessor 2034. In at least one embodiment, the thread group may include fewer threads than the number of processing engines within the graphics multiprocessor 2034. In at least one embodiment, when the number of threads included in the thread group is less than the number of processing engines, one or more processing engines may be idle during a loop that is processing the thread group. In at least one embodiment, the thread group may also include more threads than the number of processing engines within the graphics multiprocessor 2034. In at least one embodiment, when the thread group includes more threads than the number of processing engines within the graphics multiprocessor 2034, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 2034.

[0367] In at least one embodiment, the graphics multiprocessor 2034 includes an internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 2034 may forgo the internal cache and use a cache memory within the processing cluster 2094 (e.g., L1 cache 2048). In at least one embodiment, each graphics multiprocessor 2034 may also access partition units (e.g., Figure 20AThe L2 cache is located within partition units 2020A-2020N, ​​which are shared among all processing clusters 2094 and can be used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 2034 can also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory outside of the parallel processing unit 2002 can be used as global memory. In at least one embodiment, the processing cluster 2094 includes multiple instances of the graphics multiprocessor 2034, which can share common instructions and data that can be stored in the L1 cache 2048.

[0368] In at least one embodiment, each processing cluster 2094 may include an MMU 2045 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 2045 may reside in Figure 20A Within the memory interface 2018. In at least one embodiment, the MMU 2045 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles (more on tiles) and optionally to cache line indices. In at least one embodiment, the MMU 2045 may include an address translation back buffer (TLB) or a cache that may reside within the graphics multiprocessor 2034, L1 cache 2048, or processing cluster 2094. In at least one embodiment, physical addresses are processed to allocate surface data access locality for efficient request interleaving between partition units. In at least one embodiment, cache line indices may be used to determine whether a request for a cache line is a hit or a miss.

[0369] In at least one embodiment, the processing cluster 2094 can be configured such that each graphics multiprocessor 2034 is coupled to a texture unit 2036 to perform texture mapping operations, which may involve determining texture sample locations, reading texture data, and filtering texture data. In at least one embodiment, texture data is read as needed from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2034, and texture data is also retrieved from an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 2034 outputs a processed task to a data crossbar switch 2040 to provide the processed task to another processing cluster 2094 for further processing or to store the processed task in an L2 cache, local parallel processor memory, or system memory via a memory crossbar switch 2016. In at least one embodiment, a pre-raster operation unit (preROP) 2042 is configured to receive data from the graphics multiprocessor 2034 and direct the data to a ROP unit, which may be associated with a partitioning unit (e.g., [missing information]). Figure 20A The PreROP2042 unit is located together with the partition units 2020A-2020N. In at least one embodiment, the PreROP2042 unit can perform optimizations for color blending, organize pixel color data, and perform address translation.

[0370] Figure 20C A graphics multiprocessor 2096 according to at least one embodiment is illustrated. In at least one embodiment, the graphics multiprocessor 2096 is Figure 20B The graphics multiprocessor 2034 is included. In at least one embodiment, the graphics multiprocessor 2096 is coupled to the pipeline manager 2032 of the processing cluster 2094. In at least one embodiment, the graphics multiprocessor 2096 has an execution pipeline including, but not limited to, an instruction cache 2052, an instruction unit 2054, an address mapping unit 2056, a register file 2058, one or more GPGPU cores 2062, and one or more LSUs 2066. The GPGPU cores 2062 and LSUs 2066 are coupled to cache memory 2072 and shared memory 2070 via memory and cache interconnect 2068.

[0371] In at least one embodiment, instruction cache 2052 receives a stream of instructions to be executed from pipeline manager 2032. In at least one embodiment, instructions are cached in instruction cache 2052 and dispatched to instruction unit 2054 for execution. In one embodiment, instruction unit 2054 may dispatch instructions as thread groups (e.g., thread bundles), assigning each thread of the thread group to a different execution unit within GPGPU core 2062. In at least one embodiment, instructions can access any local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, address mapping unit 2056 may be used to translate addresses in the unified address space into different memory addresses that can be accessed by LSU 2066.

[0372] In at least one embodiment, register file 2058 provides a set of registers for functional units of graphics multiprocessor 2096. In at least one embodiment, register file 2058 provides temporary storage for operands of data paths connected to functional units of graphics multiprocessor 2096 (e.g., GPGPU core 2062, LSU 2066). In at least one embodiment, register file 2058 is partitioned among each functional unit, such that a dedicated portion of register file 2058 is allocated to each functional unit. In at least one embodiment, register file 2058 is partitioned among different thread groups being executed by graphics multiprocessor 2096.

[0373] In at least one embodiment, each of the GPGPU cores 2062 may include an FPU and / or an ALU for executing instructions of the graph multiprocessor 2096. The GPGPU cores 2062 may be architecturally similar or may differ in architecture. In at least one embodiment, a first portion of the GPGPU core 2062 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 2096 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores 2062 may also include fixed-function or special-function logic.

[0374] In at least one embodiment, the GPGPU core 2062 includes SIMD logic capable of executing a single instruction on multiple sets of data. In at least one embodiment, the GPGPU core 2062 can physically execute SIMD4, SIMD8, and SIMD9 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a Single Program Multiple Data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed using a single SIMD instruction. For example, in at least one embodiment, eight SIMD threads performing the same or similar operations can be executed in parallel using a single SIMD8 logic unit.

[0375] In at least one embodiment, the memory and cache interconnect 2068 is an interconnect network connecting each functional unit of the graphics multiprocessor 2096 to the register file 2058 and the shared memory 2070. In at least one embodiment, the memory and cache interconnect 2068 is a cross-switch interconnect that allows the LSU 2066 to perform load and store operations between the shared memory 2070 and the register file 2058. In at least one embodiment, the register file 2058 can operate at the same frequency as the GPGPU core 2062, resulting in very low latency for data transfer between the GPGPU core 2062 and the register file 2058. In at least one embodiment, the shared memory 2070 can be used to enable communication between threads executing on functional units within the graphics multiprocessor 2096. In at least one embodiment, the cache memory 2072 can be used, for example, as a data cache to cache texture data communicated between functional units and texture units 2036. In at least one embodiment, the shared memory 2070 can also be used as a program-managed cache. In at least one embodiment, in addition to the automatically cached data stored in cache memory 2072, the thread executing on GPGPU core 2062 can also programmatically store data in shared memory.

[0376] In at least one embodiment, a parallel processor or GPGPU, as described herein, is communicatively coupled to the host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., high-speed interconnects such as PCIe or NVLink). In at least one embodiment, the GPU may be integrated with the core on the same package or chip and communicatively coupled to the core via an internal processor bus / interconnect (i.e., within the package or chip). In at least one embodiment, regardless of how the GPU is connected, the processor core may assign work to the GPU in the form of a sequence of commands / instructions contained in the WD. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0377] In at least one embodiment, Figures 20A-20C The described system is used to detect and / or predict (e.g., within a multi-GPU system) signals conducted by signal conductors, using various algorithms, formulas, and / or processes (e.g., combining...). Figure 1-8 Those described herein are signal conductors that transition between active and inactive states, and / or otherwise perform the operations described herein. In at least one embodiment, Figures 20A-20C The one or more systems described herein are used to implement one or more systems and / or processes, such as in combination. Figures 1-8 Those described.

[0378] Figure 21 A graphics processor 2100 according to at least one embodiment is illustrated. In at least one embodiment, the graphics processor 2100 includes a ring interconnect 2102, a pipeline front end 2104, a media engine 2137, and graphics cores 2180A-2180N. In at least one embodiment, the ring interconnect 2102 couples the graphics processor 2100 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, the graphics processor 2100 is one of many processors integrated within a multi-core processing system.

[0379] In at least one embodiment, the graphics processor 2100 receives multiple batches of commands via a ring interconnect 2102. In at least one embodiment, the input commands are interpreted by a command stream converter 2103 in a pipeline front-end 2104. In at least one embodiment, the graphics processor 2100 includes scalable execution logic to perform 3D geometry processing and media processing via graphics cores 2180A-2180N. In at least one embodiment, for 3D geometry processing commands, the command stream converter 2103 provides commands to the geometry pipeline 2136. In at least one embodiment, for at least some media processing commands, the command stream converter 2103 provides commands to a video front-end 2134, which is coupled to a media engine 2137. In at least one embodiment, the media engine 2137 includes a video quality engine (VQE) 2130 for video and image post-processing, and a multi-format encoding / decoding (MFX) engine 2133 for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2136 and the media engine 2137 each generate an execution thread for the thread execution resources provided by at least one graphics core 2180A.

[0380] In at least one embodiment, the graphics processor 2100 includes scalable thread execution resources characterized by modular graphics cores 2180A-2180N (sometimes referred to as core slices), each modular core having multiple sub-cores 2150A-2150N, 2160A-2160N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 2100 may have any number of graphics cores 2180A to 2180N. In at least one embodiment, the graphics processor 2100 includes a graphics core 2180A having at least a first sub-core 2150A and a second sub-core 2160A. In at least one embodiment, the graphics processor 2100 is a low-power processor having a single sub-core (e.g., 2150A). In at least one embodiment, the graphics processor 2100 includes multiple graphics cores 2180A-2180N, each graphics core including a set of first sub-cores 2150A-2150N and a set of second sub-cores 2160A-2160N. In at least one embodiment, each of the first sub-cores 2150A-2150N includes at least a first set of execution units (EUs) 2152A-2152N and media / texture samplers 2154A-2154N. In at least one embodiment, each of the second sub-cores 2160A-2160N includes at least a second set of execution units 2162A-2162N and samplers 2164A-2164N. In at least one embodiment, each sub-core 2150A-2150N, 2160A-2160N shares a set of shared resources 2170A-2170N. In at least one embodiment, the shared resources include shared cache memory and pixel operation logic.

[0381] In at least one embodiment, the first group 712 (see Figure 7 ) and / or Group 2 714 (see Figure 7 It may include one or more graphics processors 2100. In at least one embodiment, Figure 21 One or more systems are described as being used to detect and / or predict signals conducted by signal conductors (e.g., within a multi-GPU system), and to utilize various algorithms, formulas, and / or processes (such as combining...). Figures 1 to 8 Those described herein) cause the signal conductor to transition between an active and inactive state, and / or otherwise perform the operations described herein. In at least one embodiment, Figure 21 One or more systems described in the text are used to achieve, for example, combination Figures 1-8 The description refers to one or more systems and / or processes of the like.

[0382] Figure 22 A processor 2200 is illustrated according to at least one embodiment. In at least one embodiment, the processor 2200 may include, but is not limited to, logic circuitry for executing instructions. In at least one embodiment, the processor 2200 can execute instructions, including x86 instructions, ARM instructions, special-purpose instructions for ASICs, etc. In at least one embodiment, the processor 2200 may include registers for storing packaged data, such as the 64-bit wide MMX™ registers in an Intel microprocessor enabled by MMX technology in Santa Clara, California. In at least one embodiment, the MMX registers available in integer and floating-point forms can operate with packaged data elements accompanying SIMD and Streaming SIMD Extensions (“SSE”) instructions. In at least one embodiment, a 128-bit wide XMM register associated with SSE2, SSE3, SSE4, AVX, or later (generally referred to as “SSEx”) technologies can hold such packaged data operands. In at least one embodiment, the processor 2200 can execute instructions to accelerate CUAD programs.

[0383] In at least one embodiment, processor 2200 includes an ordered front end (“front end”) 2201 to fetch instructions to be executed and prepare instructions for later use in the processor pipeline. In at least one embodiment, front end 2201 may include several units. In at least one embodiment, instruction prefetcher 2226 fetches instructions from memory and provides the instructions to instruction decoder 2228, which in turn decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 2228 decodes the received instructions into one or more operations, so-called “micro-instructions” or “micro-operations” (also referred to as “micro-operations” or “micro-instructions”), for execution. In at least one embodiment, instruction decoder 2228 parses the instructions into opcodes and corresponding data and control fields, which can be used by the microarchitecture to perform operations. In at least one embodiment, trace cache 2230 may assemble the decoded micro-instructions into a program-ordered sequence or trace in micro-instruction queue 2234 for execution. In at least one embodiment, when trace cache 2230 encounters complex instructions, microcode ROM 2232 provides the micro-instructions required to complete the operation.

[0384] In at least one embodiment, some instructions may be converted into a single micro-operation, while others require several micro-operations to complete the entire operation. In at least one embodiment, if more than four micro-instructions are required to complete an instruction, the instruction decoder 2228 may access the microcode ROM 2232 to execute the instruction. In at least one embodiment, an instruction may be decoded into a small number of micro-instructions for processing at the instruction decoder 2228. In at least one embodiment, if multiple micro-instructions are required to complete an operation, the instructions may be stored in the microcode ROM 2232. In at least one embodiment, the trace cache 2230 references an entry point programmable logic array (“PLA”) to determine the correct micro-instruction pointer for reading a microcode sequence from the microcode ROM 2232 to complete one or more instructions, according to at least one embodiment. In at least one embodiment, after the microcode ROM 2232 has completed the micro-operation ordering of the instructions, the machine front end 2201 may resume fetching micro-operations from the trace cache 2230.

[0385] In at least one embodiment, the out-of-order execution engine (“out-of-order engine”) 2203 can prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the instruction flow to optimize performance as instructions descend the pipeline and are scheduled for execution. The out-of-order execution engine 2203 includes, but is not limited to, an allocator / register renamer 2240, a memory microinstruction queue 2242, an integer / floating-point microinstruction queue 2244, a memory scheduler 2246, a fast scheduler 2202, a slow / general-purpose floating-point scheduler (“slow / general-purpose FP scheduler”) 2204, and a simple floating-point scheduler (“simple FP scheduler”) 2206. In at least one embodiment, the fast scheduler 2202, the slow / general-purpose floating-point scheduler 2204, and the simple floating-point scheduler 2206 are also collectively referred to as “microinstruction schedulers 2202, 2204, 2206”. The allocator / register renamer 2240 allocates the machine buffers and resources required for the sequential execution of each microinstruction. In at least one embodiment, allocator / register renaming unit 2240 renames logical registers to entries in a register file. In at least one embodiment, allocator / register renaming unit 2240 also assigns entries for each microinstruction in one of two microinstruction queues, memory microinstruction queue 2242 for memory operations and integer / floating-point microinstruction queue 2244 for non-memory operations, preceding memory scheduler 2246 and microinstruction schedulers 2202, 2204, 2206. In at least one embodiment, microinstruction schedulers 2202, 2204, 2206 determine when they are ready to execute a microinstruction based on the readiness of their dependent input register operand sources and the availability of the execution resource microinstructions that need to be completed. In at least one embodiment, fast scheduler 2202 of at least one embodiment can schedule on each half of the master clock cycle, while slow / general-purpose floating-point scheduler 2204 and simple floating-point scheduler 2206 can schedule once per master processor clock cycle. In at least one embodiment, microinstruction schedulers 2202, 2204, and 2206 arbitrate the scheduling port to schedule microinstructions for execution.

[0386] In at least one embodiment, execution block 2211 includes, but is not limited to, integer register file / tribute network 2208, floating-point register file / tribute network (“FP register file / tribute network”) 2210, address generation units (“AGU”) 2212 and 2214, fast arithmetic logic units (“fast ALU”) 2216 and 2218, slow ALU 2220, floating-point ALU (“FP”) 2222, and floating-point movement unit (“FP movement”) 2224. In at least one embodiment, integer register file / tribute network 2208 and floating-point register file / bypass network 2210 are also referred to herein as “register files 2208, 2210”. In at least one embodiment, AGUS 2212 and 2214, fast ALU 2216 and 2218, slow ALU 2220, floating-point ALU 2222, and floating-point movement unit 2224 are also referred to herein as "execution units 2212, 2214, 2216, 2218, 2220, 2222, and 2224". In at least one embodiment, the execution block may include, but is not limited to, any number (including zero) and type of register files, branch networks, address generation units, and execution units (in any combination).

[0387] In at least one embodiment, register files 2208, 2210 may be arranged between microinstruction schedulers 2202, 2204, 2206 and execution units 2212, 2214, 2216, 2218, 2220, 2222, and 2224. In at least one embodiment, integer register file / tribute network 2208 performs integer operations. In at least one embodiment, floating-point register file / tribute network 2210 performs floating-point operations. In at least one embodiment, each of register files 2208, 2210 may include, but is not limited to, a tribute network that can bypass or forward recently completed results not yet written to the register file to a new dependent object. In at least one embodiment, register files 2208, 2210 may communicate data with each other. In at least one embodiment, integer register file / tribute network 2208 may include, but is not limited to, two separate register files, one register file for low-order 32-bit data and a second register file for high-order 32-bit data. In at least one embodiment, the floating-point register file / branch network 2210 may include, but is not limited to, entries with a width of 128 bits, since floating-point instructions typically have operands with a width of 64 to 128 bits.

[0388] In at least one embodiment, execution units 2212, 2214, 2216, 2218, 2220, 2222, and 2224 can execute instructions. In at least one embodiment, register files 2208 and 2210 store integer and floating-point data operation values ​​that the microinstructions need to execute. In at least one embodiment, processor 2200 may include, but is not limited to, any number of execution units 2212, 2214, 2216, 2218, 2220, 2222, and 2224, and combinations thereof. In at least one embodiment, floating-point ALU 2222 and floating-point move unit 2224 can perform floating-point, MMX, SIMD, AVX, and SSE or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 2222 may include, but is not limited to, a 64-bit multiplication-64-bit floating-point divider to perform division, square root, and remainder micro-operations. In at least one embodiment, floating-point hardware can be used to process instructions involving floating-point values. In at least one embodiment, ALU operations can be passed to fast ALUs 2216 and 2218. In at least one embodiment, fast ALUs 2216 and 2218 can perform fast operations with an effective delay of half a clock cycle. In at least one embodiment, most complex integer operations are routed to slow ALU 2220, because slow ALU 2220 can include, but is not limited to, integer execution hardware for long-latency type operations, such as multipliers, shifters, flag logic, and branching. In at least one embodiment, memory load / store operations can be performed by ALUs 2212 and 2214. In at least one embodiment, fast ALU 2216, fast ALU 2218, and slow ALU 2220 can perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 2216, fast ALU 2218, and slow ALU 2220 can be implemented to support various data bit sizes including 16, 32, 128, 256, etc. In at least one embodiment, the floating-point ALU 2222 and the floating-point movement unit 2224 can be implemented to support a range of operands with various bit widths. In at least one embodiment, the floating-point ALU 2222 and the floating-point movement unit 2224 can operate on 128-bit wide packaged data operands in conjunction with SIMD and multimedia instructions.

[0389] In at least one embodiment, microinstruction schedulers 2202, 2204, and 2206 schedule dependent operations before the parent load completes execution. In at least one embodiment, since microinstructions can be speculatively scheduled and executed within processor 2200, processor 2200 may also include logic for handling memory misses. In at least one embodiment, if a data load miss occurs in the data cache, there may be a dependent operation running in the pipeline that temporarily deprives the scheduler of the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and may allow independent operations to be completed. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences for text string comparison operations.

[0390] In at least one embodiment, the term "register" may refer to an onboard processor storage location that can be used as part of an instruction that identifies an operand. In at least one embodiment, a register may be one that can be used from outside the processor (from a programmer's perspective). In at least one embodiment, a register may not be limited to a particular type of circuitry. Rather, in at least one embodiment, a register may store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein may be implemented using a variety of different techniques via circuitry within the processor, such as dedicated physical registers, dynamically allocated physical registers renamed using register renaming, a combination of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, an integer register stores 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for encapsulating data.

[0391] In at least one embodiment, the first group 712 (see Figure 7 ) and / or Group 2 714 (see Figure 7 This may include one or more processors 2200. In at least one embodiment, Figure 22 One or more systems are described as being used to detect and / or predict signals conducted by signal conductors (e.g., within a multi-GPU system), utilizing various algorithms, formulas, and / or processes (such as combining...). Figures 1 to 8 Those described herein) cause the signal conductor to transition between an active and inactive state, and / or otherwise perform the operations described herein. In at least one embodiment, Figure 22 One or more systems described in the text are used to achieve, for example, combination Figures 1-8 The description refers to one or more systems and / or processes of the like.

[0392] Figure 23A processor 2300 according to at least one embodiment is illustrated. In at least one embodiment, the processor 2300 includes, but is not limited to, one or more processor cores (cores) 2302A-2302N, an integrated memory controller 2314, and an integrated graphics processor 2308. In at least one embodiment, the processor 2300 may include additional cores up to and including additional processor cores 2302N, indicated by dashed boxes. In at least one embodiment, each processor core 2302A-2302N includes one or more internal cache units 2304A-2304N. In at least one embodiment, each processor core may also access one or more shared cache units 2306.

[0393] In at least one embodiment, internal cache units 2304A-2304N and shared cache unit 2306 represent a cache memory hierarchy within processor 2300. In at least one embodiment, cache memory units 2304A-2304N may include at least one level of instruction and data within each processor core, as well as one or more levels of cache in a shared intermediate cache, such as L2, L3, L4, or other levels of cache, wherein the highest level of cache is classified as LLC before external memory. In at least one embodiment, cache coherence logic maintains coherence between the various shared cache units 2306 and 2304A-2304N.

[0394] In at least one embodiment, the processor 2300 may further include a set of one or more bus controller units 2316 and a system agent core 2310. In at least one embodiment, the one or more bus controller units 2316 manage a set of peripheral buses, such as one or more PCI or PCI Express buses. In at least one embodiment, the system agent core 2310 provides management functions for various processor components. In at least one embodiment, the system agent core 2310 includes one or more integrated memory controllers 2314 to manage access to various external memory devices (not shown).

[0395] In at least one embodiment, one or more processor cores 2302A-2302N include support for concurrent multithreading. In at least one embodiment, system agent core 2310 includes components for coordinating and operating processor cores 2302A-2302N during multithreaded processing. In at least one embodiment, system agent core 2310 may additionally include a power control unit (PCU) including logic and components for regulating one or more power states of processor cores 2302A-2302N and graphics processor 2308.

[0396] In at least one embodiment, processor 2300 further includes graphics processor 2308 to perform graphics processing operations. In at least one embodiment, graphics processor 2308 is coupled to a shared cache unit 2306 and a system proxy core 2310 including one or more integrated memory controllers 2314. In at least one embodiment, system proxy core 2310 further includes a display controller 2311 for driving graphics processor output to one or more coupled displays. In at least one embodiment, display controller 2311 may also be a separate module coupled to graphics processor 2308 via at least one interconnect, or it may be integrated within graphics processor 2308.

[0397] In at least one embodiment, the ring-based interconnect unit 2312 is used to couple internal components of the processor 2300. In at least one embodiment, alternative interconnect units, such as point-to-point interconnects, switched interconnects, or other technologies, may be used. In at least one embodiment, the graphics processor 2308 is coupled to the ring interconnect 2312 via I / O link 2313.

[0398] In at least one embodiment, I / O link 2313 represents at least one of a variety of I / O interconnects, including packaged I / O interconnects that facilitate communication between various processor components and high-performance embedded memory module 2318 (e.g., eDRAM module). In at least one embodiment, each of processor cores 2302A-2302N and graphics processor 2308 uses embedded memory module 2318 as a shared LLC.

[0399] In at least one embodiment, processor cores 2302A-2302N are homogeneous cores executing a common instruction set architecture. In at least one embodiment, processor cores 2302A-2302N are heterogeneous in terms of the instruction set architecture (ISA), with one or more processor cores 2302A-2302N executing a common instruction set, while one or more other processor cores 2302A-2302N execute a common instruction set or a subset of a different instruction set. In at least one embodiment, processor cores 2302A-2302N are heterogeneous in terms of microarchitecture, with one or more cores having relatively high power consumption coupled to one or more power cores having lower power consumption. In at least one embodiment, processor 2300 can be implemented on one or more chips or implemented as a SoC integrated circuit.

[0400] In at least one embodiment, the first group 712 (see Figure 7 ) and / or Group 2 714 (see Figure 7 The processor 2300 may include one or more processors. In at least one embodiment, the first group 712 (see...) Figure 7) and / or Group 2 714 (see Figure 7 It may include an integrated graphics processor 2308 and / or one or more processor cores 2302A-2302N. In at least one embodiment, a ring interconnect 2312 may be used to implement the switching circuit system 110. In at least one emb...

Claims

1. A network device, the network device comprising one or more circuits, the one or more circuits being used for: Receive network packets; According to a network service distribution policy, the network packets are allocated to one of multiple port groups, wherein the network service distribution policy distributes network packets proportionally among the multiple port groups based on network parameters; and The network packets are forwarded through the ports of the port group.

2. The network device as claimed in claim 1, wherein the network service distribution strategy includes a multi-path data structure, the multi-path data structure mapping different entries to different port groups among the plurality of port groups.

3. The network device of claim 2, wherein the multipath data structure includes an Equivalent Multipath (ECMP) table with multiple entries, wherein different percentages of the multiple entries are mapped to different port groups among the multiple port groups.

4. The network device of claim 3, wherein the one or more circuits are further configured to: perform a longest prefix matching (LPM) operation based on the destination address of the network packet to select the multipath data structure from a plurality of multipath data structures.

5. The network device of claim 4, wherein the one or more circuits are further configured to: Calculate the hash value based on the information in the network packets; and An entry is selected from the plurality of entries in the multipath data structure based on the hash value, wherein the selected entry determines a port group among the plurality of port groups for the network packet.

6. The network device of claim 2, wherein each entry in the multipath data structure is associated with at least one of a rule or action that identifies a corresponding port group among the plurality of port groups.

7. The network device of claim 6, wherein the rule or action indicates which ports of the network device are included in the corresponding port group.

8. The network device of claim 7, wherein the rule or action is updated based on network asymmetric information received via Border Gateway Protocol (BGP).

9. The network device of claim 1, wherein the plurality of port groups includes at least one port group configured to receive oversubscribed service load according to the network parameters.

10. The network device as claimed in claim 9, wherein: The network parameters include available capacity information for the multiple port groups; as well as Based on the available capacity information, the ratio is determined to direct more traffic to another port group than to the at least one port group.

11. The network device of claim 1, wherein the one or more circuits are further configured to: perform congestion control to limit traffic flow directed through at least one of the plurality of port groups.

12. The network device of claim 11, wherein the congestion control is further configured to: Over-booking at least one port in at least one of the plurality of port groups to cause controlled congestion; and The reduction in total traffic throughput corresponds to a specific amount of reduction in network capacity.

13. The network device of claim 1, wherein the one or more circuits are further configured to: Receive network status information indicating changes in network capacity; and The proportion of network packets distributed among the multiple port groups is adjusted based on the network condition information.

14. The network device of claim 13, wherein the network condition information indicates a reduction in capacity of a network path downstream of the network device.

15. The network device of claim 14, wherein the network status information is received via a Border Gateway Protocol (BGP) update message indicating at least one of a link failure or a link degradation.

16. The network device of claim 1, wherein forwarding the network packets through the ports of the one port group comprises: The port is selected from multiple available ports in the port group using at least one of adaptive routing, random selection, round-robin selection, or hash-based forwarding.

17. The network device of claim 1, wherein the network parameters include at least one of the following: Available bandwidth of the network link; Network congestion level; Link failure information; Service quality requirements; or The administrative weight assigned to a network path.

18. A network device, the network device comprising one or more circuits, the one or more circuits being configured to: Receive network packet streams; Based on network parameters, the network packets of the network packet flow are distributed proportionally among multiple port groups; and The network packets are forwarded through ports in the plurality of port groups.

19. The network device of claim 18, wherein the one or more circuits are further configured to: adjust the proportion of network packets distributed among the plurality of port groups in response to a change in the network parameters.

20. A system comprising: First network device; and A second network device connected to the first network device via multiple network links; The first network device includes one or more circuits, which are used for: Receive network traffic destined for the second network device; The network services are distributed among the multiple network links according to a service distribution strategy, wherein the service distribution strategy allocates different proportions of the network services to different subsets of the multiple network links based on capacity information associated with the multiple network links; as well as The different ratios are adjusted in response to changes in the capacity information.

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