Switching policies and APIs for changing state in a communication interface link

Abstract

Switching policies and APIs for changing states in a communication interface link. A switch connected to a plurality of devices via a plurality of respective links initiates a change to a bandwidth of a respective link between the switch and at least one of the plurality of devices. Initiating the change to the bandwidth of the respective link includes sending a bandwidth change request to the at least one device.

Description

Technical Field

[0001] Various aspects and embodiments of this disclosure relate to communication interfaces in computing systems, and more particularly to switch policies and APIs for changing the state in a communication interface link. Background Technology

[0002] Communication interfaces enable data transfer between various components in a computing system, such as the central processing unit (CPU), graphics processing unit (GPU), data processing unit (DPU), network interface controller (NIC), and data storage devices. Attached Figure Description

[0003] Various embodiments according to this disclosure will be described with reference to the accompanying drawings, in which: Figure 1A This is a block diagram of an example system architecture for a communication system according to an embodiment; Figure 1B This is a block diagram of an example system architecture for a communication system according to an embodiment; Figure 1C This is a block diagram of an example system architecture for a communication system according to an embodiment; Figure 1D This is a block diagram of an example system architecture for a communication system according to an embodiment; Figure 2 This is a block diagram of an example switch in a communication system according to an embodiment; Figure 3A This is a block diagram illustrating example communication between two devices via a switch according to an embodiment; Figure 3B This is a block diagram illustrating example communication between a device and a switch according to an embodiment; Figure 3C This is a block diagram illustrating example communication between an application and a switch according to an embodiment; Figure 4A An example link bandwidth policy for a switch according to an embodiment is described; Figure 4B An example link bandwidth strategy for a switch according to an embodiment is described; Figure 4C An example link bandwidth strategy for a switch according to an embodiment is described; Figure 4D An example link bandwidth strategy for a switch according to an embodiment is described; Figure 5 This is a flowchart of an example method for changing the state in a communication interface link using switch policies and APIs, according to an embodiment. Figure 6This is a flowchart of an example method for updating link bandwidth in a communication interface link according to an embodiment; Figure 7 This is a flowchart of an example method for determining link bandwidth updates in a communication interface link, according to an embodiment. Figure 8 This is a block diagram illustrating an exemplary computer system according to an embodiment; Figure 9 It is a block diagram of a computing system having two processing devices coupled to each other and multiple networks according to an embodiment; Figure 10 This is a block diagram of a computing system having a CPU and a GPU in a single integrated circuit according to an embodiment; and Figure 11 This is a block diagram of a computing system with a tensor core GPU according to an embodiment. Detailed Implementation

[0004] This disclosure relates to communication interfaces in computing systems, such as multi-channel communication interfaces. Communication interfaces enable data transfer between various components in a computing system, such as central processing units (CPUs), graphics processing units (GPUs), data processing units (DPUs), network interface controllers (NICs), data storage devices, etc. Multi-channel communication interfaces can use one or more channels to connect two devices to form a link, where channel aggregation can achieve higher bandwidth for the link compared to a single channel. Examples of multi-channel communication interfaces include Peripheral Component Interconnect Fast (PCIe), Compute Fast Link (CXL), NVLINK, InfiniBand, and Ethernet. Communication interfaces can be used in a wide range of applications, from data centers (e.g., high-performance computing, artificial intelligence, gaming, etc.) to consumer electronics (e.g., desktops, mobile devices).

[0005] Some communication interfaces can support changing link bandwidth to balance factors such as bandwidth requirements and power consumption. For example, some multi-channel communication interfaces can support link width resizing, where the number of channels used in the link can be dynamically reduced or increased on demand based on factors such as those mentioned above. Bandwidth updates can be achieved through negotiation between linked devices. However, some communication interfaces do not provide standardized strategies or communication methods for bandwidth updates, leaving it to the devices themselves to determine when to initiate bandwidth updates and whether to accept update requests from linked devices. This is particularly challenging for switches (dedicated devices that connect multiple devices to each other via multiple links). Switches can receive bandwidth update requests from one or more linked devices and must determine whether to accept the update request and how to propagate it to other linked devices. However, switches typically lack insight into the data transmission workload of connected devices and therefore cannot effectively initiate dynamic bandwidth updates with their link partners. Switches may also lack standardized interfaces for receiving and / or initiating bandwidth updates. Furthermore, how a switch responds to or initiates a bandwidth update request may depend on the associated application or current operating mode, factors that the switch is often unaware of.

[0006] Various aspects of this disclosure address these and other challenges by providing a communication interface switch that implements multiple policies for updating link bandwidth and provides an application programming interface (API) for receiving and / or initiating bandwidth update requests with connected devices. Software components such as drivers and applications can select policies best suited to the needs of each application and / or set policy configuration parameters best suited to the needs of each application, and can instruct the switch to apply the given policies according to the configuration. The switch can receive requests to update link bandwidth from connected devices and can determine the updated link bandwidth of other connected devices based on a combination of the selected / configured policies, the received requests, and / or the data streams observed by the switch. The switch can communicate with other connected devices via the API to update the corresponding link bandwidth. In one embodiment, the switch's API can conform to an existing protocol of the communication interface, which allows the switch to determine link bandwidth updates without extending the protocol. In another embodiment, the switch's API can extend the protocol and use new types of messages to convey additional information not available in the existing protocol.

[0007] In various embodiments, the switch can use various strategies. In an upstream pass-through strategy, the switch can receive bandwidth update requests from devices on downstream facing ports and provide the same request to devices on upstream facing ports. In a downstream pass-through strategy, the switch can receive bandwidth update requests from devices on upstream facing ports and provide the same request to devices on one or more downstream facing ports. In a aggregation strategy, the switch can provide a request to an upstream facing port based on the combined link bandwidth of one or more downstream facing ports. For example, the switch can request link bandwidth equal to the sum or maximum value of the link bandwidths of the downstream facing ports. In various cases, combinations of the above and other strategies can be used.

[0008] In one embodiment, a link bandwidth policy can define additional factors that the switch uses to determine which link bandwidth to request. For example, the switch can determine the requested link bandwidth on an upstream-facing port based on the link bandwidth of the downstream-facing port and the measured bandwidth utilization of the downstream links. In another example, the switch can determine the requested link bandwidth based on the performance requirements of the device communicated on the upstream-facing port or downstream-facing port (including, for example, performance requirements accumulated by another upstream / downstream switch). Furthermore, link bandwidth update requests can be prioritized based on, for example, power requirements or thermal requirements. Thus, a switch incorporating the aspects described above can more effectively propagate and initiate bandwidth updates based on data transmission workloads observed at the switch or communicated to the switch, and the switch can also respond to characteristic workloads of associated applications or operating modes.

[0009] Figure 1A This is a block diagram of an example system architecture 100A for a communication system according to an embodiment. System architecture 100A (also referred to herein as the "system") includes a switch 110, upstream devices 120A-N, and downstream devices 130A-N. System 100A also includes communication interface links 122A-N and 132A-N connecting the aforementioned components. In various embodiments, system 100A may include configuration and... Figure 1A The components described may have different configurations, with more or fewer components. For example, system 100A may include additional switches operating upstream or downstream of switch 110.

[0010] Communication system 100A is associated with a communication interface. A communication interface can define the common media and / or protocols that devices and applications running on it can use to communicate with each other. For example, a communication interface can define one or more layers of the Open Systems Interconnection (OSI) model, such as the physical layer, data link layer, application layer, etc. Examples of communication interfaces that can be associated with communication system 100A include Fast Peripheral Component Interconnect (PCIe), Compute Fast Link (CXL), NVLINK, InfiniBand, Ethernet, Universal Serial Bus (USB), Internal Integrated Circuit (I2C), Serial Peripheral Interface (SPI), etc.

[0011] Devices participating in the communication system 100A can be connected together via links compatible with the communication interface. A link can be a unidirectional or bidirectional channel for sending and / or receiving data between two devices and can be associated with the underlying physical medium and protocols defined by the communication interface. Link performance can be characterized in various ways. For example, link bandwidth can refer to the amount of data that can traverse the link within a time period, while link latency can refer to the time it takes for data to traverse the link. Link error rate can refer to the frequency at which data is lost or corrupted on the link. In various embodiments, some of these performance characteristics can be tunable. For example, a link can be associated with multiple bandwidth states that can support more or less bandwidth depending on the needs of the connected devices / applications.

[0012] In various embodiments, the communication interface may support different types of devices, such as switches and endpoint devices. Switch 110 may be a device that routes data traffic between two or more devices connected to switch 110. In various embodiments, switch 110 may use lookup tables, addresses embedded in data packets, and / or other techniques to determine which device(s) to route traffic to. In various embodiments, data packets received at switch 110 may be routable to any connected device or a subset of connected devices. For example, switch 110 may be a physical device that implements two or more virtual switches, which may be associated with a corresponding routable device tree connected to switch 110.

[0013] In various embodiments, upstream devices 120A-N are endpoint devices capable of performing host or controller roles. Upstream devices 120A-N can be connected to one or more downstream devices 130A-N via switch 110. In various embodiments, downstream devices 130A-N can perform managed or controlled roles. Examples of upstream devices include PCIe root complexes or their root ports and USB host-class devices. Examples of downstream devices include PCIe endpoint devices and USB device-class devices. In one embodiment, the communication system may have a single upstream device and one or more downstream devices.

[0014] Figure 1B This is a block diagram of an example system architecture 100B for a communication system according to an embodiment. System architecture 100B (also referred to herein as the "system") includes a switch 110 and endpoint devices 140A-N. System 100B also includes communication interface links 142A-N connecting the aforementioned components. In various embodiments, system 100B may include configuration and... Figure 1B The described components may have different configurations with more or fewer components. For example, system 100B may include additional switches operating upstream or downstream of switch 110. System 100B differs from system 100A in that there is no distinction between upstream and downstream devices; all devices can perform host / device, controller / controlled, transmitter / receiver, or other types of roles. An example communication system that may correspond to system 100B is an Ethernet system. In various embodiments, the device roles of systems 100A-B may be combined with aspects of one or more systems 100C-D.

[0015] Figure 1C This is a block diagram of an example system architecture 100C for a communication system according to an embodiment. System architecture 100C (also referred to herein as the "system") includes a bus 150 and endpoint devices 140A-N. System 100C also includes communication interface links 142A-N connecting the aforementioned components. In various embodiments, system 100C may include configuration and... Figure 1C The described components may have different configurations with more or fewer components. For example, system 100C may include an additional bus 150. System 100C differs from systems 100A-B in that there is no switch connecting multiple devices; instead, all devices share the same physical or virtual media bus 150. An example communication system that may correspond to system 100C is an I2C system. In various embodiments, the bus configuration of system 100C may be combined with aspects of one or more of systems 100A, 100B, or 100D.

[0016] Figure 1DThis is a block diagram of an example system architecture 100D for a communication system according to an embodiment. System architecture 100D (also referred to herein as the "system") includes a switch 110, upstream devices 120A-N, and downstream devices 130A-N. System 100D also includes multi-channel communication interface links 124A-N and 134A-N connecting the aforementioned components. In various embodiments, system 100D may include configuration and... Figure 1D The described components may be configured with more or fewer components. For example, system 100D may include additional switches operating upstream or downstream of switch 110. System 100D includes communication interface links, each of which may have two or more channels. An example communication system that may correspond to system 100D is a PCIe system. In various embodiments, the multi-channel communication interface links of system 100D may be combined with aspects of one or more systems 100A-C.

[0017] Multichannel communication interface links 124A-N may each have two or more channels for sending and / or receiving traffic, and the number of active channels (also referred to as "link width") may be configurable in various embodiments. For example, multichannel communication interface link 124A may be configured with active channels, while multichannel communication interface link 124B may be configured with four active channels. In another example, multichannel communication interface link 124A may transition from one active channel to four active channels at a certain point in time. The bandwidth characteristics described above may refer to the overall bandwidth of the link, while the channel bandwidth characteristics may refer to the bandwidth of a single channel. In a multichannel communication interface link, the link bandwidth may be the sum of the bandwidths of the individual channels. As described above, some embodiments of the communication system may support tunable link bandwidth, which in systems such as system 100D may include changing the link width (e.g., from one to four) or changing the bandwidth of individual channels (e.g., from low bandwidth to high bandwidth).

[0018] Figure 2 This is a block diagram of an example switch 200 in a communication system according to an embodiment. In one embodiment, device 200 may be... Figure 1A-1D Switch 110. Switch 200 is connected to one or more devices via one or more communication interface links 210A-N. In various embodiments, communication interface links 210A-N can be single-channel links or multi-channel links. Switch 200 includes a link negotiation module 220, a traffic observation module 230, a switch API module 240, and a link bandwidth policy 250. In various embodiments, switch 200 may include more than Figure 2The components depicted may include more or fewer components. For example, switch 200 may provide more than one type of API. In another example, switch 200 may include a routing module and a lookup table for routing messages between attached devices. In various embodiments, switch 200 may be a PCIe device, an Ethernet device, a USB device, or other types of device.

[0019] Link negotiation module 220 can communicate with connected devices to configure the connection link and can implement various protocols to accomplish this configuration. Link negotiation module 220 is used to initialize the link or update link parameters. For example, link negotiation module 220 can negotiate an updated bandwidth state. In a single-channel or multi-channel communication interface link, the updated bandwidth state can be a transition from a low bandwidth state to a high bandwidth state, or vice versa. In a multi-channel communication interface link, the updated bandwidth state can be a change in link width, as depicted in bandwidth states 212A-B (a transition from one channel to two channels). The link negotiation module can send or receive messages (e.g., message 222) to / from connected devices to facilitate link configuration.

[0020] Traffic observation module 230 can observe or measure one or more link traffic metrics for one or more communication interface links 210A-N. Link traffic metrics may include traffic size, traffic latency, traffic error rate, traffic source and destination, or other metrics. Link traffic metrics can be measured for all link traffic or a subset of link traffic (such as traffic destined for a specific device or switch 200). In one embodiment, traffic observation module 230 can observe the content of link traffic, such as source and destination addresses and / or message payloads. For example, traffic observation module 230 can observe performance-related messages (e.g., L0p messages defined in the PCIe protocol) that conform to the protocol of the communication interface and are sent to other devices, and identify actual or expected link traffic characteristics (e.g., whether connected devices are expected to increase the amount of traffic sent / received) based on the performance-related messages.

[0021] Switch API module 240 can provide devices and applications (e.g., application 280) with one or more endpoints to send notifications to switch 200 or request actions or behaviors of switch 200 related to link and traffic management. For example, an application can use switch API module 240 to provide link bandwidth policies to switch 200, and a device can use switch API module 240 to request link bandwidth updates or report current or expected usage patterns. In one embodiment, the endpoint of switch API module 240 may conform to the protocol of the communication interface. In other words, switch 200 can operate on existing messages specified in the communication protocol without any modification to the protocol. For example, in a PCIe embodiment, the endpoint of switch API module 240 may respond to a LOP latency-tolerant (LTR) message. In one embodiment, the endpoint of switch API module 240 may also be additionally or alternatively implemented as an extension of the protocol (e.g., a vendor-defined extension) and communicate with switch 200 using new message types. The endpoint of switch API module 240 can operate at various layers of the OSI model, such as data link layer packets or transaction layer packets in a PCIe embodiment.

[0022] Link bandwidth policy 250 includes one or more policies for initiating link bandwidth updates with attached devices. Link bandwidth policies may be embedded in the switch (e.g., in firmware, which may be unique to the device SKU) and / or provided by external sources such as applications, operating systems (e.g., via boot settings), or drivers (e.g., via switch API module 240). Similarly, policies can be selected internally via switch 200 or via instructions from the device or application. See also: Figure 4A The example link bandwidth policy is described. The link bandwidth policy can be updated, enabled, or disabled during runtime based on changes in the application, user reconfiguration, OS / driver reconfiguration, etc.

[0023] Figure 3AThis is a block diagram illustrating example communication 300 between two devices 310 and 312 via switch 200 according to an embodiment. As depicted, device 310 sends traffic destined for device 312 to switch 200 via a link, which forwards the traffic to device 312 via a second link. The traffic may contain data (e.g., application-related), metadata (e.g., related to the communication itself), instructions, etc. For example, the traffic may include source and destination addresses and performance-related messages (e.g., reflecting current or expected bandwidth, latency, error rate, etc.). Although not the intended recipient of the traffic, switch 200 may observe and / or measure the traffic to determine when a change in link state is useful or necessary. For example, switch 200 may measure the current bandwidth and determine whether the current bandwidth meets one or more thresholds that trigger a link bandwidth update. In another example, switch 200 may examine performance-related messages in the traffic to determine whether to update the link bandwidth. Performance-related messages may conform to the protocol of the communication interface, and message inspection at switch 200 may be part of the protocol or may be a non-protocol activity. An example of a performance-related message that can be observed by the switch 200 in a PCIe embodiment is a delay-tolerant (LTR) message.

[0024] Figure 3B This is a block diagram illustrating example communication 320 between device 310 and switch 200 according to an embodiment. As depicted, device 310 sends one or more messages to switch 200 via API module 240 of switch 200. These messages may contain link metadata, requests, instructions, etc. For example, a message may request negotiation of new link bandwidth between device 310 and switch 200. The message may conform to the protocol of the communication interface or may be a vendor-specific (e.g., non-protocol) message supported by switch 200.

[0025] Figure 3CThis is a block diagram illustrating example communication 330 between application 280 and switch 200 according to an embodiment. As depicted, application 280 is associated with device 312 and sends one or more messages to switch 200 via API module 240 through device 312. These messages may contain link metadata, requests, instructions, etc. For example, a message may provide or indicate one or more link bandwidth policies to be implemented by switch 200. In another example, a message may indicate the current or expected traffic pattern of the link between device 312 and switch 200 (and potentially other devices involved in the application), such as current / expected bandwidth, data / usage type, allowable latency, etc. The message may conform to the protocol of the communication interface or may be a vendor-specific message supported by switch 200. The message may originate directly from application 280, associated drivers (e.g., drivers for device 312 or switch 200), or other software endpoints.

[0026] Figures 4A-4D Example link bandwidth policies 400-430 for switch 200 according to embodiments are described. (Reference) Figure 4A Policy 400 is a follow-only policy, where switch 200 supports pass-through for existing protocols (e.g., L0p) but does not initiate any link bandwidth updates. (See reference) Figure 4B Strategy 410 is a downstream-to-the-port pass-through strategy, whereby when a request is sent to the downstream-to-the-port, switch 200 initiates a matching link bandwidth update on the upstream-to-the-port. (Reference) Figure 4C Strategy 420 is a downstream-facing port aggregation strategy, in which switch 200 initiates link bandwidth updates on upstream-facing ports based on a combination of the states of one or more downstream-facing ports. For example, switch 200 may initiate a link bandwidth update corresponding to the sum of the link bandwidths of the downstream-facing ports or the maximum value of the link bandwidths of the downstream-facing ports. In another example, switch 200 may use lookup table 422 to select the link bandwidth update for the upstream-facing port based on the state of the downstream-facing ports. (See reference...) Figure 4D Strategy 430 is an upstream-to-the-port pass-through strategy, in which when an upstream-to-the-port sends a request, switch 200 initiates a matching link bandwidth update on one or more downstream-to-the-ports.

[0027] Figures 4A-4D Other strategies not described herein may also be used with switch 200. For example, a strategy based on hardware bandwidth monitoring (e.g., performed by traffic observation module 230) may use one or more thresholds to trigger link bandwidth updates. Other strategies may rely on triggers from software endpoints, such as software requests for updated link bandwidth.

[0028] Figure 5 This is a flowchart of an example method 500 for changing the state in a communication interface link using switch policies and APIs according to at least one embodiment. Method 500 can be executed by processing logic, which may include hardware (e.g., circuitry, dedicated logic, etc.), computer-readable instructions such as software or firmware (e.g., running on a general-purpose computing system or a dedicated machine), or a combination thereof. For example, the example system may include a memory and a processing device coupled to the memory device to perform operations including the block of method 500. Method 500 may also be associated with a set of instructions stored on a non-transitory computer-readable medium (e.g., a disk or optical disk, etc.). When executed by the processing device, the instructions may cause the processing device to perform operations including the block of method 500. In at least one embodiment, method 500 is performed by… Figure 1A-1D Switch 110, Figure 2 The method is performed by the switch 200 or its components. In at least one embodiment, the method 500 is performed by... Figure 8 The computing system 800 executes. In some embodiments, Figure 5 The boxes depicted may be executed simultaneously or in a different order than those depicted. Various embodiments may include... Figure 5 Additional boxes not depicted in the text or Figure 5 A subset of the boxes depicted in the text.

[0029] At block 502, the processing logic of the switch associated with the multi-channel communication interface receives an indication to apply one of multiple link width reset policies. This indication can be the policy itself or a reference to a policy stored at the switch (or otherwise available) (e.g., link bandwidth policy 250). In one embodiment, the indication to apply the link width reset policy is associated with an application (e.g., application 280), which could be a high-performance computing (HPC) application, an artificial intelligence (AI) application, a gaming application, or other types of applications. For example, the system (e.g., a driver) can identify or infer (e.g., based on submitted work / data) the type of application in use and provide the switch with an appropriate policy indication. In another example, the system can identify a specific application (e.g., a specific game, a specific HPC application, etc.) and provide the switch with an appropriate policy indication. In one embodiment, this indication can be a runtime update based on changing workloads or user reconfiguration.

[0030] At block 504, the processing logic determines a link bandwidth update for the link between the first device and one of the multiple ports of the switch. This link can be one of the communication interface links 210A-N, and multiple ports can be associated with corresponding links in the communication interface links 210A-N. The link bandwidth update can be determined by the switch in various ways, such as by monitoring link traffic and / or receiving messages at the switch's API. In one example, the switch can receive a request from the first device to reset the link width of the first port to a second link width. This request can be directed to the switch itself, for example, via the switch's API (such as a vendor-specific protocol). In a second example, the switch can receive a performance-related message from the first device, which can conform to the protocol of the communication interface (e.g., the PCIe protocol) and can be directed to another device connected to the switch. The performance-related message can provide performance data (e.g., bandwidth, latency, error rate) or can be a performance request (e.g., changing link bandwidth or latency). A L0p Latency Tolerance (LTR) message is an example of this type of performance-related message. In a third example, the switch can determine a bandwidth utilization metric based on the data flow observed at the first port. The data stream observed at the first port can include traffic volume, message error rate, latency, or similar metrics. These metrics can be used individually or in combination to derive bandwidth utilization metrics.

[0031] At box 506, the processing logic determines the first link width associated with the second port among multiple ports of the switch based on link bandwidth update and link width reset policies. (See reference) Figure 4A Various link width reset policies are described. For example, the first port can be a downstream-facing port, the second port can be an upstream-facing port, the link width reset policy can be a pass-through policy (e.g., policy 410), and the first link width can be equal to the second link width. In another example, the first port can be a downstream-facing port, the second port can be an upstream-facing port, one or more downstream-facing third ports can be associated with one or more corresponding third link widths, and the first link width can be equal to the second link width and the sum or maximum of one or more corresponding third link widths (e.g., policy 420). In yet another example, the first port can be an upstream-facing port, the second port can be a downstream-facing port, the link width reset policy can be a pass-through policy (e.g., policy 430), the first link width can be equal to the second link width, and the processing logic can also send a request to a third device connected to a downstream-facing third port among multiple ports of the switch to reset the link width of the third port to the first link width.

[0032] At block 508, the processing logic sends a request to a second device connected to the second port to reset the link width of the second port to the first link width. This request may conform to the protocol of the communication interface or may be a vendor-specific protocol. In one embodiment, the first port and the second port are the same port, and the first device and the second device are the same device. For example, the switch may observe traffic patterns originating from the first device and then send a request to reset the link with the first device based on the observed traffic patterns and one or more policies.

[0033] In one embodiment, a switch is one of a plurality of logical switches hosted by a physical switch. The links and ports described above can belong to one of the plurality of logical switches, and a link width reset policy can be applied to one or more of the plurality of logical switches. For example, an embodiment of a physical PCIe switch can be partitioned such that a first subset of the physical switch's channels is associated with a first logical switch and a second subset of the physical switch's channels is associated with a second logical switch. In another example, a physical Ethernet switch can operate as one or more logical switches for Ethernet frames with VLAN tags.

[0034] Figure 6 This is a flowchart of an example method 600 for updating link bandwidth in a communication interface link according to at least one embodiment. Method 600 can be executed by processing logic, which may include hardware (e.g., circuitry, dedicated logic, etc.), computer-readable instructions such as software or firmware (e.g., running on a general-purpose computing system or a dedicated machine), or a combination thereof. For example, the example system may include a memory and a processing device coupled to the memory device to perform operations including the block of method 600. Method 600 may also be associated with a set of instructions stored on a non-transitory computer-readable medium (e.g., a disk or optical disk, etc.). When executed by the processing device, the instructions may cause the processing device to perform operations including the block of method 600. In at least one embodiment, method 600 is performed by… Figure 1A-1D Switch 110, Figure 2 The method 600 is performed by the switch 200 or its components. In at least one embodiment, the method 600 is performed by... Figure 8 The computing system 800 executes. In some embodiments, Figure 6 The boxes depicted may be executed simultaneously or in a different order than those depicted. Various embodiments may include... Figure 6 Additional boxes not depicted in the text or Figure 6 A subset of the boxes depicted in the text.

[0035] At block 602, the processing logic of a switch connected to multiple devices via multiple corresponding links receives a request from a first device connected to the switch via a first link to change the bandwidth of the first link. In one embodiment, the request (e.g., a vendor-specific message) is received via the switch's API.

[0036] At block 604, processing logic determines a new bandwidth for a corresponding link between the switch and at least one of a plurality of devices. In one embodiment, the new bandwidth for the corresponding link is determined via an API based on a performance request or other performance-related message received at the switch (e.g., at switch API module 240). In one embodiment, the determination is based on traffic flow measured at the switch (e.g., via traffic observation module 230). In one embodiment, the determination is based on the switch's link bandwidth policy (e.g., one of the link bandwidth policies in link bandwidth policy 250). In one embodiment, the link bandwidth policy is associated with an application type or a specific application (such as HPC applications, AI applications, gaming applications, etc., as described above). In one embodiment, the first device in block 602 is different from at least one device in block 604. In one embodiment, the first device is included in at least one device.

[0037] At block 606, the processing logic initiates a change in the bandwidth of a corresponding link between the switch and at least one device, wherein initiating the change in bandwidth of the corresponding link includes sending a bandwidth change request to at least one device. This bandwidth change request may conform to the protocol of the communication interface or may be a vendor-specific message. In one embodiment, the switch is associated with a multi-channel communication interface, and the request to change the bandwidth of the corresponding link is a request to reset the link width of the corresponding link.

[0038] Figure 7 This is a flowchart of an example method 700 for determining a link bandwidth update in a communication interface link according to at least one embodiment. Method 700 can be executed by processing logic, which may include hardware (e.g., circuitry, dedicated logic, etc.), computer-readable instructions such as software or firmware (e.g., running on a general-purpose computing system or a dedicated machine), or a combination thereof. For example, the example system may include a memory and a processing device coupled to the memory device to perform operations including the block of method 700. Method 700 may also be associated with a set of instructions stored on a non-transitory computer-readable medium (e.g., a disk or optical disk, etc.). When executed by the processing device, the instructions may cause the processing device to perform operations including the block of method 700. In at least one embodiment, method 700 is performed by… Figure 1A-1D Switch 110, Figure 2 The method 700 is performed by the switch 200 or its components. In at least one embodiment, the method 700 is performed by... Figure 8 The computing system 800 executes. In some embodiments, Figure 7 The boxes depicted may be executed simultaneously or in a different order than those depicted. Various embodiments may include... Figure 7 Additional boxes not depicted in the text or Figure 7 A subset of the boxes depicted in the text.

[0039] At box 702, the processing logic of a switch connected to multiple devices via multiple corresponding links of a communication interface receives the link bandwidth policy from the application. The application can be a specific application or application type, such as HPC applications, AI applications, gaming applications, etc., as previously described.

[0040] At block 704A, processing logic receives a performance message conforming to a protocol of the communication interface from a first device among a plurality of devices. In one embodiment, the performance message is associated with the bandwidth or latency of the first link. In another embodiment, the received performance message is to be forwarded to a second device among the plurality of devices. For example, the performance message may be a latency-tolerant (LTR) message addressed to the second device.

[0041] Alternatively, at block 704B, the processing logic receives a performance message conforming to the switch's API (such as a vendor-specified protocol) from a first device among a plurality of devices. In one embodiment, the received performance message is a request to update the first bandwidth of the first link.

[0042] Alternatively, at box 704C, the processing logic receives performance messages from a software endpoint that conform to the switch's API. For example, a driver or application can communicate current or expected traffic patterns to the switch via the API.

[0043] At box 706, the processing logic determines, based on the received performance message and link bandwidth policy, that the first bandwidth of the first link between the switch and the first device among multiple devices should be updated to the second bandwidth.

[0044] At block 708, the processing logic causes the first bandwidth of the first link to be updated to a second bandwidth. For example, the processing logic may send a message or otherwise negotiate a bandwidth update with the linked device. In one embodiment, the switch is associated with a multi-channel communication interface, and causing the first bandwidth of the first link to be updated to the second bandwidth includes: resetting the first link width associated with the first bandwidth to the second link width associated with the second bandwidth.

[0045] Figure 8This is a block diagram illustrating an exemplary computer system according to at least one embodiment. The exemplary computer system may be a system having interconnect devices and components, a system-on-a-chip (SOC), or some combination thereof formed with a processor 800, which may include an execution unit for executing instructions. In at least one embodiment, according to this disclosure (such as in the embodiments described herein), the computing system 800 may include, but is not limited to, components such as a processor 802 employing an execution unit including logic for performing algorithms for processing data. In at least one embodiment, the computer system 800 may include processors available from Intel Corporation, Santa Clara, California, such as the Pentium® processor family, Xeon™, Itanium®, XScale™ and / or StrongARM™, Intel® Core. TM Or Intel® Nervana TM The microprocessor may also be used, although other systems (including PCs, engineering workstations, set-top boxes, etc.) with other microprocessors may also be used. In at least one embodiment, the computer system 800 may execute a version of the Windows operating system available from Microsoft Corporation, Redmond, Washington, although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0046] These embodiments can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor (“DSP”), a system-on-a-chip, a network computer (“NetPC”), a set-top box, a network hub, a wide area network (“WAN”) switch, an edge device, an Internet of Things (“IoT”) device, or any other system that can execute one or more instructions according to at least one embodiment.

[0047] In at least one embodiment, the computer system 800 may include, but is not limited to, a processor 802, which may include, but is not limited to, one or more execution units 808 for performing machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, the computer system 800 is a single-processor desktop or server system, but in another embodiment, the computer 800 may be a multiprocessor system. In at least one embodiment, the processor 802 may include, but is not limited to, a Complex Instruction Set Computer (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, a processor implementing instruction set combinations, or any other processor device, such as, for example, a digital signal processor. In at least one embodiment, the processor 802 may be coupled to a processor bus 810, which may transmit data signals between the processor 802 and other components in the computer system 800.

[0048] In at least one embodiment, processor 802 may include, but is not limited to, a level 1 (“L1”) internal cache memory (“cache”) 804. In at least one embodiment, processor 802 may have a single internal cache or multiple internal cache levels. In at least one embodiment, the cache memory may reside external to processor 802. Depending on the specific implementation and requirements, other embodiments may also include a combination of both internal and external caches. In at least one embodiment, register file 806 may store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0049] In at least one embodiment, execution unit 808 (including, but not limited to, logic for performing integer and floating-point operations) also resides in processor 802. In at least one embodiment, processor 802 may further include a microcode (“ucode”) read-only memory (“ROM”) storing microcode for certain macro instructions. In at least one embodiment, execution unit 808 may include logic for disposing of packaged instruction set 809. In at least one embodiment, by including packaged instruction set 809 along with associated circuitry for executing instructions in the instruction set of general-purpose processor 802, packaged data in general-purpose processor 802 can be used to perform operations used by many multimedia applications. In one or more embodiments, by using the full width of the processor data bus to perform operations on packaged data, many multimedia applications can be executed more quickly and efficiently, thereby eliminating the need to transfer smaller data units across the processor data bus to perform one or more operations at a time.

[0050] In at least one embodiment, execution unit 808 may also be used as a microcontroller, embedded processor, graphics device, DSP, and other types of logic circuitry. In at least one embodiment, computer system 800 may include, but is not limited to, memory 820. In at least one embodiment, memory 820 may be implemented as a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a flash memory device, or other memory device. In at least one embodiment, memory 820 may store one or more instructions 819 and / or data 821 represented by data signals executable by processor 802.

[0051] In at least one embodiment, the system logic chip may be coupled to a processor bus 810 and a memory 820. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 816, and the processor 802 may communicate with the MCH 816 via the processor bus 810. In at least one embodiment, the MCH 816 may provide a high-bandwidth memory path 818 to the memory 820 for storing instructions and data, and for storing graphics commands, data, and textures. In at least one embodiment, the MCH 816 may direct data signals between the processor 802, the memory 820, and other components in the computer system 800, and bridge data signals between the processor bus 810, the memory 820, and the system I / O 822. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 816 may be coupled to the memory 820 via the high-bandwidth memory path 818, and the graphics / video card 812 may be coupled to the MCH 816 via an Accelerated Graphics Port (“AGP”) interconnect 814.

[0052] In at least one embodiment, computer system 800 may use system I / O 822, which serves as a proprietary hub interface bus, to couple MCH 816 to I / O controller hub (“ICH”) 830. In at least one embodiment, ICH 830 may provide direct connectivity to some I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to memory 820, chipset, and processor 802. Examples may include, but are not limited to, an audio controller 829, a firmware hub (“Flash BIOS”) 828, a wireless transceiver 826, a data storage device 824, a conventional I / O controller 823 including a user input and keyboard interface 825, a serial expansion port 827 (such as Universal Serial Bus (“USB”)), and a network controller 834, which in some embodiments may include a data processing unit. Data storage device 824 may include a hard disk drive, floppy disk drive, CD-ROM device, flash memory device, or other mass storage device.

[0053] In at least one embodiment, Figure 8 The illustration depicts a system including interconnecting hardware devices or "chips," while in other embodiments, Figure 8 An exemplary system-on-a-chip (“SoC”) may be illustrated. In at least one embodiment, the devices may be interconnected via proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 800 are interconnected using compute fast link (CXL) interconnects. In at least one embodiment, system 800 may correspond to system 100A-D or components thereof, such as devices 120A-N, 130A-N, 140A-N, 200 and connection links 122A-N, 124A-N, 132A-N, 142A-N, and 210A-N.

[0054] Figure 9This is a block diagram of a computing system 900 having two processing devices coupled to each other and multiple networks according to at least one embodiment. The computing system 900 is designed with multiple integrated circuits (referred to as processing devices), each including a CPU and two GPUs, forming a powerful and flexible architecture. These processing devices are interconnected via NVLink (or other high-speed interconnects) to enable high-speed communication between the processing devices; and are also connected via network interface cards (NICs) or data processing units (DPUs) to ensure efficient data transfer across the computing system 900. Coupling the processing devices via NVLink enables seamless data exchange and parallel processing, thereby improving overall computing performance. Additionally, these processing devices are connected to multiple networks via one or more network interface cards (NICs) or DPUs, enabling the system to handle complex multi-network tasks with high bandwidth and low latency. This configuration makes the computing system 900 ideal for demanding applications requiring high processing power, such as artificial intelligence (AI), machine learning (ML), and data-intensive computing, while ensuring robust connectivity and scalability across various networked environments. The integrated circuits of the computing system 900 may include one or more CPUs and one or more GPUs. Figure 9 The diagram illustrates an example architecture for a multi-GPU architecture.

[0055] like Figure 9 As illustrated, the computing system 900 includes a processing device 902 with a multi-GPU architecture. Specifically, the processing device 902 includes a CPU 906, a GPU 908, and a GPU 910. The CPU 906 can be coupled to the GPU 908 via die-to-die (D2D) or chip-to-chip (C2C) interconnects 912 (such as a Ground Reference Signaling Interconnect (GRS interconnect)). The CPU 906 can be coupled to the GPU 910 via a D2D or C2C interconnect 914. The CPU 906 can also be coupled to the GPU 908 and GPU 910 via a PCIe interconnect. The CPU 906 can be coupled to one or more network interface cards (NICs) or data processing units (DPUs), which in turn are coupled to one or more networks. For example, as... Figure 9 As illustrated, CPU 906 is coupled to a first NIC / DPU 926, which in turn is coupled to network 930. CPU 906 is also coupled to a second NIC / DPU 928, which is also coupled to network 930. NIC / DPU 926 and NIC / DPU 928 can be coupled to network 930 via Ethernet (ETH) or InfiniBand (IB) connections.

[0056] The computing system 900 also includes a processing device 904 with a multi-GPU architecture. Specifically, the processing device 904 includes a CPU 916, a GPU 918, and a GPU 920. The CPU 916 can be coupled to the GPU 918 via a D2D or C2C interconnect 922. The CPU 916 can be coupled to the GPU 920 via a D2D or C2C interconnect 924. The CPU 916 can also be coupled to the GPU 918 and GPU 920 via a PCIe interconnect. The CPU 916 can be coupled to one or more NICs or DPUs, which in turn are coupled to one or more networks. For example, as... Figure 9 As illustrated, CPU 916 is coupled to a first NIC / DPU 932, which in turn is coupled to network 936. CPU 916 is also coupled to a second NIC / DPU 934, which is also coupled to network 936. NIC / DPU 932 and NIC / DPU 934 can be coupled to network 936 via Ethernet (ETH) or InfiniBand (IB) connections.

[0057] In at least one embodiment, processing device 902 and processing device 904 can communicate with each other via NIC / DPU 938 (such as via PCIe interconnect). Processing device 902 and processing device 904 can also communicate with each other via high-bandwidth communication interconnect 940 (such as NVLink interconnect or other high-speed interconnect).

[0058] In at least one embodiment, the computing system 900 is used for high-speed network communication and includes processing units (e.g., CPU 906, GPU 908, GPU 910, CPU 916, GPU 918, GPU 920, NIC / DPU 926, NIC / DBU 928, NIC / DDU 932, NIC / DMU 934, or NIC / DPU 938), memory coupled to one or more processing units, and a network interface coupled to one or more processing units and memory via a link through a communication interface. In various embodiments, one or more linked devices may include reference devices. Figure 2 The described component is used to change the state of a communication interface link using switch policies and APIs.

[0059] Figure 10This is a block diagram of a computing system 1000 having a CPU 1002 and a GPU 1004 on a single integrated circuit, according to at least one embodiment. The computing system 1000 can be a highly integrated design in which the CPU 1002 and GPU 1004 are connected on a single integrated circuit, thereby enabling fast, low-latency communication between the two processing units using NVLink C2C (chip-to-chip) interconnect 1006. This tight integration allows for efficient data transfer and parallel processing between the CPU 1002 and GPU 1004, thereby optimizing the execution of complex computational tasks. The GPU elements within the computing system 1000 can be interconnected using an NVLink network, allowing for scalability of up to 256 GPU elements, creating a robust and unified processing environment particularly suitable for large-scale AI, ML, and high-performance computing applications. The NVLink network can be a GPU construct of a high-bandwidth communication interconnect 1010. Additionally, the computing system 1000 can be designed to connect to a high-speed I / O interface via a PCIe interconnect 1008, thereby ensuring rapid data transfer with external devices, further enhancing the system's ability to handle data-intensive tasks, and providing robust connectivity to peripheral components. It should be noted that since the CPU 1002 and GPU 1004 reside on the same integrated circuit, the C2C interconnect 1006 can be considered a D2D interconnect. The integrated circuit may include CPU memory (also referred to as main memory) and GPU memory, which the CPU 1002 and GPU 1004 can access respectively via the high-speed interconnect. The computing system 1000 can integrate the performance of the GPU 1004 with the versatility of the CPU 1002. The CPU 1002 can be connected to a high-bandwidth and memory-coherent C2C interconnect 1006 within a single integrated circuit. The computing system 1000 can support a link-switching system.

[0060] In at least one embodiment, the computing system 1000 is used for high-speed network communication and includes processing units (e.g., CPU 1002, GPU 1004, NVLink network), memory coupled to one or more processing units, and a network interface coupled to one or more processing units and memory via a link of a communication interface. In various embodiments, one or more linked devices may include reference devices. Figure 2 The described component is used to change the state of a communication interface link using switch policies and APIs.

[0061] Figure 11This is a block diagram of a computing system 1100 having a tensor core GPU 1108 according to at least one embodiment. The computing system 1100 may be a DGX H100 system, which is a high-performance computing platform designed to meet the needs of AL, ML, and deep learning (DL) workloads. The computing system 1100 may include multiple tensor core GPUs 1108 (e.g., NVIDIA H100 tensor core GPUs). Each of the tensor core GPUs 1108 may be one described above. Figure 10 One of the integrated circuits described is the Tensor Core GPU 1108, which is optimized for AI / ML / DL applications, delivering superior performance for deep learning training, inference, and high-performance computing tasks. The Tensor Core GPUs 1108 within the computing system 1100 are interconnected using high-speed communication interfaces such as NVLink, enabling rapid data transfer between them, which is crucial for handling large-scale AI models and datasets with low latency. The computing system 1100 is designed for scalability, allowing additional GPUs to be integrated as needed, making it sufficiently versatile for research, development, and deployment in data centers used for production AI workloads. Each GPU is equipped with a Tensor Core, a dedicated processing unit that accelerates matrix operations and is a fundamental component of AI and deep learning algorithms. These Tensor Cores enable the system to perform mixed-precision computations efficiently, balancing speed and accuracy. Given the power consumption and heat generation of multiple Tensor Core GPUs 1108, the computing system 1100 may include advanced cooling solutions and power management features to ensure safe operation while maintaining peak performance. It is powered by a comprehensive software ecosystem that includes NVIDIA's CUDA programming model, AI frameworks such as TensorFlow and PyTorch, and other HPC and AI software tools that enable developers and researchers to leverage the full power of the TensorCore GPU 1108 for their specific applications. The Computing System 1100 is ideally suited for large-scale AI model training, real-time inference, scientific simulations, data analysis, and other compute-intensive tasks requiring significant parallel processing power.

[0062] The Tensor Core GPU 1108 can be coupled to multiple CPUs, such as CPU 1102 and CPU 1104, using a switch 1106 (e.g., a CX7 HCA / NIC with a PCIe switch). The Tensor Core GPU 1108 can be coupled to each other via a switch 1110 (e.g., an NVSwitch). Switches 1106 and 1110 can be coupled to a high-speed transceiver module 1112. The high-speed transceiver module 1112 can be an Octal Small Pluggable (OSFP) module. OSFP modules are high-speed transceiver modules designed for fast data communication, specifically in environments requiring high bandwidth, such as data centers and high-performance computing systems. These modules support extremely high data rates, typically up to 400 Gbps per module, with future expansion capabilities to 800 Gbps or higher. OSFP modules interface with the system via a PCIe interface, enabling fast and efficient data transfer between the integrated CPU-GPU components and external networks or other connected systems. Their hot-swappable nature allows for easy insertion or removal without shutting down the system, providing flexibility and maintainability crucial in critical uptime environments. Additionally, OSFP modules are designed for high density, maximizing the number of high-speed connections within limited spaces, such as densely packed server racks. By complying with the latest networking standards, OSFP modules ensure the Computing System 1100 can meet ever-increasing data demands and can be upgraded to support future network speed increases, thus contributing to improved overall system performance and scalability.

[0063] In at least one embodiment, the computing system 1100 can be viewed as a data network configuration with full-bandwidth in-server NVLink. In this example, all eight tensor core GPUs 1108 can simultaneously saturate eighteen NVLinks of other GPUs within the server. Bandwidth is limited by oversubscription from multiple other GPUs. In another embodiment, the data network configuration can be half-bandwidth in-server NVLink. In this example, all eight tensor core GPUs 1108 can subscribe to eighteen NVLinks from GPUs in other servers. Four tensor core GPUs 1108 can saturate eighteen NVLinks of GPUs in other servers. This is equivalent to full bandwidth on all-reduce with a scalable hierarchical aggregation and reduction protocol (SHARP). The reduction of all-to-all (all-2-all, All2All) bandwidth is a trade-off between server complexity and cost. In at least one embodiment, all eight tensor core GPUs 1108 can independently transmit data in a multi-track InfiniBand / Ethernet configuration using the Remote Direct Memory Access (RDMA) protocol via their own dedicated switches (e.g., 400Gb / s HCA / NIC). In this example, the total full-duplex bandwidth for non-NVLink network devices is 800 GB / s.

[0064] In at least one embodiment, the computing system 1100 is used for high-speed network communication and includes a processing unit (e.g., CPU 1102, switch 1106, tensor core GPU 1108, switch 1110, high-speed transceiver module 1112) and a network interface coupled to the processing unit via a link through a communication interface. In various embodiments, one or more of the linked devices may include reference devices. Figure 2 The described component is used to change the state of a communication interface link using switch policies and APIs.

[0065] Other variations are within the spirit of this disclosure. Therefore, while the disclosed technology is susceptible to various modifications and alternative constructions, certain illustrated embodiments are shown in the accompanying drawings and have been described in detail above. However, it should be understood that this disclosure is not intended to be limited to one or more specific forms disclosed, but rather is intended to cover all modifications, alternative constructions, and equivalents falling within the spirit and scope of this disclosure as defined by the appended claims.

[0066] Unless otherwise indicated herein or obviously contradicted by the context, the terms “a,” “an,” and “the,” and similar designations, used in the context of describing the disclosed embodiments (especially in the context of the following claims), should be interpreted as encompassing both the singular and plural, and not as definitions of the terms. Unless otherwise stated, the terms “comprising,” “having,” “including,” and “containing” are to be interpreted as open-ended terms (meaning “including, but not limited to”). The term “connection,” when unmodified and referring to a physical connection, is to be interpreted as partially or completely contained, attached to, or combined, even with intervening elements. Unless otherwise indicated herein, statements of value ranges herein are intended only as a shorthand for individually referring to each individual value falling within the range, and each individual value is incorporated into the specification as if it were individually stated herein. Unless otherwise indicated or contradicted by the context, the use of the terms “set” (e.g., “item set”) or “subset” is to be interpreted as a non-empty set comprising one or more members. Furthermore, unless otherwise indicated or contradicted by the context, the term "subset" in the context of a corresponding set does not necessarily mean a proper subset of the corresponding set, but rather that a subset and the corresponding set can be equal.

[0067] Unless explicitly stated otherwise or clearly contradicted by the context, connective language (such as phrases of the form "at least one of A, B, and C" or "at least one of A, B, and C") is otherwise understood, along with the context, as generally used to represent any non-empty subset of a set, such as items, terms, etc., that can be A or B or C, or A and B and C. For example, in an illustrative example of a set with three members, the connective phrases "at least one of A, B, and C" and "at least one of A, B, and C" refer to any of the following sets: {A}, {B}, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}. Therefore, such connective language is generally not intended to imply that certain embodiments require the existence of at least one of A, at least one of B, and at least one of C. Additionally, unless otherwise indicated by or contradicted by the context, the term "multiple" indicates a state of multiple (e.g., "multiple items" indicates many items). Multiple means at least two items, but can be more when explicitly indicated or indicated by the context. Furthermore, unless otherwise stated or clearly implied by the context, the phrase “based on” means “at least partially based on” rather than “based on only”.

[0068] Unless otherwise indicated herein or clearly contradicted by the context, the operations of the processes described herein may be performed in any suitable order. In at least one embodiment, processes such as those described herein (or variations and / or combinations thereof) are executed under the control of one or more computer systems configured with executable instructions and are implemented by hardware or a combination thereof as code (e.g., executable instructions, one or more computer programs, or one or more application programs) that executes jointly on one or more processors. In at least one embodiment, the code is stored on a computer-readable storage medium, for example, in the form of a computer program comprising a plurality of instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable storage medium that does not include transient signals (e.g., propagation of transient electrical or electromagnetic transmissions) but includes non-transitory data storage circuitry (e.g., buffers, caches, and queues) within a transceiver that includes transient signals. In at least one embodiment, code (e.g., executable code or source code) is stored on a set of one or more non-transitory computer-readable storage media (or other memory for storing executable instructions) that, when executed by one or more processors of a computer system (i.e., due to being executed), cause the computer system to perform the operations described herein. In at least one embodiment, the set of non-transitory computer-readable storage media comprises a plurality of non-transitory computer-readable storage media, and one or more of the various non-transitory storage media lack all the code, while the plurality of non-transitory computer-readable storage media collectively store all the code. In at least one embodiment, the executable instructions are executed such that different instructions are executed by different processors; i.e., for example, the non-transitory computer-readable storage media stores the instructions, and the main central processing unit (“CPU”) executes some of the instructions, while the graphics processing unit (“GPU”) executes the others. In at least one embodiment, different components of the computer system have separate processors, and different processors execute different subsets of instructions.

[0069] Therefore, in at least one embodiment, the computer system is configured to implement one or more services that individually or collectively perform the processes described herein, and such a computer system is configured with applicable hardware and / or software capable of performing the operations. Further, the computer system implementing at least one embodiment of this disclosure is a single device, and in another embodiment, it is a distributed computer system comprising multiple devices that operate in different ways such that the distributed computer system performs the operations described herein, and that a single device does not perform all the operations.

[0070] The use of any and all examples or exemplary language (e.g., “such as”) provided herein is intended only to better illustrate embodiments of this disclosure and, unless otherwise required, does not constitute a limitation on the scope of the disclosure. No language in the specification should be construed as indicating that any unclaimed element is essential for implementing this disclosure.

[0071] All references cited herein, including publications, patent applications and patents, are incorporated herein by reference to the same extent that each reference is separately and specifically indicated to be incorporated by reference and fully elaborated herein.

[0072] The terms “coupled” and “connected” and their derivatives may be used in the specification and claims. It should be understood that these terms are not intended to be synonyms with each other. Rather, in specific examples, “connected” or “coupled” can be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other. “Coupled” can also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

[0073] Unless otherwise explicitly stated, it should be understood throughout this specification that terms such as “processing,” “computing,” “calculating,” “determining,” etc., refer to the actions and / or processes of a computer or computing system or similar electronic computing device that manipulate and / or transform data representing physical (such as electronic) quantities in the registers and / or memory of the computing system into other data representing physical quantities in the memory, registers, or other such information storage, transmission, or display devices of the computing system.

[0074] Similarly, the term "processor" can refer to any device or part of a device that processes electronic data from registers and / or memory and transforms that electronic data into other electronic data that can be stored in registers and / or memory. As a non-limiting example, a "processor" can be a CPU or a GPU. A "computing platform" can include one or more processors. As used herein, a "software" process can include, for example, software and / or hardware entities that perform work over time, such as tasks, threads, and intelligent agents. Furthermore, each process can refer to multiple processes for executing instructions sequentially or in parallel, continuously or intermittently. The terms "system" and "method" are used interchangeably herein, provided that a system can embody one or more methods and a method can be considered a system.

[0075] This document describes the process of acquiring, obtaining, receiving, or inputting analog or digital data into a subsystem, computer system, or computer implementation machine. Acquiring, obtaining, receiving, or inputting analog and digital data can be accomplished in various ways, such as by receiving data as a parameter to a function call or a call to an application programming interface (API). In some implementations, the process of acquiring, obtaining, receiving, or inputting analog or digital data can be accomplished by transmitting data via a serial or parallel interface. In another implementation, the process of acquiring, obtaining, receiving, or inputting analog or digital data can be accomplished by transmitting data from a providing entity to an acquiring entity via a computer network. Reference can also be made to providing, outputting, transmitting, sending, or presenting analog or digital data. In various examples, the process of providing, outputting, transmitting, sending, or presenting analog or digital data can be accomplished by transmitting data as an input or output parameter to a function call, an API, or an inter-process communication mechanism.

[0076] While the foregoing discussion illustrates exemplary implementations of the described technologies, other architectures may also be used to implement the aforementioned functionality and are intended to fall within the scope of this disclosure. Furthermore, although specific assignments of responsibilities have been defined above for discussion purposes, various functions and responsibilities may be distributed and divided in different ways depending on the circumstances.

[0077] Furthermore, although the subject matter has been described in language specific to structural features and / or methodological actions, it should be understood that the subject matter claimed in the appended claims is not necessarily limited to the specific features or actions described. Rather, specific features and actions are disclosed as exemplary forms for implementing the claims.

Claims

1. A system comprising: A switch, which is connected to multiple devices via multiple corresponding links of a communication interface, wherein the switch is used to perform operations including the following: Receive performance messages conforming to the protocol of the communication interface from the first device among the plurality of devices; as well as Based on the received performance message and link bandwidth policy, it is determined that the first bandwidth of the first link between the switch and the first device among the plurality of devices should be updated to the second bandwidth.

2. The system of claim 1, wherein the operation further includes: This causes the first bandwidth of the first link to be updated to the second bandwidth.

3. The system of claim 2, wherein the switch is associated with a multi-channel communication interface, and wherein updating the first bandwidth of the first link to the second bandwidth comprises: This causes the first link width associated with the first bandwidth to be reset to the second link width associated with the second bandwidth.

4. The system of claim 1, wherein the received performance message is to be forwarded to a second device among the plurality of devices.

5. The system of claim 1, wherein the link bandwidth policy is associated with an application, and wherein the application is one of the following: a high-performance computing (HPC) application, an artificial intelligence (AI) application, or a gaming application.

6. The system of claim 5, wherein the operation further comprises: Receive the link bandwidth policy from the application.

7. The system of claim 1, wherein the performance message is associated with the first bandwidth of the first link or the latency of the first link.

8. A system comprising: A switch, which is connected to multiple devices via multiple corresponding links of a communication interface, wherein the switch is used to perform operations including the following: Receive a performance message conforming to the application programming interface (API) of the switch from the first of the plurality of devices; as well as Based on the received performance message and link bandwidth policy, it is determined that the first bandwidth of the first link between the switch and the first device among the plurality of devices should be updated to the second bandwidth.

9. The system of claim 8, wherein the operation further comprises: This causes the first bandwidth of the first link to be updated to the second bandwidth.

10. The system of claim 9, wherein the switch is associated with a multi-channel communication interface, and wherein updating the first bandwidth of the first link to the second bandwidth comprises: This causes the first link width associated with the first bandwidth to be reset to the second link width associated with the second bandwidth.

11. The system of claim 8, wherein the received performance message is a request to update the first bandwidth of the first link.

12. The system of claim 8, wherein the link bandwidth policy is associated with an application, and wherein the application is one of the following: a high-performance computing (HPC) application, an artificial intelligence (AI) application, or a gaming application.

13. The system of claim 12, wherein the operation further comprises: Receive the link bandwidth policy from the application.

14. The system of claim 8, wherein the performance message is associated with the first bandwidth of the first link or the latency of the first link.

15. A system comprising: A switch, which is connected to multiple devices via multiple corresponding links of a communication interface, wherein the switch is used to perform operations including the following: Receive performance messages conforming to the application programming interface (API) of the switch from the software endpoint; as well as Based on the received performance message and link bandwidth policy, it is determined that the first bandwidth of the first link between the switch and the first device among the plurality of devices should be updated to the second bandwidth.

16. The system of claim 15, wherein the operation further comprises: This causes the first bandwidth of the first link to be updated to the second bandwidth.

17. The system of claim 16, wherein the switch is associated with a multi-channel communication interface, and wherein updating the first bandwidth of the first link to the second bandwidth comprises: This causes the first link width associated with the first bandwidth to be reset to the second link width associated with the second bandwidth.

18. The system of claim 15, wherein the link bandwidth policy is associated with an application, and wherein the application is one of the following: a high-performance computing (HPC) application, an artificial intelligence (AI) application, or a gaming application.

19. The system of claim 18, wherein the operation further comprises: Receive the link bandwidth policy from the application.

20. The system of claim 15, wherein the performance message is associated with the first bandwidth of the first link or the latency of the first link.

21. A system for high-speed network communication in a data center, the system comprising: One or more processing units; A memory coupled to one or more processing units; A switch, which is coupled to one or more processing units and the memory via multiple corresponding links; as well as A network interface coupled to the switch via the plurality of corresponding links, wherein the switch is configured to perform operations including the following: Receive performance messages conforming to the protocol of the communication interface from the network interface; as well as Based on the received performance message and link bandwidth policy, it is determined that the first bandwidth of the first link between the switch and the network interface should be updated to the second bandwidth.

22. The system of claim 21, wherein the operation further comprises: This causes the first bandwidth of the first link to be updated to the second bandwidth.

23. The system of claim 22, wherein the switch is associated with a multi-channel communication interface, and wherein updating the first bandwidth of the first link to the second bandwidth comprises: This causes the first link width associated with the first bandwidth to be reset to the second link width associated with the second bandwidth.

24. The system of claim 21, wherein the received performance message is to be forwarded to the second device.

25. The system of claim 21, wherein the link bandwidth policy is associated with an application, and wherein the application is one of the following: a high-performance computing (HPC) application, an artificial intelligence (AI) application, or a gaming application.

26. The system of claim 25, wherein the operation further comprises: Receive the link bandwidth policy from the application.

27. The system of claim 21, wherein the performance message is associated with the first bandwidth of the first link or the latency of the first link.

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