A packet processing method and switch device for a packet switching network

Abstract

The present disclosure relates to the technical field of data communication, and provides a packet processing method for a packet switching network and a switching device. The method comprises: receiving a data packet to be transmitted and determining single packet description information of the data packet; determining whether a first data packet and a subsequent data packet satisfy preset packet splicing conditions according to the single packet description information of the first data packet and the subsequent data packet; if the first data packet and the subsequent data packet satisfy a preset condition item, performing a packet splicing transmission operation matched with the preset condition item; and if the first data packet and the subsequent data packet do not satisfy all the preset condition items, independently transmitting the first data packet and the subsequent data packet, so that a scheduling module of the switching device starts to transmit the subsequent data packet in a next transmission cycle of the target transmission cycle. The technical scheme provided by one or more embodiments of the present disclosure can effectively improve the data packet scheduling efficiency and bandwidth resource utilization rate of the switching device.

Description

Technical Field

[0001] This disclosure relates to the field of data communication technology, specifically to a packet processing method and switching device for packet switching networks. Background Technology

[0002] As the core interconnection device in a network communication system, the quality of the internal switching architecture and scheduling algorithm of a switch can directly determine the throughput performance, transmission latency, and hardware implementation cost of the entire network communication system.

[0003] In existing data switching technology systems, data transmission typically employs two basic transmission units. One is the fixed-length "cell," commonly found in switching modes such as ATM (Asynchronous Transfer Mode), whose advantages lie in its simple scheduling rules and strong deterministic latency. The other is the variable-length "packet" or "frame," the most common transmission form in mainstream network environments such as Ethernet and PCIe (Peripheral Component Interconnect Express), but due to its variable length and diverse protocols, it requires more complex processing mechanisms during scheduling and forwarding. The complete packet processing flow encompasses multiple stages, including packet reception, fragmentation, route lookup, queue management, and scheduling and forwarding. Packet scheduling, as a crucial stage in this process, is responsible for determining the transmission order, timing, and channel allocation of each packet on the output port, fundamentally affecting the switching efficiency and bandwidth utilization of the switch.

[0004] However, traditional switching networks generally adopt a single-packet serial processing mode. Although they have basic packet processing capabilities, they lack mechanisms for multi-packet concurrent scheduling, dynamic adaptation of large and small packets, and cross-rule coordination. As a result, they suffer from problems such as low scheduling efficiency, high bandwidth waste, and high latency. Especially in multi-device, multi-channel scenarios, scheduling algorithms based on the single-packet serial processing mode are difficult to implement, have timing convergence difficulties, and are not easy to implement in hardware. Summary of the Invention

[0005] In view of this, one or more embodiments of this disclosure provide a packet processing method and switching device for packet switching networks, which can effectively improve the packet scheduling efficiency and bandwidth resource utilization of the switch in multi-device interconnection scenarios.

[0006] In a first aspect, this disclosure provides a packet processing method for packet-switched networks, applied to a switching device. The method includes: receiving data packets to be transmitted sent by various access devices connected to the switching device, and determining single-packet description information for each of the data packets to be transmitted, the single-packet description information including routing information, data structure information, and data volume information of the data packets to be transmitted; classifying and storing the data packets to be transmitted into various transmission buffer queues according to the single-packet description information, and performing queue arbitration on each of the transmission buffer queues; for the target queue that has obtained arbitration authorization in the transmission buffer queues, determining the first data packet based on the single-packet description information of the first data packet and subsequent data packets. The system checks whether the first data packet and the subsequent data packets meet any of the preset conditions in the preset packet assembly conditions. If the first data packet and the subsequent data packets meet any of the preset conditions, then a packet assembly transmission operation matching the preset condition is performed, so that the scheduling module of the switch device transmits the header control information of the first data packet and the header control information of the subsequent data packets together within the target transmission cycle for the complete transmission of the first data packet. If the first data packet and the subsequent data packets do not meet all the preset conditions, then the first data packet and the subsequent data packets are transmitted independently, so that the scheduling module of the switch device starts transmitting the subsequent data packets in the next transmission cycle of the target transmission cycle.

[0007] In one optional implementation, the preset condition includes a first condition, which includes: the routing information of the first data packet and the subsequent data packets are consistent; within one or more time periods corresponding to the target transmission period, the header control information channel of the switch device has an idle path for at least one of the time periods; and the subsequent data packets do not carry payload data.

[0008] In one optional implementation, when the first data packet and the subsequent data packets satisfy the first condition, the step of performing a packet concatenation transmission operation matching the preset condition includes: transmitting the load data of the first data packet through the load data channel of the switch device within the target transmission period; and transmitting the header control information of the first data packet and the header control information of the subsequent data packets through different paths of the header control information channel within the target transmission period.

[0009] In one optional implementation, the preset condition includes a second condition, which includes: the routing information of the first data packet and the subsequent data packets are consistent; in the last time period corresponding to the target transmission period, the first data length of the remaining load data of the first data packet is less than the bus width of the load data channel of the switch device in a single time period; and the sum of the first data length and the total length of the load data of at least one of the subsequent data packets is less than or equal to the bus width of the load data channel in a single time period.

[0010] In one optional implementation, when the first data packet and the subsequent data packets satisfy the second condition, the execution of the packet concatenation transmission operation matching the preset condition includes: transmitting the header control information of the subsequent data packets through an independent path of the header control information channel of the switch device during the last time period corresponding to the target transmission period; and merging and transmitting the remaining load data of the first data packet and the load data of the subsequent data packets through the load data channel during the last time period corresponding to the target transmission period.

[0011] In one optional implementation, the preset condition item includes a third condition item, which includes: the routing information of the first data packet and the subsequent data packets are consistent; the first data packet does not carry load data; the subsequent data packets do not carry load data, or the load data length of the subsequent data packets does not exceed the bus width of the load data channel of the switch device in a single time period.

[0012] In an optional implementation, when the first data packet and the subsequent data packets satisfy the third condition, performing a packet concatenation transmission operation matching the preset condition includes: within the target transmission period, transmitting the header control information of the first data packet and the header control information of the subsequent data packets respectively through different paths of the header control information channel of the switch device; within the target transmission period, if the subsequent data packets do not carry payload data, then idling the payload data channel of the switch device; if the subsequent data packets carry payload data, then transmitting the payload data of the subsequent data packets through the payload data channel.

[0013] In one optional implementation, the step of performing packet concatenation transmission operation matching the preset condition includes: integrating the single packet description information of the first data packet and the subsequent data packets into concatenation description information; and synchronously sending the concatenation description information to the scheduling module when transmitting the first data packet to the scheduling module.

[0014] Secondly, this disclosure provides a switching device for packet-switched networks. The switching device includes: a data packet receiving unit, configured to receive data packets to be transmitted sent by various access devices connected to the switching device, and determine single-packet description information for each data packet to be transmitted, the single-packet description information including routing information, data structure information, and data volume information of the data packet to be transmitted; a data packet caching unit, configured to classify and store the data packets to be transmitted into various transmission buffer queues according to the single-packet description information, and perform queue arbitration on each transmission buffer queue; and a packet assembly confirmation unit, configured to determine the first data packet for the target queue that has obtained arbitration authorization in the transmission buffer queues, based on the single-packet description information of the first data packet and subsequent data packets. The first packet and the subsequent data packets are configured to: 1) determine whether they satisfy any of the preset conditions in the preset packet concatenation conditions; 2) perform a packet concatenation transmission operation matching the preset condition if the first packet and the subsequent data packets satisfy any of the preset conditions, so that the scheduling module of the switch device transmits the header control information of the first packet and the header control information of the subsequent data packets together within the target transmission period for the complete transmission of the first packet; and 3) transmit the first packet and the subsequent data packets independently if they do not satisfy all the preset conditions, so that the scheduling module of the switch device starts transmitting the subsequent data packets in the next transmission period of the target transmission period.

[0015] In an optional implementation, the packet concatenation transmission unit is further configured to: integrate the single packet description information of the first data packet and the subsequent data packets into concatenation description information; and synchronously send the concatenation description information to the scheduling module when transmitting the first data packet to the scheduling module.

[0016] In one optional implementation, the preset condition includes a first condition, which includes: the routing information of the first data packet and the subsequent data packets are consistent; within one or more time periods corresponding to the target transmission period, the header control information channel of the switch device has an idle path for at least one of the time periods; and the subsequent data packets do not carry payload data. The packet transmission unit is specifically used for: transmitting the load data of the first data packet through the load data channel of the switch device within the target transmission period; and transmitting the header control information of the first data packet and the header control information of subsequent data packets through different paths of the header control information channel within the target transmission period.

[0017] In one optional implementation, the preset condition item includes a second condition item, which includes: the routing information of the first data packet and the subsequent data packets are consistent; in the last time period corresponding to the target transmission period, the first data length of the remaining load data of the first data packet is less than the bus width of the load data channel of the switch device in a single time period; the sum of the first data length and the total length of the load data of at least one of the subsequent data packets is less than or equal to the bus width of the load data channel in a single time period. The packet concatenation transmission unit is specifically used for: transmitting the header control information of the subsequent data packets through an independent path of the header control information channel of the switch device during the last time period corresponding to the target transmission period; and merging and transmitting the remaining load data of the first data packet and the load data of the subsequent data packets through the load data channel during the last time period corresponding to the target transmission period.

[0018] In one optional implementation, the preset condition item includes a third condition item, which includes: the routing information of the first data packet and the subsequent data packets are consistent; the first data packet does not carry load data; the subsequent data packets do not carry load data, or the load data length of the subsequent data packets does not exceed the bus width of the load data channel of the switch device in a single time period; The packet transmission unit is specifically used to: transmit the header control information of the first data packet and the header control information of the subsequent data packets respectively through different paths of the header control information channel of the switch device within the target transmission period; if the subsequent data packets do not carry payload data within the target transmission period, the payload data channel of the switch device is idle; if the subsequent data packets carry payload data, the payload data of the subsequent data packets is transmitted through the payload data channel.

[0019] This disclosure provides a technical solution through one or more embodiments, which determines the single-packet description information of each packet upon receiving the data packet. Subsequent queue classification and storage, queue arbitration, and packet assembly determination are all based on the single-packet description information, eliminating the need for repeated parsing of data packet content. For the target queue that has obtained arbitration authorization, it is determined whether any preset condition is met based on the description information of the first and subsequent data packets, and packet assembly or independent transmission operations are performed according to the determination result. This description-based preprocessing mechanism allows the switch's scheduling module to process multiple packets within a single clock cycle, but presents only a single scheduling request externally, simplifying the scheduler's state management.

[0020] This disclosure provides one or more embodiments of the technical solution that, in terms of bandwidth utilization and transmission delay, when the packet concatenation condition is met, transmits the header control information of the first packet and subsequent packets simultaneously within the target transmission cycle used for the complete transmission of the first packet. This allows the header control information of multiple packets to be output concurrently without waiting for subsequent independent transmission cycles, thereby reducing transmission delay. Regarding bandwidth utilization, packet concatenation can merge multiple packets for processing, matching the egress bandwidth of the switch scheduling module with its ingress bandwidth and avoiding bandwidth waste. During network congestion, maximizing packet concatenation can more fully utilize the egress bandwidth resources of the switch scheduling module, thereby improving the overall throughput of the switch.

[0021] This disclosure provides a technical solution with one or more embodiments. In terms of hardware implementation and applicable scenarios, based on the existing dual-channel parallel hardware architecture, packet assembly determination and operation are implemented at the scheduling module entry side based on descriptive information, without requiring additional buffers or physical links for the scheduling module. The switch scheduling module does not need to be aware of the difference in the number of egress channels, and can focus on the optimization and implementation of the scheduling algorithm, which is beneficial for module reuse and timing convergence. This solution is suitable for high-speed interconnection scenarios, is particularly friendly to small-sized packets, and can improve the overall performance of the data exchange system with lower hardware overhead. Attached Figure Description

[0022] The features and advantages of the embodiments of this disclosure will be more clearly understood by referring to the accompanying drawings, which are illustrative and should not be construed as limiting the present disclosure in any way. In the drawings: Figure 1 A schematic diagram illustrating the workflow of a switch in the related art is shown; Figure 2 This diagram illustrates the data processing flow of a switch executing a single-packet serial scheduling strategy in related technologies. Figure 3 This diagram illustrates the data scheduling input timing of a switch scheduling module in related technologies. Figure 4 This diagram illustrates the timing sequence of data scheduling output from a switch scheduling module in related technologies. Figure 5 This illustration shows a step diagram of a packet processing method for a packet-switched network according to one embodiment of the present disclosure; Figure 6 A schematic diagram illustrating the workflow of a switch according to one embodiment of this disclosure is shown; Figure 7 This diagram illustrates a data reception schematic of the pre-input port control module of the scheduling module in one embodiment of the present disclosure. Figure 8This diagram illustrates the data output of a packet transmission operation of the pre-input port control module of the scheduling module in one embodiment of the present disclosure. Figure 9 This diagram illustrates the data output of an independent transmission operation of the scheduling module's front input port control module in one embodiment of this disclosure. Figure 10 This illustration shows another data reception diagram of the pre-input port control module of the scheduling module in one embodiment of the present disclosure; Figure 11 This diagram illustrates the data output of another packet transmission operation of the scheduling module's front input port control module in one embodiment of this disclosure. Figure 12 This illustration shows a data output diagram of another independent transmission operation of the scheduling module's front input port control module in one embodiment of the present disclosure; Figure 13 This illustration shows another data reception diagram of the pre-input port control module of the scheduling module in one embodiment of the present disclosure; Figure 14 This illustration shows a data output diagram of another packet transmission operation of the scheduling module's front input port control module in one embodiment of the present disclosure; Figure 15 This illustration shows a schematic diagram of the data output of another independent transmission operation of the scheduling module's front input port control module in one embodiment of this disclosure; Figure 16 A schematic diagram of the functional units of a switching device for a packet-switched network is shown in one embodiment of this disclosure. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0024] In related technologies, switches, which use "data packets" as the basic transmission unit, can connect to multiple external devices, thereby enabling data interaction between these devices. Internally, a switch may contain functional modules such as an input buffer module, a scheduling module (also referred to as a switching switch in some technical documents), and an output management module. The scheduling module is the core arbitration unit for data forwarding in the switch, responsible for establishing dynamic connections between multiple input and output ports, determining which input port's data can be transmitted to which output port in each time slot. Its efficiency directly determines the switch's throughput and latency characteristics. Since each external device may have multiple access ports, the switch may need to use multiple input buffer queues to store the input data from each input port before it enters the switch's scheduling module. To improve performance, the switch may also need to use a VOQ (Virtual Output Queue) to sequentially output the data scheduled by the scheduling module from each output port to the target receiving device.

[0025] For related technologies, please refer to Figure 1 After a switch connects to four external devices, its workflow can be summarized as follows: First, any external device (e.g., Figure 1 Devices 1 to 4 send the target data packet containing control information and load data to the switch. Next, the switch routes the data packet at the ingress bus according to the control information, obtains the expected receiving address, priority, and other information of the target data packet, and generates descriptor information to enter the specified descriptor queue. Then, the switch's scheduling module arbitrates multiple descriptor queues to determine the data that needs to be scheduled and performs data scheduling. Finally, the switch uses the egress bus to transmit the data packet processed by the scheduling module to the target receiving device / address.

[0026] In related technologies, the data length of each specific target data packet is generally not fixed. Each data packet may require a predetermined time period (depending on the actual hardware performance of the switch) to complete transmission, or it may require multiple predetermined time periods. In the traditional single-packet serial scheduling mode (also known as one-packet-per-cycle mode), the core scheduling module (cross) of the switch can only transmit one target data packet in one transmission cycle (corresponding to one or more time periods). Therefore, when the data input rate of external access devices is high, the bandwidth input to the switch scheduling module will also increase accordingly. Since the switch scheduling module maintains the single-packet serial scheduling working mode, problems such as performance degradation in small packet scenarios, numerous bus idle bubbles, and wasted bandwidth resources are inevitable.

[0027] Specifically, please refer to Figure 2 The switch follows a single-packet serial scheduling strategy of "one packet per scan," and its data processing flow can be as follows: Figure 2 As shown. First, the external access device sends the data packets to be transmitted to the switch's ingress point. Each data packet carries a header control information (head). Each data packet may carry one or more payload data packets, or none at all. Generally, the header control information and payload data of the data packets enter the switch through the header control information channel (head-chnl, also abbreviated as hd_chnl) and the payload data channel (payload_chnl, also abbreviated as pd_chnl), respectively, where the switch performs ingress management (e.g., routing information parsing, adding local description information, etc.). Second, the switch's scheduling module (cross) can perform data scheduling and accurately output the data to the target receiving device through the header control information channel and the payload data channel. When outputting data, the switch can perform egress management (e.g., data verification, output port status management, etc.).

[0028] It should be noted that the header control information channel and load data channel described in this disclosure are logical interface concepts (i.e., functional division at the bus protocol level) in the switch chip architecture, used to distinguish the transmission of control information and data load. In hardware implementation, these logical channels are carried by their own independent physical signal lines (internal data buses), thus possessing physical independence. During the data input (entry) and data output (exit) stages, although logically both are called the header control information channel and load data channel, they are instantiated in hardware as two independent physical paths—the entry-side bus (from the port to the scheduling module) and the exit-side bus (from the scheduling module to the port). Furthermore, the data flow is sequential in time (after entry processing, the data is buffered and arbitrated by the scheduling module before being output through another independent channel on the exit side). In addition, the scheduling module (cross) internally maintains routing flags and direction control signals, which can clearly distinguish whether the current data flow is in the input or output stage, thereby ensuring that the two channels are not confused logically or physically.

[0029] Please see Figure 3 For the core scheduling module (cross) of the switch, the input timing for data scheduling is as follows: In the first time period of each transmission cycle, the description information, header control information, and payload data of a data packet are transmitted from the description information channel (desc_chnl), the header control information channel (hd_chnl), and the payload data channel (pd_chnl), respectively. If a data packet does not contain payload data (e.g., a read request message), the payload data channel also needs to be idle for one time period (e.g., ...). Figure 3The "T4" time period in the context. If a packet contains excessively long payload data, it may require multiple time periods of the payload data transmission (e.g., ...). Figure 3 The "T2-T3" time period in the text describes the information channel and the head control information channel being idle for at least one time period (e.g., Figure 3 (the "T3" time period).

[0030] Please see Figure 4 For the core scheduling module (cross) of the switch, the data scheduling output timing is as follows: In the first time period of each transmission cycle, the header control information channel (hd_chnl) and the payload data channel (pd_chnl) transmit the header control information and payload data of a certain data packet, respectively. If a data packet does not contain payload data (e.g., a read request message), the payload data channel also needs to be idle for one time period (e.g., ...). Figure 4 The "T4" time period in the context. If a packet contains excessively long payload data, it may require multiple time periods of the payload data transmission (e.g., ...). Figure 4 The "T2-T3" time period in the text describes the information channel and the head control information channel being idle for at least one time period (e.g., Figure 4 (the "T3" time period).

[0031] In summary, this publicly available study found that, for example... Figure 1 and Figure 2 In data exchange systems, if the switch follows the traditional "one packet per tick" serial output strategy, the following shortcomings are likely to exist.

[0032] In some real-world business scenarios, data packet lengths exhibit a wide dynamic range. Each data packet contains only one set of control information but can carry varying amounts of payload data. When the header control path and payload data path are separated, within a transmission cycle allocated to a specific data packet, the switch's header control information channel only needs to output one set of control information, while the payload data channel needs to continuously output payload data. Therefore, during this transmission cycle, the header control information channel is idle for most of the time, forming what is known as a "bus bubble." When the total amount of payload data is small (i.e., the data packet is a short message), the idle time of the header control information channel is relatively short, and the impact on overall bandwidth utilization is still within an acceptable range. However, when the total amount of payload data is large (i.e., the data packet is a long message), the idle time of the header control information channel increases significantly, and the bus bubble problem becomes particularly prominent. Furthermore, when the payload data volume of a data packet is less than the bus width of the payload data channel, the payload data channel itself will also experience partial bandwidth idleness. This single-packet serial scheduling mode, because it cannot insert the payload transmission of subsequent data packets within the same transmission cycle, causes the actual effective throughput of the switch to be far lower than the theoretical peak, thus wasting valuable hardware bandwidth resources.

[0033] In scenarios involving multiple parallel external devices, the internal scheduling algorithms of switches in related technologies exhibit extremely high complexity and implementation difficulty. For access devices supporting multiple virtual channels or multiple queues, traditional scheduling architectures require the switch's scheduling module (cross) to perceive and process every independent input queue request. This means that if the entire data exchange system contains N input ports, and each input port maintains M input queues, the switch's scheduling module needs to simultaneously deal with a massive request matrix of size N×M and perform global queue arbitration. This "large queue scheduling" mode forces the switch's scheduling module to directly manage the underlying fine-grained channel states, resulting in a dramatic increase in the number of fan-in arguments in the arbitration logic and a significant increase in critical path latency. Under high-speed clock design conditions, such centralized arbitration logic is extremely difficult to meet timing convergence requirements, severely restricting the improvement of chip operating frequency and the expansion of design scale.

[0034] In view of this, the packet processing method for packet-switched networks provided by one or more embodiments of this disclosure can be applied to switching devices and can effectively improve the packet scheduling efficiency and bandwidth resource utilization of the switch.

[0035] Please see Figure 5 The packet processing method for packet-switched networks provided in one embodiment of this disclosure may include the following steps.

[0036] S1: Receive data packets to be transmitted sent by each access device connected to the switch device, and determine the single packet description information of each data packet to be transmitted. The single packet description information includes the routing information, data structure information and data volume information of the data packet to be transmitted.

[0037] In this embodiment, once the data packet to be transmitted enters the switch stage, the extraction of the single packet description information is completed. This allows all subsequent scheduling and packet assembly decisions to be executed based solely on the lightweight description information without repeatedly accessing the data packet itself.

[0038] In this embodiment, the routing information covered by the single-packet description information can be used to represent the expected transmission address of each data packet and confirm whether multiple data packets are destined for the same destination. The data structure information covered by the single-packet description information is used to represent the data packet type of the data packet to be transmitted and whether it carries payload data. The data volume information covered by the single-packet description information represents the data length of the payload data. Optionally, the single-packet description information may also include priority information characterizing the importance of the data packets.

[0039] In this embodiment, the pre-extraction mechanism of single packet description information provides a complete decision basis for the switch scheduling module to perform packet concatenation and transmission operations, without affecting the normal storage and flow of data packets within the switch.

[0040] S2: Based on the single packet description information, classify and store the data packets to be transmitted into various transmission buffer queues, and perform queue arbitration on each of the transmission buffer queues.

[0041] In this embodiment, the switch can not only generate single packet description information for each data packet to be transmitted, but also allocate the data packets to be transmitted to each transmission buffer queue according to the single packet description information, thereby achieving traffic isolation by target port or service type.

[0042] In this implementation, the queue arbitration mechanism is responsible for selecting the authorized target queue from multiple buffer queues, ensuring that each queue receives a fair or priority transmission opportunity according to a preset scheduling strategy. By decoupling packet storage from queue scheduling, the switch can directly perform subsequent packet assembly determination based on the packets in the queue after obtaining the target queue, without needing to know the specific location of the packets in the physical buffer.

[0043] S3: For the target queue that has obtained arbitration authorization in the transmission buffer queue, determine whether the first data packet and the subsequent data packets meet any of the preset conditions in the preset packet assembly conditions based on the single packet description information of the first data packet and the subsequent data packets.

[0044] In this implementation, after the target queue obtains arbitration authorization, the switch reads the description information of the first data packet and one or more subsequent data packets in the queue as input parameters for packet concatenation determination. The preset concatenation conditions can include multiple preset condition items, each corresponding to a specific scenario where packet concatenation is feasible (e.g., the first packet's load is less than one time period and subsequent packets do not carry load). By comparing the description information with the determination rules for each condition item, the switch can determine whether the current first packet and subsequent packets satisfy any condition item, thereby deciding whether to perform concatenated transmission or independent transmission.

[0045] S4: If the first data packet and the subsequent data packets satisfy any of the preset conditions, then perform a packet concatenation transmission operation that matches the preset conditions, so that the scheduling module of the switch device transmits the header control information of the first data packet and the header control information of the subsequent data packets together within the target transmission period for the complete transmission of the first data packet.

[0046] In this implementation, when any preset condition is met, the switch can execute the packet concatenation operation corresponding to that condition. The concatenation actions triggered by different conditions differ in the way the payload data is concatenated or the channel allocation for header control information. However, overall, within the target transmission cycle of the first data packet, the header control information channel transmits not only the header of the first packet but also the header control information of subsequent data packets, allowing the header control information of subsequent data packets to be sent ahead of schedule without waiting for an independent cycle. The practical application value of packet concatenation is particularly evident in the processing of subsequent packets that do not carry payload data or only carry a small amount of payload data, effectively alleviating the switch's bus idle bubble problem.

[0047] In this embodiment, the specific data scheduling work of packet concatenation transmission operation can be performed by the scheduling module of the switch device. However, the judgment of packet concatenation conditions and the determination of packet concatenation strategy can be performed by the input port controller (IPC) module in front of the scheduling module. This allows the scheduling module to focus on the implementation of the scheduling algorithm and reduces the strong coupling between the scheduling logic of the scheduling module and the processing of channels, protocols and descriptors.

[0048] In some implementations, the preset condition includes a first condition, which includes: the routing information of the first data packet and the subsequent data packets are consistent; within one or more time periods corresponding to the target transmission period, the header control information channel of the switch device has an idle path for at least one of the time periods; and the subsequent data packets do not carry payload data.

[0049] Specifically, the first condition sets three quantifiable sub-conditions to ensure the feasibility and determinism of packet concatenation at the engineering level. Consistent routing information is a fundamental prerequisite for packet concatenation, ensuring that multiple data packets belonging to the same destination port can be merged for transmission, avoiding logical errors caused by cross-port concatenation. The determination of whether there is an idle path in the header control information channel binds the concatenation decision to the actual hardware resource status in real time, ensuring that the concatenation action will not lead to channel conflicts or data loss, thus enhancing hardware robustness. When subsequent packets do not carry payload, occupying a complete transmission cycle alone would result in a significant waste of egress bandwidth resources. The condition that subsequent data packets do not carry payload data precisely identifies the most suitable message type for concatenation processing.

[0050] The setting of the first condition allows the switch to use the idle path of the header control information channel to forward subsequent specific types of packets that do not carry load data (e.g., file read request packets) in parallel while the first long packet occupies the load data channel, thus completing the concurrent output of multiple packets without increasing the bandwidth overhead.

[0051] The header control information channel can have multiple parallel transmission paths. The first message only needs to use a single transmission path of the header control information channel during the first time period of the target transmission cycle. Therefore, during the first time period, the other idle transmission paths of the header control information channel can be used to transmit the header control information of subsequent messages, reducing resource waste. In subsequent time periods (if any), all idle transmission paths of the header control information channel can be used to transmit the header control information of subsequent messages, further reducing resource waste.

[0052] Preferably, the first condition also includes a sub-condition: "there is no preset timing requirement between the first data packet and subsequent data packets." This sub-condition can further enhance the rationality of data packet concatenation and transmission and the accuracy of data transmission.

[0053] In some practical applications, data exchange networks may contain a large number of short control messages such as acknowledgment packets and flow control packets. In such cases, performing packet concatenation transmission operations that match the first condition has high practical value, effectively reducing average transmission latency and improving system throughput in small packet scenarios.

[0054] In some implementations, when the first data packet and the subsequent data packets satisfy the first condition, the execution of the packet concatenation transmission operation matching the preset condition includes: transmitting the load data of the first data packet through the load data channel of the switch device within the target transmission period; and transmitting the header control information of the first data packet and the header control information of the subsequent data packets through different paths of the header control information channel within the target transmission period.

[0055] Specifically, under the scenario where the first condition is met, the actual packet concatenation operation only involves the reallocation of the header control information path, without affecting the normal transmission process of the payload data channel. This operation method has the significant advantage of low invasiveness. The payload data of the first packet is transmitted through the payload data channel along the original path, and the length of its target transmission period and the sending sequence of the payload data remain unchanged, ensuring that the transmission of the first packet itself is not interfered with by the concatenation decision. Regarding the header control information channel, by allocating the first packet header and subsequent packet headers to multiple different paths for parallel transmission, concurrent transmission of multiple message header control information is achieved within the same time period, fully utilizing the hardware parallel capabilities of the multi-path header channel.

[0056] In some implementations, the preset condition includes a second condition, which includes: the routing information of the first data packet and the subsequent data packets are consistent; in the last time period corresponding to the target transmission period, the first data length of the remaining load data of the first data packet is less than the bus width of the load data channel of the switch device in a single time period; and the sum of the first data length and the total length of the load data of at least one of the subsequent data packets is less than or equal to the bus width of the load data channel in a single time period.

[0057] Specifically, the second condition addresses a common scenario where the remaining payload data length of the first data packet is insufficient to fill the entire bus width of the payload data channel during the last time period of its target transmission cycle, resulting in idle bandwidth in the payload data channel during that period. The second condition first requires consistent routing information to ensure that the merged subsequent data packets go to the same destination port. Based on this, it ensures that the sum of the remaining payload length of the first packet and the total payload length of at least one subsequent data packet does not exceed the bus width by determining that the merged data can be transmitted completely within the same time period.

[0058] The setting of the second condition allows the switch to fully utilize the idle bandwidth of the bus at the end of the cycle, which would otherwise be wasted. By concatenating multiple small payload packets into the same cycle for transmission, the effective bandwidth utilization is improved without expanding the bus width or increasing the clock frequency.

[0059] Preferably, the second condition also includes a sub-condition: "there is no preset timing requirement between the first data packet and subsequent data packets." This sub-condition can further enhance the rationality of data packet concatenation and transmission and the accuracy of data transmission.

[0060] In some implementations, when the first data packet and the subsequent data packets satisfy the second condition, the execution of the packet concatenation transmission operation matching the preset condition includes: transmitting the header control information of the subsequent data packets through an independent path of the header control information channel of the switch device during the last time period corresponding to the target transmission period; and merging and transmitting the remaining load data of the first data packet and the load data of the subsequent data packets through the load data channel during the last time period corresponding to the target transmission period.

[0061] Specifically, in the last time period, the payload data of subsequent data packets is directly appended to the remaining payload data of the first data packet, and they are transmitted together using the payload data channel. At the same time, the header control information of subsequent data packets is sent through a separate path of the header control information channel, and is transmitted in parallel with the merged payload data in the same clock cycle. Load merging only involves data concatenation and does not change the transmission timing of the original payload channel, requiring minimal modification to the hardware logic.

[0062] It should be further explained that the target transmission period may consist of only one time period (i.e., the first data packet is a short message, and its entire payload data can be transmitted within one time period). In this case, the "last time period" is essentially the unique time period, and the above-mentioned determination condition for the remaining payload data in the last period applies the same as the merged transmission operation, without needing to make any additional distinction in the determination logic due to the different number of periods. In other words, regardless of whether the target transmission period contains a single or multiple time periods, the determination of the second condition is anchored to the last period, and the single-period scenario can be regarded as a special case of the multi-period scenario and is naturally compatible.

[0063] In some implementations, the preset condition includes a third condition, which includes: the routing information of the first data packet and the subsequent data packets are consistent; the first data packet does not carry load data; the subsequent data packets do not carry load data, or the load data length of the subsequent data packets does not exceed the bus width of the load data channel of the switch device in a single time period.

[0064] Specifically, the third condition addresses scenarios where the first data packet itself does not carry payload data (i.e., it is a pure control message), a type of message that is abundant in high-speed interconnected networks. The third condition first requires consistent routing information to ensure that merged packets are destined for the same port. Based on this, subsequent data packets are categorized into two deterministic scenarios: either they do not carry payload data, or their payload data length does not exceed the bus width of a single time period. The parameters for determining these two scenarios are deterministic values ​​that the switch can obtain in real time, ensuring the engineering feasibility of condition matching.

[0065] The first packet of a pure control message only occupies the header control information channel, while the payload data channel remains completely idle during its target transmission cycle. The header control information of subsequent packets is then sent in parallel with the first packet header through different paths within the header control information channel. This fully utilizes the transmission cycle of the pure control message, enabling concurrent output of header information for multiple control messages or small-payload messages. Especially for small packet scenarios such as control plane messages and acknowledgment messages that are prevalent in networks, setting the second condition can significantly reduce queuing latency for these messages and improve the overall scheduling efficiency of the switch.

[0066] Preferably, the third condition also includes a sub-condition: "There is no preset timing requirement between the first data packet and subsequent data packets." This sub-condition can further enhance the rationality of data packet concatenation and transmission and the accuracy of data transmission.

[0067] In some implementations, when the first data packet and the subsequent data packets satisfy the third condition, performing a packet concatenation transmission operation matching the preset condition includes: within the target transmission period, transmitting the header control information of the first data packet and the header control information of the subsequent data packets respectively through different paths of the header control information channel of the switch device; within the target transmission period, if the subsequent data packets do not carry payload data, then idling the payload data channel of the switch device; if the subsequent data packets carry payload data, then transmitting the payload data of the subsequent data packets through the payload data channel.

[0068] Specifically, since the first data packet does not carry payload data, its payload data channel in the target transmission cycle can theoretically be used by subsequent data packets. Utilizing the multi-path of the header control information channel, the first packet header and subsequent packet headers can be sent in parallel. The payload data channel is then flexibly handled according to the actual situation of subsequent data packets. If subsequent packets also do not carry payload data, the payload data channel remains idle for a single time cycle; if subsequent packets carry a small amount of payload data, the payload data channel can be directly used to transmit the payload data of subsequent packets. The entire packet assembly process does not change the original transmission timing of the first data packet, has minimal intrusion into the hardware pipeline, and is easy to implement logically and achieve timing convergence.

[0069] In some implementations, performing the packet concatenation transmission operation matching the preset condition includes: integrating the single packet description information of the first data packet and the subsequent data packets into concatenation description information; and synchronously sending the concatenation description information to the scheduling module when transmitting the first data packet to the scheduling module.

[0070] Specifically, the individual packet descriptions of the first data packet and subsequent data packets are merged into a single packet description. This allows the scheduling module to process only one unified description to make scheduling decisions for multiple data packets. Simultaneously with the transmission of the first data packet to the scheduling module, the packet description is sent to the module, ensuring the timing alignment of the description and data packet transmission and avoiding scheduling errors caused by information lag. This approach enables the scheduling module to process the packet assembly operation without being aware of whether it is processing one or multiple data packets, which facilitates decoupling between modules and the reuse of existing scheduling logic.

[0071] It is important to emphasize that, under different communication protocol specifications, different numbers of transmission channels, or different numbers of buffer queues, the "preset condition items" and the "packet concatenation transmission operation matching the preset condition items" can be flexibly adjusted according to the actual scenario.

[0072] S5: If the first data packet and the subsequent data packets do not meet all the preset conditions, the first data packet and the subsequent data packets are transmitted independently, so that the scheduling module of the switch device starts transmitting the subsequent data packets in the next transmission cycle of the target transmission cycle.

[0073] In this implementation, when none of the preset conditions are met, the switch does not perform any packet reassembly processing on the first packet and subsequent packets. The first packet completes the transmission of its full payload data and header control information within the target transmission cycle. The transmission of subsequent packets is postponed to the next transmission cycle of the target transmission cycle, meaning that subsequent packets must wait until the transmission cycle fully occupied by the first packet ends before they can be sent. This avoids the timing chaos caused by forced merging in scenarios where packet reassembly is not applicable.

[0074] In some implementations, please refer to Figure 6 An internal switch can contain a scheduling module (cross), an input port controller (IPC) before the scheduling module, and an output port controller (EPC) after the scheduling module. Data packets sent by different external devices enter the switch and can be split into header control information transmitted through the header control information channel (hd_chnl) and load data transmitted through the load data channel (pd_chnl). The header control information channel (hd_chnl) can contain two parallel transmission paths (…). Figure 5 (hd_chnl0 and hd_chnl1). Unlike related technologies where the scheduling module directly performs data scheduling, the IPC designed in this disclosure can pre-generate description information and perform packet assembly processing. Based on preset packet assembly conditions, if packet assembly transmission is feasible, the IPC can determine the packet assembly scheme and instruct the scheduling module to schedule the assembled data; if packet assembly transmission is not feasible, the IPC can instruct the scheduling module to independently schedule each data packet. The EPC can further process the output data of the scheduling module (e.g., data reassembly, output flow control and backpressure processing, link layer encapsulation, etc.) before sending it to various external devices.

[0075] In a practical application example, please refer to Figure 7Assume the first data packet entering the IPC (header control information HD0) carries payload data (PD0-0, PD0-1, and PD0-2), followed by two data packets without payload data (header control information HD1 and HD2 respectively). If the routing information of these three data packets is consistent (both ingress and egress ports are consistent), and there are no special timing requirements, these three data packets can be considered to meet the first condition of the preset conditions. The IPC can then reassemble these three data packets, and the data delivery result from the IPC to the scheduling module can be as follows: Figure 8 As shown. In some practical application scenarios, although the routing information of these three data packets is consistent, due to the special timing requirements of the data packets themselves, these three data packets still do not meet the first condition of the preset condition. Therefore, IPC does not perform packet reassembly on these three data packets, and the data delivery result from IPC to the scheduling module can be as follows: Figure 9 As shown.

[0076] Figure 8 In this process, the payload data (PD0-0, PD0-1, and PD0-2) of the first data packet needs to occupy the payload data channel (pd_chnl) for three time periods (T1, T2, and T3). In the first time period T1, the header control information (HD0 and HD1) of the first two data packets is output in parallel from both paths (hd_chnl0 and hd_chnl1) of the header control information channel. In the second time period T2, the header control information (HD2) of the third data packet is output from either path (e.g., hd_chnl0). Also in the first time period T1, IPC can utilize the description information channel (desc_chnl) to transmit packet description information (desc0) to subsequent scheduling modules.

[0077] Figure 9 In this process, the payload data (PD0-0, PD0-1, and PD0-2) of the first data packet itself needs to occupy three time periods (T1, T2, and T3) of the payload data channel (pd_chnl). In the first time period T1, the description information (desc0), header control information (HD0), and a portion of the payload data (PD0-0) of the first data packet are output from either the description information channel (desc_chnl), the header control information channel (e.g., hd_chnl0), or the payload data channel (pd_chnl), respectively. After the first data packet is transmitted, in the fourth time period T4, the description information (desc1) and header control information (HD1) of the second data packet begin to be transmitted. After the second data packet is transmitted, in the fifth time period T5, the description information (desc2) and header control information (HD2) of the second data packet begin to be transmitted.

[0078] In a practical application example, please refer to Figure 10 Assume the first data packet entering the IPC (header control information HD0) is a short message carrying a small amount of payload data (PD0), and subsequent data packets (header control information HD1) are also short messages carrying a small amount of payload data (PD1). If the routing information of these two data packets is consistent (both ingress and egress ports are consistent), and there are no special timing requirements, these two data packets can be considered to meet the second condition of the preset conditions. The IPC can then reassemble these two data packets, and the data delivery result from the IPC to the scheduling module can be as follows: Figure 11 As shown. In some practical application scenarios, although the routing information of these two data packets is the same, due to the special timing requirements of the data packets themselves, these two data packets still do not meet the second condition of the preset condition. Therefore, IPC does not perform packet reassembly on these two data packets, and the data delivery result from IPC to the scheduling module can be as follows: Figure 12 As shown.

[0079] Figure 11 In the process, the payload data (PD0) of the first data packet needs to occupy the payload data channel (pd_chnl) for one time period T1. Within time period T1, the header control information (HD0 and HD1) of the two data packets can be output in parallel from the two paths (hd_chnl0 and hd_chnl1) of the header control information channel. Within time period T1, the payload data (PD0 and PD1) of the two data packets can be merged and output from the header payload data channel (pd_chnl). Within time period T1, IPC can also use the description information channel (desc_chnl) to transmit packet description information (desc0) to subsequent scheduling modules.

[0080] Figure 12 In this process, the payload data (PD0) of the first data packet needs to occupy the payload data channel (pd_chnl) for one time period T1. During the first time period T1, the description information (desc0), header control information (HD0), and payload data (PD0) of the first data packet are output from either the description information channel (desc_chnl), the header control information channel (e.g., hd_chnl0), or the payload data channel (pd_chnl), respectively. After the first data packet has been transmitted, in the second time period T2, the description information (desc1), header control information (HD1), and payload data (PD1) of the second data packet begin to be transmitted.

[0081] In a practical application example, please refer to Figure 13Assume the first data packet entering the IPC (header control information is HD0) is a long message carrying a large amount of payload data (PD0-0, PD0-1, and PD0-2), and subsequent data packets (header control information is HD1) are short messages carrying a small amount of payload data (PD1-0). If the routing information of these two data packets is consistent (both ingress and egress ports are consistent), and there are no special timing requirements, these two data packets can be considered to meet the second condition of the preset conditions. The IPC can then reassemble these two data packets, and the data delivery result from the IPC to the scheduling module can be as follows: Figure 14 As shown. In some practical application scenarios, although the routing information of these two data packets is the same, due to the special timing requirements of the data packets themselves, these two data packets still do not meet the second condition of the preset condition. Therefore, IPC does not perform packet reassembly on these two data packets, and the data delivery result from IPC to the scheduling module can be as follows: Figure 15 As shown.

[0082] Figure 14 In this process, the payload data (PD0-0, PD0-1, and PD0-2) of the first data packet itself needs to occupy the payload data channel (pd_chnl) for three time periods (T1, T2, and T3). In time period T1, the header control information (HD0) and part of the payload data (PD0-0) of the first data packet are output from either path of the header control information channel (e.g., hd_chnl0) and the payload data channel (pd_chnl), respectively. In the last time period T3 corresponding to the first data packet, the remaining payload data (PD0-2) of the first data packet and the payload data (PD1-0) of the second data packet can be merged and output from the payload data channel (pd_chnl). In the last time period T3 corresponding to the first data packet, the header control information of the second data packet is output from either path of the header control information channel (e.g., hd_chnl0). Furthermore, in time period T1, IPC can also use the description information channel (desc_chnl) to transmit the combined packet description information (desc0) of the two data packets to the subsequent scheduling module.

[0083] Figure 15In this process, the payload data (PD0-0, PD0-1, and PD0-2) of the first data packet itself needs to occupy the payload data channel (pd_chnl) for three time periods (T1, T2, and T3). In the first time period T1, the description information (desc0), header control information (HD0), and all payload data (PD0-0) of the first data packet are output from the description information channel (desc_chnl), any path of the header control information channel (e.g., hd_chnl0), and the payload data channel (pd_chnl), respectively. After the first data packet has been transmitted, in the fourth time period T4, IPC begins transmitting the description information (desc1), header control information (HD1), and payload data (PD0-2) of the second data packet.

[0084] The above practical application examples demonstrate that, in specific scenarios, the technical solution provided in this disclosure significantly improves the data scheduling efficiency of switches. Especially when the data packets to be transmitted are mostly small packets, the probability of packet concatenation is relatively higher, resulting in a more pronounced performance improvement for the switch.

[0085] This disclosure provides a technical solution through one or more embodiments, which determines the single-packet description information of each packet upon receiving the data packet. Subsequent queue classification and storage, queue arbitration, and packet assembly determination are all based on the single-packet description information, eliminating the need for repeated parsing of data packet content. For the target queue that has obtained arbitration authorization, it is determined whether any preset condition is met based on the description information of the first and subsequent data packets, and packet assembly or independent transmission operations are performed according to the determination result. This description-based preprocessing mechanism allows the switch's scheduling module to process multiple packets within a single clock cycle, but presents only a single scheduling request externally, simplifying the scheduler's state management.

[0086] This disclosure provides one or more embodiments of the technical solution that, in terms of bandwidth utilization and transmission delay, when the packet concatenation condition is met, transmits the header control information of the first packet and subsequent packets simultaneously within the target transmission cycle used for the complete transmission of the first packet. This allows the header control information of multiple packets to be output concurrently without waiting for subsequent independent transmission cycles, thereby reducing transmission delay. Regarding bandwidth utilization, packet concatenation can merge multiple packets for processing, matching the egress bandwidth of the switch scheduling module with its ingress bandwidth and avoiding bandwidth waste. During network congestion, maximizing packet concatenation can more fully utilize the egress bandwidth resources of the switch scheduling module, thereby improving the overall throughput of the switch.

[0087] This disclosure provides a technical solution with one or more embodiments. In terms of hardware implementation and applicable scenarios, based on the existing dual-channel parallel hardware architecture, packet assembly determination and operation are implemented at the scheduling module entry side based on descriptive information, without requiring additional buffers or physical links for the scheduling module. The switch scheduling module does not need to be aware of the difference in the number of egress channels, and can focus on the optimization and implementation of the scheduling algorithm, which is beneficial for module reuse and timing convergence. This solution is suitable for high-speed interconnection scenarios, is particularly friendly to small-sized packets, and can improve the overall performance of the data exchange system with lower hardware overhead.

[0088] Please see Figure 16 This disclosure also provides a switching device for packet-switched networks, the switching device comprising: The data packet receiving unit 100 is used to receive data packets to be transmitted sent by various access devices connected to the switch device, and to determine the single packet description information of each data packet to be transmitted. The single packet description information includes the routing information, data structure information and data volume information of the data packet to be transmitted. The data packet caching unit 200 is used to classify and store the data packets to be transmitted into various transmission buffer queues according to the single packet description information, and to perform queue arbitration on each of the transmission buffer queues. The packet assembly confirmation unit 300 is used to determine, for the target queue that has obtained arbitration authorization in the transmission buffer queue, whether the first packet and the subsequent packets meet any preset condition item in the preset packet assembly conditions based on the single packet description information of the first packet and the subsequent packets; The packet concatenation transmission unit 400 is used to perform a packet concatenation transmission operation matching the preset condition if the first packet and the subsequent packets satisfy any of the preset condition items, so that the scheduling module of the switch device can transmit the header control information of the first packet and the header control information of the subsequent packets together within the target transmission period for the complete transmission of the first packet. The packet transmission unit 500 is configured to independently transmit the first data packet and the subsequent data packets if the first data packet and the subsequent data packets do not meet all the preset conditions, so that the scheduling module of the switch device can start transmitting the subsequent data packets in the next transmission cycle of the target transmission cycle.

[0089] In this embodiment, the specific functions of each unit can be explained by referring to the corresponding content of the method embodiments above, and will not be repeated here.

[0090] In one embodiment, the packet concatenation transmission unit 400 is further configured to: integrate the single packet description information of the first data packet and the subsequent data packets into concatenation description information; and synchronously send the concatenation description information to the scheduling module when transmitting the first data packet to the scheduling module.

[0091] In one embodiment, the preset condition includes a first condition, which includes: the routing information of the first data packet and the subsequent data packets are consistent; within one or more time periods corresponding to the target transmission period, the header control information channel of the switch device has an idle path for at least one of the time periods; and the subsequent data packets do not carry payload data.

[0092] In one embodiment, the packet transmission unit 400 is specifically used to: transmit the load data of the first data packet through the load data channel of the switch device during the target transmission period; and transmit the header control information of the first data packet and the header control information of the subsequent data packets through different paths of the header control information channel during the target transmission period.

[0093] In one embodiment, the preset condition item includes a second condition item, which includes: the routing information of the first data packet and the subsequent data packets are consistent; in the last time period corresponding to the target transmission period, the first data length of the remaining load data of the first data packet is less than the bus width of the load data channel of the switch device in a single time period; and the sum of the first data length and the total length of the load data of at least one of the subsequent data packets is less than or equal to the bus width of the load data channel in a single time period.

[0094] In one embodiment, the packet concatenation transmission unit 400 is specifically used to: transmit the header control information of the subsequent data packets through an independent path of the header control information channel of the switch device during the last time period corresponding to the target transmission period; and to merge and transmit the remaining load data of the first data packet and the load data of the subsequent data packets through the load data channel during the last time period corresponding to the target transmission period.

[0095] In one implementation, the preset condition includes a third condition, which includes: the routing information of the first data packet and the subsequent data packets are consistent; the first data packet does not carry load data; the subsequent data packets do not carry load data, or the length of the load data of the subsequent data packets does not exceed the bus width of the load data channel of the switch device in a single time period.

[0096] In one embodiment, the packet transmission unit 400 is specifically configured to: transmit the header control information of the first data packet and the header control information of the subsequent data packets respectively through different paths of the header control information channel of the switch device within the target transmission period; if the subsequent data packets do not carry payload data within the target transmission period, the payload data channel of the switch device is idled; if the subsequent data packets carry payload data, the payload data of the subsequent data packets is transmitted through the payload data channel.

[0097] The various units described in the above embodiments can be implemented by computer chips or by hardware products with computing capabilities. For example, these hardware products can be chips such as Central Processing Units (CPUs), Digital Signal Processors (DSPs), Application-Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or combinations of the above types of chips. Of course, in implementing this application, the functions of each unit can be implemented in one or more software and / or hardware components.

[0098] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), random access memory (RAM), flash memory, hard disk drive (HDD), or solid-state drive (SSD), etc.; the storage medium can also include combinations of the above types of memory.

[0099] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the embodiments for the switching device are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0100] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

[0101] Although embodiments of the present disclosure have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present disclosure, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A packet processing method for packet-switched networks, characterized in that, The method is applied to a switch device, and the method includes: The device receives data packets to be transmitted from each access device connected to the switch device, and determines the single packet description information of each data packet to be transmitted. The single packet description information includes the routing information, data structure information and data volume information of the data packet to be transmitted. Based on the single packet description information, the data packets to be transmitted are classified and stored in various transmission buffer queues, and queue arbitration is performed on each of the transmission buffer queues. For the target queue that has obtained arbitration authorization in the transmission buffer queue, based on the single packet description information of the first packet and the subsequent packets, determine whether the first packet and the subsequent packets meet any of the preset conditions in the preset packet concatenation conditions; If the first data packet and the subsequent data packets satisfy any of the preset conditions, then a packet concatenation transmission operation matching the preset conditions is executed, so that the scheduling module of the switch device transmits the header control information of the first data packet and the header control information of the subsequent data packets together within the target transmission period for the complete transmission of the first data packet. If the first data packet and the subsequent data packets do not meet all the preset conditions, the first data packet and the subsequent data packets are transmitted independently, so that the scheduling module of the switch device starts transmitting the subsequent data packets in the next transmission cycle of the target transmission cycle.

2. The method according to claim 1, characterized in that, The preset condition item includes a first condition item, which includes: The routing information of the first data packet and the subsequent data packets is consistent; Within one or more time periods corresponding to the target transmission period, the header control information channel of the switching device has an idle path for at least one of the time periods. The subsequent data packets do not carry payload data.

3. The method according to claim 2, characterized in that, When the first data packet and the subsequent data packets satisfy the first condition, the step of performing the packet concatenation transmission operation matching the preset condition includes: During the target transmission cycle, the load data of the first data packet is transmitted through the load data channel of the switching device; Within the target transmission period, the header control information of the first data packet and the header control information of subsequent data packets are transmitted through different paths of the header control information channel.

4. The method according to claim 1, characterized in that, The preset condition item includes a second condition item, which includes: The routing information of the first data packet and the subsequent data packets is consistent; In the last time period corresponding to the target transmission period, the first data length of the remaining load data of the first data packet is less than the bus width of the load data channel of the switch device in a single time period. The sum of the first data length and the total length of the payload data of at least one of the subsequent data packets is less than or equal to the bus width of the payload data channel in a single time period.

5. The method according to claim 4, characterized in that, When the first data packet and the subsequent data packets satisfy the second condition, the step of performing the packet concatenation transmission operation matching the preset condition includes: During the last time period corresponding to the target transmission period, the header control information of the subsequent data packets is transmitted through an independent path of the header control information channel of the switching device. During the last time period corresponding to the target transmission period, the remaining load data of the first data packet and the load data of the subsequent data packets are transmitted together through the load data channel.

6. The method according to claim 1, characterized in that, The preset condition item includes a third condition item, which includes: The routing information of the first data packet and the subsequent data packets is consistent; The first data packet does not carry payload data; The subsequent data packet does not carry payload data, or the payload data length of the subsequent data packet does not exceed the bus width of the payload data channel of the switch device in a single time period.

7. The method according to claim 6, characterized in that, When the first data packet and the subsequent data packets satisfy the third condition, the step of performing a packet concatenation transmission operation matching the preset condition includes: Within the target transmission period, the header control information of the first data packet and the header control information of the subsequent data packets are transmitted through different paths of the header control information channel of the switching device. During the target transmission cycle, if the subsequent data packet does not carry payload data, the payload data channel of the switch device is idle; if the subsequent data packet carries payload data, the payload data of the subsequent data packet is transmitted through the payload data channel.

8. The method according to claim 1, characterized in that, The execution of packet concatenation transmission operations matching the preset condition items includes: The single packet description information of the first data packet and the subsequent data packets are integrated into a packet concatenation description information; When transmitting the first data packet to the scheduling module, the packet description information is simultaneously sent to the scheduling module.

9. A switching device for packet-switched networks, characterized in that, The switching device includes: The data packet receiving unit is used to receive data packets to be transmitted sent by each access device connected to the switch device, and to determine the single packet description information of each data packet to be transmitted. The single packet description information includes the routing information, data structure information and data volume information of the data packet to be transmitted. The data packet caching unit is used to classify and store the data packets to be transmitted into various transmission buffer queues according to the single packet description information, and to perform queue arbitration on each of the transmission buffer queues. The packet assembly confirmation unit is used to determine, for the target queue that has obtained arbitration authorization in the transmission buffer queue, whether the first packet and the subsequent packets meet any preset condition item in the preset packet assembly conditions based on the single packet description information of the first packet and the subsequent packets. The packet concatenation transmission unit is used to perform a packet concatenation transmission operation matching the preset condition if the first packet and the subsequent packets satisfy any of the preset condition items, so that the scheduling module of the switch device can transmit the header control information of the first packet and the header control information of the subsequent packets together within the target transmission period for the complete transmission of the first packet. The packet transmission unit is configured to independently transmit the first data packet and the subsequent data packets if the first data packet and the subsequent data packets do not meet all the preset conditions, so that the scheduling module of the switch device can start transmitting the subsequent data packets in the next transmission cycle of the target transmission cycle.

10. The switching device according to claim 9, characterized in that, The packet concatenation and transmission unit is also used for: The single packet description information of the first data packet and the subsequent data packets are integrated into a packet concatenation description information; When transmitting the first data packet to the scheduling module, the packet description information is simultaneously sent to the scheduling module.

11. The switching device according to claim 9, characterized in that, The preset condition includes a first condition, which includes: the routing information of the first data packet and the subsequent data packets are consistent; within one or more time periods corresponding to the target transmission period, the header control information channel of the switch device has an idle path for at least one of the time periods; and the subsequent data packets do not carry payload data. The packet transmission unit is specifically used for: transmitting the load data of the first data packet through the load data channel of the switch device within the target transmission period; and transmitting the header control information of the first data packet and the header control information of subsequent data packets through different paths of the header control information channel within the target transmission period.

12. The switching device according to claim 9, characterized in that, The preset condition includes a second condition, which includes: the routing information of the first data packet and the subsequent data packets are consistent; in the last time period corresponding to the target transmission period, the first data length of the remaining load data of the first data packet is less than the bus width of the load data channel of the switch device in a single time period; the sum of the first data length and the total length of the load data of at least one of the subsequent data packets is less than or equal to the bus width of the load data channel in a single time period. The packet concatenation transmission unit is specifically used for: transmitting the header control information of the subsequent data packets through an independent path of the header control information channel of the switch device during the last time period corresponding to the target transmission period; and merging and transmitting the remaining load data of the first data packet and the load data of the subsequent data packets through the load data channel during the last time period corresponding to the target transmission period.

13. The switching device according to claim 9, characterized in that, The preset condition includes a third condition, which includes: the routing information of the first data packet and the subsequent data packets are consistent; the first data packet does not carry load data; the subsequent data packets do not carry load data, or the load data length of the subsequent data packets does not exceed the bus width of the load data channel of the switch device in a single time period. The packet transmission unit is specifically used to: transmit the header control information of the first data packet and the header control information of the subsequent data packets respectively through different paths of the header control information channel of the switch device within the target transmission period; if the subsequent data packets do not carry payload data within the target transmission period, the payload data channel of the switch device is idle; if the subsequent data packets carry payload data, the payload data of the subsequent data packets is transmitted through the payload data channel.

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