Video processing circuit for multi-chip tiled infrared focal plane and related methods

Abstract

The application discloses a kind of video processing circuit and related method for multi-chip splicing infrared focal plane, it is related to infrared focal plane video processing technical field, in the present application, FPGA real-time video processing main controller provides the driving control signal of each detector chip in splicing infrared focal plane detector array and the sampling time sequence of multichannel analog-digital conversion synchronous acquisition module based on the homologous clock uniform generation module, multichannel analog front-end signal conditioning module carries out signal conditioning to multiple analog electric signal after, multiple analog electric signal is sent into multichannel analog-digital conversion synchronous acquisition module, cooperate the sampling time sequence of FPGA real-time video processing main controller output, control multichannel analog-digital conversion synchronous acquisition module to execute synchronous analog-digital conversion, FPGA real-time video processing main controller carries out time sequence alignment to multiple parallel digital image data streams, then carries out partition radiation non-uniformity correction and blind element replacement, meet the comprehensive demand to high sensitivity and high image quality.

Description

Technical Field

[0001] This invention relates to the field of infrared focal plane video processing technology, and in particular to a video processing circuit and related methods for multi-chip stitched infrared focal planes. Background Technology

[0002] Infrared imaging technology, with its advantages of all-weather detection and strong weak target recognition capabilities, has been widely used in aerospace remote sensing, Earth observation, and other fields. As the requirements for imaging swath width in infrared detection missions continue to increase, constructing a large field-of-view focal plane using multiple infrared detector chips has become the mainstream technical approach that balances imaging swath width and resolution. However, the multi-chip stitching architecture has given rise to several technical challenges that urgently need to be addressed. During the multi-chip assembly process, due to the influence of chip assembly tolerances, pixel manufacturing deviations, and the discreteness of readout circuit characteristics, the spatial positions of pixels in the overlapping area of ​​adjacent chips are discontinuous, and the photoelectric response consistency between different chip channels is poor. Furthermore, inherent blind pixel and odd pixel response differences in the detector, as well as the mismatch of the multi-chip time delay integral series, directly lead to geometric distortion, grayscale discontinuity, and stripe noise in the stitched image, severely degrading image quality. Furthermore, multi-chip splicing of the focal plane requires multiple drive clocks and control signals with strictly consistent phases. If there is a phase deviation between the integration signals, vertical drive signals, and horizontal drive signals of each chip, and the horizontal synchronization signals are not synchronized, it will cause phase misalignment in the time-delay integration, directly reducing the signal-to-noise ratio gain of the time-delay integration, and even causing integration failure. At the same time, when using a multi-channel analog-to-digital converter for analog-to-digital conversion, the data output in sample-and-hold mode has a fixed pixel delay and high / low byte splitting characteristics. If the data decoding and channel splicing logic design is improper, problems such as metadata misalignment and channel crosstalk will occur, resulting in loss of image resolution and grayscale accuracy. The analog signal output by the infrared detector has a weak amplitude and is easily affected by factors such as power supply ripple, digital circuit crosstalk, and transmission line electromagnetic interference. The large number of analog channels and long transmission paths under the multi-chip splicing architecture further amplify the risk of noise coupling. If the total root mean square noise of the system exceeds the standard, it will directly compress the imaging dynamic range and weaken the ability to detect weak targets. The space radiation environment can easily cause single-event upsets and single-event interrupts in SRAM-based FPGAs, leading to imaging logic anomalies or even system paralysis. Simultaneously, space electromagnetic interference can cause data transmission errors at communication interfaces, affecting the reliability of remote control command execution and telemetry data feedback, further reducing the system's on-orbit survivability. The video processing circuit needs to interface with multiple external units, including infrared detectors, satellite data transmission subsystems, and integrated controllers, encompassing various interfaces such as primary power input, remote control and telemetry, hardware time synchronization, program uploading, and image data transmission. Existing solutions suffer from fragmented interface functions and low board-level integration, resulting in large circuit size and high power consumption, making it difficult to meet the stringent constraints of weight, power consumption, and installation space required for spacecraft payloads.

[0003] Existing multi-chip splicing infrared video processing circuits mostly use FPGAs as the core control unit to generate detector drive timing and bias voltage, complete analog-to-digital conversion of analog signals, splicing of multi-chip data and format arrangement, and output image data. They also include power management and remote control / telemetry functions. For multi-chip signal readout, existing solutions employ a multi-module splicing TDI infrared detector readout processing architecture. All spliced ​​infrared chips share the same external clock signal to achieve unified clock synchronization, ensuring perfect alignment of acquisition and readout times for each line of the image. Each chip converts infrared light into an electrical signal and then superimposes multiple lines of signals passing the same target to brighten the signal. After a single round of acquisition, all chips output electrical signals sequentially column by column, simultaneously amplifying the signals. Zoned power supply reduces interference between chips. In terms of radiometric correction, existing solutions employ a multi-channel stitched imaging real-time radiometric correction signal processing architecture. The camera is aimed at a uniformly bright reference object to capture calibration benchmark data and record the original brightness value of each imaging unit. Based on the benchmark data, the brightness correction coefficient corresponding to each imaging unit is calculated and stored in the storage space of a dedicated processing chip for later use. During normal shooting, after the image data of each pixel is generated, the corresponding correction coefficient is immediately applied to adjust the brightness to eliminate the difference in brightness between different channels. The corrected images from each channel are stitched together into a complete wide-angle image according to the physical position of the chip stitching. The stitched and corrected complete image is packaged in an agreed format and transmitted to the back-end storage or display system. In digital domain image processing, existing solutions employ an FPGA-based digital domain TDI infrared imaging processing architecture. The FPGA receives the digitized image output from the infrared detector and stores it in a high-speed cache chip. Inside the FPGA, the data arrangement is adjusted to convert the row-stored image into a column-processed format. Based on the scanning motion speed, pixels corresponding to the same target in multiple consecutive frames are precisely aligned and then digitally superimposed to improve the brightness and clarity of dark targets. Two sets of caches work alternately to ensure uninterrupted imaging and real-time output. The final image data after superimposition and brightening is output to the backend display or storage device in a pre-defined format.

[0004] The existing solutions still have many shortcomings. Regarding non-uniformity correction, the non-uniformity correction parameters rely on ground pre-calibration and have poor on-orbit update capabilities. They cannot adapt to the dynamic changes in non-uniformity caused by temperature fluctuations and device parameter drift in the on-orbit environment, nor can they switch between multiple sets of parameters to adapt to different imaging scenarios. After long-term on-orbit operation, the imaging quality shows significant degradation. Regarding multi-chip timing synchronization, existing solutions simply share an external clock signal without an independent channel delay compensation mechanism. The analog-to-digital conversion sampling of each chip has fixed pixel delays and byte misalignments, causing phase shifts in the integration of time delays, thus weakening the integration signal-to-noise ratio. Furthermore, the large step size for integration time adjustment makes it difficult to meet the requirements for fine-grained adaptation of imaging dynamic range under different lighting conditions and different detection targets. Regarding analog link noise suppression, insufficient accuracy in detector bias voltage generation, imperfect power supply filter network design, and insufficient physical isolation between analog and digital regions result in link noise that fails to meet the requirements of aerospace-grade high-sensitivity imaging. At the same time, the lack of independent gain adjustment capability for multiple channels cannot specifically compensate for the response differences of each channel. Regarding radiation hardening, most solutions suffer from inadequate FPGA configuration refresh mechanisms and a lack of redundant hardening for critical functional modules. This makes rapid autonomous recovery difficult in the event of a single-event fault, and the insufficient on-orbit program upgrade capability fails to meet the demands of on-orbit functional iteration and fault repair. In terms of circuit integration, existing solutions suffer from fragmented interface functions and low board-level integration, resulting in large circuit size and high power consumption. This makes it difficult to meet the stringent constraints of weight, power consumption, and installation space required by aerospace payloads. Furthermore, the limited interface options reduce system adaptability and backup capabilities, making it unable to address the transmission protocol requirements of different application scenarios. Summary of the Invention

[0005] This invention aims to address the shortcomings of existing technologies, specifically providing a video processing circuit and related methods for multi-chip stitched infrared focal plane arrays, as detailed below: 1) In a first aspect, the present invention provides a video processing circuit for multi-chip stitched infrared focal plane arrays, the specific technical solution of which is as follows: Includes: a multi-channel analog front-end signal conditioning module, a multi-channel analog-to-digital conversion synchronous acquisition module, an FPGA real-time video processing main controller, a clock timing generation module, and a data output module; The FPGA real-time video processing main controller generates drive control signals for each detector chip in the stitched infrared focal plane detector array and sampling timing for the multi-channel analog-to-digital conversion synchronous acquisition module based on the same clock provided by the clock timing generation module. The FPGA real-time video processing main controller outputs the drive control signals to the stitched infrared focal plane detector array to control the stitched infrared focal plane detector array to perform integration and readout operations, so that the stitched infrared focal plane detector array outputs multiple analog electrical signals to the multi-channel analog front-end signal conditioning module. The multi-channel analog front-end signal conditioning module conditions the received multi-channel analog electrical signals and then sends them to the multi-channel analog-to-digital conversion synchronous acquisition module. The FPGA real-time video processing main controller outputs the sampling timing sequence to the multi-channel analog-to-digital conversion synchronous acquisition module. Under the control of the sampling timing sequence, the multi-channel analog-to-digital conversion synchronous acquisition module performs synchronous analog-to-digital conversion on the conditioned analog electrical signals to obtain multiple parallel digital image data streams and transmits them to the FPGA real-time video processing main controller. The FPGA real-time video processing main controller receives and performs timing alignment on multiple parallel digital image data streams. It then performs partitioned radiometric non-uniformity correction, blind pixel replacement, and image packing on the time-aligned data streams. Finally, it outputs the processed images through the data output module.

[0006] The beneficial effects of the video processing circuit for multi-chip stitched infrared focal plane array provided by this invention are as follows: The FPGA real-time video processing main controller generates the drive control signals for each detector chip in the spliced ​​infrared focal plane detector array and the sampling timing sequence for the multi-channel analog-to-digital converter synchronous acquisition module based on the same clock provided by the clock timing generation module. This ensures phase consistency of all timing signals in the entire system, eliminates TDI integration phase misalignment and signal-to-noise ratio gain loss caused by phase deviation of multi-chip drive signals, and supports fine adjustment of integration time to adapt to different lighting conditions and the dynamic range requirements of the detection target. The multi-channel analog front-end signal conditioning module conditions multiple analog electrical signals and sends them to the multi-channel analog-to-digital converter synchronous acquisition module. Working in conjunction with the sampling timing sequence output by the FPGA real-time video processing main controller, the multi-channel analog-to-digital converter synchronous acquisition module performs synchronous analog-to-digital conversion, reducing power supply ripple and digital crosstalk interference to the analog signal from the signal link source, improving the system signal-to-noise ratio, and enhancing the sensitivity of weak target detection. The FPGA real-time video processing main controller performs time-series alignment on multiple parallel digital image data streams, eliminating pixel delays and byte misalignments caused by analog-to-digital conversion in each channel, ensuring the spatial continuity of the stitched image. Then, it performs partitioned radiometric non-uniformity correction and blind pixel replacement on the time-aligned data streams, eliminating grayscale discontinuities and stripe noise caused by inconsistencies in photoelectric response between different detector chips, and filling in black or white spots in the image caused by damaged pixels, achieving a smooth grayscale transition in the stitched area. This ensures the consistency of the stitched image in both spatial geometry and radiometric response dimensions. The processed image is output through the data output module, meeting the comprehensive requirements of aerospace remote sensing imaging for high sensitivity and high image quality.

[0007] 2) In a second aspect, the present invention also provides a signal processing method for multi-chip stitched infrared focal plane arrays, employing any of the above-mentioned video processing circuits for multi-chip stitched infrared focal plane arrays, the method comprising: The FPGA real-time video processing main controller generates the drive control signals for each detector chip in the spliced ​​infrared focal plane detector array and the sampling timing of the multi-channel analog-to-digital conversion synchronous acquisition module based on the same source clock provided by the clock timing generation module. The FPGA real-time video processing main controller outputs drive control signals to the spliced ​​infrared focal plane detector array, controls the spliced ​​infrared focal plane detector array to perform integration and readout operations, and enables the spliced ​​infrared focal plane detector array to output multiple analog electrical signals to the multi-channel analog front-end signal conditioning module. The multi-channel analog front-end signal conditioning module conditions the received multi-channel analog electrical signals and sends the conditioned analog electrical signals to the multi-channel analog-to-digital conversion synchronous acquisition module. The FPGA real-time video processing main controller outputs the sampling timing sequence to the multi-channel analog-to-digital conversion synchronous acquisition module. Under the control of the sampling timing sequence, the multi-channel analog-to-digital conversion synchronous acquisition module performs synchronous analog-to-digital conversion on the conditioned analog electrical signal to obtain multiple parallel digital image data streams and transmits them to the FPGA real-time video processing main controller. The FPGA real-time video processing main controller receives multiple parallel digital image data streams and performs timing alignment on the multiple parallel digital image data streams to obtain the timing-aligned data stream. The FPGA real-time video processing main controller performs partitioned radiometric non-uniformity correction and blind pixel replacement on the time-aligned data stream to obtain the corrected image data. The FPGA real-time video processing main controller performs image packaging processing on the corrected image data and outputs the processed image through the data output module.

[0008] It should be noted that the beneficial effects of the technical solution of the second aspect of the present invention and the corresponding possible implementation can be found in the above description of the technical effects of the first aspect and its corresponding possible implementation, and will not be repeated here. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of the structure of a video processing circuit for multi-chip splicing infrared focal plane according to an embodiment of the present invention; Figure 2 This is a schematic flowchart of a signal processing method for multi-chip stitched infrared focal plane array according to an embodiment of the present invention. Detailed Implementation

[0010] like Figure 1As shown, an embodiment of the present invention provides a video processing circuit for multi-chip stitched infrared focal plane arrays, comprising: a multi-channel analog front-end signal conditioning module, a multi-channel analog-to-digital conversion synchronous acquisition module, an FPGA real-time video processing main controller, a clock timing generation module, and a data output module.

[0011] The FPGA real-time video processing main controller generates drive control signals for each detector chip in the stitched infrared focal plane detector array and sampling timing signals for the multi-channel analog-to-digital conversion synchronous acquisition module based on the same clock provided by the clock timing generation module. The FPGA real-time video processing main controller outputs the drive control signals to the stitched infrared focal plane detector array to control the stitched infrared focal plane detector array to perform integration and readout operations, so that the stitched infrared focal plane detector array outputs multiple analog electrical signals to the multi-channel analog front-end signal conditioning module. The specific implementation process is as follows: 1) The clock timing generation module generates a synchronous clock signal and sends it to the global clock input of the FPGA real-time video processing main controller. After receiving the synchronous clock signal, the clock management unit inside the FPGA real-time video processing main controller divides, multiplies, and adjusts the phase of the synchronous clock signal through the internal digital clock management module or phase-locked loop, generating multiple sub-clock signals with fixed phase relationships. These sub-clock signals are used to drive different internal logic modules and external interfaces.

[0012] 2) The FPGA real-time video processing main controller, based on the timing specifications of each detector chip in the spliced ​​infrared focal plane detector array, uses the master clock signal obtained by frequency division of the same source clock as the time base. Through internal finite state machine logic, it generates the integral signal, vertical drive signal, horizontal drive signal, and horizontal synchronization signal required for each detector chip. The vertical and horizontal drive signals are generated by counting the master clock signal according to the pixel array size of the detector chip. During the generation of the above drive control signals, the switching time of the integral signal, the rising edge of the vertical drive signal, the rising edge of the horizontal drive signal, and the rising edge of the horizontal synchronization signal are all aligned with a specific phase of the same source clock, thereby ensuring a fixed phase relationship between all drive control signals.

[0013] 3) The FPGA real-time video processing main controller outputs all generated drive control signals to the control input terminals of each corresponding detector chip in the stitched infrared focal plane detector array through its general-purpose input / output interface. Each detector chip, upon receiving its respective integration signal, begins charge accumulation; the integration time is determined by the duration of the high-level integration signal. Upon receiving the vertical drive signal, it begins vertical row transfer operations; upon receiving the horizontal drive signal, it begins horizontal pixel-by-column readout operations. The row synchronization signal is used to mark the start time of each row of pixel readouts, ensuring that the row readout actions of multiple detector chips are aligned in time.

[0014] 4) While generating drive control signals, the FPGA real-time video processing main controller generates sampling timing signals for the multi-channel analog-to-digital converter synchronous acquisition module based on a common clock source. This sampling timing signal includes a sampling start signal and a sampling clock signal. The transition edge of the sampling start signal is aligned with a specific phase of the common clock source, and the frequency of the sampling clock signal has an integer division relationship with the common clock source. The FPGA real-time video processing main controller outputs the sampling timing signal to the synchronization control input of the multi-channel analog-to-digital converter synchronous acquisition module through its general-purpose input / output interface. When the valid level of the sampling start signal arrives, the analog-to-digital converters of each channel simultaneously begin sampling the analog electrical signals at the input terminal, and complete a quantization conversion at each valid edge of the sampling clock signal, outputting one bit of digital image data. Since the sampling start signal and sampling clock signal of all channels originate from the same common clock source and are in phase, the digital image data streams output by each channel remain synchronized in time. After the spliced ​​infrared focal plane detector array completes integration and readout operations under the control of the drive control signal, each detector chip outputs the readout analog electrical signal to the multi-channel analog front-end signal conditioning module through its respective analog signal output terminal.

[0015] The "same-source clock" refers to a single clock source generated by the clock timing generation module, providing a unified time reference for all sub-modules in the entire video processing circuit that require clock signals. All drive control signals, sampling timing signals, and integration time control signals are generated based on this same-source clock through frequency division or multiplication to ensure a fixed phase relationship between the signals. The "drive control signal" refers to the set of control signals generated by the FPGA real-time video processing main controller and output to each detector chip in the stitched infrared focal plane detector array. This includes, but is not limited to, integration signals, vertical drive signals, horizontal drive signals, and line synchronization signals, used to control the detector chips to perform charge accumulation and signal readout operations according to a specified timing sequence. The "sampling timing" refers to the control signals generated by the FPGA real-time video processing main controller and output to the multi-channel analog-to-digital converter synchronous acquisition module. This controls the analog-to-digital converters of each channel in the multi-channel analog-to-digital converter synchronous acquisition module to sample and quantize the conditioned analog electrical signals at the same time, ensuring that the digital image data streams are aligned in time. A stitched infrared focal plane detector array refers to a large-field-of-view focal plane detector device composed of multiple infrared detector chips stitched together in a specific spatial position. Each detector chip receives infrared radiation and converts it into an analog electrical signal output. The multi-channel analog-to-digital conversion synchronous acquisition module includes acquisition circuits for multiple analog-to-digital conversion channels corresponding to the number of detector chips in the stitched infrared focal plane detector array. Under the synchronous control of the sampling timing of each channel, it simultaneously converts the multiple conditioned analog electrical signals into digital image data streams.

[0016] The multi-channel analog front-end signal conditioning module conditions the received multi-channel analog electrical signals and then sends them to the multi-channel analog-to-digital conversion synchronous acquisition module. The FPGA real-time video processing main controller outputs the sampling timing sequence to the multi-channel analog-to-digital conversion synchronous acquisition module. Under the control of the sampling timing sequence, the multi-channel analog-to-digital conversion synchronous acquisition module performs synchronous analog-to-digital conversion on the conditioned analog electrical signals to obtain multiple parallel digital image data streams, which are then transmitted to the FPGA real-time video processing main controller. The specific implementation process is as follows: 1) The multiple analog electrical signals output from the spliced ​​infrared focal plane detector array are respectively fed into the independent channels of the multi-channel analog front-end signal conditioning module. Each analog electrical signal first passes through a multi-stage power supply filtering network, which consists of multiple inductor-capacitor units connected in series. Each inductor-capacitor unit attenuates the ripple voltage on the power transmission path, so that the power supply voltage entering the subsequent circuit remains stable.

[0017] 2) Each analog electrical signal after power supply filtering enters the programmable bias generation circuit. The programmable bias generation circuit contains a digital-to-analog converter and an operational amplifier. The digital-to-analog converter receives the bias digital quantity sent by the FPGA real-time video processing main controller and converts the digital quantity into the corresponding analog bias voltage. The operational amplifier performs impedance transformation on the analog bias voltage and superimposes it onto the analog electrical signal so that the DC operating point of the analog electrical signal matches the input dynamic range of the multi-channel analog-to-digital conversion synchronous acquisition module.

[0018] 3) Each analog signal, after being superimposed with a bias voltage, enters a multi-channel independent analog gain adjustment channel. Each of these channels contains a programmable gain amplifier, the gain of which is configured by the FPGA real-time video processing main controller via a digital interface. There are eight selectable gain levels. After each analog signal is amplified by its respective programmable gain amplifier, the signal amplitude is adjusted to the optimal quantization range of the multi-channel analog-to-digital conversion synchronous acquisition module.

[0019] 4) Between the output of the multi-channel independent analog gain adjustment channel and the input of the multi-channel analog-to-digital conversion synchronous acquisition module, the analog-to-digital partition isolation cabling structure separates the analog signal transmission lines and digital signal transmission lines in physical space. The ground wires of the analog signal area and the digital signal area are connected at a single point to avoid high-frequency interference on the digital signal transmission line from coupling into the analog electrical signal.

[0020] 5) The multi-channel analog electrical signals that have undergone signal conditioning are sent from the output of the multi-channel analog front-end signal conditioning module to the analog input of each channel of the multi-channel analog-to-digital converter synchronous acquisition module. Each channel in the multi-channel analog-to-digital converter synchronous acquisition module contains an independent analog-to-digital converter, and the sampling start pins of all analog-to-digital converters are connected in parallel to the sampling timing signal line output by the FPGA real-time video processing main controller.

[0021] 6) The FPGA real-time video processing main controller outputs the sampling timing sequence to the multi-channel analog-to-digital converter synchronous acquisition module. The sampling timing sequence includes a sampling start pulse and subsequent continuous sampling clock signals. The rising edge of the sampling start pulse notifies all analog-to-digital converters to simultaneously sample and hold the analog electrical signals at their respective input terminals. Each cycle of the sampling clock signal corresponds to one quantization conversion operation.

[0022] 7) The multi-channel analog-to-digital converter synchronous acquisition module performs synchronous analog-to-digital conversion under the control of the sampling timing. All analog-to-digital converters latch the analog voltage value at their respective input terminals on the same rising edge of the sampling start pulse. Then, at each valid edge of the sampling clock, the latched analog voltage value is compared with the internal reference voltage, and the binary digital bits of the quantization result are output bit by bit. Since all analog-to-digital converters share the same sampling start pulse and the same sampling clock source, each channel completes sampling and quantization at the same time, and the output digital codes remain time-aligned.

[0023] 8) After synchronous analog-to-digital conversion is completed, each channel of the multi-channel analog-to-digital conversion synchronous acquisition module outputs one serial or parallel digital image data stream. The digital image data streams of all channels constitute multiple parallel digital image data streams. The multi-channel analog-to-digital conversion synchronous acquisition module transmits these digital image data streams simultaneously to the input pins of the FPGA real-time video processing main controller via the data bus. The grayscale value of each pixel in each digital image data stream corresponds to the quantized digital representation of the analog electrical signal amplitude of one pixel in the stitched infrared focal plane detector array.

[0024] The multi-channel analog front-end signal conditioning module refers to an analog signal processing circuit containing a programmable bias generation circuit, a multi-stage power supply filtering network, an analog-digital partitioned isolation wiring structure, and multiple independent analog gain adjustment channels. It is used to apply bias voltage, suppress noise, and amplify the multiple analog electrical signals output from the stitched infrared focal plane detector array. The multi-channel analog-to-digital conversion synchronous acquisition module refers to an acquisition circuit containing multiple analog-to-digital conversion channels corresponding to the number of detector chips in the stitched infrared focal plane detector array. Under the synchronous control of the sampling timing of each channel, it simultaneously converts the multiple conditioned analog electrical signals into digital image data streams. Synchronous analog-to-digital conversion means that, under the unified control of the sampling timing, the analog-to-digital converters of each channel in the multi-channel analog-to-digital conversion synchronous acquisition module simultaneously perform sample-and-hold and quantization encoding operations on the analog electrical signals at their respective input terminals, so that the digital image data of all channels are generated at the same time. Multi-channel parallel digital image data stream refers to the set of digital image data output by each channel analog-to-digital converter in the multi-channel analog-to-digital conversion synchronous acquisition module. Each data stream corresponds to the pixel grayscale value sequence of a detector chip, and the data streams maintain a parallel transmission relationship in time.

[0025] The FPGA real-time video processing main controller receives and performs timing alignment on multiple parallel digital image data streams. It then performs partitioned radiometric non-uniformity correction, blind pixel replacement, and image packing on the time-aligned data streams. The processed images are output via the data output module. The specific implementation process is as follows: 1) The FPGA real-time video processing main controller receives multiple parallel digital image data streams and sends each stream into its corresponding independent delay FIFO buffer. After each stream enters the buffer, a frame marker recognition counter monitors the start-of-frame (FOB) marker in each stream. When the FOB marker arrives, the counter records the current time. After the arrival times of the FOB markers for each stream are recorded, the FPGA real-time video processing main controller calculates the arrival time difference between them based on the recording results, identifying the data streams that arrive ahead of their time. For the data streams that arrive ahead of their time, the phase compensation register writes a delay configuration value to the corresponding independent delay FIFO buffer. This delay configuration value is equal to the time difference of the time difference. The independent delay FIFO buffer delays the input data by the specified time according to this delay configuration value before reading it from the output. After delay compensation, the pixel data, line synchronization signal, and FOB marker of all channels appear at the same time, completing the timing alignment of the multiple parallel digital image data streams.

[0026] 2) The time-aligned multi-channel parallel digital image data stream is alternately stored in two buffers of equal capacity. While the time-aligned image data of the first frame is being written to the first buffer, the second buffer synchronously outputs the image data already stored in the previous frame to the subsequent correction processing logic. After the first buffer has completely received all the pixel data of a frame, the read / write state machine switches the read / write roles of the two buffers. The first buffer switches to the read state and outputs data to the subsequent correction processing logic, while the second buffer switches to the write state and receives the time-aligned image data of the new frame. This alternating read / write process is repeated at the end of each frame to ensure that the image data stream is continuously fed into the subsequent correction processing logic.

[0027] 3) Image data output from the buffer enters the partitioned radiometric nonuniformity correction process pixel by pixel. The FPGA real-time video processing main controller reads the gain correction coefficient and offset correction coefficient corresponding to each detector chip in the stitched infrared focal plane detector array from the on-orbit parameter storage module. For each currently input pixel, the corresponding gain correction coefficient and offset correction coefficient are first selected according to the detector chip number to which the pixel belongs. Then, the original grayscale value of the pixel is multiplied by the gain correction coefficient and added to the offset correction coefficient to obtain the corrected grayscale value. The corrected grayscale value replaces the original grayscale value and continues to be passed to subsequent processing logic. All pixels flow through this multiplication and addition pipeline one by one, completing the radiometric nonuniformity correction for all pixels.

[0028] 4) After radiation non-uniformity correction, the image data is processed pixel by pixel for blind pixel replacement. The FPGA real-time video processing main controller reads the blind pixel coordinate list of all damaged pixels in the stitched infrared focal plane detector array from the on-orbit parameter storage module. For each input pixel, its coordinates are compared with each coordinate in the blind pixel coordinate list. If the current pixel coordinates match any item in the blind pixel coordinate list, the current pixel is determined to be a blind pixel. The gray values ​​of the four adjacent normal pixels (top, bottom, left, and right) are read, the average of these four gray values ​​is calculated, and the average is used to replace the gray value of the current pixel. If the current pixel coordinates do not match any item in the blind pixel coordinate list, the gray value of the current pixel remains unchanged. The output image data after blind pixel replacement is the processed complete image.

[0029] 5) After processing, the complete image is processed frame by frame and then packaged. The FPGA real-time video processing main controller first inserts a frame header identifier and an imaging parameter label at the beginning of each frame of image data. The frame header identifier marks the start position of a frame, and the imaging parameter label contains the integration time, gain level, and correction parameter version number information corresponding to the current frame. The FPGA real-time video processing main controller inserts a checksum at the end of each frame of image data. This checksum is calculated by using a cyclic redundancy check algorithm based on the frame header identifier, imaging parameter label, and all pixel grayscale values.

[0030] The input of the image packaging processing logic receives the complete image data stream from the multi-channel partitioned radiometric correction unit, which has completed independent correction of each channel. The output of the image packaging processing logic sends the packaged image data stream out of the FPGA real-time video processing main controller and into the data output module. The data output module contains three image output channels: fiber optic output interface, LVDS output interface, and CXP output interface. The FPGA real-time video processing main controller switches the packaged data stream to the corresponding output channel according to the currently selected output interface type.

[0031] 6) After image packaging is completed, the FPGA real-time video processing main controller switches the packaged data stream to the corresponding data output channel according to the currently selected output interface type. If the LVDS output interface is selected, the data stream is output to the LVDS output interface in low-voltage differential signal format; if the CXP output interface is selected, the data stream is output to the CXP output interface in CXP protocol format; if the fiber optic output interface is selected, the data stream is converted to optical signal format and output to the fiber optic output interface. The data output module transmits the processed image outward through the LVDS output interface, CXP output interface, and fiber optic output interface.

[0032] Timing alignment refers to the process of adjusting the pixel timing, row timing, and frame timing of each channel in a multi-channel parallel digital image data stream to be completely consistent, ensuring that the data output by all channels at the same time corresponds to the pixel positions in the same row and column of the stitched infrared focal plane detector array. Partition radiation non-uniformity correction refers to the process of recalculating the grayscale value of each pixel in the timing-aligned data stream using independent gain correction coefficients and offset correction coefficients for each detector chip in the stitched infrared focal plane detector array. This is used to eliminate inconsistencies in photoelectric response caused by pixel manufacturing variations and readout circuit discreteness between different detector chips. Blind pixel replacement refers to the process of searching pixel by pixel in the timing-aligned data stream to see if the current pixel coordinates match the pre-stored blind pixel coordinates. If a match is found, the grayscale value of the current pixel is replaced with the grayscale value of a surrounding normal pixel. This is used to eliminate black or white spots in the image caused by damaged pixels in the detector chip.

[0033] Optionally, in the above technical solution, the FPGA real-time video processing main controller includes a cross-chip timing synchronization calibration unit. This unit includes multiple independent delay FIFOs, a frame marker recognition counter, and a phase compensation register, corresponding to the number of channels in the multi-channel analog-to-digital conversion synchronous acquisition module. Each parallel digital image data stream enters its corresponding independent delay FIFO. The frame marker recognition counter identifies the frame start marker in each digital image data stream and calculates the arrival time difference between them. Based on the arrival time difference, the phase compensation register configures the delay amount of each independent delay FIFO, compensating for the delay of the timing-advanced digital image data stream. This aligns the pixel timing, line timing, and frame timing of each digital image data stream, resulting in a timing-aligned data stream. The specific implementation process is as follows: 1) The parallel digital image data streams output by the multi-channel analog-to-digital conversion synchronous acquisition module are respectively entered into the write end of the independent delay FIFO corresponding to the number of channels in the cross-chip timing synchronization calibration unit. Each digital image data stream is continuously written to the corresponding independent delay FIFO at a rate determined by the sampling timing. The write operation is not subject to any delay control, and the data is written to the buffer at its original arrival time.

[0034] 2) While each parallel digital image data stream is written to an independent delayed FIFO, a frame marker identification counter monitors each data stream in real time. Within each data bit period, the frame marker identification counter checks whether a specific binary sequence corresponding to a frame start marker appears in the data stream. This sequence is composed of a pre-agreed fixed bit pattern. When a frame marker identification counter detects a frame start marker in the current data stream, it immediately latches the current count value as the arrival time of the frame start marker for that data stream.

[0035] 3) After the cross-chip timing synchronization calibration unit detects the start-of-frame marker of its respective data stream in all channels' frame marker recognition counters, it reads out the arrival time count values ​​latched in each channel. The cross-chip timing synchronization calibration unit selects the channel with the smallest arrival time count value among all channels as the timing reference benchmark, and calculates the arrival time difference of each digital image data stream relative to the timing reference benchmark by subtracting the smallest arrival time count value from the arrival time count values ​​of the other channels.

[0036] 4) The cross-chip timing synchronization calibration unit writes the calculated arrival time differences of each channel into the corresponding phase compensation register. For channels with an arrival time difference of 0, the value in the phase compensation register remains 0, the corresponding independent delay FIFO delay is 0, and the data is directly transmitted from the write end to the read end. For channels with an arrival time difference greater than 0, the value in the phase compensation register is equal to the arrival time difference of that channel, expressed in units of pixel clock cycles.

[0037] 5) The independent delay FIFO performs delay compensation on the input data based on the delay value written in the phase compensation register. The independent delay FIFO contains a read pointer and a write pointer. The write pointer increments cyclically according to the data write rate, pointing to the next memory unit. The read pointer starts incrementing after the write pointer begins writing data, with the delay number of clock cycles equal to the value in the phase compensation register. During the delay period, data is continuously written to the independent delay FIFO, but the read pointer does not move; the data is temporarily stored in the buffer. After the delay ends, the read pointer starts incrementing, and data is output bit by bit from the read end. Independent delay FIFOs for timing-advanced digital image data streams are configured with larger delay values, while those for timing-lagging digital image data streams are configured with smaller delay values. The timing of data output from the independent delay FIFO read end of each channel tends to be consistent.

[0038] 6) After all channels of digital image data streams are output from their respective independent delayed FIFO readouts, the cross-chip timing synchronization calibration unit monitors whether the frame start markers output from each readout appear at the same time. If the frame start markers appear at the same time, it indicates that the pixel timing, line timing, and frame timing are all aligned, and the cross-chip timing synchronization calibration unit outputs the timing-aligned data stream. If the frame start markers do not appear at the same time, the cross-chip timing synchronization calibration unit recalculates the arrival time difference based on the actual arrival time of the frame start markers for each channel, updates the value in the phase compensation register, and repeats the delay compensation operation until the pixel timing, line timing, and frame timing of each data stream are completely aligned.

[0039] The cross-chip timing synchronization calibration unit refers to the digital logic circuit inside the FPGA real-time video processing main controller used to eliminate time deviations between multiple parallel digital image data streams. It consists of multiple independent delay FIFOs, frame marker recognition counters, and phase compensation registers.

[0040] The independent delay FIFO refers to a first-in, first-out (FIFO) buffer. Each digital image data stream corresponds to an independent delay FIFO. After data is written, it undergoes a configurable delay before being output from the read end. The delay time is determined by the value in the phase compensation register. The frame marker identification counter is a digital counter that monitors each digital image data stream. It identifies the frame start marker representing the start position of a frame in the data stream and records the arrival time of the frame start marker. The phase compensation register stores the required delay configuration value for each digital image data stream. This value is equal to the arrival time difference between the data streams and is used to control the delay amount of the independent delay FIFO. The frame start marker is a specific binary sequence embedded in the header of each frame of digital image data, used to identify the start position of a frame. The frame marker identification counter detects this binary sequence to determine the arrival of a new frame. The arrival time difference is the time difference between the arrival times of the frame start markers in each digital image data stream and the input of the cross-chip timing synchronization calibration unit. This difference is obtained by subtracting the arrival times recorded by the frame marker identification counter. Delay compensation refers to the process of applying an additional delay to a leading digital image data stream to align its output time with that of a lagging data stream. Pixel timing refers to the time interval between two adjacent pixel data outputs in a single digital image data stream, determined by the sampling timing and analog-to-digital conversion rate. Line timing refers to the time interval between two adjacent lines of pixel data in a single digital image data stream, determined by the line readout period of the detector chip. Frame timing refers to the time interval between two adjacent frames of image data in a single digital image data stream, determined by the frame readout period of the detector chip. Timing-aligned data stream refers to the set of parallel data streams where the pixel timing, line timing, and frame timing of each data stream are completely consistent after processing by a cross-chip timing synchronization calibration unit.

[0041] Optionally, in the above technical solution, the FPGA real-time video processing main controller includes a multi-channel partitioned radiometric correction unit. This unit comprises multiple sets of parallel multiplication units and a blind pixel coordinate register. The multi-channel partitioned radiometric correction unit reads the gain correction coefficient, offset correction coefficient, and blind pixel coordinates corresponding to each detector chip in the stitched infrared focal plane detector array. Each set of parallel multiplication units calculates the corrected grayscale value pixel by pixel for the input channel based on the gain correction coefficient and offset correction coefficient of its corresponding detector chip. The blind pixel coordinate register checks whether the current pixel coordinates match the blind pixel coordinates. If they match, the grayscale value of the surrounding normal pixels is read to replace the current pixel's grayscale value. After independent correction of each channel, the output is completed. The specific implementation process is as follows: 1) After timing alignment, the data stream enters the multi-channel partitioned radiometric correction unit pixel by pixel. The multi-channel partitioned radiometric correction unit reads the gain correction coefficient, offset correction coefficient, and all blind pixel coordinates within the chip's range from the on-orbit parameter storage module based on the detector chip number to which the current pixel belongs. The original grayscale value of the current pixel is sent to the parallel multiplication unit of the corresponding channel. The multiplier in the parallel multiplication unit multiplies the original grayscale value with the read gain correction coefficient to obtain the product. The adder in the parallel multiplication unit adds the product to the read offset correction coefficient to obtain the corrected grayscale value. This multiplication-addition operation is completed within one clock cycle. Each group of parallel multiplication units independently performs the above operation on multiple pixels simultaneously.

[0042] 2) After grayscale correction is completed, the current pixel coordinates are sent to the blind pixel coordinate register for retrieval. The blind pixel coordinate register stores a pre-written list of all blind pixel coordinates. The retrieval operation compares the row and column numbers of the current pixel with the row and column numbers of each item in the list one by one.

[0043] If the row and column numbers of the current pixel perfectly match any entry in the blind pixel coordinate register, the blind pixel coordinate register outputs a valid match signal. After receiving the valid match signal, the multi-channel partition radiometric correction unit reads the gray values ​​of the adjacent pixels above, below, to the left, and to the right of the current pixel, calculates the arithmetic mean of these four gray values, and replaces the corrected gray value of the current pixel with this arithmetic mean.

[0044] If the row and column numbers of the current pixel do not match any of the entries in the blind pixel coordinate register, the blind pixel coordinate register outputs an invalid match signal. The multi-channel partitioned radiometric correction unit keeps the corrected grayscale value of the current pixel unchanged and does not perform a replacement operation.

[0045] 3) After all pixels have undergone gain correction, offset correction, and blind pixel search and replacement in sequence, the multi-channel partitioned radiometric correction unit outputs the complete image data stream with independent corrections for each channel to the subsequent processing logic. The pixel data corresponding to each detector chip maintains its original spatial arrangement order during output, ensuring that the geometric position of the output image corresponds to the actual focal plane.

[0046] The image input terminal of the multi-channel partitioned radiometric correction unit receives time-aligned image data output from the ping-pong buffer RAM group. The parameter reading port of the multi-channel partitioned radiometric correction unit is connected to the on-orbit parameter storage module, and reads the gain correction coefficient, offset correction coefficient, and blind pixel coordinates corresponding to each detector chip from the on-orbit parameter storage module through the parallel data bus. The multi-channel partitioned radiometric correction unit has multiple sets of parallel multiplication operation units and blind pixel coordinate registers. Each detector chip in the stitched infrared focal plane detector array corresponds to a set of independent parallel multiplication operation units and blind pixel coordinate register channels. Each set of parallel multiplication operation units independently uses the gain correction coefficient and offset correction coefficient of the channel to perform pixel-by-pixel operations. The multi-channel partitioned radiometric correction unit outputs the corrected image data stream to the subsequent image packaging processing logic. The gray values ​​of the stitching seam area in the corrected image data stream have been smoothly fused during the pixel-by-pixel correction process by uniformly using the same gain correction coefficient and offset correction coefficient.

[0047] The multi-channel partitioned radiation correction unit refers to the digital logic circuitry within the FPGA real-time video processing main controller used to eliminate response non-uniformity between chips in the stitched infrared focal plane detector array and replace damaged pixels. It includes multiple sets of parallel multiplication units and blind pixel coordinate registers. The parallel multiplication unit consists of multiple sets of multiplier and adder combination circuits operating simultaneously. Each unit independently processes the grayscale value correction calculation for one pixel, and each parallel multiplication unit performs multiplication and addition operations on different pixels within the same clock cycle. The blind pixel coordinate register stores the plane position coordinates of all damaged pixels in the stitched infrared focal plane detector array, used for comparison with the current pixel coordinates during pixel-by-pixel processing. The gain correction coefficient is a pre-calculated scaling factor for each pixel of each detector chip in the stitched infrared focal plane detector array, used to correct differences in photoelectric response sensitivity between different pixels. Multiplying this coefficient by the original grayscale value yields a normalized grayscale value. Offset correction coefficient refers to a pre-calculated addition / subtraction coefficient for each pixel of each detector chip in the stitched infrared focal plane detector array. It is used to correct differences in dark current and readout circuit bias voltage between different pixels, and is added to the original grayscale value or the grayscale value multiplied by the gain to obtain the final corrected grayscale value. Blind pixel coordinates refer to the row and column numbers in the focal plane array of pixels that cannot respond normally to incident infrared radiation due to manufacturing defects or irradiation damage. Peripheral normal pixels refer to pixels in the focal plane array that are spatially adjacent to the current blind pixel but are not themselves blind pixels; they are used to calculate replacement values ​​to fill blind pixel positions.

[0048] Optionally, in the above technical solution, the multi-channel analog front-end signal conditioning module includes a programmable bias generation circuit, a multi-stage power supply filter network, an analog-to-digital partitioned isolation wiring structure, and multiple independent analog gain adjustment channels. The multi-channel analog front-end signal conditioning module provides bias voltage to each detector chip in the spliced ​​infrared focal plane detector array through a programmable bias generation circuit composed of a digital-to-analog converter and operational amplifiers. It suppresses power supply ripple through a multi-stage power supply filter network, isolates crosstalk between analog and digital signals through the analog-to-digital partitioned isolation wiring structure, and independently amplifies the gain of multiple analog electrical signals through multiple independent analog gain adjustment channels before outputting them to the multi-channel analog-to-digital converter synchronous acquisition module. The specific implementation process is as follows: 1) The multi-channel analog front-end signal conditioning module generates bias voltages for each detector chip in the stitched infrared focal plane detector array. The digital-to-analog converter (DAC) receives the digitally encoded bias voltage value from the FPGA real-time video processing main controller and converts it into a corresponding analog differential voltage output. An operational amplifier converts the analog differential voltage output from the DAC into a single-ended voltage signal and buffers and amplifies it to reduce the output impedance to below 1Ω. The output of the operational amplifier is directly connected to the bias voltage input pin of each detector chip in the stitched infrared focal plane detector array. The bias voltage amplitude for each detector chip is independently adjustable by changing the transmitted digital encoding value.

[0049] 2) The power supply to the multi-channel analog front-end signal conditioning module first enters a multi-stage power supply filtering network. The first stage of this network consists of an inductor connected in series in the positive path of the power supply, a first capacitor connected between the inductor's input and the power supply ground, and a second capacitor connected between the inductor's output and the power supply ground. After the first stage of filtering, the AC ripple component of the power supply voltage is bypassed to ground by the first and second capacitors, while the DC component is transmitted to the next stage through the inductor. Each stage of the filtering network repeats the same inductor series and capacitor bypass structure. After at least three stages of series filtering, the peak-to-peak value of the power supply ripple is reduced from its original value to less than 1% of its original value.

[0050] 3) The power supply voltage, purified by a multi-stage power filtering network, powers the analog circuitry in the multi-channel analog front-end signal conditioning module. The analog-digital partitioned isolated wiring structure separates the analog signal area and the digital signal area on the printed circuit board. The analog signal area houses all the analog circuitry and components of the multi-channel analog front-end signal conditioning module, while the digital signal area houses the FPGA real-time video processing main controller and digital interface circuitry. Signal transmission lines between the two areas are crossed by an isolation strip, with no copper plating or traces underneath. The ground planes of the analog signal area and the digital signal area are joined only at the return end of the power module, using a ferrite bead connection at the junction. Grounding protection traces are placed on both sides of the analog signal transmission lines, and the digital signal transmission lines are kept at least 5mm away from the analog signal transmission lines.

[0051] 4) The analog electrical signals output from the spliced ​​infrared focal plane detector array enter multiple independent analog gain adjustment channels. Each analog electrical signal first passes through an AC coupling capacitor to remove the DC bias component, and then enters the non-inverting input of a set of programmable gain amplifiers. The feedback resistor network inside the programmable gain amplifier contains eight resistor branches with different resistance values, each branch corresponding to a gain level. The FPGA real-time video processing main controller sends a gain selection code to the programmable gain amplifier through a digital control interface. The gain selection code controls the internal switch to select the corresponding feedback resistor branch, thereby setting the voltage gain value of the amplifier. The eight selectable gain levels cover a range from 1x to 10x, with a step interval of 1x. Each programmable gain amplifier independently receives its own gain selection code, without affecting each other, realizing independent gain adjustment of multiple analog electrical signals.

[0052] 5) After each analog electrical signal is amplified by its respective programmable gain amplifier, its voltage amplitude is increased from the original microvolt level to the optimal input range of the analog-to-digital converter, that is, between 50% and 80% of the full-scale input voltage. The amplified analog electrical signals are directly sent from the output of the multiple independent analog gain adjustment channels to the analog input of each channel of the multi-channel analog-to-digital converter synchronous acquisition module.

[0053] The programmable bias generation circuit refers to an analog voltage source circuit composed of a digital-to-analog converter (DAC) and an operational amplifier. The DAC receives digital control signals and converts them into analog voltages. The operational amplifier performs impedance transformation and power amplification on the analog voltage before outputting it to provide an adjustable DC bias voltage for the detector chip. The multi-stage power supply filtering network refers to a power supply noise suppression circuit composed of multiple inductors and capacitors connected in series in a π-type topology. Each stage consists of an inductor connected in series in the power path, and two capacitors connected between the inductor input and output terminals and ground, respectively. The multi-stage series connection attenuates power supply ripple step by step. The analog-digital partitioned isolated wiring structure refers to a structure in which analog signal transmission lines and digital signal transmission lines are arranged in different physical areas in the printed circuit board layout. The ground wire of the analog signal area and the ground wire of the digital signal area are connected at a single point at the power input to prevent high-frequency current coupling from the digital signal lines into the analog signal loop. The multi-channel independent analog gain adjustment channel refers to a signal amplification circuit containing multiple sets of independent programmable gain amplifiers. Each analog electrical signal corresponds to a programmable gain amplifier, and the gain value of each amplifier can be independently configured to one of eight different levels. A digital-to-analog converter (DAC) is an electronic device that converts digital encoded values ​​into corresponding analog voltage amplitudes, with its output analog voltage exhibiting a linear proportional relationship to the input digital encoded value. An operational amplifier (OPA) is a differential amplifier device with high gain, high input impedance, and low output impedance, used in conjunction with a feedback network to achieve precise voltage amplification and impedance transformation. Bias voltage is a DC voltage applied to a specific pin of a detector chip, used to set the operating point of the internal photodiode and readout circuit, ensuring the detector chip is in optimal photoelectric conversion mode. Power supply ripple is the AC fluctuation component superimposed on the DC power supply output voltage, caused by the switching action of the power converter or changes in load current, expressed as peak-to-peak or RMS value. Crosstalk is signal interference between analog and digital signal transmission lines caused by parasitic capacitance and inductance coupling, manifested as noise voltage induced on adjacent analog signal lines by high-frequency transitions in the digital signal.

[0054] Optionally, in the above technical solution, the FPGA real-time video processing main controller also includes a ping-pong buffer RAM group. The ping-pong buffer RAM group is located after the cross-chip timing synchronization calibration unit. The ping-pong buffer RAM group includes two buffer areas of the same capacity and a read / write state machine. The read / write state machine controls the two buffer areas to alternately perform image frame writing and reading operations. When one frame of image in the timing-aligned data stream is written to one of the buffer areas, the other buffer area synchronously outputs the buffered image frame to the multi-channel partition radiometric correction unit. The specific implementation process is as follows: 1) The ping-pong buffer RAM group receives the timing-aligned data stream from the cross-chip timing synchronization calibration unit. Pixel data in the timing-aligned data stream enters the input data bus of the ping-pong buffer RAM group row by row, pixel by pixel. The read / write state machine within the ping-pong buffer RAM group enters the initial state after system power-on reset, setting the first buffer area to write mode and the second buffer area to read mode. In the initial state, the second buffer area has no valid image frames, and the read operation outputs empty data.

[0055] 2) The read / write state machine determines whether the write address counter of the first buffer has reached the total number of pixels in a frame. The write address counter increments by 1 in each pixel clock cycle. When the value of the write address counter is equal to the total number of pixels in a frame minus 1, it indicates that the current image frame has been completely written to the first buffer, and the read / write state machine latches the write completion flag.

[0056] 3) After the write completion flag is valid, the read / write state machine switches the operating states of the two buffers within one clock cycle. The first buffer switches from write state to read state, and the second buffer switches from read state to write state. After the switch is complete, the read address counter of the first buffer increments from 0, and the stored image frame pixel data is output bit by bit to the data bus; the write address counter of the second buffer increments from 0, and the pixel data of the next frame of the image is written from the timing-aligned data stream.

[0057] 4) The output data of the first buffer is continuously transmitted to the multi-channel partitioned radiometric correction unit via the data bus. While the first buffer outputs a complete image frame, the second buffer continuously receives and completely writes the time-aligned data stream of the new frame. When the write address counter of the second buffer reaches the total number of pixels of a frame minus 1, the writing of the new frame is completed, and the read / write state machine switches the working states of the two buffers again.

[0058] 5) The read / write state machine repeatedly performs the working state switching operation after the first buffer has been read and the second buffer has been written. The two buffers alternately write and read in units of frames. At any given time, one buffer is always in the write state receiving the timing-aligned data stream, while the other buffer is in the read state outputting the buffered image frames to the multi-channel partitioned radiometric correction unit. Starting from the first image frame, each subsequent image frame is sequentially written to the two buffers alternately, while the previously buffered image frames are output synchronously, ensuring uninterrupted transmission of image data from the cross-chip timing synchronization calibration unit to the multi-channel partitioned radiometric correction unit. Simultaneously with the output of each frame of image data to the multi-channel partitioned radiometric correction unit, the ping-pong buffer RAM group reads the gain correction coefficients, offset correction coefficients, and blind pixel coordinates required for the current frame processing from the on-orbit parameter storage module. The read correction parameters and the corresponding pixel data are then synchronously sent to the multi-channel partitioned radiometric correction unit, ensuring that the correction parameters are ready when the pixel data enters the parallel multiplication unit and the blind pixel coordinate register, without requiring additional waiting time.

[0059] The ping-pong buffer RAM group refers to an image data buffer structure consisting of two buffer areas of the same capacity. Under the control of the read / write state machine, it alternately executes the write and read operations of image frames, ensuring that the reception and output of image data do not block each other. The read / write state machine refers to a finite state logic circuit that controls the switching of the working modes of the two buffer areas. It determines whether each buffer area is in the write state or the read state at the next moment based on the write completion flag and read completion flag of the current buffer area.

[0060] Optionally, in the above technical solution, the data output module includes an LVDS output interface, a CXP output interface, and an optical fiber output interface. The image packaging processing includes the FPGA real-time video processing main controller adding a frame header identifier and imaging parameter label to the header of the processed image data according to the currently selected output interface type, adding a checksum to the tail, and outputting the packaged data stream to the interface of the data output module corresponding to the output interface type. The specific implementation process is as follows: 1) The FPGA real-time video processing main controller reads the output interface type selection value stored in its internal register. This selection value is pre-written into the register by ground injection commands or system configuration parameters, and can be one of three: LVDS output interface, CXP output interface, or fiber optic output interface. The FPGA real-time video processing main controller determines the target interface type to use for the current image packet output based on the selection value.

[0061] 2) After receiving a complete frame of image from the multi-channel partitioned radiometric correction unit, the FPGA real-time video processing main controller initiates image packetization. Based on the currently selected output interface type, the FPGA real-time video processing main controller selects a packetization format from three preset formats that matches the interface type. The packetization format corresponding to the LVDS output interface uses a transmission protocol with a fixed parallel data bit width of 16 bits; the packetization format corresponding to the CXP output interface includes additional control words and line synchronization markers; and the packetization format corresponding to the fiber optic output interface uses an 8B / 10B encoded serial data stream format.

[0062] 3) The FPGA real-time video processing main controller inserts a frame header identifier at the beginning of the frame image data. The frame header identifier is a fixed 32-bit binary sequence containing a continuous frame start synchronization code and a frame number. The synchronization code uses a specific code pattern to lock byte boundaries at the receiving end, and the frame number is the incrementing sequence number of the frame in the continuous output sequence, starting from 0 and incrementing by 1 for each frame, modulo 256.

[0063] 4) After the frame header identifier is written, the FPGA real-time video processing main controller immediately writes the imaging parameter label. The imaging parameter label contains the integration time setting value of the current frame, the gain level encoding value of each channel, and the correction coefficient version number. The integration time setting value is expressed in the number of clock cycles from the same source, the gain level encoding value corresponds to the current level number in the eight gain levels, and the correction coefficient version number identifies the batch number of the currently used gain correction coefficient and offset correction coefficient. The above parameter values ​​are arranged in a fixed byte order, with a total length of 16 bytes.

[0064] 5) After the imaging parameter labels are written, the FPGA real-time video processing main controller writes the corrected grayscale values ​​of all pixels in a frame into the data stream in row order. Each row of pixel data is arranged continuously with no extra interval between rows until the grayscale value of the last pixel in the last row of the frame is written.

[0065] 6) After all pixel data has been written, the FPGA real-time video processing main controller adds a checksum to the end of the frame data. The checksum is generated by the cyclic redundancy check (CRC) calculation unit inside the FPGA real-time video processing main controller by performing serial operations on the frame header identifier, imaging parameter label, and all pixel grayscale values. The generator polynomial is a 32nd-order standard polynomial, and the calculation result is a 32-bit checksum. The FPGA real-time video processing main controller appends this 32-bit checksum to the last pixel data, completing the encapsulation of one frame of data.

[0066] 7) The encapsulated complete data stream is sent from the output pins of the FPGA real-time video processing main controller to the data output module. The FPGA real-time video processing main controller outputs the encapsulated data stream through the corresponding output pin group according to the currently selected output interface type. If the LVDS output interface is selected, the data stream is output in 16-bit parallel format to the corresponding differential pin pair of the LVDS output interface; if the CXP output interface is selected, the data stream is converted to a serial bit stream and embedded with a control word before being output to the corresponding coaxial drive pin of the CXP output interface; if the fiber optic output interface is selected, the data stream undergoes parallel-to-serial conversion and electro-optic conversion before being output to the corresponding laser drive pin of the fiber optic output interface. The output data of all three interfaces includes a complete frame header identifier, imaging parameter label, pixel data, and checksum structure, differing only in physical layer encoding and electrical format.

[0067] The LVDS output interface refers to a low-voltage differential signal output interface that transmits image data through a pair of differential signal lines, using the voltage difference between the two lines to represent binary data. It is suitable for short-distance local debugging and image display applications. The CXP output interface refers to a CoaxPress high-speed image transmission interface that simultaneously transmits image data, control commands, and power signals through a coaxial cable. It supports high-bandwidth long-distance transmission and is suitable for high-speed image storage applications. The fiber optic output interface converts electrical signals into optical signals for transmission through optical fibers. It uses light pulses to represent data and features long transmission distances and strong resistance to electromagnetic interference, making it suitable for long-distance data transmission on satellites. The frame header identifier is a fixed bit sequence located at the beginning of each frame of image data, used to mark the start of a frame. The receiver synchronizes frame boundaries by detecting the frame header identifier. The imaging parameter label is a variable-length data field following the frame header identifier, containing information such as the integration time value, gain level code, and correction parameter version number corresponding to the current image frame, used to assist the receiver in correctly parsing the image data. The checksum refers to the redundant check bit sequence located at the end of each frame of image data. It is calculated using a cyclic redundancy check algorithm from the frame header identifier, imaging parameter label, and all pixel grayscale values. The receiving end uses the checksum to verify the correctness of the data transmission. The output interface type refers to the currently selected image data transmission channel category, which can be LVDS, CXP, or fiber optic, and is used to determine the data packet format and output physical channel. The encapsulated data stream refers to the complete data frame sequence formed by adding the frame header identifier, imaging parameter label, and checksum to the original image pixel data, organized according to the electrical protocol and transmission format of the selected output interface.

[0068] Optionally, the above technical solution also includes an on-orbit parameter storage module. This module employs a dual-partition FLASH storage architecture, comprising a first partition and a second partition. The first partition stores current operating parameters, including gain correction coefficients, offset correction coefficients, blind pixel coordinates, and timing compensation values ​​corresponding to each detector chip in the stitched infrared focal plane array. The second partition receives and stores new parameters injected from the ground, including updated gain correction coefficients, offset correction coefficients, blind pixel coordinates, and timing compensation values. The on-orbit parameter storage module automatically switches to the second partition upon power-up or when a fault is detected in the first partition. The on-orbit parameter storage module provides updated gain correction coefficients, offset correction coefficients, and blind pixel coordinates to the multi-channel partitioned radiation correction unit. The specific implementation process is as follows: 1) Upon power-up, the on-orbit parameter storage module performs a partition selection operation. The internal power-up detection circuit monitors the supply voltage. When the supply voltage rises above 90% of the nominal operating voltage, the power-up detection circuit outputs a reset release signal. Upon receiving the reset release signal, the on-orbit parameter storage module first attempts to read the preset partition status flag from the starting address of the first partition in the dual-partition FLASH storage architecture. If the read is successful and the status flag value equals the preset valid value, the on-orbit parameter storage module sets the first partition as the currently active partition. If the read fails or the status flag value does not equal the preset valid value, the on-orbit parameter storage module sets the second partition as the currently active partition.

[0069] 2) The on-orbit parameter storage module provides all parameters stored in the currently active partition to the FPGA real-time video processing main controller. The on-orbit parameter storage module sequentially transmits the gain correction coefficients, offset correction coefficients, blind pixel coordinates, and timing compensation values ​​stored in the first or second partition to the internal parameter register of the FPGA real-time video processing main controller via a parallel data bus. The multi-channel partition radiometric correction unit of the FPGA real-time video processing main controller reads the gain correction coefficients, offset correction coefficients, and blind pixel coordinates from the internal parameter register for pixel-by-pixel correction calculations. The cross-chip timing synchronization calibration unit of the FPGA real-time video processing main controller reads the timing compensation values ​​from the internal parameter register to configure the phase compensation register.

[0070] 3) When ground-based calibration parameters need to be updated, the new parameters injected from the ground are received via the dual-channel CAN remote control and telemetry interface and sent to the on-orbit parameter storage module. The ground injection command includes a target address field, which points to the starting address of the second partition of the dual-partition FLASH storage architecture. The on-orbit parameter storage module parses the received ground injection data and writes the updated gain correction coefficient, offset correction coefficient, blind pixel coordinates, and timing compensation values ​​sequentially into the address space corresponding to the second partition. During the writing process, the content of the first partition remains unchanged, and the FPGA real-time video processing main controller continues to use the current operating parameters in the first partition for image processing.

[0071] 4) During normal operation, the on-orbit parameter storage module continuously monitors the working status of the first partition. Within each image frame processing cycle, the on-orbit parameter storage module reads a verification flag from the first partition and compares the read flag value with a preset valid value. If the comparison results match, the first partition is considered to be working normally, and the current working parameters in the first partition continue to be used. If the comparison results do not match, the first partition is considered to be faulty, and the on-orbit parameter storage module performs an automatic switching operation, switching the parameter reading source of the FPGA real-time video processing main controller from the first partition to the second partition.

[0072] 5) After the automatic handover operation is completed, the on-orbit parameter storage module reads the new parameters from the second partition and transmits them to the internal parameter register of the FPGA real-time video processing main controller. The multi-channel partition radiometric correction unit of the FPGA real-time video processing main controller uses the updated gain correction coefficients, offset correction coefficients, and blind pixel coordinates to process each subsequent frame of image data. After the handover is completed, the on-orbit parameter storage module writes the current active partition flag into the internal status register for ground telemetry to read and confirm the handover status.

[0073] The dual-channel CAN remote control and telemetry interface employs differential transmission and a dual-channel hot backup circuit design to achieve space electromagnetic interference protection. The dual-channel CAN remote control and telemetry interface includes two completely independent differential transmission links: a main channel and a backup channel. These two links are completely independent at the physical and protocol layers, each containing its own transceiver and isolation circuitry. The receiving and transmitting ends of the two links are connected in parallel to the FPGA real-time video processing main controller. The main channel and backup channel simultaneously receive ground-based commands and transmit telemetry data. The status monitoring logic within the FPGA real-time video processing main controller continuously monitors the received signal quality of the main channel. When the signal error rate of the main channel exceeds a preset threshold or a communication timeout occurs, the FPGA real-time video processing main controller automatically switches the data transmission link from the main channel to the backup channel, without losing previously received command data during the switching process. The FPGA real-time video processing main controller performs real-time comparison of the received data from the dual-channel CAN remote control and telemetry interface, comparing the same frame of command data received from the main channel and backup channel bit by bit. If the main channel data is correct, it is used; otherwise, the backup channel data is used.

[0074] The on-orbit parameter storage module refers to a non-volatile storage circuit employing a dual-partition FLASH storage architecture. It stores the gain correction coefficients, offset correction coefficients, blind pixel coordinates, and timing compensation values ​​of each detector chip in the stitched infrared focal plane detector array. Located outside the FPGA real-time video processing main controller and connected to it via a parallel data bus, the dual-partition FLASH storage architecture divides the physical address space of the FLASH memory into two independent storage areas. Each area can independently perform erase, write, and read operations, and the two areas are isolated from each other. Erasing or writing operations in one area do not affect the data already stored in the other area. The first partition is the storage area in the dual-partition FLASH storage architecture used to store the currently used operating parameters. Upon power-up, the FPGA real-time video processing main controller reads all correction parameters and configuration data from the first partition by default. The second partition is the storage area in the dual-partition FLASH storage architecture used to receive and store new parameters injected from the ground. Ground injection operations only write to the second partition and do not affect the currently running operating parameters in the first partition. Current operating parameters refer to the complete set of gain correction coefficients, offset correction coefficients, blind pixel coordinates, and timing compensation values ​​currently used by the FPGA real-time video processing main controller. These parameters are read from the first partition and loaded into the parameter register inside the FPGA real-time video processing main controller. New parameters refer to the updated gain correction coefficients, offset correction coefficients, blind pixel coordinates, and timing compensation values ​​transmitted from the ground control station. These parameters are received via remote control commands through the dual-channel CAN remote control and telemetry interface and written to a specified address range in the second partition. Timing compensation values ​​refer to a set of digital values ​​stored in the on-orbit parameter storage module. These values ​​are used to configure the delay value of the phase compensation register in the cross-chip timing synchronization calibration unit, representing the arrival time difference between each digital image data stream, expressed in units of pixel clock cycles. Ground control station transmission refers to the process of the ground control station sending data to the on-orbit equipment via a wireless communication link. The data is transmitted in the form of remote control command frames, containing the target address, write command, and parameter data body to be written. The first partition fault refers to the situation where, when the on-orbit parameter storage module reads data from the first partition, the read check code is inconsistent with the check code recalculated based on the read data content, or the read specific flag bit does not match the preset value.

[0075] Optionally, in the above technical solution, the FPGA real-time video processing main controller further includes an SEFI detection and refresh circuit. The SEFI detection and refresh circuit is used to detect the configuration status of the FPGA real-time video processing main controller in real time and perform a configuration refresh when a single-event function interrupt is detected. The timing alignment logic and partition radiation correction logic in the FPGA real-time video processing main controller adopt a triple-modulus redundancy design, and the specific implementation process is as follows: 1) The SEFI detection and refresh circuit inside the FPGA real-time video processing main controller continuously monitors the configuration status after the FPGA real-time video processing main controller is powered on. The SEFI detection and refresh circuit is connected to the INIT_B and DONE pins of the FPGA real-time video processing main controller through dedicated monitoring pins. The INIT_B pin level indicates whether the configuration memory initialization is complete, and the DONE pin level indicates whether the configuration data has been successfully loaded. The SEFI detection and refresh circuit samples the level values ​​of the INIT_B and DONE pins in each clock cycle and compares the sampled values ​​with the expected level values ​​under normal operating conditions.

[0076] 2) When the SEFI detection refresh circuit detects that the DONE pin level transitions from high to low and remains low for more than a preset counting threshold, it determines that a single-event interrupt has occurred in the FPGA real-time video processing main controller. The preset counting threshold is 1024 clock cycles, used to filter out instantaneous level jitter. After determining that a single-event interrupt has occurred, the SEFI detection refresh circuit sets the configuration refresh start flag register to the valid state.

[0077] 3) After the configuration refresh start flag register becomes valid, the SEFI detection refresh circuit triggers the configuration refresh execution process. The SEFI detection refresh circuit first pulls the PROGRAM_B pin of the FPGA real-time video processing main controller low, causing the internal configuration memory of the FPGA real-time video processing main controller to clear all existing configuration data, and all user logic output pins of the FPGA real-time video processing main controller switch to a high-impedance state. The PROGRAM_B pin is pulled low for at least 300 nanoseconds.

[0078] 4) After the PROGRAM_B pin is pulled low, the SEFI detection refresh circuit releases the PROGRAM_B pin, and the FPGA real-time video processing main controller enters the configuration data loading state. The FPGA real-time video processing main controller reads the pre-stored configuration bit stream starting from the starting address of the external FLASH memory. The read operation is performed through the serial configuration interface, reading one bit from the external FLASH memory each clock cycle. The configuration bit stream stored in the external FLASH memory contains complete logical function description data of the FPGA real-time video processing main controller.

[0079] 5) After the complete configuration bitstream is loaded into the internal configuration memory of the FPGA real-time video processing main controller, the FPGA real-time video processing main controller automatically performs configuration data verification and internal reset operations. After the configuration data verification is successful, the DONE pin level changes from low to high, indicating that the configuration refresh is complete. After the SEFI refresh detection circuit detects the high level on the DONE pin, it clears the configuration refresh start flag register, continues to monitor the configuration status, and waits for the next single-event interrupt to occur.

[0080] 6) The timing alignment logic and partitioned radiation correction logic in the FPGA real-time video processing main controller employ a triple-modular redundancy design to achieve single-event upset protection. The three redundant copies of the timing alignment logic independently execute frame start marker identification, arrival time difference calculation, and independent delay FIFO delay configuration operations. The input signals for the three copies are identical, all originating from the parallel digital image data streams output by the multi-channel analog-to-digital converter synchronous acquisition module. The output signals of the three copies are three sets of phase compensation register configuration values, which are fed in parallel into the majority voter.

[0081] 7) The majority voter receives three sets of phase compensation register configuration values ​​from three redundant copies of the timing alignment logic output. It performs a majority vote operation on each bit of these three configuration values. The majority vote operation is performed bit-by-bit, with each bit corresponding to three input values. If at least two of the three input values ​​are high, the output is high; if at least two are low, the output is low. The voting result output by the majority voter is written as the final phase compensation register configuration value to the delay control terminal of the independent delay FIFO.

[0082] 8) The three redundant replicas of the partitioned radiometric correction logic independently perform the gain correction coefficient multiplication, offset correction coefficient addition, and blind pixel coordinate retrieval and comparison operations. The input signals to the three replicas are identical, each containing the gain correction coefficient, offset correction coefficient, and blind pixel coordinates read from the on-orbit parameter storage module, as well as the current pixel coordinates and current pixel grayscale value from the time-aligned data stream. The output signals of the three replicas are three sets of corrected grayscale values, which are fed in parallel into another majority voter.

[0083] 9) The majority voter corresponding to the partitioned radiometric correction logic receives three sets of corrected grayscale values ​​from the outputs of three redundant replicas and performs a majority vote operation on each bit of the three sets of grayscale values. The voting result output by the majority voter is used as the final corrected grayscale value of the partitioned radiometric correction logic and output to the image packaging processing logic. In the triple redundancy design, if any redundant replica experiences a single-event upset (SEOR) that causes an output error, the outputs of the other two redundant replicas remain correct, the majority voter outputs the correct result, and the logic error caused by the SEOR is masked.

[0084] The configuration logic of the multi-channel analog-to-digital converter (ADC) synchronous acquisition module and the communication logic of the dual-channel CAN remote control and telemetry interface in the FPGA real-time video processing main controller employ a triple-modular redundancy design to achieve single-event upset protection. The three redundant copies of the configuration logic of the multi-channel ADC synchronous acquisition module independently execute the generation operations of sampling timing configuration parameters and bias digital values. The input signals of the three copies are identical, all originating from the configuration values ​​written to the internal registers of the FPGA real-time video processing main controller. The output signals of the three copies are three sets of configuration parameters, which are fed in parallel to a majority voter. The majority voter performs a majority vote operation on each bit of the three sets of configuration parameters, and the voting result is output as the final configuration parameter to the control terminal of the multi-channel ADC synchronous acquisition module. Similarly, the three redundant copies of the communication logic of the dual-channel CAN remote control and telemetry interface independently execute the remote control command reception and decoding and telemetry data transmission and encoding operations. The input signals of the three copies are identical, all originating from the receive data line of the dual-channel CAN remote control and telemetry interface. The output signals of the three replicas are three sets of telemetry data to be sent. The three sets of telemetry data are sent to the majority voter in parallel. The majority voter performs a majority vote operation on each bit of the three sets of telemetry data. The voting result is sent out as the final telemetry data through the dual-channel CAN remote control and telemetry interface.

[0085] The SEFI detection refresh circuit refers to a dedicated digital logic circuit within the FPGA real-time video processing main controller used to monitor the configuration memory status and trigger a reconfiguration operation when an anomaly is detected. It monitors the configuration pin levels of the FPGA real-time video processing main controller in real time. Configuration status refers to the integrity status of the bitstream data loaded in the configuration memory of the FPGA real-time video processing main controller. This is determined by monitoring the INIT_B and DONE pin levels of the FPGA real-time video processing main controller to determine whether the configuration was successfully completed and whether any errors occurred in the configuration data. Single-event interrupt (SEE) refers to the phenomenon where a high-energy particle in the space radiation environment collides with the configuration memory unit of the FPGA real-time video processing main controller, causing one or more bits in the configuration bitstream to flip, resulting in errors or complete loss of functionality within the FPGA real-time video processing main controller's internal logic. Configuration refresh refers to the process of rereading the complete configuration bitstream from external FLASH memory and reloading it into the FPGA real-time video processing main controller's internal configuration memory without disconnecting the power supply to the FPGA real-time video processing main controller. This is used to recover configuration data damaged by a SEE. Timing alignment logic refers to the combinational and sequential logic circuits within the cross-chip timing synchronization calibration unit of the FPGA real-time video processing main controller that implement frame start marker recognition, arrival time difference calculation, and independent delay FIFO delay configuration. Partition radiometric correction logic refers to the combinational and sequential logic circuits within the multi-channel partition radiometric correction unit of the FPGA real-time video processing main controller that implement gain correction coefficient multiplication, offset correction coefficient addition, and blind cell coordinate retrieval and comparison. Triple modular redundancy design refers to replicating the same functional logic circuit into three identical independent logic circuits. All three circuits receive identical input signals and perform the same operations simultaneously. Their outputs are connected to a majority voter, which votes bit-by-bit on the three outputs, selecting at least two identical output values ​​as the final output result.

[0086] Optionally, in the above technical solution, the FPGA real-time video processing main controller generates an integration time control signal based on a common clock. The integration time control signal continuously adjusts the integration time of each detector chip in the stitched infrared focal plane detector array with a minimum step size of one clock cycle of the common clock. The FPGA real-time video processing main controller outputs the integration time control signal to the stitched infrared focal plane detector array to control the charge accumulation time of each detector chip, so that the video processing circuit can adapt to the corresponding imaging dynamic range under different lighting conditions and different detection targets. The integration time control signal and the drive control signal are uniformly generated by the FPGA real-time video processing main controller based on the common clock. The switching time of the horizontal synchronization signal in the drive control signal and the integration time control signal maintains a fixed phase relationship. The specific implementation process is as follows: 1) The integration time counter inside the FPGA real-time video processing main controller receives the integration time value written by the ground injection command. This value is in units of the same source clock cycles, with a minimum value of 1 and a maximum value determined by the saturation charge capacity of the detector chip and the line readout cycle. The FPGA real-time video processing main controller clears the integration time counter to zero at the beginning of each frame cycle, and the integration time counter begins to increment the count for the rising edge of the same source clock.

[0087] 2) The integration time control signal generation logic inside the FPGA real-time video processing main controller sets the integration time control signal output pin to a high level while simultaneously clearing the integration time counter. The integration time counter increments by 1 for each rising edge of a corresponding clock signal. The current count value of the integration time counter is compared in real-time with the integration time value written by the ground injection command in a digital comparator. When the current count value of the integration time counter equals the integration time value, the digital comparator outputs a match signal, and the integration time control signal generation logic switches the integration time control signal output pin from high to low, thus controlling the high-level duration of the integration time control signal.

[0088] 3) The high-level duration of the integration time control signal is equal to the integration time value multiplied by the length of one clock cycle of the same source clock. Adjusting the integration time value changes the high-level duration of the integration time control signal. When the ground needs to extend the integration time, a larger integration time value is used. The integration time counter needs to count more clock cycles of the same source clock to reach the matching value, thus extending the high-level duration of the integration time control signal and correspondingly extending the charge accumulation time of each detector chip. When the ground needs to shorten the integration time, a smaller integration time value is used. The high-level duration of the integration time control signal is shortened, thus shortening the charge accumulation time of each detector chip. The minimum step size for each adjustment of the integration time is equal to the length of one clock cycle of the same source clock.

[0089] 4) The FPGA real-time video processing main controller simultaneously generates integral time control signals and drive control signals, both using the same source clock as their time base. The horizontal synchronization signal in the drive control signal is generated by dividing the source clock using a horizontal synchronization counter. The counting period of the horizontal synchronization counter is fixed and equal to the total number of clock cycles required to read one line of pixels. The switching time of the integral time control signal is controlled by the integral time counter. The integral time counter and the horizontal synchronization counter share the rising edge of the source clock for incrementing. The two counters operate synchronously within the same clock domain, and the phase deviation between the two counters remains 0 at any given time.

[0090] 5) The timing constraint logic inside the FPGA real-time video processing main controller ensures that the time difference between the switching moment of the integration time control signal from high to low and the rising edge of the horizontal synchronization signal remains constant. The timing constraint logic connects the matched output signal of the integration time counter and the overflow signal of the horizontal synchronization counter to the data inputs of two flip-flops, which are driven by the same edge of the same source clock. Since the integration time counter and the horizontal synchronization counter share the same source clock and operate simultaneously, the time difference between the switching moment of the integration time control signal and the switching moment of the horizontal synchronization signal is equal to a fixed number of source clock cycles. This difference does not change with the value of the integration time and always remains the phase offset value pre-written for the ground injection command.

[0091] 6) The FPGA real-time video processing main controller outputs the integration time control signal and drive control signal to the corresponding control pins of each detector chip in the stitched infrared focal plane detector array through a general-purpose input / output interface. During the high-level period of the integration time control signal, each detector chip continuously accumulates charge, and the amount of accumulated charge is proportional to the incident infrared radiation intensity and the integration time length. After the integration time control signal switches to a low level, each detector chip stops accumulating charge, and the drive control signal initiates the signal readout operation, converting the accumulated charge into an analog electrical signal output.

[0092] 7) In low-light conditions, the amplitude of the analog electrical signal output by the detector chip is low. A larger integration time value is input via remote control from the ground. The FPGA real-time video processing main controller extends the high-level duration of the integration time control signal to the length corresponding to the new integration time value. This increases the charge accumulation time of each detector chip, raising the amplitude of the output analog electrical signal to the optimal quantization range of the analog-to-digital converter. Conversely, in high-light conditions, the amplitude of the analog electrical signal output by the detector chip is high. A smaller integration time value is input via remote control from the ground. The FPGA real-time video processing main controller shortens the high-level duration of the integration time control signal to the length corresponding to the new integration time value. This reduces the charge accumulation time of each detector chip, lowering the amplitude of the output analog electrical signal to the optimal quantization range of the analog-to-digital converter, thus avoiding signal saturation and adapting to the imaging dynamic range requirements under different lighting conditions and different detection targets.

[0093] The integral time control signal refers to the control pulse signal output by the FPGA real-time video processing main controller to each detector chip in the stitched infrared focal plane detector array. Its high-level duration determines the time for charge accumulation in the photodiodes within the detector chip. The low-level signal ends charge accumulation and initiates signal readout. The integral time refers to the duration of the high-level integral time control signal, equal to the time interval between the start and stop of infrared radiation reception by each detector chip in the stitched infrared focal plane detector array, measured in units of clock cycles. The charge accumulation duration refers to the duration for which the photodiodes in each detector chip in the stitched infrared focal plane detector array continuously convert incident infrared photons into photogenerated charge within the integral time. A longer charge accumulation duration results in a larger total charge and a higher amplitude of the output analog signal. The imaging dynamic range refers to the range of infrared radiation intensity changes that the video processing circuit can effectively respond to. The lower limit is determined by the system's total root mean square noise, and the upper limit is determined by the full-scale input voltage of the analog-to-digital converter. The imaging dynamic range determines the system's ability to distinguish between bright and dim targets. Illumination conditions refer to the total power density of incident infrared radiation in the operating environment of the video processing circuit. This is affected by factors such as the temperature of the observed target, the observation season, the observation time, and atmospheric transmission attenuation. The intensity of illumination conditions directly affects the amplitude level of the analog electrical signal output by the detector chip. The detected target refers to the specific ground or spatial target observed by the video processing circuit. Different targets have significantly different infrared radiation characteristics; high-temperature targets have strong radiation, while low-temperature targets have weak radiation, requiring different integration times for matching. The switching moment refers to the instantaneous point in time when the integration time control signal transitions from a high level to a low level or vice versa. The switching moment is determined by a logic flip triggered when the counter inside the FPGA real-time video processing main controller reaches a preset value. The fixed phase relationship means that the time difference between the switching moment of the integration time control signal and the switching moment of the horizontal synchronization signal in the drive control signal remains constant. This difference does not change with the value of the integration time and is measured in the number of clock cycles from the same source.

[0094] The multi-chip stitched infrared focal plane video processing circuit of this invention comprises four physical layers. Specifically, ① the first layer is a stitched infrared focal plane detector array, composed of multiple independent infrared detector chips stitched together according to spatial positions. Each detector chip receives infrared radiation and converts it into an analog electrical signal; ② the second layer is a multi-channel analog front-end signal conditioning module, which includes multiple independent analog signal conditioning channels corresponding to the number of detector chips. Each channel performs signal conditioning operations such as power supply ripple filtering, bias voltage superposition, and programmable gain amplification on the analog electrical signal output by the corresponding detector chip; ③ the third layer is a multi-channel analog-to-digital conversion synchronous acquisition module, which includes multiple analog-to-digital conversion channels corresponding to the number of detector chips. Each channel simultaneously performs sampling on the conditioned analog electrical signal under the synchronous control of the sampling timing. The sample holding and quantization encoding operations convert analog electrical signals into multi-channel parallel digital image data streams; the fourth layer is the core main control layer, which is the FPGA real-time video processing main controller. The input pins of the FPGA real-time video processing main controller receive all multi-channel parallel digital image data streams output by the multi-channel analog-to-digital conversion synchronous acquisition module. Inside the FPGA real-time video processing main controller, pipeline operations such as cross-chip timing synchronization calibration, ping-pong buffer alternating read and write, multi-channel partitioned radiometric non-uniformity correction, blind pixel replacement, and image packaging processing are completed sequentially; the data output module integrates three high-speed image output channels: fiber optic output interface, LVDS output interface, and CXP output interface. The image data processed by the FPGA real-time video processing main controller is transmitted outward through one of the three interfaces according to the currently selected output interface type.

[0095] In terms of physical connections, the analog signal output of each detector chip in the spliced ​​infrared focal plane detector array is connected one by one to the analog signal input of the corresponding channel in the multi-channel analog front-end signal conditioning module. The output of each channel of the multi-channel analog front-end signal conditioning module is connected one by one to the analog input of the corresponding analog-to-digital conversion channel in the multi-channel analog-to-digital conversion synchronous acquisition module. The digital output of each channel of the multi-channel analog-to-digital conversion synchronous acquisition module is connected to the input pin of the FPGA real-time video processing main controller through a parallel data bus. The output pin of the FPGA real-time video processing main controller is connected to the input of the data output module through a parallel data bus. The clock signal generated by the clock timing generation module is sent to the global clock input of the FPGA real-time video processing main controller. Based on this clock signal, the FPGA real-time video processing main controller generates drive control signals for each detector chip in the stitched infrared focal plane detector array and sampling timing signals for the multi-channel analog-to-digital converter synchronous acquisition module. The drive control signals are transmitted back to the control inputs of each detector chip in the stitched infrared focal plane detector array via a general-purpose input / output interface, and the sampling timing signals are sent to the synchronization control terminal of the multi-channel analog-to-digital converter synchronous acquisition module via a general-purpose input / output interface. The multi-channel independent power supply bias control module is bidirectionally connected to the FPGA real-time video processing main controller via a digital control bus. The FPGA real-time video processing main controller sends the digitally encoded bias voltage values ​​of each channel to the multi-channel independent power supply bias control module. The power bias control module contains a digital-to-analog converter and operational amplifier that convert the digital encoded value into an analog bias voltage, which is then supplied to each channel in the multi-channel analog front-end signal conditioning module. The on-orbit parameter storage module is bidirectionally connected to the FPGA real-time video processing main controller via a parallel data bus. The gain correction coefficient, offset correction coefficient, blind pixel coordinates, and timing compensation values ​​stored in the on-orbit parameter storage module are read in real time after the FPGA real-time video processing main controller is powered on and during operation, and loaded into the internal parameter register of the FPGA real-time video processing main controller. This is used for pixel-by-pixel calculations in the cross-chip timing synchronization calibration unit and the multi-channel partitioned radiation correction unit. At the same time, new parameters injected from the ground are sent to the FPGA real-time video processing main controller through the remote control interface and then written to the on-orbit parameter storage module via the parallel data bus to update the parameters.

[0096] A multi-channel programmable reference source chip can be used to directly output graded bias voltages. This chip integrates multiple independent digital-to-analog conversion channels and output buffers. Each channel can directly output a stable and adjustable DC voltage without the need for external operational amplifiers for impedance transformation and amplification. The FPGA real-time video processing main controller sends the digitally encoded bias voltage values ​​for each channel to the chip. Each channel within the chip independently converts the digitally encoded values ​​into corresponding analog voltages and outputs them directly to the bias voltage input pins of each detector chip in the spliced ​​infrared focal plane detector array. In addition to using a multi-stage π-type filter network structure, the multi-stage power supply filter network can be replaced with an LC composite filter network or a second-order RC active filter network. The LC composite filter network consists of series inductors and parallel capacitors connected in an L-type or T-type topology. After LC composite filtering, the AC ripple component of the power supply voltage is attenuated by the combined inductive and capacitive reactance. The second-order RC active filter network consists of an operational amplifier, resistors, and capacitors. Resistors connected in series in the power transmission path form the first-stage low-pass filter, while the operational amplifier, in conjunction with the feedback capacitor, forms the second-stage active low-pass filter. After passing through these two stages of filtering, the peak-to-peak ripple of the power supply voltage is further attenuated. Channel gain adjustment, except for the eight independent analog gain amplification levels within the multi-channel analog front-end signal conditioning module, can be entirely transferred to the FPGA real-time video processing main controller for pixel-level digital domain gain scaling. In the digital domain gain scaling scheme, the programmable gain amplifier on the analog end is eliminated. Multiple analog electrical signals, after being superimposed with bias voltages, are directly fed into the multi-channel analog-to-digital conversion synchronous acquisition module for analog-to-digital conversion without gain amplification. The converted multi-channel parallel digital image data streams then enter the FPGA real-time video processing main controller. The parallel multiplication unit in the multi-channel partitioned radiation correction unit multiplies the original grayscale value of each pixel by a digital gain coefficient. This digital gain coefficient can be independently configured for each channel with a step size as fine as 0.1 times. After scaling, the corrected grayscale value is obtained. This scheme simplifies analog circuit board wiring but increases the internal digital logic resource usage of the FPGA real-time video processing main controller to some extent. Besides using analog-to-digital partitioned isolation wiring structures, digital-to-analog isolation can also be further achieved using ferrite beads, isolation operational amplifiers, or differential analog transmission lines to isolate digital crosstalk. Ferrite beads are connected in series at the junction of the analog and digital power paths, utilizing their high-frequency loss characteristics to absorb high-frequency digital noise. An isolation operational amplifier is placed at the boundary between the analog and digital signal regions. The analog signal is transmitted to the digital region through the magnetic or capacitive isolation barrier inside the isolation operational amplifier, preventing high-frequency noise from the digital region from coupling back to the analog signal path. The differential analog transmission line uses two parallel wires of equal length to transmit the analog signal. Common-mode interference on the two wires is canceled in the differential amplifier at the receiving end, further reducing the impact of digital crosstalk on the analog signal and adapting to the digital-analog isolation requirements under different board size constraints.

[0097] Optionally, in addition to using an on-orbit parameter storage module, electrically erasable programmable read-only memory (EEPROM) or on-orbit erasable random access memory (ORAM) can be used to cache temporary correction coefficients for storing calibration parameters. EEPROM supports byte-level erase and write operations, and data is not lost after power failure, making it suitable for long-term storage of calibration parameters. On-orbit ORAM supports high-speed read and write operations, but data is lost after power failure. It is suitable for temporarily caching correction coefficients in short-period observation scenarios, eliminating the need for frequent writes to the on-orbit parameter storage module, reducing the number of erase / write cycles of the on-orbit parameter storage module, and extending its lifespan.

[0098] Optionally, a lightweight scheme using dual-mode redundancy design and checksum verification can be adopted to reduce logic resource overhead. This scheme replicates the same functional logic circuit into two identical independent logic circuits. Both circuits receive identical input signals and perform the same operations simultaneously. The output signals of both circuits are fed into comparators, which compare the two outputs bit by bit. Simultaneously, each logic circuit's output is accompanied by a checksum generated from its output. This checksum is calculated from the output data using a cyclic redundancy check (CRC) or parity check (PCM) algorithm. While comparing the two output data bit by bit, the comparator verifies the correctness of the checksum attached to each output data. When the two output data are identical bit by bit and both checksums are correct, the comparator outputs this data as the final result. When the two output data are different bit by bit or one of the checksums is incorrect, the comparator outputs the data with the correct checksum as the final result.

[0099] In addition to employing a dual-partition FLASH storage architecture, the on-orbit parameter storage module can be replaced with two independent FLASH chips for hardware hot backup. The two independent FLASH chips are connected in parallel to the same set of parallel data buses of the FPGA real-time video processing main controller. The address and data lines of both chips are connected in parallel to this data bus, and the control lines are connected to different chip select pins of the FPGA real-time video processing main controller. Upon power-up, the FPGA real-time video processing main controller reads the configuration bitstream and correction parameters from the first FLASH chip by default, while simultaneously setting the second FLASH chip to backup mode. When the FPGA real-time video processing main controller detects a data verification error or timeout when reading data from the first FLASH chip, it switches to reading data from the second FLASH chip via the chip select pin. When updating parameters on the ground, the FPGA real-time video processing main controller first erases all data on the second FLASH chip, writes the new parameters to the second FLASH chip, verifies the correctness of the written data after writing, and switches the currently active chip to the second FLASH chip after successful verification. Then, it erases the first FLASH chip and writes the same new parameters to the first FLASH chip, ensuring that the two FLASH chips always maintain completely consistent data content. In addition to being compatible with LVDS, CXP, and fiber optic output interfaces, the data output module can have one interface removed or replaced with a high-speed image bus interface such as CameraLink, depending on load requirements. When removing one interface, the corresponding packet format generation logic and output pin driver circuit inside the FPGA real-time video processing main controller can be removed accordingly, freeing up printed circuit board layout space and internal logic resources. When replacing with other high-speed image buses such as CameraLink, the FPGA real-time video processing main controller is replaced with packet format generation logic and physical layer encoding circuits corresponding to the other high-speed image bus such as CameraLink, and the physical connector of the data output module interface is correspondingly replaced with the connector corresponding to the other high-speed image bus such as CameraLink. The dual-layer stacked integrated hardware architecture can also be broken down into a single, ultra-large integrated printed circuit board (PCB), achieving the same level of integration through partitioned layout. This single PCB houses all circuit modules on the same board. The original signal processing and power control / telemetry circuits are independently arranged in different physical areas of the PCB according to an analog-to-digital partitioned isolation wiring structure. These areas are connected via internal traces, eliminating the need for inter-board connectors to transmit power and control signals. This approach eliminates contact resistance and signal reflection caused by inter-board connectors and reduces signal crosstalk, but sacrifices the weight and installation space advantages of the dual-layer stacked architecture.

[0100] The overall technical effects of this invention are as follows: 1) The video processing circuit provided by this invention provides a common clock to the FPGA real-time video processing main controller through a clock timing generation module. Based on this common clock, the drive control signals of each detector chip in the spliced ​​infrared focal plane detector array and the sampling timing of the multi-channel analog-to-digital conversion synchronous acquisition module are uniformly generated. This ensures that the phase of the integration signal, vertical drive signal, horizontal drive signal and the line synchronization signal of each chip are consistent from the source, eliminates the TDI integration phase misalignment caused by timing deviation, fully releases the signal-to-noise ratio gain of time delay integration, and supports the integration time to be continuously adjustable with one clock cycle of the common clock as the minimum step size, adapting to the dynamic range requirements of different lighting conditions and detection targets.

[0101] 2) The programmable bias generation circuit, composed of a digital-to-analog converter and an operational amplifier in the multi-channel analog front-end signal conditioning module, provides high-precision bias voltage to each detector chip. A multi-stage power supply filtering network suppresses power supply ripple, and an analog-to-digital partitioned isolation wiring structure isolates crosstalk between analog and digital signals. Multiple independent analog gain adjustment channels amplify the gains of multiple analog electrical signals independently before outputting them to the multi-channel analog-to-digital conversion synchronous acquisition module. After synchronous analog-to-digital conversion under sampling timing control, multiple parallel digital image data streams are obtained. From bias power supply, power supply filtering, digital-to-analog isolation to signal amplification, the entire link suppresses power supply ripple and digital crosstalk, keeping the total root mean square noise of the system at a low level. It supports independent eight-level gain adjustment for each channel to achieve fine matching of channel response and ensure high-sensitivity imaging capability.

[0102] 3) After receiving multiple parallel digital image data streams, the FPGA real-time video processing main controller uses a cross-chip timing synchronization calibration unit to align pixel timing, line timing, and frame timing, eliminating pixel delay and byte misalignment caused by analog-to-digital conversion of each channel. Then, the multi-channel partitioned radiometric correction unit reads the gain correction coefficient, offset correction coefficient, and blind pixel coordinates corresponding to each detector chip from the on-orbit parameter storage module. Each set of parallel multiplication units performs radiometric non-uniformity correction pixel by pixel. The blind pixel coordinate register is used to check whether the current pixel coordinates match the blind pixel coordinates. If they match, the grayscale values ​​of surrounding normal pixels are read to replace the current pixel grayscale value. After each channel is independently corrected, the output is completed, eliminating spatial geometric misalignment, response non-uniformity, and black and white spots in the image caused by blind pixels caused by multi-chip stitching. At the same time, in conjunction with the dual-partition FLASH storage architecture of the on-orbit parameter storage module, the correction coefficients and timing compensation values ​​can be remotely uploaded from the ground, stored in real time, and automatically switched when powered on or when a partition fault is detected. The working parameters can be updated without equipment shutdown and restart, and the imaging quality can be kept stable for a long time on-orbit.

[0103] 4) The FPGA configuration status is monitored in real time through the SEFI detection refresh circuit and the configuration refresh is triggered when a single event fault is detected. The timing alignment logic and partition radiation correction logic adopt a triple redundancy design. The majority voter casts a majority vote on each of the three sets of outputs to shield the logic error caused by single event faults. Combined with the dual-partition FLASH storage architecture, the FPGA program can be reconfigured on the track and the fault partition can be automatically switched. The dual-channel CAN remote control and telemetry interface differential transmission and dual-channel hot backup design improve the radiation hardening level and on-track autonomous recovery capability of the entire chain from configuration refresh, logic redundancy, program storage to communication interface.

[0104] 5) The signal processing board carries a multi-channel analog front-end signal conditioning module, a multi-channel analog-to-digital conversion synchronous acquisition module, an FPGA real-time video processing main controller, a clock timing generation module, and a data output module. The power remote control and telemetry board carries a power supply conversion circuit, a multi-channel independent power bias control module, an on-orbit parameter storage module, and a dual-channel CAN remote control and telemetry interface circuit. The two boards are stacked vertically through an inter-board connector to achieve power supply and vertical transmission of control signals. It integrates all external interface functions for detector driving, power management, remote control and telemetry, and image data transmission. It is compatible with three high-speed image outputs: LVDS output interface, CXP output interface, and fiber optic output interface. It can switch between three packaging formats according to the requirements of the back-end equipment to adapt to long-distance fiber optic transmission, LVDS local debugging and display, and CXP high-speed image storage respectively. It is configured with a main and backup dual-channel CAN remote control and telemetry interface and an LVDS hardware time synchronization interface. While meeting the full functionality, it compresses the circuit size and overall power consumption to meet the miniaturization and low power consumption application requirements of aerospace payloads.

[0105] like Figure 2 As shown, the present invention also provides a signal processing method for multi-chip stitched infrared focal plane arrays, employing any of the above-mentioned video processing circuits for multi-chip stitched infrared focal plane arrays, the method comprising: S1. The FPGA real-time video processing main controller generates the drive control signals of each detector chip in the spliced ​​infrared focal plane detector array and the sampling timing of the multi-channel analog-to-digital conversion synchronous acquisition module based on the same source clock provided by the clock timing generation module. S2. The FPGA real-time video processing main controller outputs the drive control signal to the spliced ​​infrared focal plane detector array, controls the spliced ​​infrared focal plane detector array to perform integration and readout operations, and causes the spliced ​​infrared focal plane detector array to output multiple analog electrical signals to the multi-channel analog front-end signal conditioning module. S3. The multi-channel analog front-end signal conditioning module conditions the received multi-channel analog electrical signals and sends the conditioned analog electrical signals to the multi-channel analog-to-digital conversion synchronous acquisition module. S4. The FPGA real-time video processing main controller outputs the sampling timing sequence to the multi-channel analog-to-digital conversion synchronous acquisition module. Under the control of the sampling timing sequence, the multi-channel analog-to-digital conversion synchronous acquisition module performs synchronous analog-to-digital conversion on the conditioned analog electrical signal to obtain multiple parallel digital image data streams and transmits them to the FPGA real-time video processing main controller. S5. Enable the FPGA real-time video processing main controller to receive multiple parallel digital image data streams and perform timing alignment on the multiple parallel digital image data streams to obtain the timing-aligned data streams. S6. Enable the FPGA real-time video processing main controller to perform partitioned radiometric non-uniformity correction and blind pixel replacement on the time-aligned data stream to obtain the corrected image data. S7. The FPGA real-time video processing main controller performs image packaging processing on the corrected image data and outputs the processed image through the data output module.

[0106] It should be noted that the beneficial effects of the signal processing method for multi-chip stitched infrared focal plane arrays provided in the above embodiments are the same as the beneficial effects of the video processing circuit for multi-chip stitched infrared focal plane arrays described above, and will not be repeated here. Furthermore, the method and circuit embodiments provided in the above embodiments belong to the same concept, and their specific implementation processes are detailed in the circuit embodiments, and will not be repeated here.

[0107] The above description is merely a preferred embodiment of the present invention and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of disclosure in this invention is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-disclosed concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this invention.

[0108] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A video processing circuit for multi-chip stitched infrared focal plane arrays, characterized in that, include: Multi-channel analog front-end signal conditioning module, multi-channel analog-to-digital conversion synchronous acquisition module, FPGA real-time video processing main controller, clock timing generation module and data output module; The FPGA real-time video processing main controller generates drive control signals for each detector chip in the stitched infrared focal plane detector array and sampling timing for the multi-channel analog-to-digital conversion synchronous acquisition module based on the same clock provided by the clock timing generation module. The FPGA real-time video processing main controller outputs the drive control signals to the stitched infrared focal plane detector array to control the stitched infrared focal plane detector array to perform integration and readout operations, so that the stitched infrared focal plane detector array outputs multiple analog electrical signals to the multi-channel analog front-end signal conditioning module. The multi-channel analog front-end signal conditioning module conditions the received multi-channel analog electrical signals and then sends them to the multi-channel analog-to-digital conversion synchronous acquisition module. The FPGA real-time video processing main controller outputs the sampling timing sequence to the multi-channel analog-to-digital conversion synchronous acquisition module. Under the control of the sampling timing sequence, the multi-channel analog-to-digital conversion synchronous acquisition module performs synchronous analog-to-digital conversion on the conditioned analog electrical signals to obtain multiple parallel digital image data streams and transmits them to the FPGA real-time video processing main controller. The FPGA real-time video processing main controller receives and performs timing alignment on the multi-channel parallel digital image data stream, and performs partitioned radiometric non-uniformity correction, blind pixel replacement, and image packing on the timing-aligned data stream, and outputs the processed image through the data output module.

2. The video processing circuit for multi-chip stitched infrared focal plane arrays according to claim 1, characterized in that, The FPGA real-time video processing main controller includes a cross-chip timing synchronization calibration unit. The cross-chip timing synchronization calibration unit includes multiple independent delay FIFOs, frame marker recognition counters, and phase compensation registers corresponding to the number of channels of the multi-channel analog-to-digital conversion synchronous acquisition module. Each parallel digital image data stream enters its corresponding independent delay FIFO. The frame marker recognition counter identifies the frame start marker in each digital image data stream and calculates the arrival time difference between each digital image data stream. Based on the arrival time difference, the delay amount of each independent delay FIFO is configured through the phase compensation register to compensate for the delay of the timing-advanced digital image data stream, so that the pixel timing, line timing, and frame timing of each digital image data stream are aligned, resulting in a timing-aligned data stream.

3. The video processing circuit for multi-chip stitched infrared focal plane arrays according to claim 2, characterized in that, The FPGA real-time video processing main controller includes a multi-channel partitioned radiometric correction unit. The multi-channel partitioned radiometric correction unit includes multiple sets of parallel multiplication operation units and a blind pixel coordinate register. The multi-channel partitioned radiometric correction unit reads the gain correction coefficient, offset correction coefficient, and blind pixel coordinates corresponding to each detector chip in the stitched infrared focal plane detector array. Each set of parallel multiplication operation units calculates the corrected grayscale value pixel by pixel for the input channel according to the gain correction coefficient and offset correction coefficient of its corresponding detector chip. The blind pixel coordinate register searches whether the current pixel coordinates match the blind pixel coordinates. If they match, the grayscale value of the current pixel is replaced by the grayscale value of the surrounding normal pixels. After completing the independent correction of each channel, the output is completed.

4. The video processing circuit for multi-chip stitched infrared focal plane arrays according to claim 1, characterized in that, The multi-channel analog front-end signal conditioning module includes a programmable bias generation circuit, a multi-stage power supply filter network, an analog-to-digital partitioned isolation wiring structure, and multiple independent analog gain adjustment channels. The multi-channel analog front-end signal conditioning module provides bias voltage to each detector chip in the spliced ​​infrared focal plane detector array through the programmable bias generation circuit, which is composed of a digital-to-analog converter and an operational amplifier. It suppresses power supply ripple through the multi-stage power supply filter network, isolates crosstalk between analog and digital signals through the analog-to-digital partitioned isolation wiring structure, and amplifies the multiple analog electrical signals independently through the multiple independent analog gain adjustment channels before outputting them to the multi-channel analog-to-digital converter synchronous acquisition module.

5. A video processing circuit for multi-chip stitched infrared focal plane arrays according to claim 3, characterized in that, The FPGA real-time video processing main controller also includes a ping-pong buffer RAM group, which is located after the cross-chip timing synchronization calibration unit. The ping-pong buffer RAM group includes two buffer areas of the same capacity and a read / write state machine. The read / write state machine controls the two buffer areas to alternately perform image frame writing and reading operations. When one frame of image in the timing-aligned data stream is written to one of the buffer areas, the other buffer area synchronously outputs the buffered image frame to the multi-channel partitioned radiometric correction unit.

6. A video processing circuit for multi-chip stitched infrared focal plane arrays according to claim 1, characterized in that, The data output module includes an LVDS output interface, a CXP output interface, and an optical fiber output interface. The image packaging process includes the FPGA real-time video processing main controller adding a frame header identifier and imaging parameter label to the header of the processed image data according to the currently selected output interface type, adding a check code to the tail, and outputting the packaged data stream to the interface of the data output module corresponding to the output interface type.

7. A video processing circuit for multi-chip stitched infrared focal plane arrays according to claim 3, characterized in that, It also includes an on-orbit parameter storage module, which adopts a dual-partition FLASH storage architecture. The dual-partition FLASH storage architecture includes a first partition and a second partition. The first partition is used to store the current working parameters, which include the gain correction coefficient, offset correction coefficient, blind pixel coordinates, and timing compensation values ​​corresponding to each detector chip in the stitched infrared focal plane detector array. The second partition is used to receive and store new parameters injected from the ground. The new parameters include updated gain correction coefficients, offset correction coefficients, blind pixel coordinates, and timing compensation values. The on-orbit parameter storage module automatically switches to the second partition when powered on or when a fault is detected in the first partition. The on-orbit parameter storage module provides the updated gain correction coefficients, offset correction coefficients, and blind pixel coordinates to the multi-channel partitioned radiation correction unit.

8. A video processing circuit for multi-chip stitched infrared focal plane arrays according to claim 1, characterized in that, The FPGA real-time video processing main controller also includes an SEFI detection and refresh circuit, which is used to detect the configuration status of the FPGA real-time video processing main controller in real time and perform a configuration refresh when a single event interruption is detected; the timing alignment logic and partition radiation correction logic in the FPGA real-time video processing main controller adopt a triple-modular redundancy design.

9. A video processing circuit for multi-chip stitched infrared focal plane arrays according to claim 1, characterized in that, The FPGA real-time video processing main controller generates an integration time control signal based on the same source clock. The integration time control signal continuously adjusts the integration time of each detector chip in the stitched infrared focal plane detector array with one clock cycle of the same source clock as the minimum step size. The FPGA real-time video processing main controller outputs the integration time control signal to the stitched infrared focal plane detector array to control the charge accumulation time of each detector chip, so that the video processing circuit can adapt to the corresponding imaging dynamic range under different lighting conditions and different detection targets. The integration time control signal and the drive control signal are uniformly generated by the FPGA real-time video processing main controller according to the same source clock. The horizontal synchronization signal in the drive control signal and the switching time of the integration time control signal maintain a fixed phase relationship.

10. A signal processing method for multi-chip stitched infrared focal plane arrays, characterized in that, The video processing circuit for multi-chip stitched infrared focal plane arrays according to any one of claims 1 to 9 includes the following method: The FPGA real-time video processing main controller generates the drive control signals for each detector chip in the spliced ​​infrared focal plane detector array and the sampling timing of the multi-channel analog-to-digital conversion synchronous acquisition module based on the same source clock provided by the clock timing generation module. The FPGA real-time video processing main controller outputs the drive control signal to the stitched infrared focal plane detector array, controls the stitched infrared focal plane detector array to perform integration and readout operations, and causes the stitched infrared focal plane detector array to output multiple analog electrical signals to the multi-channel analog front-end signal conditioning module. The multi-channel analog front-end signal conditioning module conditions the received multi-channel analog electrical signals and sends the conditioned analog electrical signals to the multi-channel analog-to-digital conversion synchronous acquisition module. The FPGA real-time video processing main controller outputs the sampling timing sequence to the multi-channel analog-to-digital conversion synchronous acquisition module. Under the control of the sampling timing sequence, the multi-channel analog-to-digital conversion synchronous acquisition module performs synchronous analog-to-digital conversion on the conditioned analog electrical signal to obtain multiple parallel digital image data streams and transmits them to the FPGA real-time video processing main controller. The FPGA real-time video processing main controller receives the multi-channel parallel digital image data stream and performs timing alignment on the multi-channel parallel digital image data stream to obtain a timing-aligned data stream. The FPGA real-time video processing main controller performs partitioned radiometric non-uniformity correction and blind pixel replacement on the time-aligned data stream to obtain corrected image data. The FPGA real-time video processing main controller performs image packaging processing on the corrected image data and outputs the processed image through the data output module.

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