Video instruction processing method, device and chip

Abstract

The application relates to the chip technical field and provides a video instruction processing method, device and chip.The method comprises the following steps: an interrupt signal sent by a video execution unit is acquired; if the interrupt signal is an abnormal interrupt signal, a gating mechanism is used to block an instruction cache unit from issuing an instruction to the video execution unit, so that the instruction cache unit is in an instruction blocking state; during the period when the instruction cache unit is in the instruction blocking state, the instructions stored in the instruction cache unit are reserved, and the video execution unit is separately reset to obtain a reset completion signal; according to the reset completion signal, the gating mechanism is released, so that the video execution unit continues to acquire the instructions from the instruction cache unit for processing. The application is coordinated by the abnormal gating and the separate reset, the bottom-layer cache instruction is reserved, the upstream channel is prevented from falling into a hanging deadlock and global restart, the overhead of the instruction reissuing is effectively saved, and the overall operation efficiency of a video system coding and decoding is improved.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a video instruction processing method, apparatus, and chip. Background Technology

[0002] In video encoding and decoding systems, the execution unit is usually equipped with an instruction buffer unit to reduce the transmission delay of task instructions.

[0003] In current video instruction processing methods, when a video execution unit malfunctions, a global reset is typically triggered. This operation causes the instructions stored in the instruction buffer to be discarded, and instructions must be reissued after the reset. Simultaneously, this process can also cause system hangs, forcing the video command processor distribute (vcpd) and related instruction channels to restart, thus reducing overall video encoding and decoding efficiency. Summary of the Invention

[0004] This invention provides a video instruction processing method, apparatus, and chip to address the deficiencies in the prior art.

[0005] This invention provides a video instruction processing method, comprising the following steps: Obtain the interrupt signal issued by the video execution unit; If the interrupt signal is an abnormal interrupt signal, the gating mechanism is used to block the instruction buffer unit from sending instructions to the video execution unit, so that the instruction buffer unit is in an instruction blocking state. During the period when the instruction buffer unit is in the instruction blocking state, the instructions stored in the instruction buffer unit are retained, and the video execution unit is reset separately to obtain a reset completion signal; Based on the reset completion signal, the gating mechanism is released so that the video execution unit can continue to retrieve and process the instructions from the instruction cache unit.

[0006] According to a video instruction processing method provided by the present invention, after acquiring the interrupt signal issued by the video execution unit, the method further includes: Obtain the interrupt identifier carried by the interrupt signal; The interrupt identifier is compared with the reference identifier configured in the preset register to obtain the identifier comparison result; Based on the identification comparison result, determine whether the interrupt signal is the abnormal interrupt signal.

[0007] According to a video instruction processing method provided by the present invention, the step of determining whether the interrupt signal is the abnormal interrupt signal based on the identifier comparison result includes: If the identification comparison result indicates that the interruption identification number matches the reference identification number, then the interruption signal is determined to be the abnormal interruption signal; If the identification comparison result indicates that the interruption identification number does not match the reference identification number, then the interruption signal is determined to be a normal signal, and the video execution unit is triggered to continue to retrieve instructions from the instruction cache unit for execution based on the normal signal.

[0008] According to a video instruction processing method provided by the present invention, after determining that the interrupt signal is a normal signal, the method further includes: The normal signal is fed back to the instruction channel that distributes instructions to the video execution unit; Based on the normal signal received by the instruction channel, the count value of the pending instructions associated with the task distribution unit is cleared.

[0009] According to a video instruction processing method provided by the present invention, the step of retaining the instructions stored in the instruction cache unit and performing separate reset processing on the video execution unit includes: Write a reset trigger command to the reset control terminal corresponding to the video execution unit to perform the individual reset process on the video execution unit; During the execution of the separate reset process, a working clock signal is continuously provided to the instruction cache unit based on a normally open clock source, so that the control loop of the instruction cache unit is independent of the reset loop of the video execution unit, so as to retain the instructions stored in the instruction cache unit.

[0010] According to a video instruction processing method provided by the present invention, during the period of individually resetting the video execution unit, the method includes: The global reset operation of the task distribution unit that sends instructions to the instruction cache unit is blocked in order to maintain the running state of the task distribution unit; The count of pending instructions associated with the task distribution unit is retained.

[0011] According to a video instruction processing method provided by the present invention, before acquiring the interrupt signal issued by the video execution unit, the method further includes: The task distribution unit extracts the target instruction from the instruction channel and performs format splitting on the target instruction to obtain a transmission data packet adapted to the system transmission protocol. The data packet is sent to the data receiving end corresponding to the video execution unit via the system bus, and the data packet is stored in the instruction cache unit.

[0012] According to a video instruction processing method provided by the present invention, obtaining the reset completion signal includes: Detect the status of the reset completion register configured within the video execution unit; If the state of the reset completion register changes to the reset end state, then the reset completion signal is generated based on the reset completion register.

[0013] The present invention also provides a video instruction processing device, comprising the following modules: The acquisition module is used to acquire interrupt signals sent by the video execution unit; The blocking module is used to block the instruction buffer unit from sending instructions to the video execution unit by using a gating mechanism if the interrupt signal is an abnormal interrupt signal, so that the instruction buffer unit is in an instruction blocking state. The reset processing module is used to retain the instructions stored in the instruction cache unit during the instruction blocking state, and to perform separate reset processing on the video execution unit to obtain a reset completion signal. The release recovery module is used to release the gating mechanism according to the reset completion signal, so that the video execution unit can continue to obtain the instructions from the instruction cache unit for processing.

[0014] The present invention also provides a chip, comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor; the processor, when executing the computer program, implements the steps of the video instruction processing method as described in any of the preceding claims.

[0015] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the video instruction processing method described above.

[0016] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the video instruction processing method as described above.

[0017] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the video instruction processing method as described above.

[0018] The video instruction processing method, apparatus, and chip provided by this invention utilize a gating mechanism to block the continuous issuance of instructions to the video execution unit during anomalies, thereby cutting off the path of fault propagation upstream and preventing the upstream task distribution channel from falling into a suspended deadlock state due to the lack of execution completion feedback. Furthermore, by retaining the instructions stored in the instruction cache unit during a separate reset and allowing the video execution unit to continue retrieving instructions from the cache after releasing the gating mechanism based on the reset completion signal, the system can directly resume service execution from the near-end cache after reset, effectively saving the transmission overhead of reissuing instructions and improving the overall encoding and decoding efficiency of the system. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0020] Figure 1 This is a flowchart illustrating the video instruction processing method provided by the present invention.

[0021] Figure 2 This is an interactive flowchart of the video instruction processing system provided by the present invention.

[0022] Figure 3 This is a schematic diagram of the video instruction processing device provided by the present invention.

[0023] Figure 4 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0025] In the training and inference of large models on general-purpose graphics processing units (GPGPUs), extensive data processing is often required. During this stage, the video codec module is primarily responsible for encoding and decoding the training data. The decoded raw data is used by the computation cores for training, and the output of the computation cores is encoded to reduce system bandwidth. A typical video processing architecture design mainly includes a video task distribution unit (VCPD) and a video task execution unit (VCU). During system operation, the VCPD in the main control chip is responsible for sending task instruction packets to each video core via the bus. After receiving a complete instruction packet, the video core begins executing the specific video encoding and decoding operations and returns an interrupt signal to the VCPD after completing the current task.

[0026] In current technical solutions, to reduce instruction transmission latency, a corresponding instruction buffer unit is typically set up inside the video core. When an abnormal situation occurs in the video core, it sends an abnormal interrupt signal to the VCPD. At this time, the VCPD often needs to perform a global reset of the entire system. This reset causes the pending instruction packets stored in the instruction buffer unit to be discarded. After the reset, the bus needs to be re-acquired to send these instruction packets. At the same time, since previously sent instructions that encountered abnormalities cannot complete their execution and return confirmation normally, the VCPD and instruction channels cannot receive complete return results, causing the outstanding instruction count inside the system to fail to be cleared properly, thus causing the system to enter a hang state. In this state, the system usually also needs to reset the VCPD and instruction channels themselves, and then restart the relevant distribution channels after the reset is completed. This frequent system-level restart operation and the subsequent re-sending of instructions significantly affect the actual video encoding and decoding processing efficiency.

[0027] To address this, the present invention provides a video instruction processing method. When an abnormal interruption is detected in a video execution unit, the method promptly blocks the continued transmission of upstream instructions to the abnormal unit. While ensuring that the instruction cache content is not lost, the method performs a separate reset and isolation only on the faulty video execution unit. This effectively preserves the existing task data in the instruction cache unit, avoids instruction channel deadlock and system-level global restart caused by the abnormality of the underlying unit spreading upstream, thereby shortening the abnormal recovery time and improving the throughput efficiency and operational stability of the overall video encoding and decoding task.

[0028] in, Figure 1This is a flowchart illustrating the video instruction processing method provided by the present invention, as shown below. Figure 1 As shown, the method includes steps 110, 120, 130 and 140.

[0029] Step 110: Obtain the interrupt signal sent by the video execution unit.

[0030] Here, the video execution unit can be understood as the core hardware computing module in a general-purpose graphics processing unit (GPU) responsible for performing specific video data encoding and decoding operations. In a multi-core chip architecture design, the task distribution unit typically distributes video task instruction packets to downstream video execution units via a bus. After parsing the received complete instruction packet, the video execution unit begins executing the corresponding video data encoding and decoding operations. Interrupt signals are used to characterize the current operating status of the video execution unit. For example, when a video execution unit successfully completes its assigned data processing task, or encounters an internal parsing error or other fault during operation, the underlying hardware generates a corresponding status signal, which is the interrupt signal.

[0031] Interrupt signals can be obtained by monitoring the underlying system bus connecting the task distribution unit and the video execution unit, or by configuring an interrupt detection module. This embodiment does not specifically limit this method.

[0032] Step 120: If the interrupt signal is an abnormal interrupt signal, the gating mechanism is used to block the instruction buffer unit from sending instructions to the video execution unit, so that the instruction buffer unit is in the instruction blocking state.

[0033] Specifically, abnormal interrupt signals refer to interrupt types that indicate a failure such as a system crash, data parsing error, or timeout in the video execution unit. The instruction buffer unit is configured on the video execution unit side and is mainly used to temporarily store instruction packets pre-sent by the task distribution unit via the bus, thereby reducing instruction transmission latency. Gating mechanisms are hardware- or logic-based data flow interception methods used to cut off data transmission links under specific triggering conditions.

[0034] Upon receiving an interrupt signal, it can be determined whether it is an abnormal interrupt signal through comparison and other methods. If the interrupt signal is determined to be abnormal, it indicates that the video execution unit is in an abnormal state and cannot process new encoding / decoding tasks normally. Based on this, in order to prevent subsequent instructions from entering the faulty node and causing the instruction data to become unresponsive, this embodiment activates a gating mechanism to intercept and lock the output of the instruction buffer unit, preventing it from continuing to send instruction packets to the faulty video execution unit. During the period when the gating mechanism is in effect, the instruction buffer unit enters an instruction blocking state, and the temporarily stored unexecuted instructions are safely isolated in the buffer.

[0035] Step 130: While the instruction buffer unit is in the instruction blocking state, retain the instructions stored in the instruction buffer unit and perform a separate reset process on the video execution unit to obtain a reset completion signal.

[0036] Furthermore, considering that a conventional system-level global reset would result in the clearing and discarding of all instruction packets stored in the instruction cache unit, requiring the task distribution unit to reissue a large number of instructions, and that such clearing would cause errors in the recording of pending instructions, potentially leading to a deadlock in the task distribution unit due to the inability to receive results, this embodiment implements a separate reset for the faulty video execution unit while the instruction cache unit is in an instruction blocking state. This separate reset can be understood as resetting and initializing only the internal hardware logic of the video execution unit that sent the abnormal interrupt signal, without resetting the entire system or other instruction channels.

[0037] As an optional embodiment, a separate reset control port can be used to perform individual reset processing on the video execution unit while maintaining the normal operation of the instruction cache unit, thereby preserving the unexecuted instructions stored in the instruction cache unit. As the individual reset process ends, the reset-related registers of the underlying hardware will undergo corresponding state flips, thereby generating a reset completion signal indicating that the video execution unit has returned to its normal initial state.

[0038] Step 140: Release the gating mechanism according to the reset completion signal so that the video execution unit can continue to retrieve instructions from the instruction buffer unit for processing.

[0039] Specifically, the generation of the reset completion signal signifies that the video execution unit has resolved the previous abnormal fault and is ready to receive instruction data again. Therefore, based on the detected reset completion signal, the interception lock previously applied to the output of the instruction buffer unit can be revoked, i.e., the gating mechanism is released. After the gating mechanism is released, since the instructions previously stored in the instruction buffer unit are well preserved, the restored video execution unit can directly read the next instruction to be processed from the near-end instruction buffer unit and continue video encoding and decoding operations. This effectively eliminates the high-latency transmission process of retrieving instructions from the remote main control chip, ensuring efficient connection of the video encoding and decoding pipeline.

[0040] The video instruction processing method provided in this embodiment utilizes a gating mechanism to block the continuous issuance of instructions to the video execution unit during anomalies, thereby cutting off the path of fault propagation upstream and preventing the upstream task distribution channel from falling into a suspended deadlock state due to not receiving execution completion feedback. Furthermore, by retaining the instructions stored in the instruction cache unit during a separate reset and allowing the video execution unit to continue retrieving instructions from the cache after releasing the gating mechanism based on the reset completion signal, the system can directly resume service execution from the near-end cache after reset, effectively saving the transmission overhead of re-issuing instructions and improving the overall encoding and decoding efficiency of the system.

[0041] Based on the above embodiments, after obtaining the interrupt signal issued by the video execution unit, the method further includes: Obtain the interrupt identifier carried by the interrupt signal; The interrupt identifier is compared with the reference identifier configured in the preset register to obtain the identifier comparison result; Based on the identification comparison results, determine whether the interrupt signal is an abnormal interrupt signal.

[0042] Here, the interrupt identifier can be understood as a set of numerical sequences or codes predefined at the hardware level for each specific operating state, used to uniquely identify the specific type and trigger source of the interrupt signal. As an optional embodiment, an interrupt detection unit set in the control link can listen to interrupt messages on the bus and parse the header field of the interrupt message to extract the interrupt identifier carried by the interrupt signal.

[0043] After extracting the interrupt identifier carried by the interrupt signal, the interrupt identifier is compared with the reference identifier configured in the preset register to obtain the identifier comparison result. Here, the preset register refers to the storage medium inside the hardware system specifically used to store interrupt configuration information. The reference identifier refers to the set of interrupt numbers representing various faults or abnormal states that are written into the preset register during the system initialization phase.

[0044] As an optional embodiment, when the video execution unit completes its task or an exception occurs and sends an interrupt signal to the interrupt detection unit, the interrupt detection unit reads the reference identifier configured in the preset register, and then uses the internal hardware comparator to logically compare the obtained interrupt identifier with the reference identifier, thereby generating an identifier comparison result to characterize whether the two match.

[0045] After obtaining the identifier comparison result, the hardware system needs to determine the subsequent gating path based on the specific comparison and matching status, and then determine whether the interrupt signal is an abnormal interrupt signal based on the identifier comparison result. As an optional embodiment, if the identifier comparison result indicates that the interrupt identifier number matches the reference identifier number in the preset register, it means that the interrupt event that has occurred belongs to the abnormal fault type predefined by the system, and the interrupt signal is determined to be an abnormal interrupt signal; if it does not match, it is determined that it is not an abnormal interrupt signal.

[0046] Based on any of the above embodiments, determining whether an interrupt signal is an abnormal interrupt signal according to the identifier comparison result includes: If the identification comparison result indicates that the interrupt identification number matches the reference identification number, then the interrupt signal is determined to be an abnormal interrupt signal; If the identification comparison result indicates that the interruption identification number does not match the reference identification number, the interruption signal is determined to be a normal signal, and the video execution unit is triggered to continue to retrieve instructions from the instruction buffer unit for execution based on the normal signal.

[0047] Specifically, matching can be understood as the data string of the obtained interrupt identifier number being logically equal to the reference identifier number configured in the preset register. As an optional embodiment, when the identifier comparison result is high, it indicates that the interrupt identifier number has matched the reference identifier number in the system's predefined fault list. At this time, the abnormal flag bit inside the interrupt detection module is set, thereby determining that the currently received interrupt signal is an abnormal interrupt signal.

[0048] If the identifier comparison result indicates that the interrupt identifier number does not match the reference identifier number, meaning the returned interrupt is not in the preset error list, then the previous data encoding / decoding task has been successfully completed. In this case, the interrupt signal is determined to be a normal signal, and the execution unit is directly guided to continue fetching new instructions. That is, the video execution unit is triggered to continue retrieving instructions from the instruction buffer unit for execution based on the normal signal. Here, the normal signal is used to indicate that the video execution unit has successfully completed the previous stage of encoding / decoding task without any runtime errors. As an optional embodiment, when the identifier comparison result indicates a mismatch, the interrupt detection unit will feed back the determined normal signal to the control terminal of the video execution unit. After receiving the normal signal, the video execution unit's internal program counter will automatically update, thereby triggering the video execution unit to continue retrieving the next pending instruction from the nearby instruction buffer unit along the internal data bus and put it into the execution of a new encoding / decoding task.

[0049] Based on any of the above embodiments, after determining that the interrupt signal is a normal signal, the method further includes: Normal signals are fed back to the instruction channel that distributes instructions to the video execution unit; Based on the normal signals received from the instruction channel, the count value of the pending instructions associated with the task distribution unit is cleared.

[0050] Specifically, the instruction channel can be understood as a hardware trace or logic channel in a multi-channel chip architecture responsible for transmitting control instructions and feedback signals between the main control chip and the underlying execution module. As an optional embodiment, a dedicated interrupt feedback bus connecting the output of the video execution unit and the upstream task distribution unit can be used to route and send the normal signal, determined to be in a normal state, along the reverse path of data transmission to the corresponding instruction channel that was previously responsible for issuing the task instruction.

[0051] After feeding back normal signals to the corresponding command channel, considering that the upstream task distribution unit records tasks when initially issuing commands, if the corresponding pending records are not cleared in a timely manner after a task is completed, the number of incomplete tasks recorded internally by the system will continue to accumulate. When this number reaches the system limit, the task distribution unit will mistakenly believe that the underlying channel is severely congested, thus stopping the issuance of any new tasks, leading to a decline in system performance. Based on this, this embodiment clears the pending command count value associated with the task distribution unit based on the normal signals received by the command channel, in order to release the channel's recording capacity and ensure that subsequent video task commands can be continuously distributed downwards. The pending command count value refers to the number of command packets that have been issued through the bus but have not yet received completion feedback from the underlying layer, which the task distribution unit uses to dynamically record.

[0052] As an optional embodiment, when the instruction channel successfully receives a normal signal, the hardware logic circuit generates a trigger pulse and transmits it to the counter register inside the task distribution unit. After capturing a valid pulse, the counter register performs a checksum or clearing process on the count value of the instruction to be processed associated with it, so that the task distribution unit knows that the instruction packet of the current cycle has been executed by the video execution unit, thereby maintaining the smooth operation of the instruction channel.

[0053] Based on any of the above embodiments, the instructions stored in the instruction cache unit are retained, and the video execution unit is reset separately, including: Write a reset trigger command to the reset control terminal corresponding to the video execution unit to perform a separate reset process on the video execution unit; During the separate reset process, a working clock signal is continuously provided to the instruction buffer unit based on a normally open clock source, so that the control loop of the instruction buffer unit is independent of the reset loop of the video execution unit, in order to retain the instructions stored in the instruction buffer unit.

[0054] Specifically, the reset control terminal can be understood as a hardware register interface configured inside the video execution unit for receiving reset control signals from the external system. As an optional embodiment, when the upstream task distribution unit receives an abnormal interrupt signal from the downstream, it performs a write operation to the reset register inside the reset control terminal of the abnormal video execution unit via the chip's internal system bus, writing a specific reset trigger instruction. Upon detecting this reset trigger instruction, the underlying reset control logic of the video execution unit initiates a separate reset process for its own encoding / decoding core circuitry.

[0055] After initiating a separate reset process for the video execution unit, considering that the video execution unit and the instruction cache unit are closely connected on the physical hardware traces, if they share the same clock tree network during the reset, the clock pauses or logic fluctuations caused by the reset action can easily affect the cache circuit, leading to the accidental erasure of temporarily stored instructions. Therefore, in this embodiment, during the separate reset process, a normally open clock source continuously provides a working clock signal to the instruction cache unit, making the control loop of the instruction cache unit independent of the reset loop of the video execution unit, thus preserving the instructions stored in the instruction cache unit.

[0056] As an optional embodiment, a reset-controllable sub-clock domain is allocated to the video execution unit, while the clock input of the instruction buffer unit is directly connected to a normally open clock source. During a separate reset process, the video execution unit within this sub-clock domain is reset to zero, but since the normally open clock source is unaffected by the reset operation, it continuously provides the operating clock signal to the instruction buffer unit, thereby eliminating abnormal states while retaining the instructions stored in the instruction buffer unit.

[0057] Based on any of the above embodiments, during the individual reset process of the video execution unit, the following is included: The global reset operation of the task distribution unit that issues instructions to the instruction cache unit is disabled in order to maintain the running state of the task distribution unit; The count of pending instructions associated with the task dispatch unit is retained.

[0058] Specifically, the task distribution unit refers to the module in a multi-core chip architecture responsible for coordinating instruction scheduling and distributing service instruction packets to corresponding downstream units. A global reset operation refers to restoring the states of multiple layers of modules in the system to their initial values. As an optional implementation, an isolation gate can be set in the reset control logic of the video architecture to cut off or block the propagation link of the reset signal upstream of the communication bus when a separate reset signal is triggered on the underlying video execution unit, thus blocking the global reset operation of the task distribution unit that issues instructions to the instruction cache unit.

[0059] After successfully maintaining the operational state of the task distribution unit, if the relevant count records are not effectively retained during a partial reset, the task distribution unit may misjudge a channel deadlock due to the lack of feedback, leading to a halt in the entire system's processing. Therefore, this embodiment retains the pending instruction count value associated with the task distribution unit to ensure that the task verification data can correspond one-to-one after the underlying execution unit resets and recovers, thereby preventing the channel from becoming suspended. Here, the pending instruction count value refers to the account indicator used to record the number of instruction packets that have entered the instruction channel but have not yet received a downstream completion confirmation signal.

[0060] Based on any of the above embodiments, before obtaining the interrupt signal issued by the video execution unit, the method further includes: The task distribution unit extracts the target instruction from the instruction channel and performs format splitting on the target instruction to obtain a transmission data packet adapted to the system transmission protocol. The data packets are sent to the data receiving end corresponding to the video execution unit via the system bus, and the data packets are stored in the instruction buffer unit.

[0061] Specifically, a target instruction refers to the raw control command issued by the upstream application, instructing the underlying hardware to perform specific video encoding and decoding actions. A transmission data packet refers to a data sequence that has been segmented or reassembled and conforms to physical communication specifications.

[0062] As an optional implementation, the task distribution unit on the main control chip monitors multiple instruction channels in the system, selects one instruction channel using a corresponding selection strategy, and extracts the target instruction to be processed from it. Subsequently, the instruction parsing and conversion logic inside the task distribution unit processes the target instruction, truncating it and adding a communication header, that is, splitting the target instruction into its format, and finally generating a transmission data packet adapted to the system's underlying bus communication specification.

[0063] After obtaining the transmission data packets adapted to the system transmission protocol, considering that allowing these data packets to be transmitted in real-time only during the execution phase could easily lead to instruction fetching delays due to bus occupancy or long-distance transmission, resulting in idle waiting in the underlying encoding / decoding pipeline, this embodiment pre-loads task instructions and avoids memory access delay gaps. To achieve this, the transmission data packets are sent to the data receiving end corresponding to the video execution unit via the system bus, and the transmission data packets are stored in the instruction buffer unit. Here, the data receiving end refers to the bus interface node configured around the video execution unit, specifically responsible for listening to and receiving address data on the system bus.

[0064] As an optional embodiment, the task distribution unit initiates a bus transmission transaction to send the aforementioned generated transmission data packet along the main system bus to the data receiving end corresponding to the video execution unit. After successfully acquiring the transmission data packet, the data receiving end does not immediately push it into the encoding / decoding operation core, but instead writes the transmission data packet into the instruction cache unit configured inside the video execution unit for secure temporary storage.

[0065] Based on any of the above embodiments, a reset completion signal is obtained, including: Detect the status of the reset completion register configured within the video execution unit; If the state of the reset completion register changes to the reset end state, a reset completion signal is generated based on the reset completion register.

[0066] Specifically, the reset completion register refers to a state storage medium added to the video execution unit during the hardware architecture design phase. Its function is to map in real time whether the underlying encoding and decoding core circuit has finished resetting and returned to a usable state.

[0067] During the continuous monitoring of the reset completion register's state, if the reset completion register's state changes to the reset end state, a reset completion signal is generated based on the reset completion register. Here, the reset completion signal refers to the valid level pulse instruction triggered by the aforementioned state transition event.

[0068] As an optional embodiment, after the zeroing and initialization timing of the video execution unit's underlying layer is completed, the underlying hardware will set and toggle the value bits in the reset completion register. When the detection logic detects that the state of the reset completion register has changed to the reset end state, its internal edge capture circuit will output a high-level pulse based on this change in the reset completion register, i.e., generate a reset completion signal, and transmit the reset completion signal to the gating unit to notify it to perform a release operation.

[0069] Figure 2 This is an interactive flowchart of the video instruction processing system provided by the present invention, such as... Figure 2 As shown, firstly, the task distribution unit selects one of the multiple instruction channels to extract the target instruction, splits it, adapts it to the system transmission protocol, and then sends it to the underlying video execution unit (video core) via the system bus. After receiving the instruction, the video core writes it into the instruction buffer unit for storage. During this process, the system continuously provides an independent operating clock signal to the instruction buffer unit based on an always-on clock source.

[0070] Then, the video core codec unit reads the instructions stored in the instruction buffer unit and performs the corresponding data processing and video encoding / decoding tasks according to the instruction information. After completing the task or encountering an execution exception, the video core codec unit sends an interrupt signal to the underlying hardware interrupt detection logic.

[0071] Next, the interrupt detection logic compares the acquired interrupt identifier with the reference identifier configured in the register to determine whether it is an abnormal interrupt signal. If the interrupt signal is determined to be an abnormal interrupt signal, a gating mechanism is used to block the output of the instruction buffer unit, preventing the issuance of instructions and putting the instruction buffer unit in an instruction blocking state.

[0072] Subsequently, the abnormal interrupt signal was reported to the exception handling module within the upstream task distribution unit. Upon detecting the exception, this module did not reset the entire system. Instead, it wrote an instruction to the reset control terminal corresponding to the video core codec unit, triggering a sub-clock reset and performing a separate reset only on the video core codec unit. During this separate reset process, because the always-on clock and the sub-clock reset control loop are decoupled, the instruction buffer unit is not reset, thus reliably retaining the instructions stored within it. Simultaneously, the gating mechanism blocks instruction issuance, preventing the problem of instructions being swallowed during the reset and failing to return a completion signal. This allows the task distribution unit (main die VCPD) and the upstream instruction channel to maintain the current pending instruction count without entering a suspended state.

[0073] Finally, after the video core codec unit completes the aforementioned individual reset process and generates a reset completion signal, it clears and releases the gating mechanism. At this point, the video core codec unit can continue to retrieve previously stored instructions from the instruction buffer unit for processing. If the aforementioned interrupt detection logic determines that the interrupt is a normal signal, the normal signal will be normally sent back to the exception handling module along the feedback link, and further returned to the corresponding instruction channel to clear the count value of the pending instructions associated with the task distribution unit.

[0074] The video instruction processing apparatus provided by the present invention is described below. The video instruction processing apparatus described below and the video instruction processing method described above can be referred to in correspondence.

[0075] Based on any of the above embodiments Figure 3 This is a schematic diagram of the video instruction processing device provided by the present invention, as shown below. Figure 3 As shown, the device includes: The acquisition module 310 is used to acquire the interrupt signal sent by the video execution unit; The blocking module 320 is used to block the instruction buffer unit from sending instructions to the video execution unit by using a gating mechanism if the interrupt signal is an abnormal interrupt signal, so that the instruction buffer unit is in an instruction blocking state. The reset processing module 330 is used to retain the instructions stored in the instruction buffer unit and perform separate reset processing on the video execution unit during the period when the instruction buffer unit is in the instruction blocking state, so as to obtain a reset completion signal; The release recovery module 340 is used to release the gating mechanism according to the reset completion signal, so that the video execution unit can continue to obtain instructions from the instruction buffer unit for processing.

[0076] Based on any of the above embodiments, the present invention also provides a chip, comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor; when the processor executes the computer program, it implements the steps of the video instruction processing method as described in any of the above embodiments.

[0077] Here, "chip" refers to a highly integrated microelectronic device, such as a main control integrated circuit containing the video system design. "Memory" refers to a storage medium used to store business logic code, configuration parameters, and intermediate operating states. "Processor" refers to a computing unit capable of performing logical operations and system control scheduling. "Computer program" refers to a pre-written or firmware-defined set of instructions used to guide the processor to control the underlying video link according to a specific timing sequence. As an optional embodiment, in the architecture design of a general-purpose graphics processor, the chip integrates a main control processor core and a high-speed memory array, and the computer program is loaded into this memory, ready to be read and called by the processor at any time.

[0078] After configuring the aforementioned memory, processor, and computer program, the processor executes the computer program to implement the steps of the video instruction processing method described in any of the above embodiments. This drives the internal sub-modules of the driver chip to flow according to a predetermined timing and logic, thereby automatically implementing a series of abnormal response processes such as acquiring interrupt signals, activating gating mechanisms to block instruction issuance, maintaining instruction cache, and implementing individual reset processing. This avoids deadlock of the upstream channel and global restart, thereby improving the overall video encoding and decoding efficiency.

[0079] Figure 4 This is a schematic diagram of the structure of the electronic device provided by the present invention, such as... Figure 4As shown, the electronic device may include a processor 410, a communications interface 420, a memory 430, and a communication bus 440. The processor 410, communications interface 420, and memory 430 communicate with each other via the communication bus 440. The processor 410 can call logical instructions stored in the memory 430 to execute video instruction processing methods.

[0080] Furthermore, the logical instructions in the aforementioned memory 430 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0081] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer is able to execute the video instruction processing methods provided by the above methods.

[0082] In another aspect, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to perform the video instruction processing methods provided by the methods described above.

[0083] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0084] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0085] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A video instruction processing method, characterized in that, include: Obtain the interrupt signal issued by the video execution unit; If the interrupt signal is an abnormal interrupt signal, the gating mechanism is used to block the instruction buffer unit from sending instructions to the video execution unit, so that the instruction buffer unit is in an instruction blocking state. During the period when the instruction buffer unit is in the instruction blocking state, the instructions stored in the instruction buffer unit are retained, and the video execution unit is reset separately to obtain a reset completion signal; Based on the reset completion signal, the gating mechanism is released so that the video execution unit can continue to retrieve and process the instructions from the instruction cache unit.

2. The video instruction processing method according to claim 1, characterized in that, After receiving the interrupt signal from the video execution unit, the process also includes: Obtain the interrupt identifier carried by the interrupt signal; The interrupt identifier is compared with the reference identifier configured in the preset register to obtain the identifier comparison result; Based on the identification comparison result, determine whether the interrupt signal is the abnormal interrupt signal.

3. The video instruction processing method according to claim 2, characterized in that, The step of determining whether the interrupt signal is the abnormal interrupt signal based on the identifier comparison result includes: If the identification comparison result indicates that the interruption identification number matches the reference identification number, then the interruption signal is determined to be the abnormal interruption signal; If the identification comparison result indicates that the interruption identification number does not match the reference identification number, then the interruption signal is determined to be a normal signal, and the video execution unit is triggered to continue to retrieve instructions from the instruction cache unit for execution based on the normal signal.

4. The video instruction processing method according to claim 3, characterized in that, After determining that the interrupt signal is a normal signal, the process also includes: The normal signal is fed back to the instruction channel that distributes instructions to the video execution unit; Based on the normal signal received by the instruction channel, the count value of the pending instructions associated with the task distribution unit is cleared.

5. The video instruction processing method according to any one of claims 1 to 4, characterized in that, The step of retaining the instructions stored in the instruction cache unit and performing a separate reset on the video execution unit includes: Write a reset trigger command to the reset control terminal corresponding to the video execution unit to perform the individual reset process on the video execution unit; During the execution of the separate reset process, a working clock signal is continuously provided to the instruction cache unit based on a normally open clock source, so that the control loop of the instruction cache unit is independent of the reset loop of the video execution unit, so as to retain the instructions stored in the instruction cache unit.

6. The video instruction processing method according to any one of claims 1 to 4, characterized in that, During the individual reset process of the video execution unit, the following is included: The global reset operation of the task distribution unit that sends instructions to the instruction cache unit is blocked in order to maintain the running state of the task distribution unit; The count of pending instructions associated with the task distribution unit is retained.

7. The video instruction processing method according to any one of claims 1 to 4, characterized in that, Before receiving the interrupt signal from the video execution unit, the process also includes: The task distribution unit extracts the target instruction from the instruction channel and performs format splitting on the target instruction to obtain a transmission data packet adapted to the system transmission protocol. The data packet is sent to the data receiving end corresponding to the video execution unit via the system bus, and the data packet is stored in the instruction cache unit.

8. The video instruction processing method according to any one of claims 1 to 4, characterized in that, The reset completion signal obtained includes: Detect the status of the reset completion register configured within the video execution unit; If the state of the reset completion register changes to the reset end state, then the reset completion signal is generated based on the reset completion register.

9. A video instruction processing device, characterized in that, include: The acquisition module is used to acquire interrupt signals sent by the video execution unit; The blocking module is used to block the instruction buffer unit from sending instructions to the video execution unit by using a gating mechanism if the interrupt signal is an abnormal interrupt signal, so that the instruction buffer unit is in an instruction blocking state. The reset processing module is used to retain the instructions stored in the instruction cache unit during the instruction blocking state, and to perform separate reset processing on the video execution unit to obtain a reset completion signal. The release recovery module is used to release the gating mechanism according to the reset completion signal, so that the video execution unit can continue to obtain the instructions from the instruction cache unit for processing.

10. A chip, characterized in that, include: Memory, processor, and computer program stored in the memory and executable on the processor; When the processor executes the computer program, it implements the steps of the video instruction processing method as described in any one of claims 1 to 8.

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