Image sensing device

Abstract

Image sensing devices are disclosed. In an embodiment, an image sensing device includes a semiconductor substrate, and a pixel array including a plurality of pixels, each of the plurality of pixels including a photoelectric conversion region. Each of the plurality of pixels further includes a first tap region and a second tap region disposed in the semiconductor substrate, each of the first tap region and the second tap region configured to capture photocharges generated by the photoelectric conversion region, a first floating diffusion region disposed in the semiconductor substrate and having a first capacitance to accumulate the photocharges captured by the first tap region, a second floating diffusion region disposed in the semiconductor substrate and having a second capacitance to accumulate the photocharges captured by the second tap region, and a capacitor electrically connected in parallel with the second floating diffusion region and configured to modify an effective capacitance of the second floating diffusion region having the second capacitance.

Description

Technical Field

[0001] The technology and implementation disclosed in this patent document generally relate to an image sensing device, and more specifically, to an image sensing device including a capacitor connected to a floating diffusion region. Background Technology

[0002] Image sensing devices capture optical images by utilizing the properties of photosensitive semiconductor materials that react to light. With advancements in the automotive, medical, computer, and communications industries, the demand for high-performance image sensing devices is growing across various sectors, including smartphones, digital cameras, gaming consoles, the Internet of Things (IoT), robotics, surveillance cameras, and miniature medical cameras.

[0003] Image sensing devices are generally classified into charge-coupled device (CCD) image sensing devices and complementary metal-oxide-semiconductor (CMOS) image sensing devices. CCD image sensing devices offer better image quality than CMOS image sensing devices. However, CCD image sensing devices are larger and consume more power than CMOS image sensing devices. Furthermore, because CMOS image sensing devices are manufactured using CMOS technology, both the light-sensing element and the signal processing circuitry can be integrated into a single chip. This integration allows for the production of compact, low-cost image sensing devices. For these reasons, CMOS image sensing devices are being used in a wide range of applications, including mobile devices. Summary of the Invention

[0004] The disclosed techniques can be implemented in some embodiments to solve the aforementioned problems of the prior art while retaining its advantages.

[0005] One aspect of the disclosed technology provides an image sensing device designed to set a wider dynamic range of electrical signals generated by a unit pixel.

[0006] One aspect of the disclosed technology provides an image sensing device designed to capture fast-moving objects or produce high-quality video while maintaining a wide dynamic range.

[0007] In one aspect of the disclosed technology, an image sensing device may include: a semiconductor substrate; and a pixel array, the pixel array being at least partially disposed in the semiconductor substrate and including a plurality of pixels, each of the plurality of pixels including a photoelectric conversion region configured to generate an electrical signal in response to incident light. Each of the plurality of pixels may further include: a first tap region and a second tap region disposed in the semiconductor substrate, each of the first tap region and the second tap region being configured to capture photocharge generated in response to the incident light; a first floating diffusion region disposed in the semiconductor substrate and connected to the first tap region, the first floating diffusion region having a first capacitance and being configured to accumulate photocharge captured by the first tap region; a second floating diffusion region disposed in the semiconductor substrate and connected to the second tap region, the second floating diffusion region having a second capacitance and being configured to accumulate photocharge captured by the second tap region; and a capacitor electrically connected in parallel with the second floating diffusion region and configured to modify the effective capacitance of the second floating diffusion region having the second capacitance. In one embodiment, the capacitor is spaced apart from the first surface of the semiconductor substrate, connected to the second floating diffusion region, and at least partially overlaps with the first tap region or the second tap region, or overlaps with both the first tap region and the second tap region.

[0008] In embodiments of the disclosed technology, the image sensing device may further include: a first well region surrounding the first floating diffusion region and having a first depth from a first surface of the semiconductor substrate; and a second well region surrounding the second floating diffusion region and having a second depth from the first surface of the semiconductor substrate.

[0009] In the implementation of the disclosed technology, the first depth may be greater than the second depth.

[0010] In an embodiment of the disclosed technology, the first tap region may include a first control node having a third depth from the first surface of the semiconductor substrate, and the second tap region may include a second control node having a fourth depth from the first surface of the semiconductor substrate.

[0011] In embodiments of the disclosed technology, the third depth may be greater than the fourth depth.

[0012] In embodiments of the disclosed technology, the first tap region may further include a first detection node having a fifth depth from the first surface of the semiconductor substrate and configured to capture the photocharge, and the second tap region may further include a second detection node having a sixth depth from the first surface of the semiconductor substrate and configured to capture the photocharge.

[0013] In embodiments of the disclosed technology, the fifth depth may be less than the sixth depth.

[0014] In the embodiments of the disclosed technology, each of the first floating diffusion region, the second floating diffusion region, the first detection node, and the second detection node may include impurities of a first conductivity type, and each of the first well region, the second well region, the first control node, and the second control node may include impurities of a second conductivity type.

[0015] In an embodiment of the disclosed technology, the first tap region can operate in a first mode where the illuminance of the incident light is less than a first threshold, and the second tap region can operate in a second mode where the illuminance of the incident light is greater than a second threshold, the second threshold being greater than or equal to the first threshold.

[0016] In the disclosed embodiments, an electrical signal corresponding to the photocharge accumulated in the first floating diffusion region can be generated in response to the operation of the first tap region, and an electrical signal corresponding to the photocharge accumulated in the second floating diffusion region can be generated in response to the operation of the second tap region.

[0017] In an embodiment of the disclosed technology, both the first tap region and the second tap region can operate in a third mode between the first threshold and the second threshold, depending on the illuminance of the incident light.

[0018] In the implementation of the disclosed technology, the first tap region and the second tap region can operate alternately in the third mode.

[0019] In embodiments of the disclosed technology, the pixel array can operate in global shutter mode.

[0020] In an embodiment of the disclosed technology, an image sensing device may include: a substrate including a photoelectric conversion region that generates photocharge in response to incident light, a first tap region and a second tap region configured to capture the photocharge; and a capacitor spaced apart from a first surface of the substrate and perpendicularly overlapping each of the first tap region and the second tap region.

[0021] In the disclosed embodiments, the substrate may further include: a first floating diffusion region electrically connected to the first tap region via a first transmission transistor; a first well region surrounding the first floating diffusion region and having a first depth from a first surface of the substrate; a second floating diffusion region electrically connected to the second tap region via a second transmission transistor; and a second well region surrounding the second floating diffusion region and having a second depth from the first surface of the substrate, wherein the capacitor and the second floating diffusion region may be connected in parallel.

[0022] In the implementation of the disclosed technology, the first depth may be greater than the second depth.

[0023] In an embodiment of the disclosed technology, the first tap region may include a first control node having a third depth from the first surface of the substrate, and the second tap region may include a second control node having a fourth depth from the first surface of the substrate.

[0024] In embodiments of the disclosed technology, the third depth may be greater than the fourth depth.

[0025] In the embodiments of the disclosed technology, the first tap region may further include a first detection node having a fifth depth from the first surface of the substrate, and the second tap region may further include a second detection node having a sixth depth from the first surface of the substrate.

[0026] In embodiments of the disclosed technology, the fifth depth may be less than the sixth depth. Attached Figure Description

[0027] Figure 1 This is a block diagram illustrating an example of an image sensing device based on an implementation of the disclosed technology.

[0028] Figure 2 It is shown Figure 1 A circuit diagram of an example circuit model of a unit pixel included in a pixel array.

[0029] Figure 3 It is shown Figure 1 A cross-sectional view of an example of a unit pixel included in a pixel array.

[0030] Figure 4 It is shown Figure 2 The circuit diagram shows an example of the potential distribution in the first floating diffusion region and the second floating diffusion region.

[0031] Figure 5A It shows when Figure 2The circuit diagram is a graph showing an example of the signal levels of the first and second control signals when operating in the first mode.

[0032] Figure 5B It is shown in Figure 5A A graph illustrating the potential distribution of the first and second floating diffusion regions during the operating interval.

[0033] Figure 6A It shows when Figure 2 The circuit diagram is a graph showing an example of the signal levels of the first and second control signals when operating in the second mode.

[0034] Figure 6B It is shown in Figure 6A A graph illustrating the potential distribution of the first and second floating diffusion regions during the operating interval.

[0035] Figure 7A It shows when Figure 2 The circuit diagram is a graph showing the signal levels of the first and second control signals when operating in the third mode.

[0036] Figure 7B It is shown in Figure 7A A graph illustrating the potential distribution of the first floating diffusion region and the second floating diffusion region during the first operating interval.

[0037] Figure 7C It is shown in Figure 7A A graph illustrating the potential distribution of the first and second floating diffusion regions in the second operating interval.

[0038] Figure 8 It is shown Figure 1 A plan view of an example of pixel groups included in a pixel array.

[0039] Figure 9 It shows along Figure 8 The first example configuration of the cross-section diagram is shown by the line A-A'.

[0040] Figure 10 It shows along Figure 8 The second example configuration of the cross-section diagram is shown by the cross-section cut by line A-A'.

[0041] Figure 11 It shows along Figure 8 The cross-sectional view of the third example configuration of the cross section cut by line A-A'.

[0042] Figure 12 It shows along Figure 8 The fourth example configuration of the cross-section diagram is shown by the cross-section cut by line A-A'. Detailed Implementation

[0043] In the following, some embodiments of the disclosed technology will be described in detail with reference to the accompanying drawings. When assigning reference numerals / symbols to components in each drawing, the same components are represented by the same reference numerals / symbols even if shown in different drawings. Furthermore, in describing embodiments of the disclosed technology, detailed descriptions of known components or functions will be omitted if it is determined that such detailed descriptions would hinder the understanding of the embodiments of the disclosed technology.

[0044] Figure 1 This is a block diagram illustrating an example of an image sensing device 1 based on an embodiment of the disclosed technology.

[0045] Reference Figure 1 The image sensing device 1 may include a control block 10 and a pixel array 20.

[0046] The control block 10 may be a block that controls all operations of the image sensing device 1, including operations that control the operation of the pixel array 20. The control block 10 may include a timing control circuit (T / C) 11, a drive control circuit 12, and a readout circuit 13.

[0047] The timing control circuit 11 can provide a given timing signal and a given control signal to at least one or more of the drive control circuit 12 and the readout circuit 13.

[0048] The drive control circuit 12 can activate the pixel array 20 based on timing signals and control signals provided from the timing control circuit 11, so that specific operations are performed on the pixels PX included in the corresponding rows.

[0049] In one implementation, the drive control circuit 12 can select at least one pixel PX arranged in at least one row of the pixel array 20, and can provide the selected pixel PX with a signal that enables the selected pixel PX to perform a specific operation. The drive control circuit 12 can generate a row selection signal to select at least one row among a plurality of rows. When a specific row is selected to perform a specific operation, the drive control circuit 12 can prevent rows adjacent to the selected specific row from performing the operation.

[0050] The pixel PX of the row selected by the drive control circuit 12 can sequentially transmit both an analog reference signal and an image signal to the readout circuit 13. The reference signal can be an electrical signal provided to the readout circuit 13 when the floating diffusion region of the pixel PX is reset using the power supply voltage, and the image signal can be an electrical signal provided to the readout circuit 13 when the photocharge generated by the pixel PX accumulates in the floating diffusion region.

[0051] The reference signal can be a signal that indicates the unique reset noise value of pixel PX. In some implementations, the reference signal and the image signal can be collectively referred to as the "pixel signal".

[0052] Pixel array 20 may include a plurality of pixels PX arranged in a matrix comprising multiple rows and columns. The plurality of pixels PX can be connected to drive control circuitry 12 via multiple row lines extending in the row direction. The plurality of pixels PX can be connected to readout circuitry 13 via multiple column lines extending in the column direction. Pixel array 20 may include a configuration in which at least one or more pixels PX are arranged in both row and column directions. For example, in pixel array 20, the plurality of pixels PX may be arranged in the shape of a two-dimensional pixel array comprising rows and columns (or in a matrix structure). In some embodiments, the term "connection" may encompass both physical and electrical connections.

[0053] The multiple pixels PX included in the pixel array 20 can convert optical signals into electrical signals (pixel signals) and can be connected to a given internal pixel circuit.

[0054] The pixel array 20 may be provided with pixel control signals from the drive control circuit 12, including selection signals, reset signals, transmission signals, etc., and at least one pixel PX included in the selected row may perform a specific operation in response to the pixel control signals from the drive control circuit 12 (which include selection signals, reset signals, and transmission signals).

[0055] Each of the multiple pixels PX included in the pixel array 20 can respond to incident light from the outside and can output a pixel signal. The multiple pixels PX can be arranged in a two-dimensional shape. For example, the multiple pixels PX can be arranged in a matrix structure. The multiple pixels PX can be arranged along both row and column directions.

[0056] In the light incident on pixel PX, light in a specific wavelength band (e.g., red, green, or blue light) can pass through an optical filter disposed within pixel PX, and the light passing through the optical filter can be integrated into a photoelectric conversion region. A photocharge corresponding to the incident light can be generated in the photoelectric conversion region. An electrical signal corresponding to the amount of photocharge thus generated can be generated by pixel PX.

[0057] When pixel PX operates under very low or no incident light conditions, pixel PX can generate a dark signal. The signal generated under dark conditions can be a signal corresponding to the noise component generated within the image sensing device 1.

[0058] The readout circuit 13 can sample the electrical signals output from the pixel array 20, convert the sampled electrical signals into digital signals, and output the digital signals to an image signal processor (not shown). The readout circuit 13 may include, for example, a correlated dual sampler (not shown), an analog-to-digital (A / D) converter (not shown), an output buffer (not shown), a column driver (not shown), etc.

[0059] For example, a correlation double sampler can receive a reference signal and an image signal corresponding to each column in the pixel array 20, and can sample the levels of the reference signal and the image signal. In the case of a CMOS-based image sensing device, the correlation double sampler can sample the pixel signal twice to eliminate the difference between the two samples, and can perform correlation double sampling to remove unwanted values ​​such as fixed noise from the pixel PX. The correlation double sampler can remove unwanted values, for example, by comparing the voltage output from the pixel PX before and after the photocharge generated by the incident light accumulates in the floating diffusion region, and can measure the pixel output voltage based on the incident light.

[0060] The correlated double sampler can transmit the reference signal and image signal generated in columns as correlated double sample (CDS) signals to the A / D converter based on the timing signal or control signal of the timing control circuit 11.

[0061] For example, an A / D converter can convert a CDS signal, which is output from a correlated dual sampler and has an analog form, into a digital signal and output it.

[0062] The output buffer can temporarily hold and output the digital signal provided by the A / D converter.

[0063] The column driver can select columns in the output buffer based on the timing signal and control signal of the timing control circuit 11, so that the temporarily held digital signals are output in the order of the selected columns.

[0064] Figure 2 It is shown Figure 1 The circuit diagram of the circuit model of the pixel PX included in the pixel array 20.

[0065] Reference Figure 1 and Figure 2 The pixel PX may include a substrate 100 and an internal circuit region 200.

[0066] The substrate 100 may include a photoelectric conversion region 330 that generates photocharge in response to light incident from the outside, and a plurality of tap regions 310a and 310b that capture the photocharge.

[0067] The first tap region 310a may include a first detection node 314a and a first control node 312a. The first tap region 310a may be connected to a portion of the internal circuit region 200. The second tap region 310b may include a second detection node 314b and a second control node 312b. The second tap region 310b may be connected to another portion of the internal circuit region 200.

[0068] The first detection node 314a may be a region including impurities of a first conductivity type (e.g., n-type impurities). The first detection node 314a may be a region for capturing photocharge generated in the photoelectric conversion region 330. The first detection node 314a may be connected to a first terminal of the first transfer transistor TXa. The first detection node 314a may be connected to a first terminal of the first reset transistor RXa.

[0069] The second detection node 314b may be a region including impurities of a first conductivity type. The second detection node 314b may be a region for capturing photocharge generated in the photoelectric conversion region 330. The second detection node 314b may be connected to the first terminal of the second transmission transistor TXb. The second detection node 314b may be connected to the first terminal of the second reset transistor RXb.

[0070] The first control node 312a may be a region including impurities of a second conductivity type (e.g., p-type impurities). The first control node 312a may receive a first control signal Va from the drive control circuit 12. The second control node 312b may be a region including impurities of a second conductivity type. The second control node 312b may receive a second control signal Vb from the drive control circuit 12.

[0071] The potential difference between the first control signal Va and the second control signal Vb may cause a current to be generated in the photoelectric conversion region 330. The current can control the flow of photocharge generated in the photoelectric conversion region 330.

[0072] For example, when the voltage of the first control signal Va is higher than the voltage of the second control signal Vb, current can flow from the vicinity of the first control node 312a to the vicinity of the second control node 312b. Conversely, when the voltage of the first control signal Va is lower than the voltage of the second control signal Vb, current can flow from the vicinity of the second control node 312b to the first control node 312a.

[0073] As the current flows, the first detection node 314a or the second detection node 314b can capture and accumulate photocharge.

[0074] The photoelectric conversion region 330 can be a region in which the photoelectric effect is generated by incident light incident on the substrate 100, thereby generating photocharge corresponding to the incident light. The incident light can generate electron-hole pairs corresponding to the intensity of the incident light according to the photoelectric effect.

[0075] The internal circuit region 200 may include one or more circuits that generate electrical signals corresponding to the photocharges generated and captured in the substrate 100, and one or more circuits that output the electrical signals to the readout circuit 13. The internal circuit region 200 may include a first reset transistor RXa, a second reset transistor RXb, a first transmission transistor TXa, a second transmission transistor TXb, a first floating diffusion region FDa, a second floating diffusion region FDb, a first driving transistor DXa, a second driving transistor DXb, a first selection transistor SXa, and a second selection transistor SXb.

[0076] The control signals Va, Vb, RST, TRG, and SEL provided to the internal circuitry area 200 can be supplied from the drive control circuitry 12. The pixel voltage Vpx can be the power supply voltage.

[0077] The first reset transistor RXa can be set to an on or off state in response to the signal level of the reset signal RST applied to its gate electrode. For example, when the reset signal RST is high, the first reset transistor RXa can be set to an on state. When the first reset transistor RXa is on, the first intermediate node Ma can be reset. When the first transmission transistor TXa is on, the first reset transistor RXa can also be on; in this case, the first floating diffusion region FDa can also be reset together with the first intermediate node Ma. When the reset signal RST is low, the first reset transistor RXa can be set to an off state, thereby preventing the reset of the first intermediate node Ma. In some embodiments, the terms "high level" and "low level" can refer to logic high level and logic low level, respectively.

[0078] The second reset transistor RXb can be set to an on or off state in response to the signal level of the reset signal RST applied to its gate electrode. When the reset signal RST is high, the second reset transistor RXb can be set to the on state. When the second reset transistor RXb is on, the second intermediate node Mb can be reset. When the second reset transistor RXb is on, the second transmission transistor TXb can also be on; in this case, the second floating diffusion region FDb can also be reset together with the second intermediate node Mb. When the reset signal RST is low, the second reset transistor RXb can be set to the off state, thereby preventing the reset of the second intermediate node Mb.

[0079] The first transmission transistor TXa can be set to an on or off state in response to the signal level of the transmission signal TRG applied to its gate electrode. When the transmission signal TRG is high, the first transmission transistor TXa can be set to an on state. When the first transmission transistor TXa is on, the photocharge accumulated at the first detection node 314a can be transferred to the first floating diffusion region FDa for accumulation through the first intermediate node Ma. When the transmission signal TRG is low, the first transmission transistor TXa can be set to an off state. When the first transmission transistor TXa is off, the first transmission transistor TXa can block charge transfer between the first detection node 314a and the first floating diffusion region FDa.

[0080] The second transmission transistor TXb can be set to an on or off state in response to the signal level of the transmission signal TRG applied to its gate electrode. When the transmission signal TRG is high, the second transmission transistor TXb can be set to an on state. When the second transmission transistor TXb is on, the photocharge accumulated at the second detection node 314b can be transferred to the second floating diffusion region FDb for accumulation through the second intermediate node Mb. When the transmission signal TRG is low, the second transmission transistor TXb can be set to an off state. When the second transmission transistor TXb is off, the second transmission transistor TXb can block charge transfer between the second detection node 314b and the second floating diffusion region FDb.

[0081] The first floating diffusion region FDa can be connected to the gate electrode of the first driving transistor DXa. The first floating diffusion region FDa can be a node used to accumulate photocharge transmitted from the first detection node 314a.

[0082] The second floating diffusion region FDb can be connected to the gate electrode of the second driving transistor DXb. The second floating diffusion region FDb can be a node used to accumulate photocharge transferred from the second detection node 314b.

[0083] The first parasitic capacitor PCa can be connected to the first floating diffusion region FDa. The first parasitic capacitor PCa can provide a given capacitance to the first floating diffusion region FDa.

[0084] The second parasitic capacitor PCb can be connected to the second floating diffusion region FDb. The second parasitic capacitor PCb can provide a given capacitance to the second floating diffusion region FDb.

[0085] Capacitor CAP can be connected to the second floating diffusion region FDb. Capacitor CAP can be connected in parallel with the second parasitic capacitor PCb. Capacitor CAP can be connected in parallel with the second floating diffusion region FDb. Capacitor CAP can provide a given capacitance to the second floating diffusion region FDb.

[0086] The second floating diffusion region FDb to which the capacitor CAP is connected can have a larger capacitance than the first floating diffusion region FDa not connected to the capacitor CAP; in this case, the second floating diffusion region FDb can accumulate more photocharge and achieve high dynamic range (HDR). For example, in a high-illuminance environment with relatively high incident light, the pixel signal can be output through the second floating diffusion region FDb. Conversely, in a low-illuminance environment with relatively low incident light, the pixel signal can be output through the first floating diffusion region FDa. According to the implementation, whether pixel PX outputs a pixel signal through any floating diffusion region can be determined based on the illuminance range.

[0087] The first driving transistor DXa may include a drain electrode connected to the pixel voltage Vpx and a source electrode connected to the first vertical signal line SLa via a first selection transistor SXa. The gate electrode of the first driving transistor DXa may be connected to a first floating diffusion region FDa. The first driving transistor DXa may operate as a source follower transistor, which outputs a current (pixel signal) of a magnitude corresponding to the potential of the first floating diffusion region FDa.

[0088] The second driving transistor DXb may include a drain electrode connected to the pixel voltage Vpx and a source electrode connected to the second vertical signal line SLb via a second selection transistor SXb. The gate electrode of the second driving transistor DXb may be connected to the second floating diffusion region FDb. The second driving transistor DXb may operate as a source follower transistor, which outputs a current (pixel signal) of a magnitude corresponding to the potential of the second floating diffusion region FDb.

[0089] The first selection transistor SXa can be set to an on or off state based on the signal level of the selection signal SEL applied to its gate electrode. When the selection signal SEL is high, the first selection transistor SXa can be set to an on state. When the first selection transistor SXa is on, it can output a pixel signal from the first driving transistor DXa to the first vertical signal line SLa, the pixel signal having a magnitude corresponding to the potential of the first floating diffusion region FDa. The first vertical signal line SLa can be connected to the readout circuit 13. When the selection signal SEL is low, the first selection transistor SXa can be set to an off state. When the first selection transistor SXa is off, it prevents the pixel signal output from the first driving transistor DXa from being output to the first vertical signal line SLa.

[0090] The second selection transistor SXb can be set to an on or off state based on the signal level of the selection signal SEL applied to its gate electrode. When the selection signal SEL is high, the second selection transistor SXb can be set to an on state. When the second selection transistor SXb is on, it can output a pixel signal from the second driving transistor DXb to the second vertical signal line SLb, the pixel signal having a magnitude corresponding to the potential of the second floating diffusion region FDb. The second vertical signal line SLb can be connected to the readout circuit 13. When the selection signal SEL is low, the second selection transistor SXb can be set to an off state. When the second selection transistor SXb is off, it prevents the pixel signal output from the second driving transistor DXb from being output to the second vertical signal line SLb.

[0091] The pixel signal output from either the first vertical signal line SLa or the second vertical signal line SLb can be converted into image data through noise removal and analog-to-digital conversion in the readout circuit 13.

[0092] Figure 2 An example is shown where the same reset signal RST is applied to the first reset transistor RXa and the second reset transistor RXb. However, embodiments of the disclosed technology may include implementations where the reset signal RST applied to the first reset transistor RXa and the reset signal RST applied to the second reset transistor RXb are controlled independently of each other. Similarly, Figure 2An example is shown where the same transmission signal TRG is applied to the first transmission transistor TXa and the second transmission transistor TXb. However, embodiments of the disclosed technology may include implementations where the transmission signal TRG applied to the first transmission transistor TXa and the transmission signal TPG applied to the second transmission transistor TXb are controlled independently of each other. Furthermore, Figure 2 An example is shown in which the same selection signal SEL is applied to the first selection transistor SXa and the second selection transistor SXb. However, implementations of the disclosed technology may include implementations in which the selection signal SEL applied to the first selection transistor SXa and the selection signal SEL applied to the second selection transistor SXb are controlled independently of each other.

[0093] An image signal processor (not shown) can generate an image using image data obtained from photocharge captured at the first detection node 314a. The image signal processor can also generate an image using image data obtained from photocharge captured at the second detection node 314b.

[0094] Figure 3 It is partially shown Figure 1 A cross-sectional view of the pixels PX included in the pixel array 20.

[0095] Reference Figure 2 and Figure 3 The pixel PX may include a substrate 100 and a wiring (interconnection) region 210. The substrate 100 may include a rear surface BS on which incident light is incident and a front surface FS away from the rear surface BS. The wiring region 210 may be located adjacent to the front surface FS.

[0096] Substrate 100 may include a given doped structure formed by doping the interior of a semiconductor substrate with impurities, and a given separation structure formed by forming trenches from one surface (e.g., the front surface FS) of the semiconductor substrate and filling the trenches with an insulating material. For example, substrate 100 may include a given doped region formed by implanting impurities of a first conductivity type (n-type) and a second conductivity type (p-type) into a semiconductor substrate comprising a silicon material (e.g., Si or SiGe). Substrate 100 may include a given separation structure for physically separating some of the doped regions.

[0097] The substrate 100 may include a first detection node 314a, a first control node 312a, a first intermediate node MDa, a first floating diffusion region FDa, a first well region PWa, a second detection node 314b, a second control node 312b, a second intermediate node MDb, a second floating diffusion region FDb, a second well region PWb, a first separation structure STI, and a photoelectric conversion region 330.

[0098] The first detection node 314a may be located on the front surface FS of the substrate 100. The first detection node 314a may be spaced apart from the rear surface BS of the substrate 100. The first detection node 314a may be a region formed by implanting impurities of a first conductivity type into the semiconductor substrate. The first detection node 314a may be disposed adjacent to one side of the first control node 312a. Figure 3 The example shown illustrates an implementation where the first detection node 314a is positioned to one side of the first control node 312a; however, implementations where the first detection node 314a surrounds the first control node 312a are also possible. The first detection node 314a may be in contact with the wiring structure 250.

[0099] The first control node 312a may be located on the front surface FS of the substrate 100. The first control node 312a may be spaced apart from the rear surface BS of the substrate 100. The first control node 312a may be a region formed by implanting impurities of a second conductivity type into the semiconductor substrate. The first control node 312a may be in contact with the wiring structure 250.

[0100] The first intermediate node MDa can be located on the front surface FS of the substrate 100. The first intermediate node MDa can be spaced apart from the rear surface BS of the substrate 100. The first intermediate node MDa can be a region formed by implanting an impurity of a first conductivity type into the semiconductor substrate. The first intermediate node MDa can be in contact with the wiring structure 250. The first intermediate node MDa can be disposed inside the first well region PWa.

[0101] The first floating diffusion region FDa can be located on the front surface FS of the substrate 100. The first floating diffusion region FDa can be spaced apart from the rear surface BS of the substrate 100. The first floating diffusion region FDa can be a region formed by implanting impurities of a first conductivity type into the semiconductor substrate. The first floating diffusion region FDa can be in contact with the wiring structure 250. The first floating diffusion region FDa can be disposed inside the first well region PWa.

[0102] The first well region PWa may be located on the front surface FS of the substrate 100. The first well region PWa may be spaced apart from the rear surface BS of the substrate 100. The first well region PWa may be a region formed by implanting impurities of a second conductivity type into the semiconductor substrate. The first well region PWa may surround the first intermediate node MDa and the first floating diffusion region FDa. For example, the first well region PWa may contact the side surface and the bottom surface of each of the first intermediate node MDa and the first floating diffusion region FDa.

[0103] Since a PN junction is formed between the first floating diffusion region FDa and the first well region PWa, a capacitor can be formed in the first floating diffusion region FDa. The circuit model obtained by modeling the capacitor formed by the PN junction in the circuit diagram can correspond to... Figure 2 The first parasitic capacitor PCa.

[0104] The second detection node 314b may be located on the front surface FS of the substrate 100. The second detection node 314b may be spaced apart from the rear surface BS of the substrate 100. The second detection node 314b may be a region formed by implanting impurities of a first conductivity type into the semiconductor substrate. The second detection node 314b may be disposed adjacent to one side of the second control node 312b. Figure 3 The example shown illustrates an implementation where the second detection node 314b is positioned to one side of the second control node 312b; however, implementations where the second detection node 314b surrounds the second control node 312b are also possible. The second detection node 314b may contact the wiring structure 250.

[0105] The second control node 312b may be located on the front surface FS of the substrate 100. The second control node 312b may be spaced apart from the rear surface BS of the substrate 100. The second control node 312b may be a region formed by implanting impurities of a second conductivity type into the semiconductor substrate. The second control node 312b may be in contact with the wiring structure 250.

[0106] The second intermediate node MDb can be located on the front surface FS of the substrate 100. The second intermediate node MDb can be spaced apart from the rear surface BS of the substrate 100. The second intermediate node MDb can be a region formed by implanting impurities of a first conductivity type into the semiconductor substrate. The second intermediate node MDb can be in contact with the wiring structure 250. The second intermediate node MDb can be disposed inside the second well region PWb.

[0107] The second floating diffusion region FDb can be located on the front surface FS of the substrate 100. The second floating diffusion region FDb can be spaced apart from the rear surface BS of the substrate 100. The second floating diffusion region FDb can be a region formed by implanting impurities of a first conductivity type into the semiconductor substrate. The second floating diffusion region FDb can be in contact with the wiring structure 250. The second floating diffusion region FDb can be disposed inside the second well region PWb.

[0108] The second well region PWb may be located on the front surface FS of the substrate 100. The second well region PWb may be spaced apart from the rear surface BS of the substrate 100. The second well region PWb may be a region formed by implanting impurities of a second conductivity type into the semiconductor substrate. The second well region PWb may surround the second intermediate node MDb and the second floating diffusion region FDb. For example, the second well region PWb may contact the side surface and the bottom surface of each of the second intermediate node MDb and the second floating diffusion region FDb.

[0109] Since a PN junction is formed between the second intermediate node MDb and the second floating diffusion region FDb, a capacitor can be formed in the second floating diffusion region FDb. The circuit model obtained by modeling the capacitor formed by the PN junction in the circuit diagram can correspond to... Figure 2 The second parasitic capacitor PCb.

[0110] The first separation structure STI can be located between the first control node 312a and the second control node 312b, the first detection node 314a and the second detection node 314b, the first well region PWa and the second well region PWb, to electrically isolate the components from each other. The first separation structure STI can have a shape in which insulating material is embedded in a trench formed by etching a portion of the front surface FS of the substrate 100. The depth of the first separation structure STI extending from the front surface FS into the interior of the semiconductor substrate can be less than the depth of each of the first well region PWa and the second well region PWb, the first control node 312a and the second control node 312b, and the first detection node 314a and the second detection node 314b.

[0111] The photoelectric conversion region 330 can react to incident light incident from the rear surface BS of the substrate 100 to generate photocharge. The transmission direction of the photocharge in the photoelectric conversion region 330 can be determined according to the control signals Va and Vb respectively applied to the first control node 312a and the second control node 312b. The photoelectric conversion region 330 can also be a region in the semiconductor substrate that includes a given impurity.

[0112] The wiring region 210 may include a first transmission gate TXGa, a second transmission gate TXGb, a capacitor CAP, a wiring structure 250, and an interlayer insulating layer 270.

[0113] The first transmission gate TXGa can be disposed on the front surface FS of the substrate 100. The first transmission gate TXGa can partially overlap with the first floating diffusion region FDa. The first transmission gate TXGa can partially overlap with the first intermediate node MDa. The first transmission gate TXGa can contact the wiring structure 250.

[0114] The second transmission gate TXGb can be disposed on the front surface FS of the substrate 100. The second transmission gate TXGb can partially overlap with the second floating diffusion region FDb. The second transmission gate TXGb can partially overlap with the second intermediate node MDb. The second transmission gate TXGb can contact the wiring structure 250.

[0115] The capacitor CAP can be spaced apart from the front surface FS of the substrate 100. For example, the capacitor CAP can be configured to be spaced apart from the front surface FS in the vertical direction. The capacitor CAP can be connected to the second floating diffusion region FDb via wiring structure 250. The capacitor CAP can overlap with the first tap region 310a. For example, when viewed in the vertical direction, the capacitor CAP can overlap with the first tap region 310a. The capacitor CAP can overlap with the second tap region 310b. For example, when viewed in the vertical direction, the capacitor CAP can overlap with the second tap region 310b.

[0116] Capacitor CAP can be used to provide additional capacitance to the second floating diffusion region FDb. As the cross-sectional area of ​​capacitor CAP increases, its capacitance can also increase. When capacitor CAP overlaps with both the second tap region 310b and the first tap region 310a, its cross-sectional area can further increase. Consequently, the capacitance of capacitor CAP may increase even further.

[0117] As the capacitance of capacitor CAP increases, as referenced Figure 2 As described, the second floating diffusion region FDb to which the capacitor CAP is connected can have a larger capacitance compared to the first floating diffusion region FDa not connected to the capacitor CAP; in this case, the second floating diffusion region FDb can accumulate more photocharge and can achieve a high dynamic range (HDR).

[0118] A capacitor CAP can be implemented as at least one of a metal-insulator-metal (MIM) capacitor, a metal-insulator-polysilicon (MIP) capacitor, a metal-oxide-semiconductor (MOS) capacitor, or a junction capacitor. An example will be described of an implementation of a capacitor CAP as a MIM capacitor.

[0119] The capacitor CAP may include a first metal layer C10, a dielectric layer C20, and a second metal layer C30. The first metal layer C10 may be an electrode layer corresponding to one electrode of the capacitor CAP. The second metal layer C30 may be an electrode layer corresponding to the opposite electrode of the capacitor CAP. The dielectric layer C20 may be disposed between the first metal layer C10 and the second metal layer C30.

[0120] Each of the first metal layer C10 and the second metal layer C30 may include a material with conductive properties. For example, each of the first metal layer C10 and the second metal layer C30 may include aluminum (Al), gold (Au), copper (Cu), tungsten (W), platinum (Pt), iridium (Ir), titanium (Ti), or an alloy using at least one of these materials.

[0121] The dielectric layer C20 may include a material with insulating properties. For example, the dielectric layer C20 may include at least one of silicon oxide (SiO2), silicon nitride (Si3N4), a high-k dielectric, or a metal oxide (e.g., aluminum oxide (Al2O3)). For example, the high-k dielectric may include TiO2, BaSrTiO3, SrTiO3, ZrO2, or HfO2.

[0122] Wiring (e.g., interconnects such as metal interconnects) structure 250 may include a material with good electrical conductivity. For example, each of the wiring structures 250 may include at least one of a material such as copper (Cu), aluminum (Al), tungsten (W), or polycrystalline silicon including impurities.

[0123] The wiring structure 250 in contact with the first floating diffusion region FDa can be an interconnect connecting the gate electrode of the first driving transistor DXa and the first floating diffusion region FDa. The wiring structure 250 in contact with the first transmission gate TXGa can be an interconnect for applying the transmission signal TRG to the first transmission gate TXGa. The wiring structure 250 in contact with the first intermediate node MDa can also be an interconnect that contacts the first detection node 314a. The wiring structure 250 in contact with the first control node 312a can be an interconnect for applying the first control signal Va to the first control node 312a.

[0124] The wiring structure 250 in contact with the second control node 312b can be an interconnect for applying the second control signal Vb to the second control node 312b. The wiring structure 250 in contact with the second intermediate node MDb can also be an interconnect that contacts the second detection node 314b. The wiring structure 250 in contact with the second transmission gate TXGb can be an interconnect for applying the transmission signal TRG to the second transmission gate TXGb. The wiring structure 250 in contact with the second floating diffusion region FDb can be an interconnect connecting the gate electrode of the second driving transistor DXb and the second floating diffusion region FDb. Furthermore, the wiring structure 250 in contact with the second floating diffusion region FDb can be an interconnect for connecting the capacitor CAP and the second floating diffusion region FDb in parallel.

[0125] Interlayer insulation 270 electrically isolates the wiring structures 250 from each other. Interlayer insulation 270 can be disposed between spaced-apart wiring structures 250. Interlayer insulation 270 minimizes signal interference between wiring structures 250. Interlayer insulation 270 may comprise a material with insulating properties. For example, interlayer insulation 270 may comprise at least one of silicon oxide (SiO2) or silicon nitride (Si3N4).

[0126] Figure 4 It is shown Figure 2 The circuit diagram shows an example of the potential distribution of the first floating diffusion region FDa and the second floating diffusion region FDb.

[0127] Reference Figure 2 and Figure 4 When neither the first tap region 310a nor the second tap region 310b is in operation, both the first transmission transistor TXa and the second transmission transistor TXb can be in the off state.

[0128] When the first transmission transistor TXa is in the off state, it can form a potential barrier between the first floating diffusion region FDa and the first intermediate node Ma, thereby blocking charge transfer between them. The potential of the first floating diffusion region FDa can be lower than the potential of the first intermediate node Ma.

[0129] When the second transfer transistor TXb is in the off state, it can form a potential barrier between the second floating diffusion region FDb and the second intermediate node Mb, thereby blocking charge transfer between them. The potential of the second floating diffusion region FDb can be lower than the potential of the second intermediate node Mb.

[0130] Because the second floating diffusion region FDb and the capacitor CAP are connected in parallel, the capacitance of the second floating diffusion region FDb can be greater than the capacitance of the first floating diffusion region FDa.

[0131] Reference Figures 5A to 7B In order to describe the image sensing device 1 (see Figure 1Example operating methods are described, as an example, including three driving modes: a first mode, in which the first tap region 310a operates in a low-illuminance environment with a relatively small amount of incident light; a second mode, in which the second tap region 310b operates in a high-illuminance environment with a relatively large amount of incident light; and a third mode, in which the first tap region 310a and the second tap region 310b operate in a medium-illuminance environment with incident light amounts between those of the low-illuminance and high-illuminance environments. A low-illuminance environment can be an environment where the incident light illuminance is less than a first threshold. A high-illuminance environment can be an environment where the incident light illuminance is greater than a second threshold, which is greater than or equal to the first threshold. A medium-illuminance environment can be an environment where the incident light illuminance is greater than or equal to the first threshold and less than the second threshold.

[0132] Figure 5A It shows when Figure 2 The circuit diagram is a graph showing an example of the signal levels of the first control signal Va and the second control signal Vb when operating in the first mode.

[0133] Figure 5B It is shown in Figure 5A A graph illustrating the potential distribution of the first floating diffusion region FDa and the second floating diffusion region FDb during the operating interval.

[0134] Figure 5A and Figure 5B This is a diagram illustrating an example of an operation method for driving the first tap region 310a in a low-light environment with relatively low incident light intensity.

[0135] Reference Figure 2 , Figure 4 , Figure 5A and Figure 5B During the operating interval OPa between the first tap region 310a and the second tap region 310b, the first control signal Va can have a high level "H", while the second control signal Vb can have a low level "L". During the operating interval OPa, the first transmission transistor TXa can be in the on state, while the second transmission transistor TXb can be in the off state.

[0136] When the first control signal Va has a high level "H", the first detection node 314a of the first tap region 310a can capture the photocharge generated in the photoelectric conversion region 330.

[0137] The photocharge captured at the first detection node 314a can be moved to the first intermediate node Ma, and then transferred to the first floating diffusion region FDa through the first transmission transistor TXa in the on state, so as to accumulate in the first floating diffusion region FDa.

[0138] Conversely, because the second control signal Vb has a low level "L", the second tap region 310b can be left inactive.

[0139] Figure 6A It shows when Figure 2 The circuit diagram is a graph showing an example of the signal levels of the first control signal Va and the second control signal Vb when operating in the second mode.

[0140] Figure 6B It is shown in Figure 6A A graph illustrating the potential distribution of the first floating diffusion region FDa and the second floating diffusion region FDb during the operating interval.

[0141] Figure 6A and Figure 6B This is a diagram illustrating an example of a second mode of operation for driving the second tap region 310b in a high-illuminance environment with a relatively large amount of incident light.

[0142] Reference Figure 2 , Figure 4 , Figure 6A and Figure 6B In the operating interval OPb between the first tap region 310a and the second tap region 310b, the first control signal Va can have a low level "L", while the second control signal Vb can have a high level "H". In the operating interval OPb, the first transmission transistor TXa can be in the off state, while the second transmission transistor TXb can be in the on state.

[0143] Because the first control signal Va has a low level "L", the first tap region 310a can be left unoperated.

[0144] When the second control signal Vb has a high level "H", the second detection node 314b of the second tap region 310b can capture the photocharge generated in the photoelectric conversion region 330.

[0145] The photocharge captured at the second detection node 314b can be moved to the second intermediate node Mb, and then transferred to the second floating diffusion region FDb through the second transfer transistor TXb in the on state to accumulate in the second floating diffusion region FDb.

[0146] Figure 7A It shows when Figure 2 The circuit diagram is a graph showing an example of the signal levels of the first control signal Va and the second control signal Vb when operating in the third mode.

[0147] Figure 7B It is shown in Figure 7AA graph illustrating an example of the potential distribution in the first floating diffusion region FDa and the second floating diffusion region FDb during the first operating interval.

[0148] Figure 7C It is shown in Figure 7A A graph illustrating an example of the potential distribution in the first floating diffusion region FDa and the second floating diffusion region FDb during the second operating interval.

[0149] Figures 7A to 7C This is a diagram that partially describes the operation of a third mode of driving the first tap region 310a and the second tap region 310b in a moderate illuminance environment where the incident light intensity is between that in a low illuminance environment and that in a high illuminance environment.

[0150] Reference Figure 2 , Figure 4 , Figure 7A , Figure 7B and Figure 7C The first operation interval OP1 can be the interval of operation in the first tap region 310a. The second operation interval OP2 can be the interval of operation in the second tap region 310b. According to the disclosed embodiments, the first operation interval OP1 and the second operation interval OP2 can be repeated alternately.

[0151] During the first operating interval OP1, the first control signal Va can be high ("H"), and the second control signal Vb can be low ("L"). During the first operating interval OP1, the first transmission transistor TXa can be on, and the second transmission transistor TXb can be off.

[0152] When the first control signal Va has a high level "H", the first detection node 314a of the first tap region 310a can capture the photocharge generated in the photoelectric conversion region 330. The photocharge captured at the first detection node 314a can move to the first intermediate node Ma, and then move to the first floating diffusion region FDa through the first transmission transistor TXa in the on state, so as to accumulate in the first floating diffusion region FDa.

[0153] Because the second control signal Vb has a low level "L", the second tap region 310b can be excluded from operation during the first operation interval OP1.

[0154] In the second operation interval OP2, the first control signal Va can be low ("L"), and the second control signal Vb can be high ("H"). In the second operation interval OP2, the first transmission transistor TXa can be off, and the second transmission transistor TXb can be on.

[0155] Because the first control signal Va has a low level "L", the first tap region 310a can be excluded from operation during the second operation interval OP2.

[0156] When the second control signal Vb has a high level "H", the second detection node 314b of the second tap region 310b can capture the photocharge generated in the photoelectric conversion region 330. The photocharge captured at the second detection node 314b can move to the second intermediate node Mb, and then through the second transmission transistor TXb in the on state, it can move to the second floating diffusion region FDb to accumulate in the second floating diffusion region FDb.

[0157] In the third mode, the operation of the first tap region 310a and the second tap region 310b is not limited to the above-described embodiments. For example, in the third mode, the first tap region 310a and the second tap region 310b can operate simultaneously.

[0158] Figure 8 It is shown Figure 1 A plan view of an example of pixel group PG included in pixel array 20.

[0159] Below, references will be omitted as much as possible. Figure 2 and Figure 3 The given description.

[0160] Reference Figure 1 , Figure 2 , Figure 3 and Figure 8 Pixel group PG may include a first pixel PX1, a second pixel PX2, a third pixel PX3, and a fourth pixel PX4. A second separation structure DTI can be set at the boundary between the first pixel PX1 and the fourth pixel PX4. The second separation structure DTI can prevent or reduce crosstalk between adjacent pixels. (See reference...) Figure 9 Describe the second separation structure DTI in detail.

[0161] Each of the first pixel PX1 to the fourth pixel PX4 may include substantially the same components. As an example, each of the first pixel PX1 to the fourth pixel PX4 may include a first tap region 310a, a second tap region 310b, a photoelectric conversion region 330, a first well region PWa, a first transmission gate TXGa, a first reset gate RXGa, a first drive gate DXGa, a first select gate SXGa, a first intermediate node MDa, a first reset node RDa, a first connection node CDA, a first output node ODa, a first floating diffusion region FDa, a second well region PWb, a second transmission gate TXGb, a second reset gate RXGb, a second drive gate DXGb, a second select gate SXGb, a second intermediate node MDb, a second reset node RDb, a second connection node CDb, a second output node ODb, and a second floating diffusion region FDb.

[0162] Below, as an example, the first pixel PX1 among the first pixel PX1 to the fourth pixel PX4 will be described.

[0163] The first tap region 310a may include a first detection node 314a and a first control node 312a. The second tap region 310b may include a second detection node 314b and a second control node 312b. The first tap region 310a may be spaced apart from the second tap region 310b in one direction (hereinafter referred to as the "first direction").

[0164] The first detection node 314a and the first control node 312a can be adjacent to each other. As an example, the first detection node 314a can be configured to be spaced apart from the first control node 312a in a first direction. Figure 8 The illustration shows an embodiment where the first detection node 314a and the first control node 312a are spaced apart from each other and arranged in parallel; however, in another embodiment, the first detection node 314a may be arranged in a shape surrounding the first control node 312a. A photoelectric conversion region 330 may be disposed between the first detection node 314a and the first control node 312a.

[0165] The second detection node 314b and the second control node 312b can be adjacent to each other. As an example, the second detection node 314b can be configured to be spaced apart from the second control node 312b in a direction away from the first direction (hereinafter referred to as the "second direction"). Figure 8 The illustration shows an embodiment where the second detection node 314b and the second control node 312b are spaced apart from each other and arranged in parallel; however, in another embodiment, the second detection node 314b may be arranged in a shape surrounding the second control node 312b. A photoelectric conversion region 330 may be disposed between the second detection node 314b and the second control node 312b.

[0166] The first control node 312a can be the region where the first control signal Va is applied. The second control node 312b can be the region where the second control signal Vb is applied.

[0167] The photoelectric conversion region 330 may surround the first detection node 314a, the first control node 312a, the second detection node 314b, and the second control node 312b.

[0168] The first transmission gate TXGa can be the gate electrode of the first transmission transistor TXa. The first transmission gate TXGa can also be the gate electrode to which the transmission signal TRG is applied. The first transmission gate TXGa can overlap with the first well region PWa.

[0169] The first reset gate RXGa can be the gate electrode of the first reset transistor RXa. The first reset gate RXGa can be the gate electrode to which a reset signal RST is applied. The first reset gate RXGa can overlap with the first well region PWa.

[0170] The first driving gate DXGa can be the gate electrode of the first driving transistor DXa. The first driving gate DXGa can be connected to the first floating diffusion region FDa through wiring structure 250. The first driving gate DXGa can overlap with the first well region PWa.

[0171] The first selection gate SXGa can be the gate electrode of the first selection transistor SXa. The first selection gate SXGa can be the gate electrode to which the selection signal SEL is applied. The first selection gate SXGa can overlap with the first well region PWa.

[0172] The first reset node RDa may be a region including impurities of a first conductivity type. The first reset node RDa may be located on one side of the first reset gate RXGa. The first reset node RDa may be located in the first well region PWa. The first reset node RDa may be a region where a pixel voltage Vpx is applied via a given wiring structure 250.

[0173] The first intermediate node MDa may be a region including impurities of a first conductivity type. The first intermediate node MDa may be located on the opposite side of the first reset gate RXGa. The first intermediate node MDa may be located on one side of the first transmission gate TXGa. The first intermediate node MDa may be located in the first well region PWa. The first intermediate node MDa can be connected to the first detection node 314a via a given wiring structure 250.

[0174] The first floating diffusion region FDa may be a region including impurities of a first conductivity type. The first floating diffusion region FDa may be located on the opposite side of the first transmission gate TXGa. The first floating diffusion region FDa may be located in the first well region PWa. The first floating diffusion region FDa can be connected to the first driving gate DXGa via a given wiring structure 250.

[0175] The first connection node CDa may be a region including impurities of a first conductivity type. The first connection node CDa may be located on one side of the first driving gate DXGa. The first connection node CDa may also be located on the opposite side of the first driving gate DXGa. The first connection node CDa may be located in the first well region PWa. The first connection node CDa located on one side of the first driving gate DXGa may be a region where a pixel voltage Vpx is applied through a given wiring structure 250. The first connection node CDa located on the opposite side of the first driving gate DXGa may be located on one side of the first select gate SXGa.

[0176] The first output node ODa may be a region including impurities of a first conductivity type. The first output node ODa may be located on the opposite side of the first select gate SXGa. The first output node ODa may be located in the first well region PWa. The first output node ODa may be a region connected to the readout circuit 13 via a given wiring structure 250.

[0177] The first well region PWa may be a region including impurities of the second conductivity type. The first well region PWa may be located at a position biased to one side of the center of the first pixel PX1. The first well region PWa may be in contact with the side surface of each of the plurality of doped regions RDa, MDa, FDa, CDDa, and ODa. The first well region PWa may be configured to be spaced apart from the first tap region 310a in a first direction.

[0178] The second transmission gate TXGb can be the gate electrode of the second transmission transistor TXb. The second transmission gate TXGb can be the gate electrode to which the transmission signal TRG is applied. The second transmission gate TXGb can overlap with the second well region PWb.

[0179] The second reset gate RXGb can be the gate electrode of the second reset transistor RXb. The second reset gate RXGb can be the gate electrode to which a reset signal RST is applied. The second reset gate RXGb can overlap with the second well region PWb.

[0180] The second driving gate DXGb can be the gate electrode of the second driving transistor DXb. The second driving gate DXGb can be connected to the second floating diffusion region FDb through wiring structure 250. The second driving gate DXGb can overlap with the second well region PWb.

[0181] The second selection gate SXGb can be the gate electrode of the second selection transistor SXb. The second selection gate SXGb can also be the gate electrode to which the selection signal SEL is applied. The second selection gate SXGb can overlap with the second well region PWb.

[0182] The second reset node RDb can be a region including impurities of the first conductivity type. The second reset node RDb can be located on one side of the second reset gate RXGb. The second reset node RDb can be located in the second well region PWb. The second reset node RDb can be a region where a pixel voltage Vpx is applied via a given wiring structure 250.

[0183] The second intermediate node MDb can be a region including impurities of the first conductivity type. The second intermediate node MDb can be located on the opposite side of the second reset gate RXGb. The second intermediate node MDb can be located on one side of the second transmission gate TXGb. The second intermediate node MDb can be located in the second well region PWb. The second intermediate node MDb can be connected to the second detection node 314b via a given wiring structure 250.

[0184] The second floating diffusion region FDb can be a region including impurities of the first conductivity type. The second floating diffusion region FDb can be located on the opposite side of the second transmission gate TXGb. The second floating diffusion region FDb can be located in the second well region PWb. The second floating diffusion region FDb can be connected to the second drive gate DXGb via a given wiring structure 250.

[0185] The second connection node CDb can be a region including impurities of the first conductivity type. The second connection node CDb can be located on one side of the second driving gate DXGb. The second connection node CDb can also be located on the opposite side of the second driving gate DXGb. The second connection node CDb can be located in the second well region PWb. The second connection node CDb located on one side of the second driving gate DXGb can be a region where a pixel voltage Vpx is applied through a given wiring structure 250. The second connection node CDb located on the opposite side of the second driving gate DXGb can be located on one side of the second select gate SXGb.

[0186] The second output node ODb can be a region including impurities of the first conductivity type. The second output node ODb can be located on the opposite side of the second select gate SXGb. The second output node ODb can be located in the second well region PWb. The second output node ODb can be a region connected to the readout circuit 13 via a given wiring structure 250.

[0187] The second well region PWb can be a region including impurities of a second conductivity type. The second well region PWb can be located on the opposite side of the center of the first pixel PX1. The second well region PWb can be in contact with the side surface of each of the plurality of doped regions RDb, MDb, FDb, CDb, and ODb. The second well region PWb can be configured to be spaced apart from the second tap region 310b in a second direction.

[0188] Below, in conjunction with along Figure 8 The cross-section intercepted by line A-A' will omit references as much as possible. Figure 3 The given description.

[0189] Figure 9 It shows along Figure 8 The first example configuration of the cross-section diagram is shown by the line A-A'.

[0190] Reference Figure 1 , Figure 2 , Figure 3 , Figure 8 and Figure 9 As along Figure 8 The first cross section E1 of the first example configuration cut by line A-A' may include a substrate 100, a wiring structure 250, a capacitor CAP, an anti-reflective layer AR, a mesh structure GRD, and a microlens ML.

[0191] The substrate 100 may include a rear surface BS on which incident light is incident and a front surface FS away from the rear surface BS. The substrate 100 may include a first detection node 314a, a first control node 312a, a first well region PWa, a first floating diffusion region FDa, a second detection node 314b, a second control node 312b, a second well region PWb, a second floating diffusion region FDb, a photoelectric conversion region 330, a first separation structure STI, and a second separation structure DTI.

[0192] Each of the first detection node 314a, the first control node 312a, the first well region PWa, the second detection node 314b, the second control node 312b, and the second well region PWb can extend from the front surface FS to the interior of the substrate 100 at a given depth.

[0193] In the disclosed embodiments, the depth of the first control node 312a may be greater than or equal to the depth of the second control node 312b. The depth of the second control node 312b may be greater than or equal to the depth of the second well region PWb.

[0194] When the depth of the first control node 312a is greater than or equal to the depth of the second control node 312b, the magnitude of the first current CR1 flowing between the first control node 312a and the first well region PWa can be greater than or equal to the magnitude of the second current CR2 flowing between the second control node 312b and the second well region PWb. When the first current CR1 is greater than or equal to the second current CR2, the rate at which photocharge is collected at the first detection node 314a can be faster than the rate at which photocharge is collected at the second detection node 314b.

[0195] According to the first example configuration, the first detection node 314a and the second detection node 314b can have the same depth, but due to process limitations or variables, there may be a difference between the depth of the first detection node 314a and the depth of the second detection node 314b. The first control node 312a and the second control node 312b can have the same depth, but due to process limitations or variables, there may be a difference between the depth of the first control node 312a and the depth of the second control node 312b. The depth of the first control node 312a can be deeper than the depth of the first detection node 314a. The depth of the second control node 312b can be deeper than the depth of the second detection node 314b.

[0196] The first well region PWa can be formed inside the substrate 100, with a depth reaching a first depth D1 starting from the front surface FS. The second well region PWb can be formed inside the substrate 100, with a depth reaching a second depth D2 starting from the front surface FS. The first depth D1 can be the same as the second depth D2, but there may be a difference between the first depth D1 and the second depth D2 due to process limitations or variables.

[0197] Because the depth of the first well region PWa is the same as the depth of the second well region PWb, the first current CR1 and the second current CR2 can have essentially the same magnitude in the photoelectric conversion region 330. Therefore, the rate at which photocharge is captured at the first detection node 314a can be similar to the rate at which photocharge is captured at the second detection node 314b.

[0198] To electrically separate the first well region PWa, the first detection node 314a, the first control node 312a, the second well region PWb, the second detection node 314b, and the second control node 312b from each other, a first separation structure STI can be provided between them. In another embodiment, the first well region PWa, the first detection node 314a, the first control node 312a, the second well region PWb, the second detection node 314b, and the second control node 312b can be formed without the first separation structure STI.

[0199] The second separation structure DTI can be disposed at the relative boundaries of pixels. Structurally, the second separation structure DTI can extend from the front surface FS to the interior of the substrate 100. For example, the second separation structure DTI can extend from the front surface FS to the rear surface BS. The second separation structure DTI may include a conductive layer and an insulating layer surrounding the conductive layer. The conductive layer may include, for example, impurity-containing polysilicon. The insulating layer may include, for example, silicon oxide or zirconium nitride. The second separation structure DTI can prevent crosstalk between adjacent pixels caused when light is incident on the interior of the substrate 100 through the rear surface BS.

[0200] The anti-reflective layer AR can be configured to contact the rear surface BS. The anti-reflective layer AR reduces the rate at which incident light incident on the substrate 100 via the microlens ML is reflected. The anti-reflective layer AR can include, for example, silicon nitride. The anti-reflective layer AR can have a stacked structure in which multiple materials are layered.

[0201] A mesh-structured GRD can be positioned near the boundaries of pixels. When light passes through a microlens ML, the mesh-structured GRD can prevent crosstalk between adjacent pixels. As an example, a mesh-structured GRD can include a material with high reflectivity (e.g., air). As another example, a mesh-structured GRD can include a material with high absorptivity (e.g., tungsten (W)).

[0202] The microlens ML can focus light onto a pixel on the substrate 100. The incident surface on which the incident light enters the microlens ML can be curved. An optical filter (not shown) can be further disposed between the microlens ML and the back surface BS. The optical filter can selectively transmit light of a specific wavelength (e.g., green, red, or blue wavelength).

[0203] Figure 10 It shows along Figure 8 The second example configuration of the cross-section diagram is shown by the cross-section cut by line A-A'.

[0204] Reference Figure 1 , Figure 2 , Figure 3 , Figure 8 and Figure 10 As along Figure 8 The second cross section E2 of the second example configuration cut by line A-A' may include a substrate 100, a wiring structure 250, a capacitor CAP, an anti-reflective layer AR, a mesh structure GRD, and a microlens ML.

[0205] Below, references will be omitted as much as possible. Figure 9 The given description, and the main description with Figure 9 The differences.

[0206] The first depth D1 of the first well region PWa can be greater than the second depth D2 of the second well region PWb. For example, the first depth D1 can be closer to the depth of the first control node 312a than the depth of the first detection node 314a. The second depth D2 can be closer to the depth of the second detection node 314b than the depth of the second control node 312b.

[0207] When the depths of detection nodes 314a and 314b, control nodes 312a and 312b, and trap regions PWa and PWb are designed under the above conditions, the first detection node 314a, connected to the first floating diffusion region FDa with a relatively small capacitance, can provide a faster photocharge capture rate than the second detection node 314b, connected to the second floating diffusion region FDb with a relatively large capacitance through its connection to capacitor CAP. This enables more efficient photocharge capture in low-light environments.

[0208] Assuming the depth of the first well region PWa, which includes the first floating diffusion region FDa and is adjacent to the first control node 312a, increases, the first current CR1 can be relatively large when a high-level first control signal Va is applied to the first control node 212a. Assuming the image sensing device 1 operates in the first mode in a low-light environment, the photocharge capture speed through the first detection node 314a can increase as the first current CR1 increases. Furthermore, as the depth of the second well region PWb, which includes the second floating diffusion region FDb and is adjacent to the second control node 312b, decreases, the second current CR2 can be relatively small, and the photocharge generated in the photoelectric conversion region 330 can be captured to the first detection node 314a very quickly.

[0209] Compared with the first example configuration described above and the third and fourth example configurations described below, in the second example configuration, the amount of the first current CR1 is the largest, that is, the photocharge capture rate of the first detection node 314a is the highest.

[0210] Figure 11 It shows along Figure 8 The cross-sectional view of the third example configuration of the cross section cut by line A-A'.

[0211] Reference Figure 1 , Figure 2 , Figure 3 , Figure 8 and Figure 11 As along Figure 8 The third cross section E3 of the third example configuration cut by line A-A' may include a substrate 100, a wiring structure 250, a capacitor CAP, an anti-reflective layer AR, a mesh structure GRD, and a microlens ML.

[0212] Below, references will be omitted as much as possible. Figure 9 The given description, and the main description with Figure 9 The differences.

[0213] The third depth D3 of the first control node 312a can be greater than the fourth depth D4 of the second control node 312b. For example, the third depth D3 can be greater than the first depth D1 of the first well region PWa and the second depth D2 of the second well region PWb. The fourth depth D4 can be less than the first depth D1 and the second depth D2.

[0214] When the fourth depth D4 of the second control node 312b is formed to be relatively shallow, the magnitude of the second current CR2 can be relatively small when a high-level second control signal Vb is applied to the second control node 312b. Furthermore, the third depth D3 of the first control node 312a can be formed to be relatively deep, therefore, the magnitude of the first current CR1 can be relatively larger than the magnitude of the second current CR2.

[0215] The third example configuration can achieve a difference in charge collection efficiency between the first control node 312a and the second control node 312b by making the magnitudes of the first current CR1 and the second current CR2 different. Because the current is reduced compared to the second example configuration, the third example configuration may be advantageous in terms of power consumption.

[0216] Figure 12 It shows along Figure 8 The fourth example configuration of the cross-section diagram is shown by the cross-section cut by line A-A'.

[0217] Reference Figure 1 , Figure 2 , Figure 3 , Figure 8 and Figure 12 As along Figure 8 The fourth cross section E4 of the fourth example configuration cut by line A-A' may include a substrate 100, a wiring structure 250, a capacitor CAP, an anti-reflective layer AR, a mesh structure GRD, and a microlens ML.

[0218] Below, references will be omitted as much as possible. Figure 9 The given description, and the main description with Figure 9 The differences.

[0219] The fifth depth D5 of the first detection node 314a can be less than the sixth depth D6 of the second detection node 314b. For example, the fifth depth D5 can be less than the first depth D1 of the first well region PWa and the second depth D2 of the second well region PWb. For example, the sixth depth D6 can be greater than the first depth D1 and the second depth D2.

[0220] As the depth of the second detection node 314b increases, the resistance between the second control node 312b, to which the second control signal Vb is applied, and the second floating diffusion region FDb can increase; in this case, the magnitude of the second current CR2 can decrease. Because the fifth depth D5 is less than the sixth depth D6, the magnitude of the first current CR1 can be relatively greater than the magnitude of the second current CR2.

[0221] Because the magnitude of the first current CR1 is smaller compared to the second example configuration, the fourth example configuration may be advantageous in terms of power consumption. Furthermore, a sufficient amount of photocharge can be captured in high-illuminance environments because the sensitivity increases due to the increased size of the second detection node 314b, and more photocharge accumulates in the second detection node 314b, which has a relatively large capacitance.

[0222] Figure 8 The first pixel PX1 to the fourth pixel PX4 included in the pixel group PG can have along Figure 8 The line A-A' is taken from any of the cross sections of the first example configuration to the fourth example configuration.

[0223] As an example, all of the first pixels PX1 to the fourth pixels PX4 may have the cross-sectional structure configured according to the first example. As another example, some of the first pixels PX1 to the fourth pixels PX4 may have the cross-sectional structure configured according to the first example, while the other pixels of the first pixels PX1 to the fourth pixels PX4 may have the cross-sectional structure configured according to any one of the second to fourth example configurations.

[0224] Furthermore, according to the disclosed embodiments, because the central region of the pixel array 20 receives a relatively large amount of incident light due to lens shading, the central region of the pixel array 20 may include a number of pixels, each having a cross-section whose structure is advantageous in high-illuminance environments (e.g., the fourth example configuration). Because the edge regions of the pixel array 20 receive a relatively small amount of incident light due to lens shading, the edge regions of the pixel array 20 may include a relatively large number of pixels, each having a cross-section whose structure is advantageous in low-illuminance environments (e.g., the second example configuration).

[0225] Considering the position of each pixel in the pixel array or the required characteristics of each pixel, the implementation of the disclosed technology can be designed as a suitable cross-sectional structure among the first example configuration to the fourth example configuration.

[0226] Implementations of the disclosed technology can provide an image sensing device with a wider dynamic range by including multiple floating diffusion regions with different capacitances in a unit pixel.

[0227] The disclosed technology provides an image sensing device with a further increased dynamic range by maximizing the capacitance difference between multiple floating diffusion regions included in a unit pixel, thereby maximizing the conversion gain difference.

[0228] Implementations of the disclosed technology can provide an electrical signal designed to output different dynamic ranges within the same exposure time per unit pixel.

[0229] Implementations of the disclosed technology can provide an image sensing device designed to operate in a global shutter mode while maintaining a wide dynamic range. In some implementations, the term "global shutter mode" refers to an operating mode in which all pixels of the pixel array simultaneously begin and end exposure, thereby capturing image data corresponding to equal time intervals.

[0230] As described above, some embodiments of the disclosed technology provide an image sensing device employing a dual-tap pixel architecture based on indirect time-of-flight technology, suitable for high dynamic range (HDR) imaging with global shutter operation. In some embodiments, each pixel includes a first tap region and a second tap region configured to capture photocharge from a photoelectric conversion region. The first and second tap regions are associated with floating diffusion (FD) regions with different capacitances, enabling different conversion gains. In some embodiments, the second FD region is coupled to an additional capacitor connected in parallel to adjust its effective capacitance, thereby increasing the saturation charge capacity under high illumination conditions. By sequentially or selectively operating the two tap regions, the image sensing device can capture at least two images within the same exposure time at different conversion gain values ​​(differential effective capacitance values). These images are then combined to produce an HDR image while preventing motion distortion through global shutter operation.

[0231] Although several illustrative embodiments have been described, it should be understood that modifications and enhancements to the disclosed embodiments and other embodiments can be designed based on the description and / or illustration in this patent document.

[0232] Cross-references to related applications

[0233] This application claims priority and benefit to Korean Patent Application No. 10-2025-0050668, filed on April 18, 2025, the entire contents of which are incorporated herein by reference.

Claims

1. An image sensing device, the image sensing device comprising: Semiconductor substrate; as well as A pixel array, supported by the semiconductor substrate and comprising a plurality of pixels, each of the plurality of pixels including a photoelectric conversion region that generates an electrical signal in response to incident light. Each of the plurality of pixels further includes: A first tap region and a second tap region are disposed in the semiconductor substrate, wherein each of the first tap region and the second tap region captures photocharge generated by the photoelectric conversion region. A first floating diffusion region is disposed in the semiconductor substrate and connected to the first tap region. The first floating diffusion region has a first capacitance and accumulates photocharge captured by the first tap region. A second floating diffusion region is disposed in the semiconductor substrate and connected to the second tap region. The second floating diffusion region has a second capacitance and accumulates photocharge captured by the second tap region. A capacitor is electrically connected in parallel with the second floating diffusion region, and modifies the effective capacitance of the second floating diffusion region having the second capacitor.

2. The image sensing device according to claim 1, wherein, The capacitor at least partially overlaps with the first tap region or the second tap region, or overlaps with both the first tap region and the second tap region.

3. The image sensing device according to claim 1, wherein the image sensing device further comprises: A first well region surrounds the first floating diffusion region and has a first depth from a first surface of the semiconductor substrate; as well as A second well region surrounds the second floating diffusion region and has a second depth from the first surface of the semiconductor substrate.

4. The image sensing device according to claim 3, wherein, The first depth is greater than the second depth.

5. The image sensing device according to claim 3, wherein, The first tap region includes a first control node having a third depth from the first surface of the semiconductor substrate, and The second tap region includes a second control node having a fourth depth from the first surface of the semiconductor substrate.

6. The image sensing device according to claim 5, wherein, The third depth is greater than the fourth depth.

7. The image sensing device according to claim 5, wherein, The first tap region further includes a first detection node having a fifth depth from the first surface of the semiconductor substrate and capturing the photocharge. The second tap region further includes a second detection node having a sixth depth from the first surface of the semiconductor substrate and capturing the photocharge.

8. The image sensing device according to claim 7, wherein, The fifth depth is less than the sixth depth.

9. The image sensing device according to claim 7, wherein, Each of the first floating diffusion region, the second floating diffusion region, the first detection node, and the second detection node includes impurities of a first conductivity type, and Each of the first well region, the second well region, the first control node, and the second control node includes an impurity of a second conductivity type.

10. The image sensing device according to claim 1, wherein, The first tap region operates in a first mode based on the incident light illuminance being less than a first threshold, and The second tap region operates in a second mode based on the incident light illuminance being greater than a second threshold, wherein the second threshold is greater than or equal to the first threshold.

11. The image sensing device according to claim 10, wherein, An electrical signal corresponding to the photocharge accumulated in the first floating diffusion region is generated in response to the operation of the first tap region, and The electrical signal corresponding to the photocharge accumulated in the second floating diffusion region is generated in response to the operation of the second tap region.

12. The image sensing device according to claim 10, wherein, Both the first tap region and the second tap region operate in a third mode between the first threshold and the second threshold, depending on the illuminance of the incident light.

13. The image sensing device according to claim 12, wherein, The first tap region and the second tap region operate alternately in the third mode.

14. The image sensing device according to claim 1, wherein, The pixel array operates in global shutter mode.

15. An image sensing device, the image sensing device comprising: A substrate, comprising: a photoelectric conversion region that generates photocharge in response to incident light; a first tap region; and a second tap region, wherein each of the first tap region and the second tap region captures the photocharge; and A capacitor that is spaced apart from the first surface of the substrate and perpendicularly overlaps the second tap region.

16. The image sensing device according to claim 15, wherein, The capacitor overlaps perpendicularly with the first tap region.

17. The image sensing device according to claim 15, wherein, The substrate further includes: A first floating diffusion region is electrically connected to the first tap region via a first transmission transistor; A first well region surrounds the first floating diffusion region and has a first depth from the first surface of the substrate; A second floating diffusion region, which is electrically connected to the second tap region via a second transfer transistor; and A second well region surrounds the second floating diffusion region and has a second depth from the first surface of the substrate. The capacitor and the second floating diffusion region are connected in parallel.

18. The image sensing device according to claim 17, wherein, The first depth is greater than the second depth.

19. The image sensing device according to claim 17, wherein, The first tap region includes a first control node having a third depth from the first surface of the substrate, and The second tap region includes a second control node having a fourth depth from the first surface of the substrate.

20. The image sensing device according to claim 19, wherein, The third depth is greater than the fourth depth.

21. The image sensing device according to claim 19, wherein, The first tap region further includes a first detection node having a fifth depth from the first surface of the substrate, and The second tap region further includes a second detection node having a sixth depth from the first surface of the substrate.

22. The image sensing device according to claim 21, wherein, The fifth depth is less than the sixth depth.

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