Radio voltage synchronization method, system and computer device

Abstract

The application relates to a wireless voltage synchronization method, system and computer device. The method comprises the following steps: receiving a network signal from a node, registering the node into a master node, after completing clock tree self-checking calibration and coarse synchronization, performing bidirectional ranging with the master node through micro-power wireless, and obtaining ranging observation values; inputting the ranging observation values into a whole-network clock state model to obtain clock offset and frequency drift rate of the slave node relative to the master node; performing linear mapping based on the clock offset and the frequency drift rate to obtain an ADC sampling clock correction amount; receiving a sampling time table based on the master node clock, and recording time stamps in the time table; performing time interpolation resampling and environment drift compensation based on the time table, the time stamps and the ADC sampling clock correction amount to obtain synchronous voltage data aligned with the master node clock; and transmitting the synchronous voltage data to the master node. The method can realize microsecond-level high-precision synchronization without external reference sources.

Description

Technical Field

[0001] This application relates to the field of synchronous sampling technology, and in particular to a wireless voltage synchronization method, apparatus, computer equipment, computer-readable storage medium, and computer program product. Background Technology

[0002] With the development of synchronous sampling technology, wireless synchronous acquisition technology has emerged. This technology relies on wireless communication links to replace traditional wired synchronous cables, thus eliminating the limitations of physical wiring. It features flexible deployment and adaptability to distributed mobile measurement point scenarios. Its conventional processing method relies on satellite time synchronization or ordinary low-power wireless channels to issue synchronization commands. It adopts a separate workflow of first completing the clock alignment of the entire network and then uniformly triggering ADC sampling to achieve multi-point distributed voltage synchronous acquisition.

[0003] However, current traditional methods have limitations in meeting the requirements of high-precision voltage acquisition scenarios. Summary of the Invention

[0004] Therefore, it is necessary to provide a wireless voltage synchronization method, system, computer device, computer-readable storage medium, and computer program product that can achieve microsecond-level high-precision synchronization to address the above-mentioned technical problems.

[0005] Firstly, this application provides a wireless voltage synchronization method for a slave node in a distributed network. The distributed network includes a master node and at least one slave node. The slave node's clock uses the master node's clock as the network's time reference. The master node and slave node communicate via low-power wireless and use the same physical layer radio frequency resources during communication. Based on a time-division multiplexing mechanism, a single frame period is divided into synchronization time slots, command time slots, and data time slots. The method includes:

[0006] Receive network access signals through synchronization time slots and register with the master node to join the network;

[0007] After completing the clock tree self-test calibration, coarse synchronization is achieved with the master node via low-power wireless.

[0008] The system uses low-power wireless to perform bidirectional ranging with the master node and obtains ranging observation values.

[0009] The ranging observations are input into the network clock state model, and the model is solved using Kalman filtering to obtain the clock offset and frequency drift rate of the slave node relative to the master node.

[0010] The ADC sampling clock correction is obtained by linearly mapping the clock offset to the frequency drift rate.

[0011] The sampling schedule based on the master node clock is received through the instruction time slot, and the timestamps in the schedule are recorded.

[0012] Based on the schedule, timestamp, and ADC sampling clock correction, time interpolation resampling and environmental drift compensation are performed to obtain synchronous voltage data aligned with the master node clock as the reference.

[0013] Synchronous voltage data is transmitted to the master node via data time slots.

[0014] In one embodiment, bidirectional ranging is performed with the master node via low-power wireless to obtain ranging observations, including:

[0015] The second time interval receives the ranging signal sent by the master node at the first time interval.

[0016] The system replies to the master node at the third moment so that the master node can receive it at the fourth moment.

[0017] Based on the time interval between the first and fourth moments, calculate the clock offset of the slave node relative to the master node and the signal propagation time between the master node and the slave node;

[0018] Clock offset and signal propagation time are used as ranging observations.

[0019] In one embodiment, the process of constructing the network-wide clock state model includes:

[0020] The master node is used as the reference node, and the clock offset and frequency drift rate of the master node are set to 0.

[0021] The clock offset and frequency drift rate of the slave node relative to the master node are used to construct the state vector of the slave node;

[0022] State equations are constructed based on the physical characteristics of clock drift. These state equations are used to describe the changes in the state vectors of slave nodes at different times.

[0023] The observation equation is constructed based on the mapping relationship between the ranging observations and the state vector;

[0024] A network-wide clock state model is constructed based on state vectors, state equations, and observation equations.

[0025] In one embodiment, the ADC sampling clock correction is obtained by performing a linear mapping between clock skew and frequency drift rate, including:

[0026] Based on the real-time temperature data and the calibrated temperature-clock drift curve, the additional clock drift caused by the current temperature is calculated.

[0027] Add the additional clock drift to the clock offset to obtain the total clock offset;

[0028] The ADC sampling clock correction is obtained by linearly mapping the total clock offset and frequency drift rate.

[0029] In one embodiment, the method further includes:

[0030] Extract the effective voltage value, harmonic components, or event detection results from the synchronous voltage data;

[0031] The extracted content is compressed into a feature vector;

[0032] If the synchronization voltage data does not exceed the preset abnormal threshold, the feature vector is uploaded to the master node through the data time slot; if it exceeds the abnormal threshold, the feature vector and the synchronization voltage data segment at the abnormal moment are uploaded to the master node through the data time slot.

[0033] In one embodiment, the method further includes:

[0034] When a new slave node requests to join the network, it receives the time slots dynamically allocated by the master node and the initial synchronization parameters through the synchronization time slots to support hot-plugging of nodes.

[0035] In the event of a master node going offline abnormally, a new master node will be automatically elected through a preset election mechanism to maintain the continuous operation of the network.

[0036] Secondly, this application provides a wireless voltage synchronization method for a master node in a distributed network. The distributed network includes one master node and at least one slave node. The slave node's clock uses the master node's clock as the network's time reference. The master node and slave nodes communicate via low-power wireless and use the same physical layer radio frequency resources during communication. Based on a time-division multiplexing mechanism, a single frame period is divided into synchronization time slots, command time slots, and data time slots. The method includes:

[0037] The network access signal is broadcast through synchronous time slots to receive registration and network access signals from slave nodes;

[0038] After completing the clock tree self-test calibration, coarse synchronization is achieved with the slave node via low-power wireless.

[0039] The ranging observation value is obtained by bidirectional ranging with the slave node through low-power wireless;

[0040] The slave node inputs the ranging observation value into the network clock state model, and Kalman filtering is used to solve the model to obtain the clock offset and frequency drift rate of the slave node relative to the master node; based on the clock offset and frequency drift rate, a linear mapping is performed to obtain the ADC sampling clock correction amount of the slave node;

[0041] A sampling schedule based on the master node clock is issued via instruction time slots;

[0042] The system receives synchronous voltage data uploaded from the node via data time slots.

[0043] In one embodiment, a sampling schedule based on the master node clock is issued via instruction time slots, including:

[0044] Based on the ADC sampling clock correction of each slave node, calculate the absolute sampling time of each slave node in the future multiple sampling periods;

[0045] The absolute sampling time is encapsulated into a sampling time schedule and sent to the corresponding slave node through the instruction time slot.

[0046] Thirdly, this application also provides a wireless voltage synchronization system, comprising a master node and at least one slave node, wherein the master node and slave node communicate via low-power wireless communication and use the same physical layer radio frequency resources during communication, and divide a single frame period into synchronization time slots, command time slots, and data time slots based on a time-division multiplexing mechanism; including:

[0047] The master node broadcasts the network access signal using the synchronization time slot, and the slave nodes register to join the network; after completing the clock tree self-test calibration, the master node and slave nodes complete coarse synchronization via low-power wireless.

[0048] The master node and slave node acquire ranging observations through low-power wireless bidirectional ranging;

[0049] The slave node inputs the ranging observation value into the whole network clock state model, and uses Kalman filtering to solve the model to obtain the clock offset and frequency drift rate of the slave node relative to the master node;

[0050] The ADC sampling clock correction is obtained by linearly mapping the node based on clock offset and frequency drift rate;

[0051] The master node issues a sampling schedule based on the master node's clock through a command time slot, and the slave nodes record the timestamps in the schedule.

[0052] The slave node performs time interpolation resampling and environmental drift compensation based on the schedule, timestamp, and ADC sampling clock correction to obtain synchronous voltage data aligned with the master node clock. The synchronous voltage data is then transmitted to the master node through data time slots.

[0053] Fourthly, this application also provides a computer device including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps performed by any possible implementation of any of the first to second aspects.

[0054] Fifthly, this application also provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps performed by any possible implementation of any of the first to second aspects.

[0055] Sixthly, this application also provides a computer program product, including a computer program that, when executed by a processor, performs the steps of any possible implementation of any of the first to second aspects.

[0056] The aforementioned wireless voltage synchronization method, system, computer equipment, computer-readable storage medium, and computer program product involve the following steps: A slave node receives a network access signal through a synchronization time slot and registers with the master node. After completing clock tree self-calibration, it performs coarse synchronization with the master node via low-power wireless. It then performs bidirectional ranging with the master node via low-power wireless to obtain ranging observations. These ranging observations are input into a network-wide clock state model, and a Kalman filter is used to solve the model, yielding the slave node's clock offset and frequency drift rate relative to the master node. A linear mapping is performed based on the clock offset and frequency drift rate to obtain the ADC sampling clock correction. A sampling schedule based on the master node's clock is received through a command time slot, and timestamps are recorded in the schedule. Based on the schedule, timestamps, and the ADC sampling clock correction, time interpolation resampling and environmental drift compensation are performed to obtain synchronization voltage data aligned with the master node's clock. Finally, the synchronization voltage data is transmitted to the master node through a data time slot. The slave nodes use the master node's clock as the network-wide time reference. Through low-power wireless communication, they achieve coarse synchronization and bidirectional ranging with the master node. Utilizing a network-wide clock state model combined with Kalman filtering, they accurately estimate their own clock offset and frequency drift rate, thereby obtaining the ADC sampling clock correction. Based on the sampling schedule issued by the master node, they autonomously trigger sampling locally, effectively eliminating the uncertainty of command transmission delay and achieving microsecond-level high-precision alignment between the distributed slave nodes and the master node's clock reference. Simultaneously, by dividing the synchronization time slot, command time slot, and data time slot within a single low-power wireless physical layer using time-division multiplexing, they achieve isolated coexistence of time-frequency synchronization, command issuance, and data upload within the same wireless link, avoiding mutual interference between links. Through time interpolation resampling and environmental drift compensation, the impact of environmental changes on synchronization accuracy is further offset, ensuring that slave nodes can still output high-precision synchronized voltage data aligned with the master node's clock even without external reference sources such as GPS or synchronization cables. This effectively reduces system deployment costs and complexity, and improves the synchronization accuracy, anti-interference capability, and environmental adaptability of distributed voltage acquisition. Attached Figure Description

[0057] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0058] Figure 1 This is a diagram illustrating the application environment of a wireless voltage synchronization method in one embodiment.

[0059] Figure 2 This is a schematic diagram of the steps of a wireless voltage synchronization method in one embodiment;

[0060] Figure 3 This is a flowchart illustrating the steps of a wireless voltage synchronization method in another embodiment;

[0061] Figure 4 Here is a block diagram of the structure of a node in one embodiment;

[0062] Figure 5 Here is a structural block diagram of the main node in one embodiment;

[0063] Figure 6 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0064] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0065] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0066] The wireless voltage synchronization method provided in this application embodiment can be applied to, for example... Figure 1The application environment is shown. In this environment, slave node 102 and master node 104 communicate via a low-power wireless network. A data storage system is used to store the synchronization voltage data received by master node 104; it can be integrated on the master node or deployed independently in the cloud or other network servers. The slave node's clock uses the master node's clock as the network-wide time reference. Master node 104 and slave node 102 use the same physical layer RF resources during communication, dividing a single frame period into synchronization time slots, command time slots, and data time slots based on a time-division multiplexing mechanism. The slave node receives the network entry signal broadcast by the master node through the synchronization time slot and registers to join the network. After completing the clock tree self-test calibration, it completes coarse synchronization with the master node. The slave node performs bidirectional ranging with the master node through low-power wireless to obtain ranging observation values. The ranging observation values ​​are input into the network clock state model, and Kalman filtering is used to solve the model to obtain its own clock offset and frequency drift rate relative to the master node. Based on the clock offset and frequency drift rate, a linear mapping is performed to obtain the ADC sampling clock correction amount. The slave node receives the sampling schedule based on the master node's clock through the command time slot, records the timestamps in the schedule, and performs time interpolation resampling and environmental drift compensation based on the schedule, timestamps, and ADC sampling clock correction amount to obtain synchronization voltage data aligned with the master node's clock. The synchronization voltage data is then uploaded to the master node through the data time slot.

[0067] Among them, slave nodes can be, but are not limited to, voltage acquisition modules, battery management units, smart grid monitoring terminals, industrial data acquisition equipment, or IoT devices; master nodes can be gateway devices, data aggregators, or edge computing servers.

[0068] In one exemplary embodiment, such as Figure 2 As shown, a wireless voltage synchronization method is provided, which can be applied to... Figure 1 Taking node 102 as an example, the explanation includes steps 202 to 216. Wherein:

[0069] Step 202: Receive the network access signal through the synchronization time slot and register with the master node to join the network;

[0070] The network entry signal refers to the beacon frame broadcast by the master node within the synchronization time slot to identify the network's presence and basic configuration information. Slave nodes receive this signal to detect the network's existence and obtain the initial configuration parameters required for network entry. The synchronization time slot is a pre-allocated time segment in the low-power wireless physical layer, specifically used by the master and slave nodes for transmitting time-frequency synchronization-related signals via time-division multiplexing. The synchronization time slot is dedicated to bidirectional ranging to achieve clock synchronization and the broadcasting and reception of the network entry signal.

[0071] For example, the master node periodically broadcasts a network access signal within a synchronization time slot according to a preset period. The network access signal carries a network identifier, synchronization period, time slot configuration parameters, and registration window indication information. The slave node continuously listens to the synchronization time slot when it is not in a network access state. When it receives the network access signal, it extracts the network identifier and determines whether it matches the preset network. If it matches, it sends a registration request frame to the master node. The registration request frame carries the slave node's device identifier and / or hardware fingerprint information. After receiving the registration request frame, the master node authenticates the slave node. After successful authentication, it assigns a unique identifier within the network to the slave node and returns a registration confirmation frame through the synchronization time slot. After receiving the registration confirmation frame, the slave node completes the registration and network access.

[0072] Step 204: After completing the clock tree self-test calibration, coarse synchronization is completed with the master node via low-power wireless.

[0073] Coarse synchronization refers to the process by which master and slave nodes exchange time information via low-power wireless communication within a synchronization time slot, reducing the initial clock deviation from the millisecond / second level to the microsecond level.

[0074] For example, after each slave node completes the clock tree self-test calibration, it stores the calibrated clock path delay parameters in its local register and sends a coarse synchronization request to the master node. The master node responds to the coarse synchronization request within the synchronization time slot, sends an access synchronization signal, and carries the master node's local transmission time. The slave node receives the access synchronization signal and records its local reception time. It calculates the initial time deviation based on the master node's transmission time and the local reception time, and adjusts the starting position of the local time slot window according to the initial time deviation so that the local time slot window is aligned with the master node's time slot boundary, thus completing the coarse synchronization.

[0075] Step 206: Perform bidirectional ranging with the master node via low-power wireless to obtain ranging observation values;

[0076] Two-way ranging refers to a method of measuring the signal propagation time between master and slave nodes by interactively sending and receiving ranging signals, and calculating the clock offset of the slave node relative to the master node based on the round-trip time of the signals. Two-way ranging records the sending and receiving times of the signals to compensate for measurement errors caused by signal propagation time, thereby obtaining accurate clock offset observations.

[0077] For example, the master node at the first moment Send ranging signal to slave node, slave node at second time Receive ranging signal; from the node at the third time The master node responds with the ranging signal at the fourth time. Receive ranging signal; assume signal propagation time is... The clock offset of the slave node relative to the master node is Then the following relationship exists: , Solving the simultaneous equations yields... , ; clock offset from node and signal propagation time As a distance measurement observation.

[0078] Step 208: Input the ranging observation values ​​into the whole network clock state model, and use Kalman filtering to solve the model to obtain the clock offset and frequency drift rate of the slave node relative to the master node;

[0079] The network-wide clock state model is a mathematical model representing the dynamic clock relationship between all nodes and the master node in the network. It is used to quantify and predict clock deviations, using bidirectional ranging observations as input and the calculated ADC sampling clock correction as output. Clock skew refers to the time deviation between the slave node's local clock and the master node's clock, i.e., the difference between the slave node's local time and the master node's reference time. Frequency drift rate refers to the rate of change of the slave node's local clock frequency relative to the master node's clock frequency, i.e., the rate of change of clock skew per unit time, reflecting the deviation between the slave node's crystal oscillator frequency and the master node's crystal oscillator frequency.

[0080] For example, a network-wide clock state model is pre-constructed: taking the master node as the reference node, the clock offset of the master node is set to 0 and the frequency drift rate is 0; the clock offset and frequency drift rate of the slave node relative to the master node are used to construct the state vector of the slave node; a state equation is constructed based on the physical characteristics of clock drift, and the state equation includes a state transition matrix and process noise, which are used to describe the change relationship of the state vector at different times; an observation equation is constructed based on the mapping relationship between the ranging observation value and the state vector, and the observation equation includes an observation matrix and observation noise, which are used to describe the mapping relationship between the ranging observation value and the state vector.

[0081] Based on the state equation and observation equation, the acquired ranging observations are used as inputs to the observation equation. A Kalman filter algorithm is employed to recursively estimate the state vector. The recursive process of the Kalman filter includes: predicting the prior state estimate and its covariance at the current time step based on the previous state estimate and state transition matrix; inputting the current ranging observation into the observation equation to calculate the observation residual; calculating the Kalman gain based on the observation matrix and observation noise covariance; correcting the prior state estimate using the Kalman gain to obtain the posterior state estimate at the current time step as the optimal estimate; and updating the covariance matrix to prepare for the recursion at the next time step. Through this recursive process, the Kalman filter can fuse historical state information and current ranging observation information, recursively outputting the optimal estimates of the clock offset and frequency drift rate of the slave node relative to the master node, even under the interference of ranging noise and process noise.

[0082] Step 210: Based on the clock offset and frequency drift rate, a linear mapping is performed to obtain the ADC sampling clock correction amount;

[0083] Linear mapping refers to the process of converting the clock offset and frequency drift rate output from the Kalman filter into an ADC sampling clock time correction value by combining them according to a preset linear relationship. Specifically, the sampling clock correction value equals the current clock offset plus the product of the frequency drift rate and time, reflecting the cumulative effect of clock deviation over time. The ADC sampling clock correction value refers to the time adjustment value that the slave node needs to make to compensate for the deviation between its own clock and the master node's clock. It is used to map the actual sampling time from the slave node's local clock domain to the master node's clock domain during time interpolation resampling.

[0084] For example, the optimal estimate of the clock offset of the slave node relative to the master node and the optimal estimate of the frequency drift rate output by the Kalman filter are substituted into a preset linear mapping formula to calculate the time correction of the ADC sampling clock.

[0085] Step 212: Receive the sampling time schedule based on the master node clock through the instruction time slot and record the timestamps in the time schedule;

[0086] In this sampling schedule, each sampling moment is calibrated based on the master node's clock, and the slave nodes trigger ADC sampling at the specified absolute time according to this schedule. The timestamp refers to the local time of distribution or the local time marker corresponding to each sampling point recorded by the slave node after receiving the sampling schedule.

[0087] For example, the master node calculates the absolute sampling time of each slave node within multiple future sampling periods based on the ADC sampling clock correction of each slave node. This absolute sampling time, referenced to the master node's clock, is encapsulated into a sampling schedule and sent to the corresponding slave nodes via instruction slots. The sampling schedule includes the slave node's node identifier, the absolute sampling time for each sampling period, and the sampling period number. The slave node receives the sampling schedule from the master node via instruction slots, parses the absolute sampling time corresponding to each sampling point in the schedule, and records the local time of receiving the schedule as a timestamp. The slave node stores the correspondence between each absolute sampling time in the sampling schedule and its locally recorded receiving timestamp to guide subsequent autonomously triggered sampling and time interpolation resampling. The slave node then autonomously triggers ADC sampling based on the absolute sampling time specified in the sampling schedule, rather than waiting for real-time trigger instructions from the master node, thereby eliminating the uncertainty of trigger time caused by instruction transmission delays and network congestion. The slave node records the local timestamp corresponding to each actual sampling time; this timestamp, together with the absolute sampling time in the sampling schedule, constitutes the data basis for time interpolation resampling.

[0088] Step 214: Based on the time schedule, timestamp, and ADC sampling clock correction, perform time interpolation resampling and environmental drift compensation to obtain synchronous voltage data aligned with the master node clock as the reference.

[0089] Among them, time interpolation resampling is a data processing operation that uses the target time given by the master node's timetable to perform numerical interpolation on the discrete original voltage sampling points of the slave nodes, converting the local asynchronous sampling sequences of each slave node into equivalent voltage values ​​under the unified standard sampling time of the master node; environmental drift compensation refers to the process by which the slave nodes correct the original acquired data on the time axis based on the ADC sampling clock correction amount, mapping the actual sampling time to the expected sampling time of the master node's clock reference, so as to offset the sampling time deviation caused by factors such as clock frequency drift and changes in ambient temperature, and align the voltage data with the master node's clock reference on the time axis.

[0090] For example, the slave node uses the absolute sampling time of each sampling point in the sampling schedule as the target time, the locally recorded timestamp as the reference time, and the ADC sampling clock correction amount as the deviation correction amount to interpolate and resample the original collected voltage data, calculate the voltage value corresponding to each target time, and obtain synchronized voltage data aligned with the master node clock as the reference. Environmental drift compensation is completed synchronously by using the ADC sampling clock correction amount as the deviation correction amount in the interpolation and resampling. The overall offset correction of the sampling time reflects the compensation for environmental drift.

[0091] Step 216: Transmit the synchronization voltage data to the master node through the data time slot.

[0092] Among them, synchronous voltage data refers to voltage acquisition data obtained from the node after time interpolation resampling and environmental drift compensation, and aligned with the master node clock.

[0093] For example, the slave node encapsulates the synchronization voltage data into a data upload frame according to a preset frame format in the data time slots pre-allocated in the time-division multiplexing mechanism, and sends it to the master node within the data time slot; the master node receives the data frames uploaded by each slave node within the data time slot, parses and stores the synchronization voltage data of each slave node.

[0094] In the aforementioned wireless voltage synchronization method, the slave node receives the network access signal through the synchronization time slot and registers with the master node. After completing the clock tree self-test calibration, it performs coarse synchronization with the master node via low-power wireless. It then performs bidirectional ranging with the master node via low-power wireless to obtain ranging observations. The ranging observations are input into the network-wide clock state model, and Kalman filtering is used to solve the model to obtain the clock offset and frequency drift rate of the slave node relative to the master node. A linear mapping is performed based on the clock offset and frequency drift rate to obtain the ADC sampling clock correction. The slave node receives a sampling schedule based on the master node's clock through the command time slot and records the timestamps in the schedule. Based on the schedule, timestamps, and ADC sampling clock correction, time interpolation resampling and environmental drift compensation are performed to obtain synchronization voltage data aligned with the master node's clock. The synchronization voltage data is then transmitted to the master node through the data time slot. The slave nodes use the master node's clock as the network-wide time reference. Through low-power wireless communication, they achieve coarse synchronization and bidirectional ranging with the master node. Utilizing a network-wide clock state model combined with Kalman filtering, they accurately estimate their own clock offset and frequency drift rate, thereby obtaining the ADC sampling clock correction. Based on the sampling schedule issued by the master node, they autonomously trigger sampling locally, effectively eliminating the uncertainty of command transmission delay and achieving microsecond-level high-precision alignment between the distributed slave nodes and the master node's clock reference. Simultaneously, by dividing the synchronization time slot, command time slot, and data time slot within a single low-power wireless physical layer using time-division multiplexing, they achieve isolated coexistence of time-frequency synchronization, command issuance, and data upload within the same wireless link, avoiding mutual interference between links. Through time interpolation resampling and environmental drift compensation, the impact of environmental changes on synchronization accuracy is further offset, ensuring that slave nodes can still output high-precision synchronized voltage data aligned with the master node's clock even without external reference sources such as GPS or synchronization cables. This effectively reduces system deployment costs and complexity, and improves the synchronization accuracy, anti-interference capability, and environmental adaptability of distributed voltage acquisition.

[0095] In one embodiment, bidirectional ranging is performed with the master node via low-power wireless to obtain ranging observations, including:

[0096] The second moment receives the ranging signal sent by the master node at the first moment.

[0097] The system replies to the master node at the third time, so that the master node can receive it at the fourth time.

[0098] Based on the time interval between the first and fourth moments, calculate the clock offset of the slave node relative to the master node and the signal propagation time between the master node and the slave node;

[0099] Clock offset and signal propagation time are used as ranging observations.

[0100] Specifically, the master node at the first moment Send ranging signal to slave node, slave node at second time Receive ranging signal; from the node at the third time The master node responds with the ranging signal at the fourth time. Receive ranging signal; assume signal propagation time is... The clock offset of the slave node relative to the master node is Then the following relationship exists: , Solving the simultaneous equations yields... , ; clock offset from node and signal propagation time As a distance measurement observation.

[0101] In the above embodiments, the slave node obtains ranging observations through bidirectional ranging. By using the round-trip time difference of the ranging signals between the master and slave nodes, the clock offset and signal propagation time are calculated. This can offset the impact of the wireless signal propagation delay in the air on clock measurement, effectively eliminate the measurement error caused by the propagation delay, and obtain accurate clock offset observations, providing accurate observation data input for subsequent Kalman filter modeling. At the same time, this bidirectional ranging process is completed within the synchronization time slot, which will not conflict with the command issuance and data upload, ensuring the reliability and real-time performance of the ranging process.

[0102] In one embodiment, the process of constructing the network-wide clock state model includes:

[0103] The master node is used as the reference node, and the clock offset and frequency drift rate of the master node are set to 0.

[0104] The clock offset and frequency drift rate of the slave node relative to the master node are used to construct the state vector of the slave node;

[0105] State equations are constructed based on the physical characteristics of clock drift. These state equations are used to describe the relationship between the state vectors of slave nodes at different times.

[0106] The observation equation is constructed based on the mapping relationship between the ranging observations and the state vector;

[0107] A network-wide clock state model is constructed based on state vectors, state equations, and observation equations.

[0108] Specifically, the slave nodes pre-build a network-wide clock state model: using the master node as the reference node, the master node's clock offset is set to 0 and its frequency drift rate to 0; the slave nodes... Clock offset relative to the master node and frequency drift rate Together we build from nodes The state vector is:

[0109]

[0110] in, This represents the discrete time index of the Kalman filter recursion. For the first At discrete moments from node Clock offset relative to the master node, Let be the frequency drift rate of slave node i relative to master node at time k.

[0111] Based on the physical characteristics of clock drift, the state equation is constructed as follows:

[0112]

[0113] in, Here is the state transition matrix. For process noise, the state equation is used to describe the relationship between the changes of the state vector at different times.

[0114] The observation equation is constructed based on the mapping relationship between the ranging observations and the state vector:

[0115]

[0116] in, For the observation matrix, To account for observation noise, the observation equation is used to describe the distance measurement observations. With state vector Mapping relationship between them; process noise and observation noise All were obtained through prior experimental measurements.

[0117] In the above embodiments, by constructing a network-wide clock state model that includes state equations and observation equations, the clock offset and frequency drift rate between master and slave nodes are quantized into state vectors, providing a mathematical model framework for recursive estimation of Kalman filtering. The state equations describe the change of clock state over time, and the observation equations establish the mapping relationship between ranging observations and state variables. Together, they constitute the complete mathematical basis for recursive estimation of Kalman filtering, enabling slave nodes to make optimal estimates of their own clock state using bidirectional ranging observations. At the same time, by taking the master node as the reference node and setting the clock offset and frequency drift rate of the master node to 0, the model complexity is simplified, and the clock states of all slave nodes are uniformly referenced to the same reference.

[0118] In one embodiment, the ADC sampling clock correction is obtained by performing a linear mapping between clock skew and frequency drift rate, including:

[0119] Based on the real-time temperature data and the calibrated temperature-clock drift curve, the additional clock drift caused by the current temperature is calculated.

[0120] Add the additional clock drift to the clock offset to obtain the total clock offset;

[0121] The ADC sampling clock correction is obtained by performing a linear mapping based on the total clock offset and frequency drift rate.

[0122] Specifically, the slave node calculates the additional clock drift caused by the current temperature based on the real-time temperature data collected by the temperature acquisition unit and the temperature and clock drift calibration curve determined during pre-shipment testing. The slave node then adds the additional clock drift to the optimal estimate of the clock offset output by the Kalman filter to obtain the total clock offset including the temperature effect.

[0123]

[0124] in, This is the temperature drift coefficient. As the reference offset, For the first Real-time temperature (in degrees Celsius) at discrete moments. and These are the parameters in the temperature and clock drift calibration curves tested before the product leaves the factory.

[0125] The formula for the temperature versus clock drift calibration curve is as follows: The time correction for the ADC sampling clock, calculated from the node based on the state variable estimates and the linear mapping relationship, is as follows:

[0126]

[0127] in, Indicates the first At discrete moments from node ADC sampling clock correction amount Indicates from the initial time to the nth time. The total time length (in seconds) of each discrete moment. This indicates the frequency drift from the initial time to the... Additional offset (in seconds) accumulated over discrete time intervals.

[0128] In the above embodiments, the total clock offset is obtained by adding the additional clock drift to the clock offset of the Kalman filter output. This allows the calculation of the ADC sampling clock correction to simultaneously consider the basic clock deviation between master and slave nodes and the drift effect of ambient temperature changes on the crystal oscillator frequency. By using the total clock offset and frequency drift rate to calculate the correction, the additional clock drift introduced by temperature changes can be effectively compensated. This solves the problem in traditional synchronization schemes where temperature changes cause crystal oscillator frequency drift, thus affecting synchronization accuracy. It enables slave nodes to maintain high-precision time alignment over a wide temperature range, improving the adaptability and long-term operational stability of the wireless voltage synchronization method under different ambient temperature conditions.

[0129] In one embodiment, the method further includes:

[0130] Extract the effective voltage value, harmonic components, or event detection results from the synchronous voltage data;

[0131] The extracted content is compressed into a feature vector;

[0132] If the synchronization voltage data does not exceed the preset abnormal threshold, the feature vector is uploaded to the master node through the data time slot; if it exceeds the abnormal threshold, the feature vector and the synchronization voltage data segment at the abnormal moment are uploaded to the master node through the data time slot.

[0133] Specifically, the node extracts the effective voltage value, harmonic components, and / or event detection results from the synchronization voltage data; compresses the extracted content into a feature vector; if the synchronization voltage data does not exceed the preset abnormal threshold, the feature vector is uploaded to the master node through the data time slot; if it exceeds the abnormal threshold, the feature vector and the synchronization voltage data fragment at the abnormal moment are uploaded to the master node through the data time slot.

[0134] In the above embodiments, the slave node performs feature extraction and compression on the synchronization voltage data locally, uploading only the feature vector instead of all the original data. This significantly reduces the amount of wireless data transmission and the bandwidth occupied by the data time slots, enabling the system to support more slave nodes under the same wireless resources and improving network scalability. At the same time, by judging the abnormal threshold, the slave node only uploads the compressed feature vector in the normal state to save bandwidth, and additionally uploads the data fragments at the abnormal moment in the abnormal state to retain fault information. This ensures efficient transmission of normal data and avoids the loss of abnormal information, which facilitates fault location and in-depth analysis by the master node, achieving a balance between data transmission efficiency and fault diagnosis information integrity.

[0135] In one embodiment, the method further includes:

[0136] When a new slave node requests to join the network, it receives the time slots dynamically allocated by the master node and the initial synchronization parameters through the synchronization time slots to support hot-plugging of nodes.

[0137] In the event of a master node going offline abnormally, a new master node will be automatically elected through a preset election mechanism to maintain the continuous operation of the network.

[0138] Specifically, when a new slave node requests to join the network, the master node dynamically allocates time slots and initial synchronization parameters, which the slave node receives through the synchronization time slots to support hot-swapping of nodes; when the master node goes offline abnormally, the slave nodes automatically elect a new master node through a preset election mechanism to maintain the continuous operation of the network.

[0139] In the above embodiments, by dynamically allocating time slots and initial synchronization parameters when a new slave node joins the network, the distributed network supports hot-swapping of nodes. New nodes can automatically join without restarting the network, improving the flexibility and scalability of system deployment. This is particularly suitable for distributed acquisition scenarios where the number of nodes changes dynamically. At the same time, by automatically electing a new master node when the master node goes offline abnormally, network paralysis caused by single point of failure is avoided, giving the network self-healing capabilities, ensuring the continuity of voltage synchronization acquisition tasks, and improving the reliability and robustness of the system.

[0140] In one exemplary embodiment, such as Figure 3 As shown, a wireless voltage synchronization method is provided, which can be applied to... Figure 1 Taking the master node 104 as an example, the explanation includes the following steps 302 to 312. Wherein:

[0141] Step 302: Broadcast the network access signal through the synchronization time slot to receive the registration and network access from the slave node;

[0142] For example, the master node periodically broadcasts a network access signal within a synchronization time slot according to a preset period. The network access signal carries a network identifier, synchronization period, time slot configuration parameters, and registration window indication information. The slave node continuously listens to the synchronization time slot when it is not in a network access state. When it receives the network access signal, it extracts the network identifier and determines whether it matches the preset network. If it matches, it sends a registration request frame to the master node. The registration request frame carries the slave node's device identifier and / or hardware fingerprint information. After receiving the registration request frame, the master node authenticates the slave node. After successful authentication, it assigns a unique identifier within the network to the slave node and returns a registration confirmation frame through the synchronization time slot. After receiving the registration confirmation frame, the slave node completes the registration and network access.

[0143] Step 304: After completing the clock tree self-test calibration, coarse synchronization is completed with the slave node via low-power wireless.

[0144] For example, after each slave node completes the clock tree self-test calibration, it stores the calibrated clock path delay parameters in its local register and sends a coarse synchronization request to the master node. The master node responds to the coarse synchronization request within the synchronization time slot, sends an access synchronization signal, and carries the master node's local transmission time. The slave node receives the access synchronization signal and records its local reception time. It calculates the initial time deviation based on the master node's transmission time and the local reception time, and adjusts the starting position of the local time slot window according to the initial time deviation so that the local time slot window is aligned with the master node's time slot boundary, thus completing the coarse synchronization.

[0145] Step 306: Perform bidirectional ranging with the slave node via low-power wireless to obtain ranging observation values;

[0146] For example, the master node at the first moment Send ranging signal to slave node, slave node at second time Receive ranging signal; from the node at the third time The master node responds with the ranging signal at the fourth time. Receive ranging signal; assume signal propagation time is... The clock offset of the slave node relative to the master node is Then the following relationship exists: , Solving the simultaneous equations yields... , ; clock offset from node and signal propagation time As a distance measurement observation.

[0147] Step 308: The slave node inputs the ranging observation value into the network clock state model, and uses Kalman filtering to solve the model to obtain the clock offset and frequency drift rate of the slave node relative to the master node; based on the clock offset and frequency drift rate, a linear mapping is performed to obtain the ADC sampling clock correction amount of the slave node.

[0148] For example, a network-wide clock state model is pre-constructed: taking the master node as the reference node, the clock offset of the master node is set to 0 and the frequency drift rate is 0; the clock offset and frequency drift rate of the slave node relative to the master node are used to construct the state vector of the slave node; a state equation is constructed based on the physical characteristics of clock drift, and the state equation includes a state transition matrix and process noise, which are used to describe the change relationship of the state vector at different times; an observation equation is constructed based on the mapping relationship between the ranging observation value and the state vector, and the observation equation includes an observation matrix and observation noise, which are used to describe the mapping relationship between the ranging observation value and the state vector.

[0149] Based on the state equation and observation equation, the acquired ranging observations are used as inputs to the observation equation. A Kalman filter algorithm is employed to recursively estimate the state vector. The recursive process of the Kalman filter includes: predicting the prior state estimate and its covariance at the current time step based on the previous state estimate and state transition matrix; inputting the current ranging observation into the observation equation to calculate the observation residual; calculating the Kalman gain based on the observation matrix and observation noise covariance; correcting the prior state estimate using the Kalman gain to obtain the posterior state estimate at the current time step as the optimal estimate; and updating the covariance matrix to prepare for the recursion at the next time step. Through this recursive process, the Kalman filter can fuse historical state information and current ranging observation information, recursively outputting the optimal estimates of the clock offset and frequency drift rate of the slave node relative to the master node, even under the interference of ranging noise and process noise.

[0150] The optimal estimates of the clock offset and frequency drift rate of the slave node relative to the master node from the Kalman filter output are substituted into the preset linear mapping formula to calculate the time correction of the ADC sampling clock.

[0151] Step 310: Send a sampling time schedule based on the master node clock through the instruction time slot;

[0152] For example, the master node calculates the absolute sampling time of each slave node within multiple future sampling periods based on the ADC sampling clock correction of each slave node. This absolute sampling time, referenced to the master node's clock, is encapsulated into a sampling schedule and sent to the corresponding slave nodes via instruction slots. The sampling schedule includes the slave node's node identifier, the absolute sampling time for each sampling period, and the sampling period number. The slave node receives the sampling schedule from the master node via instruction slots, parses the absolute sampling time corresponding to each sampling point in the schedule, and records the local time of receiving the schedule as a timestamp. The slave node stores the correspondence between each absolute sampling time in the sampling schedule and its locally recorded receiving timestamp to guide subsequent autonomously triggered sampling and time interpolation resampling. The slave node then autonomously triggers ADC sampling based on the absolute sampling time specified in the sampling schedule, rather than waiting for real-time trigger instructions from the master node, thereby eliminating the uncertainty of trigger time caused by instruction transmission delays and network congestion. The slave node records the local timestamp corresponding to each actual sampling time; this timestamp, together with the absolute sampling time in the sampling schedule, constitutes the data basis for time interpolation resampling.

[0153] Step 312: Receive the synchronization voltage data uploaded from the node through the data time slot.

[0154] For example, the slave node encapsulates the synchronization voltage data into a data upload frame according to a preset frame format in the data time slots pre-allocated in the time-division multiplexing mechanism, and sends it to the master node within the data time slot.

[0155] In the aforementioned wireless voltage synchronization method, the master node and slave node communicate via low-power wireless, using the same physical layer RF resources. Based on a time-division multiplexing mechanism, a single frame period is divided into synchronization time slots, command time slots, and data time slots. The master node broadcasts a network entry signal using the synchronization time slot, and the slave node registers to join the network. After completing clock tree self-calibration, the master and slave nodes achieve coarse synchronization via low-power wireless. The master and slave nodes acquire ranging observations through bidirectional ranging via low-power wireless. The slave node inputs the ranging observations into the network-wide clock state model, using a Kelvin clock. The model is solved using Mann filtering to obtain the clock offset and frequency drift rate of the slave node relative to the master node. The slave node performs a linear mapping based on the clock offset and frequency drift rate to obtain the ADC sampling clock correction. The master node issues a sampling schedule based on the master node clock through the instruction time slot, and the slave node records the timestamps in the schedule. Based on the schedule, timestamps, and ADC sampling clock correction, the slave node performs time interpolation resampling and environmental drift compensation to obtain synchronous voltage data aligned with the master node clock. The synchronous voltage data is then transmitted to the master node through the data time slot. Through the coordinated operation of master and slave nodes, using the master node clock as the network-wide time reference, the system utilizes bidirectional ranging, a network-wide clock state model, and Kalman filtering to accurately estimate the slave node clock offset and frequency drift rate, thereby obtaining the ADC sampling clock correction. A pre-scheduled absolute time triggering mechanism enables slave nodes to autonomously trigger sampling locally, effectively eliminating the uncertainty of command transmission delay and achieving microsecond-level high-precision voltage synchronization among distributed nodes. By dividing synchronization time slots, command time slots, and data time slots in a single low-power wireless physical layer based on time-division multiplexing, time-frequency synchronization, command delivery, and data upload are isolated and coexist in the same wireless link, avoiding mutual interference between links. Time interpolation resampling and environmental drift compensation further offset the impact of environmental changes on synchronization accuracy, ensuring that the system can still output high-precision synchronized voltage data aligned with the master node clock even without external reference sources such as GPS or synchronization cables.

[0156] In one embodiment, a sampling schedule based on the master node clock is issued via instruction time slots, including:

[0157] Based on the ADC sampling clock correction of each slave node, calculate the absolute sampling time of each slave node in the future multiple sampling periods;

[0158] The absolute sampling time is encapsulated into a sampling time schedule and sent to the corresponding slave node through the instruction time slot.

[0159] Specifically, the master node calculates the absolute sampling time of each slave node relative to the master node's clock in the future multiple sampling periods based on the ADC sampling clock correction of each slave node, associates the node identifier of each slave node with the corresponding absolute sampling time list, encapsulates and generates a sampling schedule, and then sends the sampling schedule to the corresponding slave node through the instruction time slot.

[0160] In the above embodiments, the master node calculates the absolute sampling time of each slave node based on the ADC sampling clock correction of each slave node and encapsulates it into a sampling schedule for distribution. This allows each slave node to know the accurate sampling time of multiple future sampling cycles in advance, thereby triggering sampling locally without waiting for the real-time trigger command from the master node. This effectively eliminates the uncertainty of the trigger time caused by command transmission delay and network congestion. At the same time, the master node calculates the absolute sampling time separately for each slave node, which can perform differentiated compensation for the clock deviation status of different slave nodes, avoiding the loss of synchronization accuracy caused by unified scheduling, and further improving the synchronization consistency among all nodes in the network.

[0161] In one embodiment, a wireless voltage synchronization method is specifically applied to a distributed voltage acquisition system. The system includes a master node and multiple slave nodes. The master node and slave nodes interact via low-power wireless communication, and the slave nodes' clocks use the master node's clock as the network's time reference. The master node has a built-in hardware reference source, which is the theoretical voltage value set at the factory, used for reference source verification during subsequent closed-loop calibration. Both the master node and slave nodes are equipped with a temperature acquisition unit, integrated into the voltage acquisition unit, used to measure the temperature around the ADC, crystal oscillator, and analog front-end in the voltage acquisition unit in real time, in order to correct the temperature and clock drift calibration curves experimentally calibrated before product delivery. The master node and slave nodes use the same physical layer RF resources, and the single frame period is divided into synchronization time slots, command time slots, and data time slots based on a time-division multiplexing mechanism. The synchronization time slot is dedicated to the broadcasting and receiving of network access signals and the transmission and reception of bidirectional ranging signals; the command time slot is dedicated to the master node issuing scheduling commands; and the data time slot is dedicated to the slave nodes uploading acquired data. The three are isolated from each other in time and do not interfere with each other. During the pre-scheduling phase, the master node allocates a unique, non-overlapping dedicated data upload time slot to each slave node and distributes the time slot table to all slave nodes. Slave nodes upload processed feature data within their assigned time slots to avoid channel congestion and data conflicts caused by simultaneous uploads from multiple nodes. The method includes:

[0162] The master node periodically broadcasts a network access signal within the synchronization time slot according to a preset period. The network access signal carries the network identifier, synchronization period, time slot configuration parameters, and registration window indication information. After powering on, the slave node continuously listens to the synchronization time slot. When it receives the network access signal, it extracts the network identifier and determines whether it matches the preset network. If it matches, it sends a registration request frame to the master node. The registration request frame carries the slave node's device identifier and hardware fingerprint information. After receiving the registration request frame, the master node authenticates the slave node. After successful authentication, it assigns a unique identifier within the network to the slave node and returns a registration confirmation frame through the synchronization time slot. After receiving the registration confirmation frame, the slave node completes the registration and network access.

[0163] After each slave node completes registration and network access, it performs a clock tree self-test calibration locally. Clock tree self-test calibration refers to the process by which each node, based on its internal single high-stability crystal oscillator, performs internal delay measurement and calibration of the clock paths of the RF chip, ADC sampling clock, and processor through the clock management unit. After completing the clock tree self-test calibration, each slave node stores the calibrated clock path delay parameters in its local register and sends a coarse synchronization request to the master node. The master node responds to the coarse synchronization request within the synchronization time slot, sending a network access synchronization signal carrying its local transmission time. The slave nodes receive the network access synchronization signal and record their local reception time. They calculate the initial time deviation based on the master node's transmission time and their local reception time, and adjust the starting position of their local time slot window according to the initial time deviation, aligning the local time slot window with the master node's time slot boundary, thus completing coarse synchronization. The purpose of coarse synchronization is to eliminate large clock deviations between nodes, achieving initial alignment of the entire network time and preventing subsequent fine synchronization from failing due to excessive initial deviations. Coarse synchronization is executed non-periodically and is triggered only in four scenarios: node registration and network entry, automatic master node election, system power-on restart, and node re-entering the network after going offline.

[0164] After coarse synchronization is complete, the master node performs bidirectional ranging for each slave node. The master node at the first moment... Send ranging signal to slave node, slave node at second time Receive ranging signal; from the node at the third time The master node responds with the ranging signal at the fourth time. Receive ranging signal; assume signal propagation time is... The clock offset of the slave node relative to the master node is Then the following relationship exists: , Solving the simultaneous equations yields... , ; clock offset from node and signal propagation time This serves as the ranging observation value. Multiple sets of clock offset observation values ​​are obtained by continuously performing bidirectional ranging multiple times. ,in, Indicates the measurement sequence number. Based on the clock offset change between two adjacent measurements and the time interval between the two measurements, calculate the frequency drift rate of the slave node relative to the master node. ,in, For the first During the next measurement, from node clock offset, This represents the time interval between two consecutive distance measurements.

[0165] The network clock state model is pre-built from the slave nodes: using the master node as the reference node, the master node's clock offset is set to 0 and its frequency drift rate to 0; the slave nodes... Clock offset relative to the master node and frequency drift rate Together we build from nodes The state vector is:

[0166] (1)

[0167] in, This represents the discrete time index of the Kalman filter recursion. For the first At discrete moments from node Clock offset relative to the master node, Let be the frequency drift rate of slave node i relative to master node at time k.

[0168] Based on the physical characteristics of clock drift, the state equation is constructed as follows:

[0169] (2)

[0170] in, Here is the state transition matrix. For process noise, the state equation is used to describe the relationship between the changes of the state vector at different times.

[0171] The observation equation is constructed based on the mapping relationship between the ranging observations and the state vector:

[0172] (3)

[0173] in, For the observation matrix, To account for observation noise, the observation equation is used to describe the distance measurement observations. With state vector Mapping relationship between them; process noise and observation noise All were obtained through prior experimental measurements.

[0174] Based on the state equation and observation equation, the ranging observations from the node are used as inputs to the observation equation. A Kalman filter algorithm is employed to recursively estimate the state vector: The prior state estimate and its covariance at the current moment are predicted based on the previous state estimate and state transition matrix; the current ranging observation is input into the observation equation to calculate the observation residual; the Kalman gain is calculated based on the observation matrix and the observation noise covariance; and the Kalman gain is used to correct the prior state estimate to obtain the posterior state estimate at the current moment, which is the optimal clock offset estimate after filtering. and optimal estimate of frequency drift rate The clock offset estimates, frequency drift rate estimates, and optimal estimation parameters of the state-space model for each slave node relative to the master node, as output by the Kalman filter, are used together as calibration parameters for subsequent dynamic compensation of the slave nodes.

[0175] The slave node calculates the additional clock drift caused by the current temperature based on the real-time temperature data collected by the temperature acquisition unit, combined with the temperature and clock drift calibration curve determined during pre-shipment testing. The slave node then adds this additional clock drift to the optimal estimate of the clock offset output by the Kalman filter to obtain the total clock offset including the temperature effect.

[0176] (4)

[0177] in, This is the temperature drift coefficient. As the reference offset, For the first Real-time temperature (in degrees Celsius) at discrete moments. and These are the parameters in the temperature and clock drift calibration curves tested before the product leaves the factory.

[0178] The formula for the temperature versus clock drift calibration curve is as follows: The time correction for the ADC sampling clock, calculated from the node based on the state variable estimates and the linear mapping relationship, is as follows:

[0179] (5)

[0180] in, Indicates the first At discrete moments from node ADC sampling clock correction amount Indicates from the initial time to the nth time. The total time length (in seconds) of each discrete moment. This indicates the frequency drift from the initial time to the... Additional offset (in seconds) accumulated over discrete time intervals.

[0181] Fine synchronization (i.e., bidirectional ranging and Kalman filter updates) is executed periodically, with an initial default period of 100ms to 1s. The specific value can be determined according to the real-time requirements of adapting to new energy battery management and smart grid monitoring. The master node dynamically adjusts the fine synchronization period, specifically according to the following rule: when the master node verifies online through the reference source and finds that the synchronization accuracy of the entire network is higher than a preset threshold (e.g., synchronization deviation), the master node performs a fine synchronization cycle adjustment. If the synchronization accuracy is found to be lower than the preset threshold (e.g., synchronization deviation), then increase the fine synchronization period (e.g., adjust from 500ms / time to 1s / time) to reduce system power consumption; If a sudden change in ambient temperature, hot-plugging of nodes, or increased channel interference is detected, the fine synchronization period is reduced (e.g., from 500ms / time to 100ms / time) to improve synchronization accuracy. The synchronization accuracy threshold can be flexibly configured at the application layer to adapt to different scenarios.

[0182] The master node calculates the absolute sampling time of each slave node relative to the master node's clock over multiple future sampling periods based on the ADC sampling clock correction of each slave node. It then associates the node identifier of each slave node with its corresponding absolute sampling time list to generate a sampling schedule, which is sent to each slave node via command slots. Slave nodes receive the sampling schedule via command slots, record the timestamp of the received time, and parse the absolute sampling time corresponding to each sampling point from the schedule. Slave nodes autonomously trigger ADC sampling when they reach the absolute sampling time specified in the sampling schedule, rather than waiting for real-time trigger commands from the master node, thus eliminating the uncertainty of trigger time caused by command transmission delays and network congestion.

[0183] The slave node performs time interpolation resampling and environmental drift compensation on the collected voltage data based on the absolute sampling time in the sampling schedule, the local recorded timestamp of the actual sampling time, and the ADC sampling clock correction amount. Specifically, the slave node uses the absolute sampling time of each sampling point in the sampling schedule as the target time, the locally recorded timestamp as the reference time, and the ADC sampling clock correction amount as the deviation correction amount to interpolate and resample the collected voltage data, calculate the voltage value corresponding to each target time, and obtain synchronized voltage data aligned with the master node clock as the reference.

[0184] The slave node performs feature extraction calculations locally based on the synchronization voltage data, extracting feature data such as the effective voltage value, peak voltage value, phase, harmonic content (THD), voltage mutation value, and event detection results (such as overvoltage, undervoltage, and voltage fluctuation). The extracted feature data is compressed into a feature vector. If the synchronization voltage data does not exceed the preset abnormal threshold, the slave node only uploads the feature vector to the master node according to the dedicated data time slot pre-allocated by the master node. If it exceeds the abnormal threshold, the slave node uploads the feature vector and the original waveform segment at the abnormal moment to the master node according to the dedicated data time slot pre-allocated by the master node.

[0185] The closed-loop calibration system operates as follows: The master node uses a microsecond-level synchronization mechanism to ensure that all slave nodes and the master node itself measure the actual voltage of the hardware reference source built into the master node at exactly the same absolute time point; the master node collects the actual measurement results from all nodes in the network, and performs a weighted average filtering on these actual measurement values, with the master node's measurement value having the highest weight to ensure reference accuracy, and all slave node measurement values ​​having the same weight. After removing outliers, a unified virtual reference source value is obtained for the entire network; the master node uses this virtual reference source value as a reference source to reverse verify and fine-tune the parameters of the entire network clock state model to ensure the stability of synchronization accuracy.

[0186] When a new slave node requests to join the network, the master node dynamically allocates time slots and initial synchronization parameters, which the slave node receives through the synchronization time slots to support hot-swapping of nodes. When the master node goes offline abnormally, the slave nodes automatically elect a new master node through a preset election mechanism to maintain the continuous operation of the network.

[0187] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0188] Based on the same inventive concept, this application also provides a wireless voltage synchronization system for implementing the aforementioned wireless voltage synchronization method. The system includes a master node and at least one slave node. The master node and slave node communicate via low-power wireless communication and use the same physical layer radio frequency resources during communication. Based on a time-division multiplexing mechanism, a single frame period is divided into synchronization time slots, command time slots, and data time slots; including:

[0189] The master node broadcasts the network access signal using the synchronization time slot, and the slave nodes register to join the network; after completing the clock tree self-test calibration, the master node and slave nodes complete coarse synchronization via low-power wireless.

[0190] The master node and slave node acquire ranging observations through low-power wireless bidirectional ranging;

[0191] The slave node inputs the ranging observation value into the whole network clock state model, and uses Kalman filtering to solve the model to obtain the clock offset and frequency drift rate of the slave node relative to the master node;

[0192] The ADC sampling clock correction is obtained by linearly mapping the node based on clock offset and frequency drift rate;

[0193] The master node issues a sampling schedule based on the master node's clock through a command time slot, and the slave nodes record the timestamps in the schedule.

[0194] The slave node performs time interpolation resampling and environmental drift compensation based on the schedule, timestamp, and ADC sampling clock correction to obtain synchronous voltage data aligned with the master node clock. The synchronous voltage data is then transmitted to the master node through data time slots.

[0195] In one exemplary embodiment, such as Figure 4 As shown, a slave node is provided, including: a registration module 402, a coarse synchronization module 404, a ranging module 406, a solution module 408, a correction module 410, a recording module 412, a sampling and compensation module 414, and a transmission module 416, wherein:

[0196] Registration module 402 is used to receive network access signals through synchronization time slots and register with the master node to join the network.

[0197] The coarse synchronization module 404 is used to complete coarse synchronization with the master node via low-power wireless after the clock tree self-test calibration is completed;

[0198] The ranging module 406 is used to perform bidirectional ranging with the master node via low-power wireless to obtain ranging observation values;

[0199] Solver module 408 is used to input ranging observations into the whole network clock state model, and use Kalman filtering to solve the model to obtain the clock offset and frequency drift rate of the slave node relative to the master node.

[0200] The correction module 410 is used to obtain the ADC sampling clock correction amount by performing a linear mapping between clock offset and frequency drift rate;

[0201] The recording module 412 is used to receive the sampling time schedule based on the master node clock through the instruction time slot and record the timestamps in the time schedule;

[0202] The sampling and compensation module 414 is used to perform time interpolation resampling and environmental drift compensation based on the schedule, timestamp and ADC sampling clock correction amount to obtain synchronous voltage data aligned with the master node clock as a reference.

[0203] The transmission module 416 is used to transmit synchronous voltage data to the master node through data time slots.

[0204] In one embodiment, the ranging module 406 is used to perform bidirectional ranging with the master node via low-power wireless to obtain ranging observation values, including:

[0205] The second time interval receives the ranging signal sent by the master node at the first time interval.

[0206] The system replies to the master node at the third time, so that the master node can receive it at the fourth time.

[0207] Based on the time interval between the first and fourth moments, calculate the clock offset of the slave node relative to the master node and the signal propagation time between the master node and the slave node;

[0208] Clock offset and signal propagation time are used as ranging observations.

[0209] In one embodiment, the solver module 408 is also used in the process of constructing the network-wide clock state model, including:

[0210] The master node is used as the reference node, and the clock offset and frequency drift rate of the master node are set to 0.

[0211] The clock offset and frequency drift rate of the slave node relative to the master node are used to construct the state vector of the slave node;

[0212] State equations are constructed based on the physical characteristics of clock drift. These state equations are used to describe the relationship between the state vectors of slave nodes at different times.

[0213] The observation equation is constructed based on the mapping relationship between the ranging observations and the state vector;

[0214] A network-wide clock state model is constructed based on state vectors, state equations, and observation equations.

[0215] In one embodiment, the correction module 410 is used to obtain the ADC sampling clock correction amount by performing a linear mapping between the clock offset and the frequency drift rate, including:

[0216] Based on the real-time temperature data and the calibrated temperature-clock drift curve, the additional clock drift caused by the current temperature is calculated.

[0217] Add the additional clock drift to the clock offset to obtain the total clock offset;

[0218] The ADC sampling clock correction is obtained by linearly mapping the total clock offset and frequency drift rate.

[0219] In one embodiment, the method further includes:

[0220] Extract the effective voltage value, harmonic components, or event detection results from the synchronous voltage data;

[0221] The extracted content is compressed into a feature vector;

[0222] If the synchronization voltage data does not exceed the preset abnormal threshold, the feature vector is uploaded to the master node through the data time slot; if it exceeds the abnormal threshold, the feature vector and the synchronization voltage data segment at the abnormal moment are uploaded to the master node through the data time slot.

[0223] In one embodiment, the method further includes:

[0224] When a new slave node requests to join the network, it receives the time slots dynamically allocated by the master node and the initial synchronization parameters through the synchronization time slots to support hot-plugging of nodes.

[0225] In the event of a master node going offline abnormally, a new master node will be automatically elected through a preset election mechanism to maintain the continuous operation of the network.

[0226] In one exemplary embodiment, such as Figure 5 As shown, a master node is provided, including: a broadcast module 502, a coarse synchronization module 504, a ranging module 506, a correction module 508, a transmission module 510, and a receiving module 512, wherein:

[0227] The broadcast module 502 is used to broadcast the network access signal through the synchronization time slot and to receive the registration and network access of slave nodes;

[0228] The coarse synchronization module 504 is used to complete coarse synchronization with the slave node via low-power wireless after the clock tree self-test calibration is completed;

[0229] The ranging module 506 is used to perform bidirectional ranging with the slave node via low-power wireless to obtain ranging observation values;

[0230] The correction module 508 is used to input the ranging observation values ​​from the slave node into the network clock state model, solve the model using Kalman filtering, and obtain the clock offset and frequency drift rate of the slave node relative to the master node; and perform a linear mapping based on the clock offset and frequency drift rate to obtain the ADC sampling clock correction amount of the slave node.

[0231] The sending module 510 is used to send a sampling time schedule based on the master node clock through instruction time slots;

[0232] The receiving module 512 is used to receive synchronous voltage data uploaded from the node through a data time slot.

[0233] In one embodiment, the sending module 510 is further configured to send a sampling time schedule based on the master node clock via an instruction time slot, including:

[0234] Based on the ADC sampling clock correction of each slave node, calculate the absolute sampling time of each slave node in the future multiple sampling periods;

[0235] The absolute sampling time is encapsulated into a sampling time schedule and sent to the corresponding slave node through the instruction time slot.

[0236] In one exemplary embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 6As shown, the computer device includes a processor, memory, input / output interfaces, a communication interface, a display unit, and an input device. The processor, memory, and input / output interfaces are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interfaces. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The input / output interfaces are used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, Near Field Communication (NFC), or other technologies. When the computer program is executed by the processor, it implements a wireless voltage synchronization method. The display unit is used to form a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the computer device, or external keyboards, touchpads, or mice, etc.

[0237] Those skilled in the art will understand that Figure 6 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0238] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0239] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0240] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0241] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0242] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0243] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0244] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A wireless voltage synchronization method, characterized in that, The method is used for slave nodes in a distributed network, which includes a master node and at least one slave node. The clock of the slave node uses the clock of the master node as the network-wide time reference. The master node and slave node communicate via low-power wireless and use the same physical layer radio frequency resources during communication. Based on a time-division multiplexing mechanism, a single frame period is divided into synchronization time slots, command time slots, and data time slots. The method includes: Receive the network access signal through the synchronization time slot and register the network access with the master node; After completing the clock tree self-test calibration, coarse synchronization is achieved with the master node via low-power wireless. The system performs bidirectional ranging with the master node using low-power wireless to obtain ranging observation values. The ranging observations are input into the network clock state model, and the model is solved using Kalman filtering to obtain the clock offset and frequency drift rate of the slave node relative to the master node. The ADC sampling clock correction amount is obtained by linearly mapping the clock offset to the frequency drift rate. The sampling timetable based on the master node clock is received through the instruction time slot, and the timestamps in the timetable are recorded. Based on the aforementioned schedule, timestamp, and ADC sampling clock correction, time interpolation resampling and environmental drift compensation are performed to obtain synchronous voltage data aligned with the master node clock as a reference. The synchronization voltage data is transmitted to the master node through the data time slot.

2. The method according to claim 1, characterized in that, The step of performing bidirectional ranging with the master node via low-power wireless to obtain ranging observation values ​​includes: The second time receives the ranging signal sent by the master node at the first time. The system replies to the master node at the third time, so that the master node can receive it at the fourth time. Based on the time interval between the first to the fourth time points, calculate the clock offset of the slave node relative to the master node and the signal propagation duration between the master node and the slave node; The clock offset and the signal propagation time are used as the ranging observation values.

3. The method according to claim 1, characterized in that, The process of constructing the network-wide clock state model includes: Using the master node as the reference node, we set the clock offset of the master node to 0 and the frequency drift rate to 0. The clock offset and frequency drift rate of the slave node relative to the master node are used to construct the state vector of the slave node; A state equation is constructed based on the physical characteristics of clock drift. The state equation is used to describe the relationship between the changes in the state vector of the slave node at different times. An observation equation is constructed based on the mapping relationship between the ranging observations and the state vector; Based on the state vector, the state equation, and the observation equation, the network-wide clock state model is constructed.

4. The method according to claim 1, characterized in that, The step of obtaining the ADC sampling clock correction amount based on the linear mapping between the clock offset and the frequency drift rate includes: Based on the real-time temperature data and the calibrated temperature-clock drift curve, the additional clock drift caused by the current temperature is calculated. Add the additional clock drift to the clock offset to obtain the total clock offset; The ADC sampling clock correction amount is obtained by performing a linear mapping based on the total clock offset and the frequency drift rate.

5. The method according to claim 1, characterized in that, The method further includes: Extract the effective voltage value, harmonic components, or event detection results from the synchronous voltage data; compress the extracted content into a feature vector; If the synchronization voltage data does not exceed the preset abnormal threshold, the feature vector is uploaded to the master node through the data time slot; if it exceeds the abnormal threshold, the feature vector and the synchronization voltage data fragment at the abnormal moment are uploaded to the master node through the data time slot.

6. The method according to claim 1, characterized in that, The method further includes: When a new slave node requests to join the network, the master node dynamically allocates the time slot and initial synchronization parameters through the synchronization time slot to support hot-plugging of the node. In the event of an abnormal offline state of the master node, a new master node will be automatically elected through a preset election mechanism to maintain the continuous operation of the network.

7. A wireless voltage synchronization method, characterized in that, The method is used for a master node in a distributed network, which includes one master node and at least one slave node. The slave node's clock uses the master node's clock as the network's time reference. The master node and slave node communicate via low-power wireless and use the same physical layer radio frequency resources during communication. Based on a time-division multiplexing mechanism, a single frame period is divided into synchronization time slots, command time slots, and data time slots. The method includes: The network access signal is broadcast through the synchronization time slot, and the registration and network access of the slave node is received. After completing the clock tree self-test calibration, coarse synchronization is achieved with the slave node via low-power wireless. The ranging observation value is obtained by performing bidirectional ranging with the slave node through low-power wireless; The slave node inputs the ranging observation value into the network clock state model, and uses Kalman filtering to solve the model to obtain the clock offset and frequency drift rate of the slave node relative to the master node; based on the clock offset and frequency drift rate, a linear mapping is performed to obtain the ADC sampling clock correction amount of the slave node; The sampling schedule based on the master node clock is issued through the instruction time slot; The synchronization voltage data uploaded by the slave node is received through the data time slot.

8. The method according to claim 1, characterized in that, The step of issuing a sampling schedule based on the master node clock via the instruction time slot includes: Based on the ADC sampling clock correction amount of each slave node, calculate the absolute sampling time of each slave node in multiple future sampling periods; The absolute sampling time is encapsulated into the sampling time schedule and sent to the corresponding slave node through the instruction time slot.

9. A wireless voltage synchronization system, characterized in that, The system includes a master node and at least one slave node. The master node and slave node communicate via low-power wireless and use the same physical layer radio frequency resources during communication. Based on a time-division multiplexing mechanism, a single frame period is divided into synchronization time slots, command time slots, and data time slots. The master node broadcasts the network access signal using the synchronization time slot, and the slave node registers to join the network; after completing the clock tree self-test calibration, the master node and slave node complete coarse synchronization via low-power wireless. The master node and the slave node acquire ranging observation values ​​through low-power wireless bidirectional ranging; The slave node inputs the ranging observation value into the network clock state model, and uses Kalman filtering to solve the model to obtain the clock offset and frequency drift rate of the slave node relative to the master node; The slave node performs a linear mapping between the clock offset and the frequency drift rate to obtain the ADC sampling clock correction amount; The master node issues a sampling timetable based on the master node's clock through the instruction time slot, and the slave node records the timestamps in the timetable; The slave node performs time interpolation resampling and environmental drift compensation based on the time schedule, timestamp, and ADC sampling clock correction amount to obtain synchronous voltage data aligned with the master node clock as a reference, and transmits the synchronous voltage data to the master node through the data time slot.

10. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 8.

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