Component carrier and method of manufacturing a component carrier

Abstract

The present application relates to a component carrier (100) and a method of manufacturing a component carrier, the component carrier comprising: a stack (102) comprising at least one electrically insulating layer structure (104) and at least one electrically conductive layer structure (106), the at least one electrically conductive layer structure (106) being arranged in direct contact with the at least one electrically insulating layer structure (104) so as to define a contact interface (132) between the at least one electrically conductive layer structure and the at least one electrically insulating layer structure; and a thin layer (128) sandwiched between the at least one electrically conductive layer structure (106) and the at least one electrically insulating layer structure (104), the thin layer (128) being arranged beside the contact interface (132).

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a component carrier and the component carrier thereof. Background Technology

[0002] With the increasing functionality of products equipped with component carriers containing one or more electronic components, the continuous miniaturization of these components, and the growing number of components such as printed circuit boards to be mounted on or embedded in component carriers, powerful array-type components or packages with multiple components are being adopted. These array-type components or packages have multiple contacts or connections with increasingly smaller distances between them. Removing heat generated during operation by these components and the component carrier itself has become an increasingly important issue. Simultaneously, the component carrier must be mechanically stable and electrically reliable to ensure operation even under harsh conditions.

[0003] It may be necessary to provide component carriers with high reliability. Summary of the Invention

[0004] According to an exemplary embodiment of the present invention, a component carrier is provided, the component carrier comprising a stack and a thin layer, the stack comprising at least one electrically insulating layer structure and at least one electrically conductive layer structure, the at least one electrically conductive layer structure being arranged to directly contact the at least one electrically insulating layer structure thereby defining a contact bonding surface between the at least one electrically conductive layer structure and the at least one electrically insulating layer structure, the thin layer being sandwiched between the at least one electrically conductive layer structure and the at least one electrically insulating layer structure, the thin layer being arranged adjacent to the contact bonding surface.

[0005] According to another exemplary embodiment of the present invention, a method for manufacturing a component carrier is provided, the method comprising: providing a stack comprising at least one electrically insulating layer structure and at least one electrically conductive layer structure; arranging the at least one electrically conductive layer structure in direct contact with the at least one electrically insulating layer structure, thereby defining a contact engagement surface between the at least one electrically conductive layer structure and the at least one electrically insulating layer structure; and sandwiching a thin layer between the at least one electrically conductive layer structure and the at least one electrically insulating layer structure, the thin layer being arranged adjacent to the contact engagement surface.

[0006] In the context of this application, the term "component carrier" may specifically refer to any support structure capable of accommodating one or more components thereon and / or therein to provide mechanical support and / or electrical connection. In other words, a component carrier can be constructed as a mechanical and / or electronic carrier for a component. In particular, a component carrier can be one of a printed circuit board, an organic interposer, and an IC (integrated circuit) substrate. A component carrier can also be a hybrid board composed of different types of component carriers of the above types.

[0007] In the context of this application, the term "stacked structure" may specifically refer to an arrangement of multiple planar layers mounted one on top of the other (e.g., mounted one on top of the other in parallel).

[0008] In the context of this application, the term "layer structure" may specifically refer to continuous layers, graphical layers, or multiple non-continuous islands in a common plane.

[0009] In the context of this application, the term "contact bonding surface" can specifically refer to the region between the electrically insulating layer structure and the electrically conductive layer structure where the electrically insulating layer structure is in direct physical contact with the electrically conductive layer structure. Therefore, there is no intermediate structure at the contact bonding structure that differs from the junction of the electrically insulating and electrically conductive layers (i.e., there are no voids or other materials). The contact bonding surface can be flat. Alternatively, the contact bonding surface can be structured, for example, it may include peaks and valleys. At least a portion of the contact bonding surface can extend in a direction perpendicular to the thickness direction. At least another portion of the contact bonding surface can extend in a direction inclined relative to the thickness direction. The contact bonding surface can follow the contour of the main surface of the electrically conductive layer structure. Additionally or alternatively, the contact bonding surface can follow the contour of the main surface of the electrically insulating layer structure.

[0010] In this application, the term "thin layer" can specifically refer to a small layer or film of material located in the bonding region between the electrically insulating layer structure and the electrically conductive layer structure. The thin layer can be a separate structure relative to the electrically insulating layer structure and the electrically conductive layer structure. The material of the thin layer can be the same as or different from the materials of the electrically insulating layer structure and the electrically conductive layer structure. The thickness of the thin layer can be less than the thickness of the electrically insulating layer structure and can also be less than the thickness of the electrically conductive layer structure. For example, the thickness of the thin layer can be less than 10 µm, particularly less than 5 µm, and more particularly less than 1 µm. In a cross-sectional view, the thin layer can be distinguished from adjacent electrically conductive layer structures and / or adjacent electrically insulating layer structures.

[0011] In this application, the term "thin layer located beside the contact bonding surface" specifically indicates that the thin layer and the contact bonding structure disposed between the electrically conductive layer structure and the electrically insulating layer structure can be arranged side by side or adjacent to each other, for example, side-by-side. The thin layer and contact bonding structures arranged adjacent to each other can be directly adjacent to each other, or there can be at least one intermediate structure (e.g., a void region or other material region) between the thin layer and the contact bonding structure. For example, the thin layer and the contact bonding structure can extend horizontally at the same vertical height. However, the thin layer and the contact bonding structure can also be inclined or curved, or even extend vertically.

[0012] In the context of this application, the term "main surface of a body" may specifically refer to one of the two largest opposing surfaces of a body or one of the two outermost opposing surfaces of a body. These main surfaces may be connected by circumferential sidewalls. The thickness of a body, such as a component carrier, stack, or layer structure, may be defined by the distance between the two opposing main surfaces.

[0013] According to an exemplary embodiment of the present invention, a component carrier, such as a printed circuit board (PCB) or integrated circuit (IC) substrate, is provided. The component carrier may include (e.g., laminated) a stack comprising one or more electrically conductive layer structures (e.g., patterned copper foil and / or structured deposited copper layers) and one or more electrically insulating layer structures (e.g., resin sheets, such as epoxy resin, and optionally reinforced by reinforcing particles such as glass fibers or spheres). The electrically conductive layer structures may be in direct physical contact with the electrically insulating layer structures along a contact bonding surface between the electrically conductive layer structures and the electrically insulating layer structures. In another region, a thin layer may be located between the electrically conductive layer structures and the electrically insulating layer structures, such that the thin layer can be positioned adjacent to the contact bonding surface. Advantageously, providing such a thin layer or film can at least reduce excessive gaps between the electrically conductive layer structures and the electrically insulating layer structures, and thus reduce the risk of delamination, warping, and / or other undesirable phenomena. Therefore, a component carrier with high reliability can be provided. For example, such a component carrier can be used as a printed circuit board or IC substrate in devices such as smartphones, computers, or automotive systems, where reliable and precise connections are crucial. Advantageously, this thin layer can be formed by adjusting the processing parameters of the component carrier manufacturing process accordingly, particularly during surface treatment. Therefore, the thin layer can be a byproduct of the surface treatment process and thus requires no additional labor to form.

[0014] In the following sections, further exemplary embodiments of the manufacturing method and component carrier will be described.

[0015] In this embodiment, the conductive layer structure and the insulating layer structure can, in particular, be in direct contact with the main surface of at least one insulating layer structure. Therefore, the outer main surface of the corresponding insulating layer structure may include an area where the insulating layer structure is in direct physical contact with the conductive layer structure, i.e., there is no gap between the insulating layer structure and the conductive layer structure. This improves the mechanical integrity of the entire component carrier.

[0016] In this embodiment, the contact bonding surface can also be the bonding surface between the embedded portion of the electrically conductive layer structure and the contacting electrically insulating layer structure. Specifically, the stack can be a laminated stack in which the electrically insulating layer structure and the electrically conductive layer structure are integrally connected. By interlocking the layer structures, these layer structures can directly and physically contact each other at the contact bonding surface. This can form a reliable component carrier without gaps at the contact bonding surface or in the thin layers.

[0017] In one embodiment, a thin layer is disposed on the main surface of at least one electrically insulating layer structure. Therefore, a thin layer or film that fills the gap between the electrically conductive layer structure and the electrically insulating layer structure can be directly disposed on the main surface of the electrically insulating layer structure, thereby suppressing undesirable delamination on that main surface.

[0018] In an embodiment, at least one electrically conductive layer structure is at least partially embedded in at least one electrically insulating layer structure. Specifically, the thin layer may be arranged on the portion of the at least one electrically conductive layer structure embedded in the at least one electrically insulating layer structure. For example, the at least one electrically conductive layer structure may be formed to include embedded pads, vias, and / or traces located in the surrounding dielectric matrix of the at least one electrically insulating layer structure. By filling the gaps in the stack with one or more thin layers, the mechanical integrity of the resulting stack can be improved, thereby contributing to the mechanical reliability of the component carrier.

[0019] In this embodiment, the thin layer is in direct contact with the contact bonding surface. In this embodiment, there is no intermediate structure (e.g., no solid structure or void) between the contact bonding surface and the thin layer. Therefore, due to the presence of the thin layer and its direct connection to the contact bonding surface, any voids around the thin layer can be avoided, thereby improving the reliability of the component carrier by suppressing undesirable phenomena such as delamination.

[0020] In this embodiment, the thin layer and the contact bonding surface are laterally separated from each other by a lateral spacing. This lateral spacing can be empty (e.g., a void) or it can be filled with other materials. Preferably, the other material filling the lateral spacing is a conductive material, such as a seed layer (the seed layer can be made of a material such as a metal, for example, titanium, nickel, silver, and / or gold). However, by arranging the thin layer adjacent to the structure defining the lateral spacing, the size of potential voids, etc., can be reduced, which can have a positive impact on mechanical reliability compared to the case without a thin layer.

[0021] In one embodiment, the component carrier includes an additional volume portion extending along the thickness direction of the stack between at least one electrically conductive layer structure and at least one insulating layer structure, and extending along a lateral extension parallel to one of the main surfaces of the stack between the thin layer and the contact bonding surface. Specifically, when the available fill space is narrow and long, for example, in the laterally exposed embedded portion of the electrically conductive structure (see... Figure 7 In situations where a vacuum space (e.g., a negative pressure space below ambient pressure) is present, such an additional volume may arise. This additional volume may be a vacuum space (e.g., a negative pressure space below ambient pressure) or it may be filled with a fluid, particularly air. While such an additional volume may be undesirable, especially when it is composed of a non-solid material such as a gas, which could be a potential cause of reliability issues, the presence of a thin film can reduce the size of this additional volume. Therefore, the thin film or membrane can have a positive impact on the reliability of the component carrier.

[0022] In this embodiment, the first surface of the thin layer is parallel to the contact bonding surface; more specifically, the first surface of the thin layer and the contact bonding surface are coplanar. For example, the first surface may be flat and / or smooth. A tight bond can be established between the thin layer and the attached layer structure at the first surface.

[0023] In one embodiment, the second surface of the thin layer, opposite to the first surface, has an irregular and / or rounded shape. For example, the second primary surface may be curved and / or rough. At the second surface, the irregular and / or rounded geometry of the thin layer can provide an enlarged bonding area to the attached layer structure. This facilitates the formation of a good adhesion between the thin layer and the attached layer structure.

[0024] In this embodiment, the thin layer is embedded in at least one electrically conductive layer structure, particularly, the thin layer is partially embedded in at least one electrically conductive layer structure. Especially when at least one electrically conductive layer structure is disposed on at least one electrically insulating layer structure, the thin layer is embedded in at least one electrically conductive layer structure, particularly, the thin layer is partially embedded in at least one electrically conductive layer structure. More particularly, the thin layer may be disposed on the main surface of at least one electrically insulating layer structure. Preferably, the thin layer is in contact with the main surface and sidewalls of at least one electrically conductive layer structure. This provides the advantage of reliable mechanical interaction between the thin layer and at least one electrically conductive layer structure, and reduces the risk of delamination between the aforementioned components of the stack.

[0025] In this embodiment, the thin layer is embedded in at least one electrically insulating layer structure, and more particularly, the thin layer is partially embedded in at least one electrically insulating layer structure. Specifically, when at least one electrically conductive layer structure is embedded in at least one electrically insulating layer structure, the thin layer is embedded in at least one electrically insulating layer structure, and more particularly, the thin layer is partially embedded in at least one electrically insulating layer structure. Preferably, the thin layer is in contact with the main surface and sidewalls of at least one electrically insulating layer structure. This provides the advantage of reliable mechanical interaction between the thin layer and at least one electrically insulating layer structure, and reduces the risk of delamination between the aforementioned components of the stack.

[0026] In an embodiment, at least one electrically conductive layer structure includes a pad. In the context of this application, the term "pad" may specifically refer to a localized area on a component carrier where a conductive material is disposed, which can serve as a location for electrical connections or component attachments. For example, a pad can serve as a contact surface for soldering electronic components, such as chips, resistors, or connectors. Depending on the specific design and function, the pad can have various shapes, such as circular, rectangular, or irregular shapes. For example, a pad may form part of a ball grid array, or a pad may serve as a terminal of a surface mount device. The pad may include multiple metal layers, including a seed layer, a plated barrier layer, and a plated patterned layer.

[0027] In an embodiment, at least one electrically conductive layer structure includes a planar frame structure. For example, such a planar frame structure can line the joint between the bottom and side walls of a cavity formed in a stack. The gap between the metallic planar frame structure and the connected electrically insulating layer structure can be at least partially filled by this thin layer, thereby improving reliability. This reduces the risk of delamination, particularly at the edges of the cavity, because the planar frame structure can fill the undercut portions located at the edges of the cavity.

[0028] In embodiments, at least one electrically conductive layer structure includes a barrier layer, particularly a planar frame structure. In this context, the term "barrier layer" can specifically refer to a layer that acts as a barrier against a laser beam (e.g., in the context of ablation, drilling, etc.). Therefore, this additional / barrier layer can also be referred to as a stopping layer, particularly a laser stopping layer. In embodiments, a laser can cut through the electrically insulating layer structure of a stack to form a cavity. However, the barrier layer (e.g., a metallic layer, such as a copper layer) can block the laser (e.g., a CO2 laser). In this way, precise depth control can be achieved during cavity formation. In embodiments, such an additional layer can be provided on the bottom wall of the cavity and the sidewalls of the openings / holes located on the bottom wall of the cavity. This barrier layer can prevent ion migration, for example, preventing cation migration and / or anion migration. This barrier layer can impart additional functionality to at least one electrically conductive layer structure, such as stopping the laser (e.g., a laser beam) at a specific location on the stack. The barrier layer may include a layer that reflects the laser beam and / or a layer that dissipates laser energy and / or a layer that cannot be removed by the laser beam.

[0029] In one embodiment, the planar frame structure is configured to at least partially define the sidewalls of the cavity in the lateral direction. This includes embodiments having a cavity in which an electrically conductive layer structure is disposed at the intermediate thickness portion of the cavity. The planar frame structure may also be disposed at the edge between the bottom of the cavity and the sidewalls. Because the planar frame structure may include a barrier layer, the cavity can be precisely formed using a laser cutting process, particularly the sidewalls of the cavity.

[0030] In implementations, the planar frame structure is either a circumferentially closed planar frame structure or an open planar frame structure. For example, the planar frame structure extends in a ring-like manner along the circumferential portion of the edge between the bottom and side walls of the cavity; specifically, the planar frame structure extends in a circumferentially closed ring-like manner along the circumferential portion of the edge between the bottom and side walls of the cavity. In a top view of the component carrier inside the cavity, the bottom-side wall edge or corner of the cavity can be a closed structure, particularly a closed rectangular structure. Without a planar frame structure and connected thin layer at the bottom-side wall edge or corner, gaps or unfilled cavities may exist along the entire bottom-side wall edge or corner. Advantageously, by forming the planar frame structure as a closed ring-like frame or ring structure extending along the entire bottom-side wall edge or corner, any risk of gaps forming along the bottom-side wall edge or corner can be reduced or eliminated. However, when the planar frame structure extends along a portion of the bottom-side wall edge or corner (preferably at least 50% of the bottom-side wall edge or corner), the improvement in reliability may already be achieved.

[0031] In one embodiment, the thin layer has a planar extension that defines a circumferential portion following the outer contour of at least one electrically conductive layer structure, the thin layer being sandwiched at the at least one electrically insulating layer structure. For example, the thin layer may also be a planar frame structure arranged along a planar frame structure of the connected electrically conductive layer structure.

[0032] In one embodiment, the circumferential portion defined by the planar extension of the thin layer follows the outer circumferential portion of at least one electrically conductive layer structure. In this case, "following" can mean that the thin layer extends from the outer contour of the at least one electrically conductive layer structure toward the inner portion of the at least one electrically conductive layer structure. Since the thin layer is in direct contact with the at least one electrically conductive layer structure because it follows the outer circumferential portion of the at least one electrically conductive layer structure, this can have the advantage of reducing the occurrence of gaps forming between the thin layer and the at least one electrically conductive layer structure in the lateral direction.

[0033] In one embodiment, a circumferential portion defined by a planar extension of a thin layer is sandwiched between at least one electrically insulating layer structure and a pad. This particularly improves the reliability of the component carrier around the critical pad area.

[0034] In one embodiment, the circumferential portion defined by the planar extension of the thin layer follows the inner circumferential portion of at least one electrically conductive layer structure. In this case, "following" can mean that the thin layer extends from the inner contour of the at least one electrically conductive layer structure toward the inner side of the at least one electrically conductive layer structure. The inner side of the at least one electrically conductive layer structure can refer to the portion defining the frame shape of the at least one electrically conductive layer structure. Since the thin layer is in direct contact with the at least one electrically conductive layer structure by following its outer circumferential portion, this can have the advantage of reducing the occurrence of gaps forming between the thin layer and the at least one electrically conductive layer structure in the lateral direction.

[0035] In one embodiment, a circumferential portion defined by a planar extension of the thin layer is sandwiched between at least one electrically insulating layer structure and a planar frame structure. Specifically, the planar frame structure partially defines the sidewalls of the cavity in the lateral direction. Preferably, at least a portion of the circumferential portion defined by the planar extension of the thin layer is sandwiched between at least one electrically insulating layer structure and the planar frame structure. In particular, the thin layer may also form a planar frame structure following an electrically conductive layer structure, thereby continuously filling the circumferential gaps between the layer structures to improve reliability by avoiding voids.

[0036] In one embodiment, the circumferential portion defined by the planar extension of the thin layer completely or partially follows the outer contour of at least one electrically conductive layer structure.

[0037] In embodiments, cavities are formed within the stack. In the context of this application, the term "cavity" may specifically refer to a blind hole, through-hole, or recess in the layered structure of a stack of component carriers. For example, a cavity may be shaped and sized to accommodate electronic components (e.g., semiconductor chips), heat sinks (e.g., copper or ceramic blocks), or plug-ins or other component carriers, which may be wholly or partially located within the cavity. In embodiments, the cavity may serve as a waveguide or at least a portion of a waveguide. Components may also be embedded within the cavity.

[0038] In one embodiment, at least one first portion of an electrically conductive layer structure is exposed within the cavity. This first portion of the electrically conductive layer structure exposed within the cavity can specifically represent a metallic structure defining or delineating a portion of the bottom wall of the cavity. The cavity and the first portion exposed at the bottom wall can be partially or completely filled with at least one electronic component, and optionally also filled with an encapsulant or electrically insulating filling medium—e.g., resin, dielectric paste, and / or adhesive. The first portion of the electrically conductive layer structure can be exposed at the bottom wall of the cavity relative to the stack material. At least one first portion of the electrically conductive layer structure can be electrically connected to at least one electronic component inserted into the cavity. This can provide the advantage of electrically connecting the cavity via the first portion.

[0039] In an embodiment, at least one second portion of the conductive layer structure has an exposed portion exposed within the cavity and an unexposed portion not exposed. The second portion of the conductive layer structure may partially define the sidewalls of the cavity and may be partially exposed within the cavity at its edges. This may specifically refer to a metal structure disposed at the junction between the sidewalls and bottom wall of the cavity for partially or completely sealing the edge between the sidewalls and bottom wall of the cavity. The cavity and the second portion within the edges may be partially or completely filled with at least one electronic component and optionally also filled with an encapsulant or electrically insulating filling medium—e.g., resin, dielectric paste, and / or adhesive. The second portion of the conductive layer structure may be partially exposed relative to the stack material and may be partially disposed within the stack material. The second portion may define a lateral extension of the cavity. Because the second portion includes the unexposed portion, this can provide the advantage of reducing delamination at the edges or corners of the cavity. The portion near the cavity in the lateral direction can be filled with the unexposed portion of the second portion, thereby enhancing the integrity of the stack at the location where the bottom of the cavity intersects with the sidewalls of the cavity.

[0040] In one embodiment, a thin layer is disposed between a first and / or second portion of the cavity on one side and at least one electrically insulating layer structure defining a portion of the bottom wall of the cavity on the other side. The thin layer, configured as an interlocking engagement structure and present at the bottom of the cavity, ensures a suitable geometry within the cavity, allowing components to be properly embedded therein, as any tendency to delamination is effectively suppressed.

[0041] In this embodiment, a thin layer is disposed between the unexposed portion of the second part and at least one electrically insulating layer structure. Specifically, the thin layer is disposed between the unexposed portion of the second part and the at least one electrically insulating layer structure that at least partially defines the sidewalls of the cavity. In particular, the thin layer can even extend into the inclined or vertical sidewalls of the stack defined by the cavity, thus improving mechanical reliability in this sidewall region. This structure allows the gap between the electrically insulating layer structure and the unexposed portion of the second part to be at least partially filled, thereby avoiding the risk of delamination or cracking between the two layers. Furthermore, the thin layer filling the gap can balance the CTE (coefficient of thermal expansion) mismatch in this region, thereby releasing internal stress, which not only reduces the risk of delamination but also improves the warpage control performance of the entire product.

[0042] In this embodiment, the bottom wall of the cavity is partially defined by a portion of at least one electrically insulating layer structure. Alternatively or additionally, the bottom wall of the cavity is partially defined by a portion of at least one electrically conductive layer structure. Preferably, a first portion of the bottom wall of the cavity is defined by an electrically insulating layer structure, while a second portion of the bottom wall is defined by an electrically conductive layer structure. The main surface of the bottom wall of the cavity (particularly the first portion) may be at a different vertical height than the main surface of the bottom of the cavity (particularly the second portion). In other words, the bottom of the cavity can be structured. The thin layer located between the corresponding portions of the layer structure can suppress delamination and achieve high reliability of the component carrier. Furthermore, this thin layer can also be configured as a buffer to redistribute stress that may accumulate at the undercut in the presence of an undercut, thereby preventing cracking problems.

[0043] In one embodiment, the thin layer is disposed between a first portion of at least one electrically conductive layer structure and at least one electrically insulating layer structure that partially defines the bottom wall of the cavity, and / or, an additional thin layer is disposed between an exposed portion of a second portion of at least one electrically insulating layer structure that defines a portion of the bottom wall of the cavity, and / or, another thin layer is disposed between an unexposed portion of the second portion and an electrically insulating layer structure that partially embeds the second portion and partially defines the sidewall of the cavity. Figure 5This embodiment is illustrated for example. For instance, the width of the thin layer in the horizontal plane is between 2µm and 10µm, and / or, another thin layer in the horizontal plane is between 2µm and 10µm, and / or, the other thin layer in the horizontal plane is between 10µm and 20µm. Therefore, it is particularly preferred that different thin layers close or avoid gaps in different regions of the cavity, thereby achieving higher quality at the larger extension of the cavity. The arrangement of the thin layers can be configured to compensate for the thickness reduction of the first portion caused by the etching process, which not only improves the quality and reliability of the component carrier but also provides sufficient height for the first portion to be connected to the components to be joined.

[0044] In this implementation, the horizontal width of the thin layer and / or the horizontal width of another thin layer are different from the horizontal width of the other thin layer; specifically, the horizontal width of the other thin layer is larger than the horizontal width of the thin layer and / or the horizontal width of the other thin layer. From a descriptive perspective, the spatial extension of the corresponding thin layer in the significantly exposed portion can be greater than the spatial extension of the thin layer in the less exposed area, because the material of the corresponding thin layer is more easily inserted into the exposed area.

[0045] In an embodiment, at least one third portion of an electrically conductive layer structure is fully embedded in the stack and is not exposed within the cavity. Specifically, at least one electrically conductive layer structure may include a third portion embedded in another electrically insulating layer structure disposed on the main surface of one of the aforementioned electrically insulating layer structures within a plurality of electrically insulating layer structures of the stack. The electrically conductive layer structures (which may be located in the same plane) may include a fully exposed first portion, a partially exposed and partially unexposed second portion, and a third portion fully encapsulated within the stack. For example, the first portion may be used for direct connection to a conductive pad of an electronic component to be embedded in the cavity, the second portion may be used to cooperate with a thin layer to suppress voids at the edges or corners of the cavity, and / or the third portion may provide functionality facilitating conductive traces and / or vertical via connections within the component carrier. Preferably, the aforementioned first electrically insulating layer structure and the other electrically insulating layer structure may be adjacent to each other and / or at least partially in direct contact in the thickness direction of the stack.

[0046] In this implementation, the third portion does not have a thin layer. This is likely due to the fact that the surface treatment portion does not extend into the internal embedded region of the stacked part. Since there is no need to provide a thin layer at the third portion, material and / or energy can be saved.

[0047] In this implementation, the ratio of the thickness of the thin layer to the thickness of at least one electrically conductive layer structure is in the range of 0.05 to 0.2. For example, the thickness of the thin layer can be 10% of the thickness of the electrically conductive layer structure. Therefore, the thin layer can have a significantly greater planar extension compared to its thickness. This can have the advantage of not requiring a large amount of material to form the thin layer. This allows for a compact stack. Furthermore, the thickness of the thin layer can form a thinner electrically conductive layer structure, thereby compensating for the thickness of the component to maintain the overall thickness of the package. This means that the electrically conductive layer structure (particularly the first portion) can be thinner, while the overall thickness of the component can be thicker, thus avoiding the risk of component cracking and / or increasing component density, thereby enabling high-performance computing applications without changing the package size. This can provide a compact design and an efficient manufacturing method for mass production.

[0048] In an embodiment, the width of the thin layer in the horizontal plane ranges from 2µm to 20µm. For example, the range can be from 5µm to 15µm. A thin layer of this thickness can close at least a majority of the typical gaps between the layers of the stack, thereby reducing or even eliminating the causes of unwanted defects. This width can completely fill the gaps, thereby preventing cracking problems and reducing electrical transmission resistance in that area. In an embodiment, the thin layer comprises or is composed of a conductive material. For example, the material of the thin layer can correspond to the material of the surface-treated portion of the stack. For example, the thin layer can include nickel, gold, and / or palladium.

[0049] In one embodiment, the conductivity of the material comprising the thin layer differs from the conductivity of the material of at least one electrically conductive layer structure. For example, the thin layer may comprise nickel, while the electrically conductive layer structure may comprise copper.

[0050] In some embodiments, the thin layer comprises a material different from that of at least one electrically conductive layer structure. The electrically conductive layer structure may comprise a material provided by a patterned metal plate and / or a deposited or plated patterned layer, particularly copper. The thin layer may be a byproduct of a surface treatment process. This can result in the thin layer's material differing from that of the electrically conductive layer structure.

[0051] In embodiments, at least one electrically conductive layer structure includes a cover conductive layer, and in particular, the first and / or second portions include a cover conductive layer. In the context of this application, the term "cover conductive layer" may specifically refer to a layer or structure of conductive material that can be formed on at least a portion of the pad of the aforementioned electrically conductive layer structure. The cover conductive layer may be a metallic structure, such as a surface-treated portion, for example comprising nickel and / or palladium and / or gold and / or silver, and may be positioned between the pad and an additional conductive structure such as solder or sintering material. The cover conductive layer can be used for various purposes, such as providing a barrier to prevent diffusion between the pad and solder, enhancing mechanical stability, and / or improving the reliability of electrical connections. For example, a nickel-based cover conductive layer may be used as part of an electroless nickel / electroless palladium / immersion gold (ENEPIG) process.

[0052] In this embodiment, a thin layer is enclosed between at least one electrically insulating layer structure, at least one electrically conductive layer structure, and a covering conductive layer. Therefore, the thin layer and the covering conductive layer can be directly connected to each other. The thin layer can be part of the covering conductive layer and formed simultaneously. This provides the advantage of mechanical protection for the thin layer.

[0053] In implementations, the conductive overlay comprises multiple sublayers. For example, the conductive overlay may be a surface treatment portion comprising multiple electrically conductive structures arranged vertically on top of each other. An example is an electroless nickel / electroless palladium / immersion gold (ENEPIG) treatment portion.

[0054] In one implementation, the conductive overlay is merged into the thin layer. More specifically, the thin layer may be an extension of a portion of the conductive overlay. This can provide the advantage of increased material thickness; for example, the thin layer and the conductive overlay may comprise nickel. When the thin layer and the conductive overlay are combined, the overall thickness of the nickel can be increased.

[0055] In one embodiment, one of the plurality of sublayers covering the conductive layer is bonded to the thin layer. The one sublayer may be the first sublayer formed covering the conductive layer. At least one other sublayer among the plurality of sublayers covering the conductive structure may be separable from the thin layer and may be made of, for example, a different material than the thin layer. In particular, all other sublayers among the plurality of sublayers covering the conductive structure may be separable from the thin layer and may be made of, for example, a different material than the thin layer. The bonded sublayer may be made of the same material as the thin layer.

[0056] In one embodiment, the conductive cover layer forms an anchoring structure around the sidewall of at least one electrically conductive layer structure. Specifically, the conductive cover layer forms an anchoring structure around the exposed portion of the second portion and / or the first portion. In particular, the first portion of the conductive cover layer may be disposed on top of the electrically conductive layer structure (particularly on the pad of the electrically conductive layer structure), while the second portion of the conductive cover layer may be located on the sidewall of the electrically conductive layer structure (particularly on the sidewall of the pad of the electrically conductive layer structure). In combination, the integral first and second portions of the conductive cover layer may surround, clamp, or grip the pad for mechanical anchoring. This can improve the mechanical integrity of the entire stack and can serve as a further measure to prevent delamination.

[0057] In this embodiment, the conductive cover layer covers at least a portion of the upper, side, and bottom surfaces of at least one electrically conductive layer structure. Specifically, the conductive cover layer covers at least a portion of the upper, side, and bottom surfaces of the exposed portions of the first and / or second portions. In this configuration, the conductive cover layer can even extend around these three surface regions at the top, bottom, and sidewalls, which further enhances the stable anchoring effect of the conductive cover layer. This structure ensures the mechanical stability and electrical performance of the welded structure, thereby preventing solder from spreading in other directions and ensuring sufficient volume in the vertical direction.

[0058] In this embodiment, the thin layer is a circumferential extension of the covering conductive layer. Therefore, the thin layer can extend integrally from the covering conductive layer as a lateral appendage. This integral molding of the thin layer and the covering conductive layer enhances the mechanical integrity of the stack. Furthermore, it can provide an interlocking structure at the edge regions of the covering conductive layer, thereby anchoring not only the electrical conductive layer structure and the covering conductive layer itself.

[0059] In one embodiment, the circumferential extension extends from the covering conductive layer toward the inner portion of the covering conductive layer. Specifically, the circumferential extension forming a thin layer of the covering conductive layer may extend from a side portion of the covering conductive layer toward the center portion of the covering conductive layer.

[0060] In one embodiment, the thickness of the circumferential extension decreases toward the interior portion covering the conductive layer. Therefore, the circumferential extension forming the thin layer can taper toward its free end.

[0061] In one embodiment, the stack includes a plurality of electrically insulating layer structures, wherein at least one electrically conductive layer structure is at least partially sandwiched between at least two of the plurality of electrically insulating layer structures. Therefore, the multilayer stack can be formed from a plurality of electrically insulating layer structures having electrically conductive layer structures therebetween, and at least one thin layer located between the electrically conductive layer structures and one or more of the electrically insulating layer structures.

[0062] In an embodiment, at least one electrically conductive layer structure comprises multiple portions, each of which has a corresponding thin layer. For example, corresponding thin layers can be formed on the top and bottom of the electrically conductive layer structure. This can suppress the tendency for voids to appear above and below the electrically conductive layer structure, and thus for delamination. For example, the action of a laser during the processing of a component carrier may loosen the insulating layer structure. Therefore, it may be advantageous to improve mechanical integrity due to multiple thin layers.

[0063] In this embodiment, the thin layers are disposed at the same vertical height, specifically on the same main surface. Therefore, the thin layers can be arranged side-by-side on the same horizontal main surface of the conductive layer structure. The different thin layers can be separated laterally. Each of the different thin layers can fill a corresponding gap or void between the conductive layer structure and the electrical insulating layer structure, and thus protects the component carrier from delamination.

[0064] In this embodiment, the thin layer is disposed at different vertical heights, specifically on different main surfaces. Therefore, the thin layer can be disposed on both the upper and lower main surfaces of the conductive layer structure, providing dual protection against delamination above and below the conductive layer structure.

[0065] In this embodiment, the thin layers have the same thickness and / or the same planar elongation. Alternatively, the thin layers may have different thicknesses and / or different planar elongations. The thickness and planar elongation of each thin layer can be adjusted by the processing conditions during the manufacturing process, and in particular, by the processing conditions during surface treatment. Thin layers with the same thickness and / or the same planar elongation can form stacks with high symmetry, thereby effectively reducing the occurrence of warpage.

[0066] In an embodiment, the thin layer is longer above at least one electrically conductive layer structure than below it. This configuration may be particularly relevant for thin layers at the corresponding walls of cavities within a stack. For example, on the sidewalls of the stack, a larger gap may form above a portion of the electrically conductive layer structure due to the potentially severe weakening of the stack in that region by laser ablation during cavity formation, resulting in a longer gap and thus a longer thin layer to fill that gap. In contrast, at the bottom of the cavity below the electrically conductive layer structure, this phenomenon may be absent or less pronounced, resulting in a shorter gap and thus a shorter thin layer to fill that gap.

[0067] In an embodiment, the component carrier comprises a stack of at least one electrically insulating layer structure and at least one electrically conductive layer structure. For example, the component carrier may be a laminate of the aforementioned one or more electrically insulating layer structures and one or more electrically conductive layer structures, particularly a laminate formed by applying mechanical pressure and / or thermal energy to the aforementioned one or more electrically insulating layer structures and one or more electrically conductive layer structures. The aforementioned stack can provide a plate-like component carrier that provides a large mounting surface for other components while being very thin and compact.

[0068] In this implementation, the component carrier is shaped as a plate. This contributes to a compact design in which the component carrier still provides a large base for the components mounted thereon. In particular, a bare die, as an example of an electronic component, can be surface-mounted onto a thin plate such as a printed circuit board.

[0069] In one embodiment, the component carrier is configured as one of a printed circuit board, a substrate (particularly an IC substrate), and an interposer.

[0070] In the context of this application, the term "printed circuit board" (PCB) can specifically refer to a plate-shaped component carrier formed by laminating multiple electrically conductive layer structures and multiple electrically insulating layer structures, for example, by applying pressure and / or supplying heat. As preferred materials for PCB technology, the electrically conductive layer structures can be made of copper, while the electrically insulating layer structures can include resin and / or glass fiber, i.e., so-called prepreg or FR4 material. The various electrically conductive layer structures can be connected to each other in a desired manner by forming holes through the laminate, for example, by laser drilling or mechanical drilling, and partially or completely filling the holes with an electrically conductive material (particularly copper), thereby forming vias or any other through-hole connections. The filled holes connect the entire stack (through-hole connections extending through multiple layers or the entire stack), or the filled holes can connect at least two electrically conductive layers, referred to as vias. Similarly, optical interconnects can be formed through the various layers of the stack to receive electro-optical circuit boards (EOCBs). Printed circuit boards are typically configured to house one or more components on one or both opposing main surfaces of a board-shaped printed circuit board. The one or more components can be soldered to the respective main surfaces. The dielectric portions of the PCB may include resin with reinforcing fibers, such as glass fiber.

[0071] In this embodiment, the component carrier is an integrated circuit substrate. In the context of this application, the term "integrated circuit substrate" (IC substrate) can specifically refer to a component carrier whose size and spacing are adjusted according to the requirements of the integrated circuit components (particularly semiconductor chips) mounted thereon. The IC substrate can be a relatively small component carrier relative to a PCB, on which one or more integrated circuit components can be mounted, and which can serve as a connector between one or more chips and the PCB or be inserted into a socket mounted on the PCB. For example, the IC substrate can have approximately the same size as the electronic components to be mounted thereon (e.g., in the case of a chip-scale package (CSP)). In another embodiment, the IC substrate can be larger than the allocated components (e.g., in a flip-chip ball grid array (FCBGA) configuration). More specifically, the IC substrate can be understood as a carrier for electrical connections or electrical networks, and a component carrier with a relatively high density of laterally and / or vertically arranged connections, comparable to a printed circuit board (PCB). Laterally arranged connections are, for example, conductive paths, while vertical connections can be, for example, drilled holes. These lateral and / or vertical connectors are arranged within the IC substrate and can be used to provide electrical, thermal, and / or mechanical connections between accommodated or unaccommodated components (such as bare wafers), particularly IC chips, and printed circuit boards or intermediate layers. The dielectric portion of the IC substrate may include resin with reinforcing particles (e.g., reinforcing spheres, particularly glass spheres). The spacing of the IC substrate, i.e., the distance between corresponding edges of two adjacent metal structures, may not exceed 150 µm, particularly 100 µm. In contrast, the spacing of certain types of PCBs may be at least 200 µm, particularly at least 300 µm.

[0072] The substrate or interlayer may include or be composed of at least one of the following: glass; silicon (Si); and / or an image-enhancing or dry-etchable organic material, such as an epoxy-based laminate (e.g., an epoxy-based laminate film); or a polymer compound (which may or may not include photosensitive and / or thermosensitive molecules), such as polyimide or polybenzoxazole.

[0073] In embodiments, at least one electrically insulating layer structure comprises at least one of the following: resins or polymers, such as epoxy resins, cyanate ester resins, benzocyclobutene resins; melamine derivatives; polybenzoxanone (PBO); bismaleimide-triazine resins; polyphenylene derivatives (e.g., based on polyphenylene ether, PPE), polyimide (PI), polyamide (PA), liquid crystal polymers (LCP), polytetrafluoroethylene (PTFE), bisbenzocyclobutene (BCB), and / or combinations thereof. Reinforcing layer structures, such as those made of glass (multilayer glass), such as meshes, fibers, spheres, or other types of filler particles, can also be used to form composite materials. The semi-cured resin combined with the reinforcing agent, such as fibers impregnated with the aforementioned resins, is called a prepreg. These prepregs are typically named according to their properties, such as FR4 or FR5, which describe their flame-retardant properties. While prepregs, particularly FR4, are generally preferred for rigid PCBs, other materials, particularly epoxy-based laminates (e.g., laminated films) or photosensitive dielectrics, can also be used. For high-frequency applications, high-frequency materials such as polytetrafluoroethylene, liquid crystal polymers, and / or cyanate resins are preferred. In addition to these polymers, low-temperature co-fired ceramics (LTCC) or other low, very low, or ultra-low DK materials can be used as electrical insulation structures in component carriers.

[0074] In embodiments, at least one electrically conductive layer structure comprises at least one of the following: copper, aluminum, nickel, silver, gold, palladium, tungsten, titanium, molybdenum, and magnesium. Although copper is generally preferred, other materials or their coating schemes, particularly those coated with superconducting materials or conductive polymers, are also possible, such as graphene or poly(3,4-ethylenedioxythiophene) (PEDOT).

[0075] At least one component may be selected from the following: a non-electrically conductive inlay, an electrically conductive inlay (e.g., a metallic inlay, preferably including copper or aluminum), a heat transfer unit (e.g., a heat pipe), an optical guiding element (e.g., an optical waveguide or optical conductor connector), an electronic component, or a combination thereof. The inlay may be, for example, a metal block (IMS inlay) with or without an insulating material coating, which may be surface-mounted for heat dissipation purposes. Suitable materials are defined by their thermal conductivity, which should be at least 2 W / mK. Such materials are typically based on, but not limited to, metals, metal oxides, and / or ceramics, such as copper, alumina (Al₂O₃), or aluminum nitride (AlN). Other geometries with increased surface area are also frequently used to improve heat exchange capacity. In addition, components can be active electronic components (having at least one implemented pn junction), passive electronic components such as resistors, inductors, or capacitors, electronic chips, storage devices (e.g., DRAM or other data memories), filters, integrated circuits (e.g., field-programmable gate arrays (FPGAs), programmable array logic (PALs), general-purpose array logic (GALs), and complex programmable logic devices (CPLDs)), signal processing components, power management components (e.g., field-effect transistors (FETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, junction field-effect transistors (JFETs), or insulated-gate field-effect transistors). Transistors (IGFETs), all based on semiconductor materials such as silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), gallium oxide (Ga2O3), indium gallium arsenide (InGaAs), indium phosphide (InP), and / or any other suitable inorganic compound, optoelectronic interface elements, light-emitting diodes, optocouplers, voltage converters (e.g., DC / DC converters or AC / DC converters), cryptographic components, transmitters and / or receivers, electromechanical transducers, sensors, actuators, microelectromechanical systems (MEMS), microprocessors, capacitors, resistors, inductors, batteries, switches, cameras, antennas, logic chips, and energy harvesting units. However, other components can be surface-mounted onto component carriers. For example, magnetic elements can be used as components. Such magnetic elements can be permanent magnets (e.g., ferromagnetic, antiferromagnetic, multiferroic, or ferrimagnetic elements, such as ferrite cores) or paramagnetic elements. However, components can also be IC substrates, interposers, or other component carriers, such as those in a board-in-board configuration. Components can be surface-mounted onto component carriers. Furthermore, other components, particularly those that generate and emit electromagnetic radiation and / or are sensitive to electromagnetic radiation propagating from the environment, can also be used as components.

[0076] In one embodiment, the component carrier is a laminated component carrier. In this embodiment, the component carrier is a multilayered composition that is stacked and connected together by applying pressure and / or heat.

[0077] After the internal layer structure of the component carrier has been treated, one or more additional electrically insulating and / or electrically conductive layer structures can be used to cover one or both opposite main surfaces of the treated layer structure in a symmetrical or asymmetrical manner (particularly by lamination). In other words, stacking can continue until the desired number of layers is obtained.

[0078] After the stacked structure of the electrical insulation layer and the electrical conductivity layer is formed, the surface of the obtained layer structure or component carrier can be treated.

[0079] Specifically, regarding surface treatment, an electrically insulating solder resist can be applied to one or both opposing main surfaces of the laminate or component carrier. For example, this solder resist can be formed over the entire main surface, and the resist layer can then be patterned to expose one or more electrically conductive surface portions that will be used to electrically connect the component carrier to electronic peripherals. The surface portions of the component carrier still covered with solder resist, particularly those containing copper, can be effectively protected against oxidation or corrosion.

[0080] Regarding surface treatment, a surface treatment portion can also be selectively applied to the exposed electrically conductive surface portion of the component carrier. This surface treatment portion can be an electrically conductive covering material on the exposed electrically conductive layer structure (e.g., pads, conductive traces, etc., particularly including or made of copper) on the surface of the component carrier. If this exposed electrically conductive layer structure is not protected, the exposed electrically conductive component carrier material (especially copper) may be oxidized, resulting in lower reliability of the component carrier. The surface treatment portion can then be formed as a joint between, for example, a surface-mounted component and the component carrier. The surface treatment portion functions to protect the exposed electrically conductive layer structure (especially copper circuitry) and enables a connection process with one or more components, for example, by soldering. Examples of suitable materials for the surface treatment portion are organic solderable corrosion inhibitors (OSP), electroless nickel immersion gold (ENIG), electroless nickel immersion palladium immersion gold (ENIPIG), gold (especially hard gold), electroless tin, nickel-gold, nickel-palladium, etc.

[0081] The above-defined aspects and other aspects of the present invention will become apparent from the examples of embodiments described below, and will be explained with reference to these examples of embodiments. Attached Figure Description

[0082] Figure 1 A cross-sectional view of a portion of a component carrier according to an exemplary embodiment of the present invention is shown.

[0083] Figure 2 A cross-sectional view of a portion of a component carrier according to another exemplary embodiment of the present invention is shown.

[0084] Figure 3 A cross-sectional image of a portion of a component carrier according to an exemplary embodiment of the present invention is shown.

[0085] Figure 4 A cross-sectional view of a preform of a component carrier according to an exemplary embodiment of the present invention is shown.

[0086] Figure 5 Cross-sectional and detailed views of a component carrier according to an exemplary embodiment of the present invention are shown. This component carrier can be based on... Figure 4 It is obtained by preforming parts.

[0087] Figure 5A An exemplary embodiment of the present invention is shown in the completed Figure 5 A cross-sectional view of the component carrier after the initial component is embedded and before the surface mounting of other components.

[0088] Figure 5B A cross-sectional view of a component carrier after component embedding and after surface mounting of other components, according to an exemplary embodiment of the present invention, is shown.

[0089] Figure 6 A cross-sectional image of a portion of a component carrier according to an exemplary embodiment of the present invention is shown.

[0090] Figure 7 A cross-sectional view of a portion of a component carrier according to another exemplary embodiment of the present invention is shown.

[0091] Figure 8 A cross-sectional image of a portion of a component carrier according to an exemplary embodiment of the present invention is shown.

[0092] Figure 9 It shows the Figure 8 The image displays details.

[0093] The illustrations in the accompanying drawings are all schematic. In different drawings, similar or identical elements are provided with the same reference numerals. Detailed Implementation

[0094] Before describing the exemplary embodiments in further detail with reference to the accompanying drawings, basic considerations will be summarized, based on which the exemplary embodiments of the present invention were developed.

[0095] In an exemplary embodiment of the present invention, a component carrier (e.g., a PCB or IC substrate) is provided. The component carrier may include a laminated stack having one or more electrically conductive layers (e.g., patterned or deposited copper) and at least one electrically insulating layer (e.g., one or more resin sheets containing epoxy resin and optionally reinforced with glass fibers or glass spheres). The electrically conductive layers are in direct contact with the insulating layers along a contact bonding surface. Furthermore, a thin layer may be positioned between the conductive and insulating layers adjacent to the contact bonding surface. This thin layer can help reduce or even minimize gaps between the layer structures, thereby reducing the risk of delamination, warping, and other problems, and thus improving reliability. This thin layer can be easily formed by adjusting manufacturing parameters; in particular, it can be easily formed by adjusting manufacturing parameters during a surface treatment process and can be obtained as a byproduct of this process, thus requiring no additional steps and therefore keeping the manufacturing process fast and simple.

[0096] More specifically, for example, a copper pad can be formed on the junction of the epoxy resin sheet. Palladium residue may remain due to the etching process. Additionally, a surface treatment layer can be formed by plating. Due to the etching of the conductive layer structure, a gap may remain between the resin sheet and the copper pad. During the formation of the surface treatment layer, this gap can be partially or completely filled by a thin layer as the residual palladium ions in the resin react with the chemicals of the surface treatment process. For example, the gap can be partially or completely filled along a length of 10µm to 20µm, or, for instance, along a length of 15µm. This thin layer may include the material of the surface treatment layer; for example, due to the use of ENIG or ENIPIG processes, the thin layer may include nickel, a nickel-palladium mixture, or other metallic components. Additionally or alternatively, the thin layer may include phosphorus. When this thin layer partially or completely fills the gap between the electrically insulating layer structure and the electrically conductive layer structure, this can reduce the risk of delamination that may be initiated or exacerbated by the voids. Furthermore, the thin layer can protect the stacked components through an anchoring effect. When a thin layer covers two or even three sides of the connection structure of a stacked component—for example, when the thin layer covers the bottom, top, and sides of the connection structure of the stacked component—this anchoring effect can be achieved through the thin layer. This also reduces the risk of short circuits. More advantageously, the growth of the thin layer can be focused on or even limited to the undercut region, and the filling of the undercut region with the thin layer can provide a protective layer to prevent copper ions from migrating from the undercut region and provide comprehensive protection for the underlying copper layer. In addition to the above advantages, the outer surface may not have such a thin layer.

[0097] According to an exemplary embodiment, a component carrier is provided, the component carrier including a stack and a thin layer structure, the stack including at least one electrically conductive layer structure and at least one electrically insulating layer structure, the at least one electrically conductive layer structure being directly disposed in contact with the at least one electrically insulating layer structure to define a contact bonding surface, the thin layer structure being sandwiched between the at least one electrically conductive layer structure and the at least one electrically insulating layer structure, the thin layer being disposed next to the contact bonding surface.

[0098] In embodiments, the at least one electrically conductive layer structure can be directly disposed on the main surface of the at least one electrically insulating layer structure. For example, a thin layer is disposed on the main surface. Specifically, the at least one electrically conductive layer structure can be at least partially embedded in the at least one electrically insulating layer structure. In embodiments, the thin layer is disposed on the portion of the at least one electrically conductive layer structure embedded in the at least one electrically insulating layer structure. For example, the thin layer is in direct contact with the contact bonding surface. For example, the thin layer and the contact bonding surface are separated from each other by planar space. Specifically, an additional volume portion is disposed between the at least one electrically conductive layer structure and the at least one electrically insulating layer structure along the thickness direction of the stack, and the additional volume portion is disposed between the thin layer and the contact bonding surface along a planar extension parallel to one of the main surfaces of the stack. In embodiments, the additional volume portion is empty (especially a vacuum). In embodiments, the additional volume portion is filled with fluid, especially air. For example, the surface of the thin layer is parallel to the surface of the contact bonding surface. For example, the surface of the thin layer is coplanar with the contact bonding surface. In embodiments, the opposite surface of the thin layer has an irregular shape and / or a rounded shape. Specifically, the thin layer is embedded in the at least one electrically conductive layer structure (especially when the at least one electrically conductive layer structure is disposed on the at least one electrically insulating layer structure). For example, the thin layer is embedded in the at least one electrically insulating layer structure (especially when the at least one electrically conductive layer structure is embedded in the at least one electrically insulating layer structure). In embodiments, the thin layer is partially embedded in the at least one electrically insulating layer structure (especially when the at least one electrically conductive layer structure is embedded in the at least one electrically insulating layer structure). For example, the at least one electrically conductive layer structure includes a pad. Specifically, the at least one electrically conductive layer structure includes a frame planar shape. For example, the frame planar shape is configured to partially define the sidewalls of a cavity in the lateral direction (this may also include a cavity in which the conductive layer is disposed at an intermediate thickness portion). In embodiments, the frame is a closed frame. In another embodiment, the frame is an open frame. Specifically, the thin layer has a planar extension defining a circumferential portion that follows the outer contour of the at least one electrically conductive layer structure, and the thin layer is sandwiched within the at least one electrically insulating layer structure by means of the at least one electrically conductive layer structure. In one embodiment, the thin layer may follow the outer contour of the at least one electrically conductive layer structure (wherein, "follow" in this case means that the thin layer extends from the outer contour of the at least one electrically conductive layer structure toward the inside of the structure). In another embodiment, the thin layer may be sandwiched between the at least one electrically insulating layer structure and the pad.For example, the thin layer may follow the inner contour of the at least one electrically conductive layer structure (wherein, "following" in this case means that the thin layer extends from the inner contour of the at least one electrically conductive layer structure to the outside of the structure). In an embodiment, the thin layer may be sandwiched between the at least one electrically insulating layer structure and a frame that, in particular, partially defines the sidewalls of the cavity laterally. For example, the thin layer may follow the outer contour of the at least one electrically conductive layer structure completely or partially. In an embodiment, the stack includes a cavity. For example, a first portion of the at least one electrically conductive layer structure is exposed inside the cavity. For example, a second portion of the at least one electrically conductive layer structure is partially exposed inside the cavity. In particular, the bottom of the cavity is partially defined by the at least one electrically insulating layer structure. In an embodiment, the thin layer is disposed between the first portion and / or the exposed second portion and the at least one electrically conductive layer structure that defines the bottom of the cavity. For example, the bottom of the cavity is partially defined by the second portion of the at least one electrically conductive layer structure. In an embodiment, the thin layer is disposed between the unexposed second portion and the at least one electrically insulating layer structure, in particular, the at least one electrically insulating layer structure that at least partially defines the sidewalls of the cavity. Specifically, a first thin layer is disposed between a first portion of the at least one electrically conductive layer structure and the at least one electrically insulating layer structure defining the bottom of the cavity, and / or, a second thin layer is disposed between an exposed second portion of the at least one electrically conductive layer structure and the at least one electrically insulating layer structure defining the bottom of the cavity, and / or, a third thin layer is disposed between the unexposed second portion and an electrically insulating layer structure that partially embeds the second portion and partially defines the sidewalls of the cavity. In embodiments, the planar width of the first and / or second thin layers differs from the planar width of the third thin layer, particularly being greater than the planar width of the third thin layer. In particular, the thickness of the first and / or second thin layers differs from the thickness of the third thin layer, particularly being greater than the thickness of the third thin layer. For example, the third portion of the at least one electrically conductive layer structure is completely embedded in the stack and is not exposed inside the cavity. In embodiments, the third portion has no thin layer. In embodiments, the thickness of the thin layer is 0.05 to 1 (particularly 0.05 to 0.2) of the thickness of the at least one electrically conductive layer structure (particularly 1 / 10 of the thickness of the conductive layer). In embodiments, when the pad thickness is very small, for example, about 2 µm, the thin layer can have a thickness similar to that of the pad. In embodiments, the planar width of the first and / or second thin layer is in the range of 2 µm to 10 µm. Specifically, the planar width of the third thin layer is in the range of 10 µm to 20 µm. In embodiments, the thin layer comprises a conductive material. For example, the thin layer comprises a material having a conductivity different from that of the material of the at least one electrically conductive layer structure.In embodiments, the thin layer comprises a material different from that of the at least one electrically conductive layer structure. For example, the at least one electrically conductive layer structure, particularly the first and / or second portion, includes a covering conductive layer. For example, the covering conductive layer encloses the thin layer between the at least one electrically insulating layer structure, the at least one electrically conductive layer structure, and the covering conductive layer. In particular, the covering conductive layer comprises multiple layers. In embodiments, the covering conductive layer is incorporated into the thin layer. For example, one of the multiple layers included in the covering conductive layer is incorporated into the thin layer. For example, the covering conductive layer forms a lateral wall surrounding the at least one electrically conductive layer structure, particularly surrounding the first portion and / or the exposed second portion. In embodiments, the covering conductive layer covers a portion of the upper surface, side surface, and bottom surface of the at least one electrically conductive layer structure, particularly covering a portion of the upper surface, side surface, and bottom surface of the first portion and / or the exposed second portion. In particular, the thin layer is a circumferential extension of the covering conductive layer. For example, the circumferential extension extends from the covering layer into the interior portion of the conductive structure. For example, the thickness of the circumferential extension decreases into the interior portion of the conductive structure. In one embodiment, the stack includes multiple insulating layers, with the at least one electrically conductive layer structure at least partially sandwiched between at least two of the multiple insulating layers. Specifically, the conductive structure may have multiple portions, each having a corresponding thin layer. These thin layers may be located at the same level, on the same main surface, at different levels, and / or on different main surfaces. In one embodiment, the thin layers have the same thickness and / or the same planar extension. Specifically, the thin layers have different extensions. For example, the thin layers may be located at different levels. Above the electrically conductive layer structure, the corresponding thin layer may be thick and long. Below the electrically conductive layer structure, the corresponding thin layer may be thick and short.

[0099] Figure 1 A cross-sectional view of a portion of a component carrier 100 according to an exemplary embodiment of the present invention is shown. Figure 4 and Figure 5 The text shows that it can be used to... Figure 1 An illustrative exemplary embodiment of the complete or more portion of the structurally integrated component carrier 100.

[0100] according to Figure 1A component carrier 100 is provided, which may be, for example, a printed circuit board or an integrated circuit substrate. The component carrier 100 includes a stack 102, which may be a laminated stack. The stack 102 may include one or more electrically insulating layer structures 104 (e.g., optionally including a patterned epoxy resin layer reinforced with glass fiber) and one or more electrically conductive layer structures 106 (e.g., structured metal layers and / or metal through-connection structures, such as including copper and / or nickel and / or other metallic materials).

[0101] The electrically conductive layer structure 106 may include one or more metal pads 108. Figure 1 The diagram shows only one pad, which may be partially disposed above or on the upper main surface 130 of the corresponding electrical insulating layer structure in the electrical insulating layer structure 104. For example, the pad 108 may be made of copper. The pad 108 may include multiple copper layers (the multiple copper layers may be, for example, three layers formed by different methods, such as a seed layer, a barrier layer, and a patterning layer). Alternatively, the pad 108 may include palladium, titanium, and / or alloys, such as bronze.

[0102] Preferably, the pad 108 may include a curved upper main surface 236. A curved cover conductive layer 110 is disposed on the curved upper main surface 236 of the pad 108. For example, the curved cover conductive layer 110 may be a surface-treated portion, such as comprising nickel, and / or palladium, and / or gold, and is made of, for example, ENEPIG. Alternatively, the curved cover conductive layer 110 may include copper. The curved cover conductive layer 110 may define a non-planar surface 212 on its side facing away from the upper main surface 236 of the pad 108 and the upper main surface 130 of the electrical insulating layer structure 104. Furthermore, the lower main surface 250 of the cover conductive layer 110 facing the upper main surface 236 of the pad 108 and the upper main surface 130 of the electrical insulating layer structure 104 may also define a non-planar surface. As shown, the cover conductive layer 110 includes a central portion 214, which extends along... Figure 1 The vertical component carrier 100 overlaps with the pad 108 in its plan view. The central portion 214 may be radially centered relative to the vertical axis 252 and may be a curved disc-shaped structure. The central portion 214 may be the portion of the conductive layer 110 positioned on the pad 108 and the thin layer 128 described below. In one embodiment, optionally, the central portion 214 may comprise the same material as the pad 108, particularly including copper; the peripheral portion 216 described below may be made of the same or different material as the pad 108 and / or the central portion 214.

[0103] Furthermore, the conductive cover 110 includes the aforementioned peripheral portion 216, which extends outward from the central portion 214 or laterally. The peripheral portion 216 may be radially peripheral relative to the vertical axis 252 or may be located away from the vertical axis 252. The peripheral portion 216 may be a portion of the conductive cover 110 positioned on the electrical insulating layer structure 104. The outline of the peripheral portion 216 may be defined by nickel plating during the ENEPIG process. Since the dielectric surface around the pad region may have some residual palladium ions, nickel can react with the palladium ions in this region. Therefore, the lower portion of the conductive cover 110 can be seen located on the main surface 130 of the electrical insulating layer structure 104. If the plating of the lower portion and the conductive cover 110 begins and ends at the same time, the thickness of the lower portion may be the same as the thickness of the conductive cover 110. The thickness of the lower portion may differ from the thickness of the conductive cover 110 due to different plating times. The angle between the central portion 214 and the peripheral portion 216 can be a right angle. In another embodiment, the angle may be different from a right angle. Furthermore, the peripheral portion 216 may include at least two sub-portions, each having a different thickness and / or another angle.

[0104] The conductive covering layer 110, particularly the main surface of the conductive covering layer 110, can be partially disposed on the main surface 130 of the electrically insulating layer structure 104, wherein the peripheral portion 216 is in direct contact with the main surface 130. Figure 1 The junction between the peripheral portion 216 and the central portion 214 is schematically represented by dashed line 254. The central portion 214 and the peripheral portion 216 may be integrally formed and made of the same material. The peripheral portion 216 may have an annular or circular shape; more specifically, the peripheral portion 216 may be closed circumferentially and extend along the entire outer periphery of the central portion 214. Figure 1 (Not shown in the image). For example, it can also be found from... Figure 1As can be seen, the surface profile, morphology, and / or curvature characteristics of the peripheral portion 216 may differ from or be different from the surface profile, morphology, and / or curvature characteristics of the central portion 214. The peripheral portion 216 may or may not follow the profile of the main surface 130 of the electrical insulating layer structure 104. The central portion 214 may follow the profile of the main surface 130 of the electrical insulating layer structure 104 and / or the main surface 236 of the pad 108. More specifically, the non-planar surface 212 covering the conductive layer 110 may include recessed non-planar portions (i.e., concave portions) and / or protruding non-planar portions (i.e., convex portions), which may be arranged at the central portion 214. The recessed and / or protruding features of the non-planar surface 212 become more pronounced towards the central portion compared to the portion away from the pad 108 and the central portion of the conductive layer 110. For example, the maximum width of the peripheral portion 216 in the horizontal plane, particularly along the central portion, is significantly greater. Figure 1 Maximum width and maximum thickness in the horizontal direction, especially along Figure 1 The ratio between the maximum thicknesses in the vertical direction is preferably in the range of 2 to 4.

[0105] The thickness of pad 108 typically decreases in the direction away from its central portion. Alternatively, the thickness of pad 108 may be constant (not shown). Furthermore, the lateral end portions of pad 108 may have a sharp profile 268 (or alternatively, a rounded profile, not shown) and lack vertical sidewalls to avoid a 90° angle at the outer surface of the pad, thereby suppressing stress peaks and cracking. The portion of the main surface 130 of the electrical insulating layer structure 104 that overlaps with the thin layer 128 located on the bottom of pad 108 may be inclined in a curved manner toward the central portion of pad 108 and away from the covering conductive layer 110. More specifically, the portion of the main surface 130 of the electrical insulating layer structure 104 that overlaps with the thin layer 128 located on the bottom of pad 108 may be inclined downwards to increase the distance from the covering conductive layer 110, which is oriented upwards toward the vertical axis 252.

[0106] As shown, the electrically conductive layer structure 106 may also include one or more vertical connecting portions 238 embedded in the electrically insulating layer structure 104. Figure 1 The vertical connecting portion 238 shown is connected to or stacked with the pad 108. Figure 1 The vertical connection portion 238 can be a metallized frustoconical via, such as a copper-filled laser via. The vertical connection portion 238 can be connected to another metal connection structure 266 on its bottom side. This metal connection structure 266 can be a flat pad, an electrically conductive trace, a metal pillar, a part of a patterned metal foil, another metallized laser via, etc.

[0107] A seed layer 222 may be laterally disposed between the vertical connection portion 238 and the electrical insulation layer structure 104. The seed layer 222 may be a thin metal layer formed without electroplating and facilitates the formation of metal in the vertical connection portion 238 by electroplating. More specifically, the seed layer 222 may partially or completely line the sidewalls of holes in the electrical insulation layer structure 104, such as those formed by laser drilling or mechanical drilling. Optionally, the seed layer 222 may contact the pad 108, but depending on… Figure 1 The seed layer 222 does not directly contact the peripheral portion 216. The seed layer 222 can be disposed below the main surface 130 of the electrical insulation layer structure 104 in a vertical and horizontal direction. The seed layer 222 can contact the lateral sidewalls of the electrical insulation layer structure 104.

[0108] An additional conductive structure 224, such as a solder bump, may be provided on the non-planar surface 212, which covers only a portion of the central portion 214. Preferably, the additional conductive structure 224 is a solder structure, but alternatively, it may be an electrically conductive adhesive or sintering material. The surface area of ​​the additional conductive structure 224 in the horizontal plane is smaller than the surface area of ​​the covering conductive layer 110. The material of the additional conductive structure 224 (the primary material of which may be tin) may differ from the materials of the covering conductive layer 110 (which may include nickel) and the pad 108 (which may include copper). The additional conductive structure 224 may form at least a portion of a connection structure for connecting the covering conductive layer 110 to an additional electrically conductive layer structure 226, such as an additional pad (e.g., a pad made of copper). Therefore, Figure 1 The stacked metal structure can provide a welded connection between pads and has a surface-treated section between the pads.

[0109] Figure 1 Component 232, shown only schematically, can be assembled with stack 102 and may include an additional conductive layer structure 226, which itself may include at least one additional pad and may be covered with a diffusion layer (not shown in detail). This additional conductive layer structure 226 may include the same material as the pad 108 and / or the covering conductive layer 110. The contact pads of component 232 may also include surface treatments such as ENIG or ENIPIG. For example, component 232 may be an electronic component, such as a semiconductor wafer.

[0110] Examples of component carrier 100 include printed circuit boards or substrates for microelectronic devices, where precise control over the geometry and material joints of conductive pads and layers is required or desired to ensure reliable electrical and mechanical performance. The technical advantages of this structure include: improved electrical connectivity and mechanical stability due to the non-planar and multi-part structure covering the conductive layer 110; enhanced solderability and reliability of the joints due to the customized surface profile; and the ability to adapt to different component assembly configurations. Figure 1 This implementation reliably suppresses undesirable phenomena such as stress peaks, crack formation, delamination, and / or voids. The recessed and protruding features allow for adjustment of stress distribution and ensure better bonding, while the use of different materials for the additional conductive structure 224 enables compatibility with various assembly processes and component types.

[0111] The thin layer 128 embedded between the pad 108 of the electrically insulating layer structure 104 and the electrically conductive layer structure 106, and the covering conductive layer 110, will be described in more detail below. Typically, the thin layer 128 can be disposed between the electrically insulating layer structure 104 and the electrically conductive layer structure 106. According to... Figure 1 In the component carrier 100, each portion of the electrically conductive layer structure 106 is positioned to directly contact each portion of the electrically insulating layer structure 104. Specifically, Figure 1 The lower electrical insulating layer structure 104 and the covered conductive layer 110 of the distributed electrical conductive layer structure 106 form a contact bonding surface 132 therebetween. Figure 1 The lower electrically insulating layer structure 104 and the cover conductive layer 110 of the allocated electrically conductive layer structure 106 are in direct physical contact at the contact bonding surface 132. Each of the two thin layers 128 shown is sandwiched between the aforementioned electrically conductive layer structure 106 and the aforementioned electrically insulating layer structure 104, and is arranged adjacent to the respective contact bonding surface 132. Each thin layer 128 is specifically arranged on the main surface 130 of the electrically insulating layer structure 104, and may also contact a portion of the electrically conductive layer structure 106 embedded in the electrically insulating layer structure 104. Each thin layer 108 is in direct contact with the allocated contact bonding surface 132, and each thin layer 108 is partially embedded in the electrically conductive layer structure 106 and partially embedded in the electrically insulating layer structure 104. Furthermore, the thin layer 128 may be in direct contact with the seed layer 222. Specifically, the thin layer 128 can be in direct contact with the seed layer 222 at the sidewall of the electrically insulating layer structure 104.

[0112] The ratio of the maximum thickness of the thin layer 128 to the maximum thickness of the electrically conductive layer structure 106 constituting the pad 108 can be in the range of 0.05 to 0.2, for example, 0.1. Depending on the application and the manufacturing process of the component carrier 100, the corresponding thin layer 128 extends along... Figure 1 The horizontal width is in the range of 2µm to 20µm, and specific embodiments have a width of 2µm to 10µm or 10µm to 20µm. The thin layer 128 may include an electrically conductive material, such as nickel, or be made of an electrically conductive material, such as nickel, and the thin layer 128 may be made of a material with a different conductivity than the copper material of the pad 108 of the electrically conductive layer structure 106.

[0113] Thin layer 128 can be formed during the formation of a surface-treated portion in the form of a conductive layer 110, and has significant technical advantages. Thin layer 128 can suppress delamination and warping at the junction between the electrically insulating layer structure 104 and the electrically conductive layer structure 106 sandwiching the respective thin layer 128, thereby improving the mechanical and electrical reliability of the overall structure. For example, in a printed circuit board or integrated circuit substrate, the presence of one or more thin layers 128 can prevent the connected layers 104, 106 from separating under thermal or mechanical stress, and can enhance electrical performance by providing stable and reliable contact joints 132 while filling adjacent gaps with the material of the thin layer 128.

[0114] Figure 2 A cross-sectional view of a portion of a component carrier 100 according to another exemplary embodiment of the present invention is shown.

[0115] In particular, Figure 2 Implementation methods and basis Figure 1 The difference in the implementation method is that, according to Figure 2The peripheral portion 216 may contain a circumferentially closed protruding sub-portion 218 and a circumferentially closed recessed sub-portion 220. The protruding sub-portion 218 may also be represented as a metal foot (e.g., including one or more surface-treated materials, such as nickel, gold, etc.). The recessed sub-portion 220 may be laterally arranged between the protruding sub-portion 218 and the central portion 214. Therefore, the protruding sub-portion 218 may be positioned further away from the central portion of the pad 108 than the recessed sub-portion 220. The protruding sub-portion 218 may also be closer in the vertical direction to the main surface 130 of the electrical insulating layer structure 104 than the highest end of the central portion 214. The recessed sub-portion 220 is closer in the vertical direction to the main surface 130 than the protruding sub-portion 218. The recessed sub-portion 220 of the peripheral portion 216 may have a concave surface. The protruding sub-portion 218 of the peripheral portion 216 may have a convex surface. The recessed sub-portion 220 may be at least one localized recess located within the covering conductive layer 110. In an example, the recessed sub-portion 220 may be a closed annular recess surrounding the highest end of the central portion 214. The protruding sub-portion 218 may be at least one localized protrusion located within the covering conductive layer 110. In an example, the protruding sub-portion 218 may be a closed annular protrusion surrounding the highest end of the central portion 214. The covering conductive layer 110 generally maintains a constant thickness except for the thicker portion located at the peripheral portion 216, i.e., at the protruding sub-portion 218.

[0116] according to Figure 2 An additional conductive structure 224, such as a solder protrusion, may be provided on the non-planar surface 212. This additional conductive structure 224 covers the entire central portion 214 and partially covers the peripheral portion 216. This additional conductive structure 224 is in direct contact with the non-planar surface 212 and may extend to the recessed sub-portion 220, and optionally to the protruding sub-portion 218 of the peripheral portion 216.

[0117] exist Figure 2In this configuration, two thin layers 128 can be sandwiched between the electrical insulating layer structure 104 on the bottom side, the pad 108 on the top side, and the cover conductive layer 110 on the lateral side. Other configurations of the thin layers 128 are also possible. The lower first surface of each respective thin layer 128 is parallel and coplanar with the horizontal contact engagement surface 132, thereby ensuring precise alignment between the electrical conductive layer structure 106 and the electrical insulating layer structure 104 at the joint. The upper second surface of each respective thin layer 128, opposite to the lower first surface, can be irregular or rounded, thereby contributing to improved adhesion and mechanical interlocking with adjacent layers. The thin layers 128 are surrounded by the lower electrical insulating layer structure 104, the pad 108 of the upper electrical conductive layer structure 106, and the cover conductive layer 110 on the lateral side of the electrical conductive layer structure 106, thereby providing robust encapsulation to enhance the stability of the joint.

[0118] The conductive cover layer 110—which may be a surface-treated portion such as ENIPIG—may include multiple sublayers. One of these sublayers, for example, a nickel-containing sublayer, is bonded to a corresponding thin layer 128, thereby establishing a continuous conductive path and enhancing structural integrity. The thin layer 128 serves as a circumferential extension of the conductive cover layer 110, wherein the extension protrudes from the conductive cover layer 110 toward the interior of the conductive cover layer, and the thickness of the extension gradually decreases in the protruding direction. The conductive cover layer 110, together with the integrally connected thin layer 128, forms a surrounding structure around the pad 108. This improves the mechanical integrity and stability of the component carrier 100.

[0119] Figure 2 Thin layers 128 are arranged at the same vertical level, and more specifically, they are arranged on the common main surface 130 of the electrical insulation layer structure 104. The thin layers 128 can have the same thickness distribution and planar extensions, thus ensuring the consistency of the entire structure. The thin layers 128 can be arranged in a mirror-like configuration. This symmetry can suppress warping and delamination. Thin layers 128 formed during the formation of the surface treatment portion in the form of the covering conductive layer 110 can provide advantages. In particular, the coplanar arrangement and the integration of sublayers into the thin layers 128 can suppress delamination and warping at critical joints. The shape of the thin layers 128, combined with the covering conductive layer 110, enhances mechanical interlocking, wherein the circumferential extensions of the covering conductive layer 110 in the form of thin layers 128 further anchor the structure, thereby reducing the risk of separation under thermal or mechanical stress.

[0120] Figure 3 A cross-sectional image of a portion of a component carrier 100 according to an exemplary embodiment of the present invention is shown.

[0121] Figure 3 The image shows an experimentally obtained cross-section of the manufactured component carrier 100. In region 199, a thin layer 128 exists as a lateral extension of a surface-treated conductive cover layer 110. The conductive cover layer 110, together with the bonded thin layer 128, forms an anchoring structure around the sidewalls of the pad 108 of the electrically conductive layer structure 106, and covers a portion of the upper, side, and bottom surfaces of the pad 108 of the electrically conductive layer structure 106. The roughness of the thin layer 128 facing the electrically insulating layer structure 104 can be higher than the roughness of the thin layer 128 facing the pad 108. The conductive cover layer 110, together with the bonded thin layer 128, can grow with the contour of the electrically conductive layer structure 106 at the corner regions, or react with palladium ions attached to the contour surface at the corner regions to fill the undercut formed by etching the electrically conductive layer structure 106. Furthermore, the conductive cover layer and the thin layer can be connected to fillers exposed on the main surface of the electrically insulating layer structure.

[0122] Figure 4 A cross-sectional view of a preform of a component carrier 100 according to an exemplary embodiment of the present invention is shown.

[0123] The preformed component carrier 100 shown may be an integrated circuit (IC) substrate or a printed circuit board (PCB). The component carrier 100 may include a laminated stack 102 comprising an electrically conductive layer structure 106 and an electrically insulating layer structure 104. For example, the electrically conductive layer structure 106 may include a patterned metal layer (such as a patterned copper foil or a patterned deposited copper layer) and vertical through-connections, such as copper-filled vias, which may be formed by drilling and plating. The electrically insulating layer structure 104 may include a suitable resin (such as a suitable epoxy resin), preferably including reinforcing particles (such as glass fibers or glass beads). For example, the electrically insulating layer structure 104 may be made of prepreg or FR4. The electrically insulating layer structure 104 may also include a resin layer without glass (especially without glass fibers), and / or the electrically insulating layer structure 104 may also include a photosensitive dielectric material.

[0124] The stack 102 has a vertical central portion 356, which may include a core. The core-shaped central portion 356 may include a fully cured dielectric material, such as FR4. On both sides of the central portion 356, stacks 358 and 360 with the aforementioned layered structure may be formed, including the electrically conductive layer structure 106 and the electrically insulating layer structure 104. The electrically conductive layer structures 106 of the stacks 358 and 360 can be connected to each other through at least one vertical through-connection 366 passing through the central portion 356. This vertical through-connection 366 may be, for example, a plated through-hole (in the illustrated embodiment, this plated through-hole is formed by a through-hole extending through the entire thickness of the central portion 356, the through-hole being filled with a metal sleeve, which in turn is filled with a dielectric paste, etc.). According to... Figure 4 The stacked components 102 are vertically symmetrical. Alternatively, the stacked components 102 may be vertically asymmetrical.

[0125] On the top and / or bottom sides of the stack 102, corresponding patterned solder resists 362, 364 may be formed to protect certain portions of the stack 102 from oxidation and to electrically insulate portions located on the top and bottom main surfaces of the component carrier 100. The uppermost and lowermost electrically conductive layer structures 106 of the stack 102 may be exposed relative to the solder resists 362, 364. The exposed portions of the electrically conductive layer structures 106 may be connected to electronic peripherals (such as electronic boards not shown) and / or may be connected to one or more surface mount components (such as semiconductor wafers not shown).

[0126] One (or more) electronic components 232 (see Figure 5 The cavity 112 can be embedded in the cavity formed in the upper portion of the stack 102. The cavity 112 can be formed by laser processing of the stack 102. For example, the horizontal central portion of the cavity 112 can be formed by a first laser processing that operates only in the central portion. The horizontal peripheral portion of the cavity 112 can be formed by a second laser processing that operates along a region that is closed in the circumferential direction around the central region.

[0127] like Figure 4As shown, in the central portion of cavity 112, an additional conductive layer 332, for example made of copper, is formed on the conductive material of the conductive layer structure 106. The peripheral regions of the exposed conductive layer structure 106 within cavity 112 may remain without this additional conductive layer 332. During laser processing to form cavity 112, this additional conductive layer 332 can serve as a laser stopping layer. Therefore, during the formation of cavity 112, this additional conductive layer 332 can prevent or inhibit the laser beam from penetrating into the stack 102. In other embodiments, this additional conductive layer 332 may also be implemented as a surface treatment layer or may be covered by a surface treatment layer (such as...). Figure 1 or Figure 2 A conductive cover layer 110 is used to protect the surface of the conductive layer structure 106.

[0128] Still refer to Figure 4 The cavity 112 is formed (preferably by laser processing) as a blind hole in the upper main surface of the stack 102. The cavity 112 is defined on its bottom side by a generally horizontal bottom wall 114 and laterally by an inclined circumferential side wall 116.

[0129] As shown, the bottom wall 114 partially exposes a first portion 118 of the electrically conductive layer structure 106 located on the electrically insulating layer structure 104. In other words, the electrically conductive layer structure 106 includes a first portion 118 exposed at the bottom wall 114 of the cavity 112. Furthermore, a second portion 120 of the electrically conductive layer structure 106 located on the electrically insulating layer structure 104 partially defines the sidewall 116 of the cavity 112 and is partially exposed to the interior of the cavity 112 at the edge 322 of the bottom wall 114. In addition, the electrically conductive layer structure 106 located on the electrically insulating layer structure 104 also includes a third portion 134 embedded in another electrically insulating layer structure 104 of the stack 102, which is disposed on the main surface 130 of one of the plurality of electrically insulating layer structures 104. Preferably, another electrically insulating layer structure 104 is in direct contact with the electrically insulating layer structure 104 defining a portion of the bottom of the cavity 112. In the example, the electrically insulating layer structure 104 and the other electrically insulating layer structure 104 may comprise the same material. Preferably, at least one of the electrically insulating layer structures 104 is fiberless. Briefly, the first portion 118 corresponds to the portion of the electrically conductive layer structure 106 (located in a horizontal plane) exposed at the bottom wall 114 of the cavity 112. The second portion 120 corresponds to the portion of the same electrically conductive layer structure 106 located at the edge 322 or corner between the bottom wall 114 and the side wall 116 of the cavity 112, wherein the second portion 120 is partially exposed relative to the stack 102 and partially embedded within the stack 102. The third portion 134 corresponds to the portion of the same electrically conductive layer structure 106 fully embedded within the stack 102. The first portion 118, the second portion 120, and the third portion 134 of the electrically conductive layer structure 106 are arranged laterally adjacent to each other. Preferably, the first portion 118, the second portion 120, and the third portion 134 of the electrically conductive layer structure 106 are not in direct contact with each other (see [link]). Figure 5 ).

[0130] In the component carrier 100 with embedded electronic component 232 that is easy to manufacture, the first portion 118 can be used to form a direct connection with an electrically conductive pad 370 located on the bottom main surface of the electronic component 232 to be embedded in the cavity 112 (see [link]). Figure 5The preferably circumferentially closed second portion 120 can be used to suppress voids at the edge 322 of the cavity 112 during the manufacture of the component carrier 100. Advantageously, suppressing voids or resin-free recesses extending from the edge 322 into the stack 102 can significantly improve the reliability of the component carrier 100, as such voids typically lead to reliability problems. The third portion 134 can provide functionality that facilitates electrical conduction traces and / or vertical through-connections in the component carrier 100. For example, the third portion 134 can be electrically coupled to the first portion 118 and / or electrically decoupled from the second portion 120.

[0131] As described above, cavity 112 can be formed based on the entire stack 102 by performing laser processing to remove stack material from the region of cavity 112 up to the exposed electrically conductive structures or substructures of the first portion 118 and the second portion 120. At least a portion of the exposed area of ​​the first portion 118 and the exposed portion 124 of the second portion 120 can serve as laser stop portions to restrict the portion of the stack 102 removed by laser processing, thereby forming cavity 112. Conversely, the embedded third portion 134 is not affected by the laser. Therefore, the roughness Ra of the electrically conductive structure in the third portion 134 may differ from the roughness Ra of the electrically conductive structure in the exposed portion 124 of the first portion 118 and the second portion 120. Furthermore, the roughness Ra of the electrically conductive structure in the third portion 134 may be approximately the same as the roughness Ra of the electrically conductive structure in the unexposed portion 126 of the second portion 120, because neither of these is subjected to laser light.

[0132] Refer again Figure 4Each electrical conductive structure in the first portion 118 is electrically connected to an interconnect structure 336 located within the bottom wall 114 of the cavity 112. In the illustrated embodiment, the interconnect structure 336 includes metallized laser vias. Below the interconnect structure 336, other interconnect structures, such as one or more additional metallized laser vias and one or more metal pads, are connected. Therefore, each electrical conductive structure in the first portion 118 can be electrically connected to the wiring structure in the stack 102, and can achieve an electrical conductive connection to the pad 370 located at the bottom main surface of the electronic component 232 embedded in the cavity 112 and electrically connected to the electrical conductive structure of the first portion 118. In contrast, the electrical conductive structure of the second portion 120 can be non-electrically connected or insulating because the function of the electrical conductive structure of the second portion 120 may be related to improved reliability due to suppression of voids, rather than to the electrical interconnection of the embedded component 232. However, in another embodiment, the electrical conductive structure of the second portion 120 may also be electrically connected to an interconnect structure to facilitate electrical interconnection within the component carrier 100 (e.g., when the corresponding pad 370 of the embedded component 232 is also connected to the electrical conductive structure of the second portion 120). The electrical conductive structure of the third portion 134 of the electrical conductive layer structure 106 may be connected to another electrical conductive layer structure 106 of the stack 102, and may also be connected to one or more electrical conductive structures of the first portion 118.

[0133] Figure 5 A cross-sectional view and details of a component carrier 100 according to an exemplary embodiment of the present invention are shown. The component carrier 100 may be based on... Figure 4 It is obtained by preforming parts.

[0134] Figure 5 The implementation method can be based on Figure 4 This is achieved by further removing a portion of the underlying material of the electrically conductive layer 332 and the electrically conductive layer structure 106 through etching (e.g., rapid etching). This process also allows the exposed first portion 118 and the exposed portion 124 of the second portion 120 to be reshaped, while the covered third portion 134 is unaffected by the etching process.

[0135] The first portion 118 includes a plurality of electrically conductive structures, each of which has a substantially flat pad portion (made in particular of copper), and the electrically conductive structures of the second portion 120 have a more complex curved shape and a greater maximum height. This results in the shape of the first portion 118 being different from that of the second portion 120, which is caused by different etching rates resulting from different chemical exchange rates at the corners and in the central region during the etching process. In addition, the maximum height of the first portion 118 is different from the maximum height of the second portion 120. Furthermore, the third portion 134 of the electrically conductive layer structure 106 has a vertical extension different from the vertical extensions of the first portion 118 and the second portion 120, because the third portion 134 is completely protected relative to the etching process. This results in the shapes of the first portion 118 and the second portion 120 being different from the shape of the third portion 134.

[0136] According to Figure 5 , the different vertical extensions of the first portion 118 and the second portion 120 comprise different maximum thicknesses d, D, where d<D. More specifically, the first portion 118 has a maximum thickness d that is smaller than the maximum thickness D of the second portion 120, such that the top region of the second portion 120 is smaller than the bottom region of the second portion 120. The dimension of the top region can be reduced to 1µm, while the dimension of the bottom region can be increased to 200µm, which allows great design flexibility to be provided in this embodiment and can also solve the void problem. According to Figure 5 , the unexposed portion 126 of the second portion 120 has a maximum thickness D that is the same as the maximum thickness D of the third portion 134.

[0137] Furthermore, the shape of the side walls of the electrically conductive structures of the third portion 134 is different from both the shape of the side walls of the electrically conductive structures of the first portion 118 and the shape of the side walls of the electrically conductive structures in the exposed portion 124 of the second portion 120. More specifically, according to Figure 5 , the side walls of the electrically conductive structures of the first portion 118 are inclined, the side walls of the electrically conductive structures of the third portion 134 are vertical, and the side walls of the electrically conductive structures of the exposed portion 124 of the second portion 322 are curved (in particular having at least one convex portion). Therefore, the inclination of the side walls of the electrically conductive structures of the third portion 134 is different from the inclination of the side walls of the electrically conductive structures in the exposed portion 124 of the second portion 120. Furthermore, the inclination of the side walls of the electrically conductive structures of the third portion 134 is the same as the inclination of the side walls of the electrically conductive structures in the unexposed portion 126 of the second portion 120. According to Figure 5 , both of these inclinations are vertical.

[0138] According to the obtained Figure 5The component carrier 100 has a vertical extension of the first portion 118 that differs from the vertical extensions of the second portion 120 and the third portion 134. These different characteristics of the first portion 118, the second portion 120, and the third portion 134 in relation to their vertical extensions allow for individual adjustment of the vertical extensions of the first portion 118, the second portion 120, and the third portion 134 according to their respective functions. Therefore, according to Figure 5 The different vertical extensions of the first portion 118, the second portion 120, and the third portion 134 include different shapes and / or heights.

[0139] exist Figure 5 In this cavity 112, the circumferential portion of the edge 322 located between the bottom wall 114 and the side wall 116 can be circumferentially closed. The entire circumferential portion of the edge 322 can be a potential weak point in terms of forming undesirable voids. To overcome this defect, the second portion 120 can be in the form of a frame extending along the entire circumferential portion of the edge 322. This can be extremely advantageous in suppressing the formation of voids and thus improving the reliability of the component carrier 100. Therefore, it is highly preferred that the second portion 120 extends along the entire circumferential portion of the edge 322 located between the bottom wall 114 and the side wall 116 of the cavity 112 into a circumferentially closed annular structure.

[0140] In summary, Figure 4 , Figure 5 In one embodiment, a copper wall is provided at the cavity corner corresponding to the edge 322. After post-etching of the copper barrier, the cavity corner corresponding to the edge 322 may be gapless. In the illustrated embodiment, the size of the copper barrier may be smaller than the size of the cavity bottom. With this structure, the second part 120 may include features located on the pad such that, due to the height difference between the copper barrier and the copper wall at the edge, the etching rate may be different, allowing for the creation of recesses or wavy portions on the top surface of the copper wall through micro-etching.

[0141] like Figure 5As shown, an electronic component 232, which can be implemented as a bridging chip, can be embedded in the cavity 112. For this purpose, the electronic component 232 can be inserted into the cavity 112 such that the pad 370 located on the bottom main surface is electrically coupled to the respective electrically conductive structures of the first portion 118. For example, this coupling can be achieved by soldering. For this purpose, the component carrier 100 can include solder structures on the exposed surface of the first portion 118 as additional conductive structures 224, such as solder bumps. This allows a solder connection to be established between the exposed surface of the first portion 118 and the pad 370 on the bottom side of the electronic component 232 to be embedded. Specifically, solder bumps can be provided on the exposed surface area of ​​the electrically conductive structure of the first portion 118 and / or on the exposed area of ​​the pad 370 on the bottom side of the component 232. Therefore, the component 232 can be electrically coupled to the first portion 118 of the electrically conductive layer structure 106. The first portion 118 can in turn be electrically coupled to the third portion 134 and / or other electrically conductive layer structures 106. This can be achieved by having the embedded component 232 serve as a bridging chip for electrically coupling two or more additional electronic components (not shown), which can be surface-mounted on the top main surface of the stack 102. Although not shown, an encapsulation material (such as an adhesive or resin) can encapsulate the embedded component 232 within the cavity 112. For this purpose, the encapsulation material can be inserted into the gap between the cavity 112 and the embedded component 232 and can be solidified by curing. This secures the embedded component 232 in place within the cavity 112. As previously mentioned, the electronic component 232 can be a semiconductor wafer, such as a semiconductor bridging chip. When the electronic component 232 is a bridging chip, it can interconnect two or more surface-mounted (particularly surface-mounted on the uppermost exposed conductive layer structure 106) electronic components (such as semiconductor wafers, not shown).

[0142] Still refer to Figure 5 The horizontal width w of the second portion 120 can range from 1µm to 200µm. Furthermore, the minimum horizontal distance b between the first portion 118 and the second portion 120 can range from 10µm to 130µm. Therefore, the described manufacturing structure is compatible with very small dimensions, thereby achieving high integration density.

[0143] The geometry of the exposed sidewalls of the first portion 118 and the exposed sidewalls of the second portion 120 of the electrically conductive layer structure 106 can be achieved by etching. Figure 4 Implementation method, Figure 5 This can be achieved through a post-copper barrier etching process. By setting copper walls in the cavity corners, no voids will appear. According to... Figure 5In the component carrier 100, the second portion 120 includes a base layer 372 (which may be made of non-electroplated copper) and a top layer 374 (which may be an electroplated copper layer) located on the base layer 372. The adjacent first portion 118 (and the third portion 134) may also include these two layers (e.g., 372, 374). The copper wall may be higher than the protrusion and may have a copper bottom.

[0144] in short, Figure 4 and Figure 5 The embodiment provides a circumferentially closed metal wall in the form of a second portion 120 along the edge 322 of the cavity 112, thereby preventing gaps from appearing in the corners of the cavity 112.

[0145] In addition, Figure 4 and Figure 5 In some embodiments, a thin layer 128 (e.g., comprising nickel) may be provided, as shown in details 195 and 197. For example, the thin layer 128 may be formed as a byproduct of forming a surface-treated portion on the exposed portion of the partially exposed electrically conductive layer structure 106 in cavity 112. Detail 195 shows the thin layer 128 adjacent to a contact bonding surface 132 and disposed between the bottom-side electrically insulating layer structure 104 and the first portion 118 of the top-side electrically conductive layer structure 106, wherein direct physical contact can be established between the electrically insulating layer structure 104 and the electrically conductive layer structure 106 at the contact bonding surface 132. The thin layer 128, according to detail 195, seals or fills the gap, thereby suppressing delamination between the layer structures 104 and 106. Detail Figure 197 shows two additional thin layers 128, each adjacent to a corresponding contact bonding surface 132, and both arranged between a corresponding electrically insulating layer structure 104 and a second portion 120 of an electrically conductive layer structure 106 in a vertically stacked electrically insulating layer structure 104, wherein a direct physical contact is established between the corresponding electrically insulating layer structure 104 and the electrically conductive layer structure 106 at the contact bonding surface 132. The thin layers 128, as shown in Detail Figure 197, respectively close and fill the gaps, thereby suppressing delamination between the layer structures 104 and 106.

[0146] Still refer to Figure 4 and Figure 5The electrically conductive layer structure 106, having portions 118, 120, and 134, includes a planar frame structure of metal in the form of a second portion 120, which is designed to laterally define the sidewalls 116 of the cavity 112. This planar frame structure, implemented as the second portion 120, is constructed as a circumferentially closed frame, thereby suppressing the formation of voids around the edge 322 of the cavity 112. Furthermore, a gap-sealing thin layer 128 (see detail 197) located on the top and bottom sides of the second portion 120 has planar extensions that define circumferential portions following the outer contour of the second portion 120 of the electrically conductive layer structure 106, the thin layer 128 being sandwiched within the electrically conductive layer structure 106 by an electrically insulating layer structure 104. The circumferential portion defined by the planar extension of thin layer 128 can follow the inner and / or outer circumferential portions of the electrically conductive layer structure 106 according to the processing parameters of the manufacturing process (especially the processing parameters of the surface treatment process), and the planar extension of thin layer 128 can be positioned between the corresponding electrically insulating layer structure 104 and the planar frame structure of the second portion 120, thereby partially defining the sidewall 116 of cavity 112 laterally. Therefore, the two thin layers 128 of detail 197 and the second portion 120 therebetween can be a circumferentially closed frame structure extending around the entire edge 322 of cavity 112. According to detail 197, one or both thin layers 128 can completely follow the outer contour of the second portion 120 of the electrically conductive layer structure 106, thereby ensuring a customized fit to enhance the structural integrity of the assembly and suppress delamination by avoiding voids. Furthermore, according to detail 197, the upper thin layer 128 may be partially located between the unexposed portion 126 of the second portion 120 and the electrically insulating layer structure 104 that defines a portion of the sidewall 116 of the cavity 112. Another portion of the upper thin layer 128 is disposed on the exposed portion 124 of the second portion 120 of the electrically conductive layer structure 104. Still referring to detail 197, one thin layer 128 may be disposed between the exposed portion 124 of the second portion 120 and the electrically insulating layer structure 104 that defines the bottom wall 114, while another thin layer 128 may be located between the unexposed portion 126 of the second portion 120 and the electrically insulating layer structure 104 that partially embeds the second portion 120 and partially defines the sidewall 116 of the cavity 112.

[0147] The corresponding function of suppressing delamination and improving the reliability of component carrier 100 by filling the hollow space can be achieved by a thin layer 128 according to detail 195, which is arranged between the first portion 118 of the electrically conductive layer structure 106 and the electrically insulating layer structure 104 that defines a portion of the bottom wall 114 of the underlying cavity 112. Still referring to detail 195, the thin layer 128 is positioned between the first portion 118 and the electrically insulating layer structure 104 that partially defines the bottom wall 114.

[0148] according to Figure 5 The horizontal widths of the individual thin layers 128 can be different from each other, thereby allowing customized mechanical and electrical properties to be achieved at different locations within the structure.

[0149] However, the fully embedded third portion 134 of the electrically conductive layer structure 106 may be without the thin layer 128, which may be advantageous for certain specific design requirements. This may be because the fully embedded third portion 134 is not exposed to the surface treatment process.

[0150] Figure 5A An exemplary embodiment of the present invention is shown in the completed Figure 5 A cross-sectional view of the component carrier 100 after the initial component is embedded and before the surface mounting of other components.

[0151] As mentioned above... Figure 5 As described, electronic component 232 can be at least partially arranged within cavity 112. Additional electrically conductive layer structures of component 232, such as metal pads 370, can be connected to a first portion 118 located at the bottom of cavity 112 via a welded additional conductive structure 224. Therefore, one (or more) electronic components 232 can be embedded in cavity 112 formed in the upper portion of stack 102. Component 232 can be connected to one or more first portions 118 having the aforementioned features. The empty space remaining in cavity 112 after insertion of component 232 can be filled with a filler material 286 (such as adhesive or resin) that encapsulates the embedded component 232 within cavity 112. For this purpose, the encapsulation material can be inserted into the gap between cavity 112 and the embedded component 232 and solidified by curing. This secures the embedded component 232 in place within cavity 112.

[0152] exist Figure 5A In this structure, the uppermost electrical insulating layer structure 104 may have an opening 239 to expose various portions of the lower electrical conductive layer structure 106, particularly the pads of the electrical conductive layer structure 106. This structured uppermost electrical insulating layer structure 104 also has an opening 139 for connecting the top-side connection terminals or pads 370 of the embedded component 232. For some applications, the uppermost electrical insulating layer structure 104 may be a solder resist layer.

[0153] Figure 5B A cross-sectional view of the component carrier 100 after component embedding and after surface mounting of other components, according to an exemplary embodiment of the present invention, is shown.

[0154] Now refer to Figure 5BThe opening 239 can be filled with a metallic material of another electrically conductive layer structure 106. Furthermore, one or more additional patterned electrically insulating layer structures 104 and one or more additional patterned electrically conductive layer structures 106 can be formed on the top side of this structure. Figure 5B In this diagram, solder resist 482 is shown as the uppermost electrically insulating layer structure 104 and exposes the pads of the uppermost electrically conductive layer structure 106. Although not shown, patterned solder resist may also be formed on the bottom main surface of the resulting component carrier 100.

[0155] In addition, the other components 156 and 158 are surface-mounted and connected to the exposed electrical conductive layer structure 106 and / or the exposed connection terminals or pads 370 of component 232.

[0156] Component 232 can be configured as a bridging element (e.g., a bridging chip) to connect two additional electronic components 156, 158 to the stack 102. Components 156, 158 can be semiconductor wafers having pads 160, 162, at least a portion of which is connected to an exposed pad 370 of the bridging component 232. For example, additional electronic component 156 can be electrically coupled to additional electronic component 158 ​​via the bridging component 232. Therefore, electronic component 232, which can be implemented as a bridging chip, can be embedded in cavity 112.

[0157] On the top and / or bottom sides (not shown) of the stack 102, a corresponding patterned solder resist 482 may be formed to protect certain portions of the stack 102 from oxidation and to electrically insulate portions located on the top and bottom main surfaces of the component carrier 100. The uppermost and lowermost electrically conductive layer structures 106 of the stack 102 may be exposed relative to the solder resist 482. The exposed portions of the electrically conductive layer structures 106 may be connected to electronic peripherals (such as electronic boards, not shown) and / or may be connected to one or more surface-mounted components (such as semiconductor wafers, not shown).

[0158] Component 232 is embedded in an encapsulation material (which may be different from solder resist 482). The encapsulation material may be the same as or different from the material of other electrically insulating layer structures in the electrically insulating layer structure 104. Solder resist 482 is formed on top of the encapsulation material and another electrically insulating layer structure 104. One or more stacked layers may be disposed on top of the encapsulation material. The stacked layers may include electrically conductive layer structures 106 and electrically insulating layer structures 104. The stacked layers may be configured as redistribution layers. The stacked layers may be electrically connected to each other. In addition, the stacked layers may be electrically connected to other electrically conductive layer structures 106 of the stack 102. Two components 156, 158 may be disposed on the same main surface of the stack 102. The two components 156, 158 may be separated from component 232 embedded in the stack 102 by the stacked layers. The stacked layers may electrically connect the embedded component 232 to the two surface-mounted components 156, 158. Preferably, the surface-mount components 156, 158 are connected to the embedded component 232 and a corresponding other electrically conductive layer structure 106 (which may be arranged laterally close to the embedded component 232). The stack 102 may be asymmetrical. The stack 358 may not have additional stack layers. The corresponding two surface-mount components 156, 158 may be connected to each other via the embedded component 232 (and additionally via the stack layers). Solder resist 482 may be exposed on the top of the stack 102.

[0159] Figure 6 A cross-sectional image of a portion of a component carrier 100 according to an exemplary embodiment of the present invention is shown.

[0160] Figure 6 A large portion of the cross-section is shown, with details as follows: Figure 3 As shown. In Figure 6In this configuration, the top side of the conductive layer 110 can be exposed in the cavity 112 for connection to electronic components (not shown). Reference numeral 193 indicates the location of a stop layer or barrier layer that may define the bottom of the cavity 112. Due to the etching of the stop layer after laser processing, undercut portions may be formed below the pad 108 and above the electrically insulating layer structure 104. During the formation of the surface treatment portion (e.g., ENIPIG) or the conductive layer 110, the undercut portions may be at least partially filled with a surface treatment material (e.g., including nickel). The surface treatment structure may be grown along with the contour at the corner of the electrically conductive layer structure 106, or react with palladium ions attached to the contour surface at the corner region, thereby filling the undercut portions formed by the etching of the electrically conductive layer structure 106. Furthermore, the contour of the surface treatment layer located inside the undercut can not only serve as an interlocking structure to anchor the surface treatment layer, the electrically conductive layer structure 106, and the electrically insulating layer structure 104, but also provide a smooth base for the metal to be plated later, thereby improving the bonding performance of the components.

[0161] Figure 7 A cross-sectional view of a portion of a component carrier 100 according to another exemplary embodiment of the present invention is shown. In short, Figure 7 The cross-sectional view shows a portion of the component carrier 100 around the edge 322 of the cavity 112 located in the stack 102.

[0162] A portion of the conductive layer structure 106 is exposed at the vertical sidewall 116 defining the cavity 112. Corresponding thin layers 128 are formed above and below this portion of the conductive layer structure 106. When the lower thin layer 128 is subjected to a stronger influence from the laser processing used to form the cavity 112, the upper thin layer 128 may have a larger horizontal extension than the lower thin layer 128. Laser energy with thermal processing can lead to a loss of insulating layer performance during cavity formation, especially at the bottom surface where it is subjected to direct thermal shock from the laser due to the barrier layer reflecting most of the laser to the sidewalls, and where less laser is absorbed.

[0163] In one embodiment, in the region of thin layer 128, the filler of the electrically insulating layer structure 104 located on the bottom surface of cavity 112 and the sidewall 116 of cavity 112 may be connected to or covered by thin layer 128 due to laser heating that can ablate the resin, and the microfiller may be exposed in these regions. By covering the thin layer 128, the filler will not fall off and can still remain in the resin, so that the dielectric properties of the insulating material will not be affected.

[0164] Typically, the thin layer 128 can be longer above the electrically conductive layer structure 106 than below it, thereby allowing customized mechanical and electrical properties to be obtained at different locations within the stack 102.

[0165] For example Figure 7 As shown, the lowest conductive layer structure 106 may include multiple portions, each associated with a corresponding thin layer 128. These thin layers 128 may be arranged at different vertical levels; specifically, they may be arranged on different main surfaces 130 of the electrically insulating layer structure 104 and may exhibit different thicknesses and planar extensions. At the bottom wall 114 of the cavity 112, the second portion 120 of the corresponding conductive layer structure 106 extending via edge 322 into the laterally stacked portion has an additional thin layer 128. This additional thin layer 128 is formed between the lower electrically insulating layer structure 104 defining a portion of the bottom wall 114 and the conductive layer structure 106 formed on the electrically insulating layer structure 104.

[0166] Furthermore, on the top side of the electrically conductive layer structure 106, at the junction with the upper electrically insulating layer structure 104 that defines at least a portion of the vertical sidewall 116, another thin layer 128 is formed. This thin layer 128 extends horizontally through the vertical sidewall 116 into the stack 102. Between the lateral ends of the thin layer 128 and the contact surfaces 132 of the layer structures 106 and 104 that sandwich the thin layer 128, minute hollow additional volume portions 136 are formed. Thus, the thin layer 128 is separated from the allocated contact surfaces 132 by a defined lateral distance, thereby introducing additional volume portions 136 between the electrically conductive layer structure 106 and the electrically insulating layer structure 104. The additional volume portion 136 extends along the thickness direction of the stack 102 and also extends laterally between the thin layer 128 and the contact engagement surface 132 in a manner parallel to one of the main surfaces 130 of the stack 102. The additional volume portion 136 can be configured as a vacuum volume portion or can be filled with a fluid, such as air. While hollow volumes are generally undesirable in the component carrier 100, the presence of the thin layer 128 significantly reduces the size of the hollow additional volume portion 136, thus making delamination less of a critical issue.

[0167] Figure 8 A cross-sectional image of a portion of a component carrier 100 according to an exemplary embodiment of the present invention is shown. Figure 9 It shows the Figure 8 The image displays details.

[0168] In principle, according to Figure 8 The actual manufactured component carrier 100 corresponds to Figure 7 The contents shown in the drawings. Therefore, you can refer to the above text for details. Figure 7 The description.

[0169] It should be noted that the term "comprising" does not exclude other elements or steps, and "a" or "an" does not exclude multiple. Furthermore, elements described in conjunction with different embodiments may be combined.

[0170] It should also be noted that the reference numerals in the claims should not be interpreted as limiting the scope of the claims.

[0171] Implementations of the present invention are not limited to the preferred embodiments shown in the accompanying drawings and described above. Rather, it is possible to use the illustrated solutions and numerous variations based on the principles of the invention, even in cases where the implementations are fundamentally different.

Claims

1. A component carrier (100), the component carrier (100) comprising: A stack (102) comprising at least one electrically insulating layer structure (104) and at least one electrically conductive layer structure (106), the at least one electrically conductive layer structure (106) being arranged to directly contact the at least one electrically insulating layer structure (104), thereby defining a contact engagement surface (132) between the at least one electrically insulating layer structure (104) and the at least one electrically conductive layer structure (106); and A thin layer (128) is sandwiched between the at least one electrically conductive layer structure (106) and the at least one electrically insulating layer structure (104), and the thin layer (128) is arranged next to the contact bonding surface (132).

2. The component carrier (100) according to claim 1, wherein, The thin layer (128) is disposed on the main surface (130) of the at least one electrically insulating layer structure (104).

3. The component carrier (100) according to claim 1 or 2, wherein, The at least one electrically conductive layer structure (106) is at least partially embedded in the at least one electrically insulating layer structure (104).

4. The component carrier (100) according to claim 3, wherein, The thin layer (128) is arranged on the portion of the at least one electrically conductive layer structure (106) that is embedded in the at least one electrically insulating layer structure (104).

5. The component carrier (100) according to any one of claims 1 to 4, wherein, The thin layer (128) is in direct contact with the contact bonding surface (132).

6. The component carrier (100) according to any one of claims 1 to 4, wherein, The thin layer (128) and the contact bonding surface (132) are laterally separated from each other by a lateral spacing.

7. The component carrier (100) according to any one of claims 1 to 4 or claim 6, the component carrier (100) comprising an additional volume portion (136) extending along the thickness direction of the stack (102) between the at least one electrically conductive layer structure (106) and the at least one electrically insulating layer structure (104), and the additional volume portion (136) extending along a lateral extension parallel to one of the main surfaces of the stack (102) between the thin layer (128) and the contact bonding surface (132).

8. The component carrier (100) according to any one of claims 1 to 7, wherein, The first surface of the thin layer (128) is parallel to the contact bonding surface (132), and in particular, the first surface of the thin layer (128) is coplanar with the contact bonding surface (132).

9. The component carrier (100) according to claim 8, wherein, The second surface of the thin layer (128), opposite to the first surface, has an irregular shape and / or a rounded shape.

10. The component carrier (100) according to any one of claims 1 to 9, wherein, The at least one electrically conductive layer structure (106) includes a pad (108).

11. The component carrier (100) according to any one of claims 1 to 10, wherein, The at least one electrically conductive layer structure (106) includes a planar frame structure.

12. The component carrier (100) according to claim 11, wherein, The planar frame structure is configured to at least partially define the sidewalls (116) of the cavity (112) in the lateral direction.

13. The component carrier (100) according to any one of claims 1 to 12, wherein, The thin layer (128) has a planar extension that defines a circumferential portion that follows the outer contour of the at least one electrically conductive layer structure (106), and the thin layer (128) is sandwiched at the at least one electrically insulating layer structure (104) by the at least one electrically conductive layer structure (106).

14. The component carrier (100) according to any one of claims 1 to 13, wherein, The ratio between the thickness of the thin layer (128) and the thickness of the at least one electrically conductive layer structure (106) is in the range of 0.05 to 0.

2.

15. The component carrier (100) according to any one of claims 1 to 14, wherein, The width of the thin layer (128) in the horizontal plane is in the range of 2µm to 20µm.

16. The component carrier (100) according to any one of claims 1 to 15, wherein, The thin layer (128) comprises an electrically conductive material, or the thin layer (128) is composed of an electrically conductive material.

17. The component carrier (100) according to any one of claims 1 to 16, wherein, The thin layer (128) comprises a material different from that of the at least one electrically conductive layer structure (106).

18. The component carrier (100) according to any one of claims 1 to 17, wherein, The at least one electrically conductive layer structure (106) includes a covering conductive layer (110), and in particular, the first portion (118) and / or the second portion (120) include the covering conductive layer (110).

19. The component carrier (100) according to claim 18, wherein, The thin layer (128) is enclosed between the at least one electrically insulating layer structure (104), the at least one electrically conductive layer structure (106), and the covering conductive layer (110).

20. The component carrier (100) according to any one of claims 18 to 19, wherein, The covering conductive layer (110) is incorporated into the thin layer (128).

21. The component carrier (100) according to any one of claims 18 to 20, wherein, The covering conductive layer (110) forms an anchoring structure around the side wall of the at least one electrically conductive layer structure (106), and in particular, the covering conductive layer (110) forms an anchoring structure around the exposed portion of the second portion (120) and / or the first portion (118).

22. The component carrier (100) according to any one of claims 18 to 21, wherein, The thin layer (128) is the circumferential extension of the covering conductive layer (110).

23. The component carrier (100) according to any one of claims 1 to 22, wherein, The at least one electrically conductive layer structure (106) comprises multiple portions, each of which has a corresponding thin layer (128).

24. The component carrier (100) according to claim 23, wherein, The thin layer (128) is longer above the at least one electrically conductive layer structure (106) than it is below the at least one electrically conductive layer structure (106).

25. A method for manufacturing a component carrier (100), wherein, The method includes: A stack (102) is provided, the stack (102) including at least one electrically insulating layer structure (104) and at least one electrically conductive layer structure (106). The at least one electrically conductive layer structure (106) is arranged to be in direct contact with the at least one electrically insulating layer structure (104), thereby defining a contact bonding surface (132) between the at least one electrically conductive layer structure (106) and the at least one electrically insulating layer structure (104); and A thin layer (128) is sandwiched between the at least one electrically conductive layer structure (106) and the at least one electrically insulating layer structure (104), the thin layer (128) being arranged next to the contact bonding surface (132).

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