Circuit board assembly and method of making the same

Abstract

A circuit board assembly and a method of manufacturing the same. The circuit board assembly includes a substrate, a first dielectric layer, a second dielectric layer, an optoelectronic die, an optical fiber, a first circuit layer, a second circuit layer, a third circuit layer, and a processor die. The substrate has a first upper surface and a first lower surface. The first upper surface of the substrate has a plurality of recesses. The first dielectric layer is disposed on the first upper surface of the substrate. The first dielectric layer fills the recesses. The second dielectric layer is disposed on the first lower surface of the substrate. The optoelectronic die is disposed in the recesses. The optical fiber is disposed in the recesses. The first circuit layer is disposed on a second upper surface of the first dielectric layer. The second circuit layer is disposed on a second lower surface of the second dielectric layer. The third circuit layer is disposed in the first dielectric layer and the second dielectric layer. The processor die is disposed in the first dielectric layer. The circuit board assembly embeds the optical fiber and electronic components therein, which avoids damaging the optical fiber during a compression process and improves the integration and quality of the circuit board.

Description

Technical Field

[0001] This invention relates to a circuit board assembly and a method for manufacturing the same. Background Technology

[0002] Traditional circuit boards rely on copper wires to transmit electrical signals, but this also has its drawbacks, such as limited transmission rate, susceptibility to electromagnetic interference, significant signal loss, low bandwidth, large size and weight, and high power consumption. They are difficult to meet the requirements of high-frequency, high-speed and long-distance transmission, and are particularly limited in complex electromagnetic environments and big data applications. Summary of the Invention

[0003] Some embodiments of the present invention provide a circuit board assembly and a method for manufacturing the same. This circuit board assembly is an optoelectronic substrate using glass as the substrate material, with optical fibers and electronic components embedded within it. The embedded design of the optical fiber lines avoids damage to the fiber during the lamination process and reduces the size (e.g., area, side length, or volume) and weight of the circuit board, thereby improving its integration and quality. Therefore, this circuit board conforms to the current trend of circuit board thinning. Furthermore, the modular design of the optical fiber and electronic components (e.g., photoelectric conversion chips) reduces signal loss during transmission, thus reducing the need for signal relays. In this way, the circuit board assembly combines the advantages of glass-based circuit boards, embedded components, and optoelectronic substrates, such as high-speed transmission, electromagnetic interference resistance, low loss, high bandwidth, small size, light weight, energy saving, multi-functional integration, and quality assurance.

[0004] This invention provides a circuit board assembly including a substrate, a first dielectric layer, a second dielectric layer, a photoelectric chip, an optical fiber, a first circuit layer, a second circuit layer, a third circuit layer, and a processor chip. The substrate has a first upper surface and a first lower surface, wherein the first upper surface of the substrate has a plurality of grooves. The first dielectric layer is disposed on the first upper surface of the substrate, wherein the first dielectric layer fills the plurality of grooves. The second dielectric layer is disposed on the first lower surface of the substrate. The photoelectric chip is disposed in a groove. The optical fiber is disposed in a groove, wherein the first dielectric layer covers the photoelectric chip and the optical fiber, wherein the optical fiber is used to transmit light, and the active surface of the photoelectric chip is located on the light transmission path. The first circuit layer is disposed on a second upper surface of the first dielectric layer. The second circuit layer is disposed on a second lower surface of the second dielectric layer. The third circuit layer is disposed in the first and second dielectric layers. The processor chip is disposed in the first dielectric layer, wherein the processor chip is electrically connected to the photoelectric chip.

[0005] According to some embodiments of the present invention, the substrate is a glass substrate.

[0006] According to some embodiments of the present invention, the melting point of the substrate is lower than the melting point of each of the first circuit layer, the second circuit layer and the third circuit layer.

[0007] According to some embodiments of the present invention, the circuit board assembly further includes a plurality of conductive buried vias. The conductive buried vias are disposed in a first dielectric layer, wherein the conductive buried vias electrically connect to the optoelectronic chip, the third circuit layer, and the processor chip.

[0008] According to some embodiments of the present invention, a conductive buried via connects at least two of a substrate, an optoelectronic chip, a third circuit layer, and a processor chip.

[0009] According to some embodiments of the present invention, the circuit board assembly further includes conductive vias. The conductive vias are disposed in the substrate, the first dielectric layer, and the second dielectric layer, wherein the conductive vias are electrically connected to the first circuit layer and the second circuit layer.

[0010] According to some embodiments of the present invention, the optical fibers disposed in the groove are distributed in a serpentine pattern.

[0011] Some embodiments of the present invention provide a method for manufacturing a circuit board assembly, comprising: forming a conductive structure, wherein the conductive structure includes a plurality of protruding portions and a flat portion, the protruding portions being located on the flat portion; forming a substrate on the conductive structure, wherein the upper surface of the substrate has a plurality of grooves; removing the flat portion of the conductive structure after forming the substrate; forming a first conductive via in the substrate; disposing a photoelectric chip in a groove of the substrate; disposing an optical fiber in a groove of the substrate, wherein the optical fiber is used to transmit light, and the active surface of the photoelectric chip is located on the light transmission path; after disposing the photoelectric chip and the optical fiber, forming a first dielectric layer and a second dielectric layer on the upper surface and lower surface of the substrate, respectively, wherein the first dielectric layer covers the photoelectric chip and the optical fiber; forming a plurality of conductive buried vias, a plurality of second conductive vias, and a plurality of third conductive vias in the first dielectric layer or the second dielectric layer; forming a first line and a second line of a first line layer on the first dielectric layer and the second dielectric layer, respectively; disposing a processor chip on the conductive buried vias; and forming a first add-on layer and a second add-on layer on the first line and the second line, respectively.

[0012] According to some embodiments of the present invention, forming the first added layer includes: forming a third dielectric layer on the first dielectric layer and the first line; and forming a second line layer on the third dielectric layer.

[0013] According to some embodiments of the present invention, forming the second add-on layer includes: forming a fourth dielectric layer on the second dielectric layer and the second circuit; and forming a third circuit layer on the fourth dielectric layer. Attached Figure Description

[0014] To gain a more complete understanding of the embodiments and their advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, wherein:

[0015] Figure 1A This is a cross-sectional schematic diagram of a circuit board assembly according to a partial embodiment of the present invention.

[0016] Figure 1B for Figure 1A A top view of the fiber optic cabling.

[0017] Figure 2 This is a flowchart of a method for manufacturing a circuit board assembly according to a partial embodiment of the present invention.

[0018] Figures 3A to 3J This is a schematic diagram of a circuit board assembly at various stages of the manufacturing process according to an embodiment of the present invention. Detailed Implementation

[0019] The embodiments of the present invention will be discussed in detail below. However, it should be understood that the embodiments provide many applicable concepts that can be implemented in a wide variety of specific situations. The embodiments discussed and disclosed are for illustrative purposes only and are not intended to limit the scope of the invention. The terms "first," "second," etc., used in this invention do not specifically refer to any order or sequence, but are merely used to distinguish components or operations described using the same technical terms.

[0020] Additionally, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and similar terms may be used in this invention to describe the relationship between one element or feature and another illustrated in the figures. Besides the orientation depicted in the figures, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used in this invention may be interpreted accordingly. As used in this invention, “approximately,” “about,” “approximately,” or “substantially” generally refers to within 20%, 10%, or 5% of a given value or range. The numerical quantities given in this invention are approximate, meaning that the terms “approximately,” “about,” “approximately,” or “substantially” may be speculative unless explicitly specified.

[0021] Please refer to Figure 1A as well as Figure 1B , Figure 1A This is a cross-sectional schematic diagram of a circuit board assembly 100 according to a partial embodiment of the present invention. Figure 1B for Figure 1AA top view of the wiring of the optical fiber 150. The circuit board assembly 100 includes a substrate 110, a dielectric layer 120, a dielectric layer 130, an optoelectronic chip 140, an optical fiber 150, a circuit layer 160, a circuit layer 170, a circuit layer 180, a processor chip 190, a conductive buried via BVH, and a conductive through-hole PTH.

[0022] In some embodiments, the substrate 110 may be a glass substrate and may be made of molten glass with a low melting point or other suitable materials, wherein the melting point of the substrate 110 is lower than that of the circuit layers 160, 170, and 180. For example, in this embodiment, the substrate 110 may be made of lead glass with a melting point below 600 degrees Celsius. Therefore, the combination of the substrate 110 and the mold facilitates the fabrication of irregularly shaped grooves, allowing the irregularly shaped grooves to be integrally formed with the substrate 110, thereby shortening the processing flow. For example, in this embodiment, the substrate 110 has an upper surface 110A and a lower surface 110B, wherein the upper surface 110A of the substrate 110 may have a plurality of grooves TH1 and TH2 formed by the mold. In addition, the lower surface 110B of the substrate 110 may have a plurality of grooves TH3 and TH4, wherein portions 900A and 900B of the conductive structure 900 are respectively disposed on and fill grooves TH3 and TH4.

[0023] In some embodiments, dielectric layer 120 may be disposed on the upper surface 110A of substrate 110, and dielectric layer 130 may be disposed on the lower surface 110B of substrate 110, wherein dielectric layer 120 fills grooves TH1 and TH2. Dielectric layers 120 and 130 may be formed of organic or inorganic insulating materials to provide the mechanical support required by the circuit board assembly 100 or electrical isolation between various conductive paths, thereby preventing short circuits. For example, in this embodiment, dielectric layers 120 and 130 may be made of ajinomoto build-film (ABF) or other suitable materials. In other embodiments, dielectric layers 120 and 130 may be made of polypropylene (PP) or other suitable materials.

[0024] In some embodiments, the optoelectronic chip 140 and the optical fiber 150 can be modularly disposed in the grooves TH1 and / or TH2 of the substrate 110, wherein the optical fiber 150 is distributed in a serpentine pattern, and the number of turns of the optical fiber 150 can be changed according to actual needs. For example, in this embodiment, the optoelectronic chip 140 can be embedded in the groove TH1 of the upper surface 110A of the substrate 110, and the active surface 140A is located on the transmission path of the light transmitted by the optical fiber 150, wherein the active surface 140A can be a light-emitting surface or a light-receiving surface. The optical fiber 150 can be embedded in the grooves TH1 and TH2 of the upper surface 110A of the substrate 110, wherein the dielectric layer 120 covers the optoelectronic chip 140 and the optical fiber 150, wherein the number of turns of the optical fiber 150 is 5 turns as an example, but is not limited thereto. The optoelectronic chip 140 can be a photoelectric conversion chip, and is electrically connected to the optical fiber 150, the circuit layer 180, the processor chip 190, and the conductive buried via BVH. The optoelectronic chip 140 can convert the electrical signal transmitted by the circuit layer 180 into an optical signal (e.g., light) through the conductive buried via BVH, and can transmit this optical signal through the optical fiber 150.

[0025] Alternatively, the optoelectronic chip 140 can convert the optical signal (e.g., light) transmitted by the optical fiber 150 into an electrical signal, and this electrical signal can be transmitted through a conductive buried via BVH. In this way, the circuit board assembly 100 can communicate with optical signals through the optical fiber 150, giving the circuit board assembly 100 advantages such as high speed, high bandwidth, strong anti-interference, and low loss, thus making it suitable for high-frequency, high-speed, and complex electromagnetic environments.

[0026] In some embodiments, circuit layers 160, 170, and 180 may be made of copper or other suitable alloy metals with a melting point higher than 1000 degrees Celsius. Circuit layers 160, 170, and 180 may be disposed in dielectric layers 120 and / or 130, respectively. For example, in this embodiment, circuit layer 160 may be disposed on the upper surface 120A of dielectric layer 120. Circuit layer 170 may be disposed on the lower surface 130A of dielectric layer 130. Circuit layer 180 may include lines 180A and 180B. Line 180A is disposed in dielectric layer 120, and line 180B is disposed in dielectric layer 130, wherein dielectric layer 120 separates circuit layer 160 from line 180A, and dielectric layer 130 separates circuit layer 170 from line 180B.

[0027] In some embodiments, the processor chip 190 may be disposed in the dielectric layer 120, wherein the processor chip 190 may be electrically connected to the optoelectronic chip 140. The processor chip 190 may be changed to different chips according to functional requirements, enabling the circuit board assembly 100 to integrate multiple functional modules to improve product performance. For example, in this embodiment, the processor chip 190 may be a graphics processing unit (GPU). In other embodiments, the processor chip 190 may be a processor chip for various sensors.

[0028] In some embodiments, a conductive buried via (BVH) may be disposed in the dielectric layer 130 and connect at least two of the substrate 110, optoelectronic chip 140, circuit layer 180, and processor chip 190, wherein the conductive buried via (BVH) is electrically connected to the optoelectronic chip 140, circuit layer 180, and processor chip 190. In this embodiment, the conductive buried via (BVH) may be made of the same material as circuit layers 160, 170, and 180, such as copper. In other embodiments, the conductive buried via (BVH) may be made of a different material than circuit layers 160, 170, and 180, such as polysilicon, tungsten, or other suitable materials.

[0029] In some embodiments, a conductive via (PTH) may be disposed in the substrate 110, dielectric layer 120, and dielectric layer 130, wherein the conductive via (PTH) penetrates the substrate 110, dielectric layer 120, and dielectric layer 130, and is electrically connected to the circuit layer 160 and circuit layer 170. In this embodiment, the conductive via (PTH) may be made of the same material as the circuit layers 160, 170, and 180, such as copper. In other embodiments, the conductive via (PTH) may be made of a different material than the circuit layers 160, 170, and 180, such as polysilicon, tungsten, or other suitable materials.

[0030] Figure 2 This is a flowchart of a method 200 for manufacturing a circuit board assembly 100 according to a partial embodiment of the present invention. Figures 3A to 3J This is a schematic diagram of a circuit board assembly 100 according to an embodiment of the present invention at various stages of the manufacturing process. Method 200 includes steps S210 to S300. It should be understood that additional steps may be added before, during, and after steps S210 to S300, and for another part of the implementation of this method, some of the steps mentioned below may be replaced or omitted. The order of steps / procedures may be changed.

[0031] Please refer to Figure 3AIn step S210 of manufacturing method 200, a conductive structure 900' can be formed, wherein the conductive structure 900' includes protruding portions 900'A and 900'B and a flat portion 900'C, and the protruding portions 900'A and 900'B are located on the flat portion 900'C. For example, in this embodiment, the flat portion 900'C can be a tearable copper foil layer, which can protect the protruding portions 900'A and 900'B in subsequent processes. The protruding portions 900'A and 900'B are formed on the flat portion 900'C by sputtering, electroplating, or similar or combined processes to form the conductive structure 900'.

[0032] Next, in method 200, we proceed to step S220. Please refer to... Figure 3B In step S220, a substrate 110 may be formed on the conductive structure 900'. For example, in this embodiment, a mold (not shown) may be disposed on the conductive structure 900', wherein the mold has a plurality of protrusions. Molten glass is then injected into the mold to form the substrate 110, wherein due to the plurality of protrusions of the mold, the upper surface 110A of the substrate 110 may have grooves TH1 and TH2, and due to the protrusions 900'A and 900'B of the conductive structure 900', the lower surface 110B of the substrate 110 may have grooves TH3 and TH4. Next, the fabrication method 200 proceeds to step S230. Please refer to... Figure 3C In step S230, after forming the substrate 110, the flat portion 900'C of the conductive structure 900' is removed, wherein the remaining protruding portions 900'A and 900'B can be referred to as portions 900A and 900B, respectively.

[0033] Next, in method 200, we proceed to step S240. Please refer to... Figure 3D In step S240, a conductive via PTH1 can be formed in the substrate 110. For example, in this embodiment, an opening OP1 can be formed in the substrate 110 by laser, drilling, a combination of the above, or other similar opening processes, wherein the opening OP1 penetrates the substrate 110. Then, a conductive material can be filled into the opening OP1 by sputtering, electroplating, a combination of the above, or other similar processes to form the conductive via PTH1.

[0034] Next, we proceed from step S250 of method 200. Please refer to... Figure 3E In step S250, the optoelectronic chip 140 and the optical fiber 150 can be respectively disposed in the groove TH1 and / or groove TH2 of the substrate 110. For example, in this embodiment, the optoelectronic chip 140 can be embedded in the groove TH1, and the optical fiber 150 can be embedded in the groove TH2, wherein the active surface 140A of the optoelectronic chip 140 is located on the transmission path of the light transmitted by the optical fiber 150.

[0035] Next, in method 200, we proceed to step S260. Please refer to... Figure 3F In step S260, after the optoelectronic chip 140 and optical fiber 150 are formed, dielectric layer 800 and dielectric layer 700 are formed on the upper surface 110A and lower surface 110B of the substrate 110, respectively. For example, in this embodiment, dielectric layer 800 may be made of PP, ABF, a combination thereof, or other similar materials. Dielectric layer 800 may be formed on the upper surface 110A of the substrate 110 by lamination or other similar processes, wherein dielectric layer 800 fills the grooves TH1 and TH2 and covers the optoelectronic chip 140, optical fiber 150, and conductive via PTH1. Dielectric layer 700 may be made of the same material as dielectric layer 800, such as ABF or other similar materials. Dielectric layer 700 may be formed on the lower surface 110B of the substrate 110 by lamination or other similar processes, wherein dielectric layer 700 covers the protrusions 900'A, 900'B, and conductive via PTH1.

[0036] Next, we proceed from step S270 of method 200. Please refer to... Figure 3G In step S270, multiple conductive buried vias BVH, multiple conductive through-holes PTH2, and multiple conductive through-holes PTH3 are formed in dielectric layer 800 and / or dielectric layer 700. For example, in this embodiment, openings OP2 and OP3 can be formed in dielectric layer 800 by laser, drilling, the above combination, or other similar opening processes, and opening OP4 can be formed in dielectric layer 700, wherein openings OP2 and OP3 penetrate dielectric layer 800, and opening OP4 penetrates dielectric layer 700. Next, conductive material is formed in openings OP2, OP3, and OP4 by sputtering, electroplating, the above combination, or other similar processes, and is formed on the upper surface 800A of dielectric layer 800 and the lower surface 700A of dielectric layer 700, respectively, to form conductive buried vias BVH, conductive through-holes PTH2, conductive through-holes PTH3, conductive layer 180A', and conductive layer 180B'.

[0037] Next, in method 200, we proceed to step S280. Please refer to... Figure 3HIn step S280, lines 180A and 180B of the line layer 180 are formed on the dielectric layer 800 and dielectric layer 700, respectively. For example, in this embodiment, the conductive layers 180A' and 180B' located on the insulating dielectric layer 800 and dielectric layer 700 can be patterned to form lines 180A and 180B, respectively. The patterning process may include exposure, etching, a combination of the above, or other similar processes. Line 180A can be connected to the conductive buried via BVH and the conductive via PTH2, and is electrically connected to the conductive buried via BVH, the conductive via PTH2, and the conductive via PTH1. Line 180B can be connected to the conductive via PTH3, and is electrically connected to the conductive via PTH3 and the conductive via PTH1.

[0038] Next, in method 200, we proceed to step S290. Please refer to... Figure 3I In step S290, the processor chip 190 can be set on the conductive buried via BVH, so that the processor chip 190 is connected to the conductive buried via BVH and electrically connected to the optoelectronic chip 140 through the conductive buried via BVH.

[0039] Next, we proceed from step S300 of method 200. Please refer to... Figure 3J In step S300, add-on layers BU1 and BU2 are formed on lines 180A and 180B of the line layer 180, respectively. For example, in this embodiment, the step of forming add-on layer BU1 may include forming dielectric layer 600 on dielectric layer 800 and line 180A of the line layer 180, and forming line layer 160 on dielectric layer 600. The step of forming add-on layer BU2 may include forming dielectric layer 500 on dielectric layer 700 and line 180B of the line layer 180, and forming line layer 170 on dielectric layer 500.

[0040] In detail, in the step of forming the add-on layer BU1, the dielectric layer 600 is first formed on the dielectric layer 800 and the line 180A of the line layer 180 by lamination or other similar processes. The dielectric layer 600 covers the dielectric layer 800, the line 180A, the conductive buried via BVH and the processor chip 190. The dielectric layer 600 can be made of PP, ABF, a combination of the above or other similar materials, and the dielectric layer 600 and the dielectric layer 800 can be collectively referred to as the dielectric layer 120.

[0041] Next, openings OP5 can be formed in the dielectric layer 600 by laser, drilling, a combination of the above, or other similar opening processes, wherein the openings OP5 penetrate the dielectric layer 600. Then, conductive material is formed in the openings OP5 and on the upper surface 600A of the dielectric layer 600 by sputtering, electroplating, a combination of the above, or other similar processes, wherein the conductive via PTH4 can be formed by the openings OP5 filled with this conductive material.

[0042] Next, the conductive material can be patterned to form a circuit layer 160, wherein the patterning process may include exposure, etching, a combination thereof, or other similar processes. The circuit layer 160 may be connected to the conductive via PTH4 and electrically connected to the conductive vias PTH4, PTH2, and PTH1.

[0043] In the step of forming the add-on layer BU2, the dielectric layer 500 is first formed on the dielectric layer 700 and the line 180B of the line layer 180 by lamination or other similar processes, and the dielectric layer 500 covers the dielectric layer 700 and the line 180B. The dielectric layer 500 may be made of PP, ABF, a combination of the above or other similar materials, and the dielectric layer 500 and the dielectric layer 700 may be collectively referred to as the dielectric layer 130.

[0044] Next, openings OP6 can be formed in the dielectric layer 500 by laser processing, drilling, a combination of the above methods, or other similar opening processes, wherein openings OP6 penetrate the dielectric layer 500. Then, conductive material is formed in the openings OP6 and on the lower surface 500A of the dielectric layer 500 by sputtering, electroplating, a combination of the above methods, or other similar processes, wherein conductive vias PTH5 can be formed by openings OP6 filled with this conductive material.

[0045] Next, the conductive material can be patterned to form a circuit layer 170, wherein the patterning process may include exposure, etching, a combination thereof, or other similar processes. The circuit layer 170 may be connected to conductive vias PTH5 and electrically connected to conductive vias PTH5, PTH3, and PTH1, wherein conductive vias PTH1, PTH2, PTH3, PTH4, and PTH5 may be collectively referred to as conductive vias PTH.

[0046] In addition, please continue to refer to Figure 3JAfter step S300, the circuit board assembly 100 can be annealed. Since the substrate 110 is very thin, the annealing process used in this invention involves annealing the entire circuit board assembly 100. The annealing process must maintain flatness to avoid bending and deformation due to gravity, and no stress should be applied during the annealing process. For example, in this embodiment, the annealing temperature can be 500 degrees Celsius, but a lower annealing temperature is required due to the very thin substrate 110. The annealing time is between 30 and 60 minutes. The cooling rate to room temperature is between 5 and 10 degrees Celsius per hour. However, it should be noted that the above-mentioned parameters for the annealing process are not limited to these.

[0047] Some embodiments of the present invention provide a circuit board assembly and a method for manufacturing the same. This circuit board assembly is an optoelectronic substrate using glass as the substrate material, with optical fibers and electronic components embedded within it. The embedded design of the optical fiber lines avoids damage to the optical fiber during the lamination process and reduces the size and weight of the circuit board, thereby improving its integration and quality. Therefore, this circuit board conforms to the current trend of circuit board thinning. Furthermore, the modular design of the optical fiber and electronic components (such as photoelectric conversion chips) reduces signal loss during transmission, thus reducing the need for signal relays. In this way, the circuit board assembly combines the advantages of glass-based circuit boards, embedded components, and optoelectronic substrates, such as high-speed transmission, electromagnetic interference resistance, low loss, high bandwidth, small size, light weight, energy saving, multi-functional integration, and quality assurance.

[0048] The foregoing summary outlines the features of several embodiments, enabling those skilled in the art to better understand the various aspects of the invention. Those skilled in the art will understand that they can readily use the invention as a basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made to the invention without departing from its spirit and scope.

[0049] [Symbol Explanation]

[0050] 100: Circuit board assembly

[0051] 110:Substrate

[0052] 110A, 120A, 800A, 600A: Top surface

[0053] 110B, 130A, 700A, 500A: Lower surface

[0054] 120, 130, 500, 600, 700, 800: Dielectric layer

[0055] 140: Optoelectronic chips

[0056] 140A: Active Surface

[0057] 150: Fiber optic cable

[0058] 160, 170, 180: Line layer

[0059] 180A, 180B: Line

[0060] 180A', 180B': Conductive layers

[0061] 190: Processor chip

[0062] 200: Method

[0063] S210, S220, S230, S240, S250, S260, S270, S280, S290, S300: Steps 900, 900': Conductive Structure

[0064] 900A, 900B: Partial

[0065] 900'A, 900'B: Protruding parts

[0066] 900°C: Flat area

[0067] BVH: Conductive buried via

[0068] BU1, BU2: Added layers

[0069] OP1, OP2, OP3, OP4, OP5, OP6: Openings

[0070] PTH, PTH1, PTH2, PTH3, PTH4, PTH5: Conductive vias; TH1, TH2, TH3, TH4: Grooves.

Claims

1. A circuit board assembly, characterized in that, include: A substrate having a first upper surface and a first lower surface, wherein the first upper surface of the substrate has a plurality of grooves; A first dielectric layer is disposed on the first upper surface of the substrate, wherein the first dielectric layer fills the plurality of grooves; A second dielectric layer is disposed on the first lower surface of the substrate; An optoelectronic chip is disposed in the plurality of grooves; An optical fiber is disposed in the plurality of grooves, wherein the first dielectric layer covers the optoelectronic wafer and the optical fiber, wherein the optical fiber is used to transmit light, and the active surface of the optoelectronic wafer is located on the transmission path of the light. The first circuit layer is disposed on the second upper surface of the first dielectric layer; The second circuit layer is disposed on the second lower surface of the second dielectric layer; The third circuit layer is disposed in the first dielectric layer and the second dielectric layer; as well as A processor chip is disposed in the first dielectric layer, wherein the processor chip is electrically connected to the optoelectronic chip.

2. The circuit board assembly according to claim 1, characterized in that, The substrate is a glass substrate.

3. The circuit board assembly according to claim 1, characterized in that, The melting point of the substrate is lower than that of each of the first circuit layer, the second circuit layer, and the third circuit layer.

4. The circuit board assembly according to claim 1, characterized in that, Also includes: Multiple conductive buried vias are disposed in the first dielectric layer, wherein the multiple conductive buried vias are electrically connected to the optoelectronic wafer, the third circuit layer and the processor wafer.

5. The circuit board assembly according to claim 1, characterized in that, The plurality of conductive buried vias connect to at least two of the substrate, the optoelectronic wafer, the third circuit layer, and the processor wafer.

6. The circuit board assembly according to claim 1, characterized in that, Also includes: A conductive via is disposed in the substrate, the first dielectric layer and the second dielectric layer, wherein the conductive via is electrically connected to the first circuit layer and the second circuit layer.

7. The circuit board assembly according to claim 1, characterized in that, The optical fibers disposed in the plurality of grooves are distributed in a serpentine pattern.

8. A method for manufacturing a circuit board assembly, characterized in that, The method includes: A conductive structure is formed, wherein the conductive structure includes a plurality of protruding portions and a flat portion, the plurality of protruding portions being located on the flat portion; A substrate is formed on the conductive structure, wherein the upper surface of the substrate has a plurality of grooves; After the substrate is formed, the flat portion of the conductive structure is removed; A first conductive via is formed in the substrate; Photoelectric wafers are disposed in the plurality of grooves of the substrate; Optical fibers are disposed in the plurality of grooves of the substrate, wherein the optical fibers are used to transmit light, and the active surface of the optoelectronic wafer is located on the transmission path of the light. After the optoelectronic wafer and the optical fiber are disposed, a first dielectric layer and a second dielectric layer are formed on the upper surface and the lower surface of the substrate, respectively, wherein the first dielectric layer covers the optoelectronic wafer and the optical fiber; Multiple conductive buried vias, multiple second conductive vias, and multiple third conductive vias are formed in the first dielectric layer or the second dielectric layer, respectively. A first line and a second line are respectively formed on the first dielectric layer and the second dielectric layer; The processor chip is disposed on the plurality of conductive buried vias; and A first add-in layer and a second add-in layer are formed on the first line and the second line, respectively.

9. The method according to claim 8, characterized in that, The formation of the first layer includes: A third dielectric layer is formed on the first dielectric layer and the first line; and A second circuit layer is formed on the third dielectric layer.

10. The method according to claim 8, characterized in that, The formation of the second layer includes: A fourth dielectric layer is formed on the second dielectric layer and the second line; and A third circuit layer is formed on the fourth dielectric layer.

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