Preparation process of POFV printed circuit board with interface stress buffering

Abstract

The present application relates to the field of printed circuit manufacturing, and proposes a preparation process of POFV type printed circuit board with interface stress buffering, which comprises the following steps: sequentially performing cutting, inner layer circuit manufacturing, brownization and pressing treatment on a copper-clad plate; drilling a through hole at the position of a solder pad of a multi-layer pressed plate part, so that the through hole is in the position area of the solder pad; sequentially performing copper deposition treatment and first plate electro-processing; performing stress pretreatment on a resin-filled plate part, so that the internal stress of the cured plug-in resin is pre-released before subsequent processing; sequentially performing black shadow treatment, second plate electro-processing, outer layer circuit manufacturing and surface treatment on a flattened plate part, to obtain a POFV type printed circuit board with interface stress buffering structure. The present application converts the plate surface flattening treatment from passive cleaning to active stress dredging tool, so that the grinding process removes the overflowed resin, and further eliminates the residual stress by using the micro-compression effect of the resin surface generated by the grinding brush.

Description

Technical Field

[0001] This invention relates to the field of printed circuit manufacturing, and in particular to a process for manufacturing a POFV type printed circuit board with interface stress buffering. Background Technology

[0002] Plating Over Filled Via (POFV) refers to a process in which conductive vias are filled with resin, the protruding resin surface is ground down, and then copper plating is applied over the vias to form pads. With the increasing demands for miniaturization and high density in PCBs from fields such as 5G communications and consumer electronics, directly designing vias at the pad locations (i.e., via-in-pad) has become an effective way to increase wiring density, and POFV is a key technology for realizing this via-in-pad structure.

[0003] Currently, the standard POFV process generally involves: drilling – electroplating – resin plugging – baking and curing – grinding – copper plating – electroplating – outer layer circuitry. After resin plugging, any excess resin overflowing from the hole openings needs to be ground down to prevent subsequent poor plating or circuit defects. However, this process still faces the following technical challenges in practical applications: Firstly, the resin undergoes volume shrinkage during curing. Constrained by the hole walls, significant shrinkage stress forms within the cured resin. During subsequent high-temperature processes such as soldering and reflow soldering, the significant difference in the coefficient of thermal expansion (CTE) between the via-filling resin, the electroplated copper layer, and the PCB substrate leads to thermal stress concentration at the interface. When this thermal stress exceeds the interfacial bonding strength, it can easily cause delamination or even detachment of the capping copper layer from the resin interface, severely impacting the electrical connection reliability and lifespan of the product.

[0004] Secondly, in existing POFV processes, the grinding (ceramic grinding plate) after resin curing is only used to remove excess resin overflowing from the orifices, its function limited to "cleaning." Current technology has not recognized that the grinding process can be given a more proactive function—for example, synergistically releasing residual stress within the resin during the leveling process. This limited understanding of the grinding process's function means that the interfacial stress problem in POFV structures has consistently failed to be effectively resolved at the source of the process.

[0005] Third, the POFV process has extremely high requirements for pad flatness, but depressions often appear after resin plugging, leading to reduced flatness of the electroplated pads and causing problems such as poor contact and abnormal signal transmission. Existing technologies mostly improve flatness by adding grinding or polishing steps, but these methods are all post-treatment repairs and fail to address the root cause of poor flatness at the source of stress. Summary of the Invention

[0006] In view of the above situation, the main objective of the present invention is to propose a manufacturing process for POFV type printed circuit boards with interface stress buffering, so as to solve the above-mentioned technical problems.

[0007] This invention proposes a fabrication process for POFV-type printed circuit boards with interface stress buffering, the process comprising the following steps: Step 1: The copper-clad laminate is sequentially cut, inner layer circuit fabrication, browning and lamination processes are performed to obtain a multi-layer laminated board. Step 2: Drill through holes at the pad positions of the multilayer laminated board, so that the through holes are within the pad position area, to obtain a board with a hole-in-pad structure; Step 3: Perform copper plating and first board electroplating on the board with the through hole structure in sequence to form a conductive metal layer on the inner wall of the through hole, and obtain a board with metallized hole wall. Step 4: Perform resin plugging treatment on the metallized hole wall plate, fill the through hole with resin and cure it to obtain resin-filled plate; Step 5: Perform stress pretreatment on the resin-filled plate to release the internal stress of the cured plugging resin before subsequent processing, and obtain the stress-pretreated plate. Step 6: Perform a surface flattening treatment on the prestressed plate to remove the resin that has overflowed onto the plate surface and make the plate surface flat, thus obtaining a flattened plate. Step 7: Perform shadow processing, second board electrical processing, outer layer circuit fabrication and surface treatment on the planarized board in sequence, so that a conductive cap layer is formed on the resin surface inside the through hole and the outer layer circuit and finished surface treatment are completed to obtain a POFV type printed circuit board with interface stress buffer structure.

[0008] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. This invention adds a stress pretreatment step between resin curing and board surface leveling, so that the pore-filling resin undergoes a controllable thermal expansion and contraction cycle before grinding. The resin is heated to above the glass transition temperature of the resin to enable the molecular chain segments to move and release the internal stress frozen during the curing process. Then, it is slowly cooled at a specific rate to make the resin reach a more stable stress state. This effectively breaks the technical prejudice of "grinding must be done immediately after curing" in the prior art, so that the resin is already at a low stress level before entering the leveling process.

[0009] 2. This invention further transforms the board surface flattening process from passive cleaning to an active stress-relieving tool. This allows the grinding process to remove excess resin while simultaneously utilizing the micro-compression effect of the brush on the resin surface to further eliminate residual stress. Stress pretreatment places the resin in a more stable stress state during flattening, making it less prone to deformation and springback. The micro-compression effect of the flattening process further releases any residual stress that the pretreatment could not completely eliminate—forming a synergistic stress management chain of "pre-release + post-guidance." This significantly reduces the interface stress level of the final POFV structure, thereby significantly improving pad flatness and the bonding reliability of the capping copper layer.

[0010] 3. This invention achieves stress relief by utilizing the existing grinding process in the POFV process, without adding extra processes or special equipment. It achieves systematic management of interface stress simply by expanding the function and adjusting the timing of existing process steps—inserting stress pretreatment between curing and grinding. This solution improves product reliability without increasing manufacturing costs, making it particularly suitable for electronic products such as Bluetooth headsets and cameras that require miniaturization and high reliability.

[0011] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by means of embodiments of the invention. Attached Figure Description

[0012] Figure 1 This is a flowchart illustrating the fabrication process of the POFV type printed circuit board with interface stress buffering proposed in this invention.

[0013] Figure 2 This is a comparative experimental diagram showing the resin indentation depth inside the POFV pores of the present invention and existing technologies under different temperature conditions and processes.

[0014] Figure 3 This is a comparative diagram of the POFV porosity of the present invention and existing technologies under different temperature conditions for various processes.

[0015] Figure 4 This is a comparative diagram of the interface crack rate after thermal shock of the present invention and the prior art in various processes after thermal shock cycles.

[0016] Figure 5 This is an experimental comparison chart showing the change in flatness after multiple reflow soldering processes of the present invention and existing technologies. Detailed Implementation

[0017] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0018] These and other aspects of the embodiments of the present invention will become clear from the following description and accompanying drawings. In these descriptions and drawings, some specific embodiments of the present invention are specifically disclosed to illustrate some ways of implementing the principles of the embodiments of the present invention; however, it should be understood that the scope of the embodiments of the present invention is not limited thereto.

[0019] Example 1: Please see Figure 1 This embodiment 1 provides a fabrication process for a POFV type printed circuit board with interface stress buffering, the process including the following steps: Step 1: Cut the copper-clad laminate (CCL) into blanks and bake it at 110℃ for 1 hour. Coat the surface of the CCL with a wet film, controlling the thickness of the wet film to be 12μm. Expose and develop the board after coating the wet film to form the inner layer circuit pattern. Then, etch the developed board to remove the copper layer not covered by the wet film to form the inner layer circuit. Brown the board at 28℃ for 40 seconds. After browning, perform lamination. The lamination process includes a preheating section, a heating section, and a curing section. The preheating section has a temperature of 80℃, a pressure of 0.35kg / cm2, and a time of 30min. The heating section has a temperature of 120℃, a pressure of 7.0kg / cm2, and a time of 30min. The curing section has a temperature of 180℃, a pressure of 21.0kg / cm2, and a time of 60min to obtain a multilayer laminated board. Step 2: Drill through holes at the pad positions of the multilayer laminated board. The drill bit speed is 30,000 rpm, the feed rate is 1.5 m / min, and the diameter of the through hole is 0.15 mm. Make the through hole located in the pad position area to obtain a board with a hole-in-pad structure. Step 3: Perform copper plating on the board with the hole-in-the-pan structure. The desmearing rate of the copper plating is 0.15 mg / cm2, and the backlight level of the hole wall after copper plating is 9. After copper plating, perform the first board electroplating treatment. The current density of the first board electroplating treatment is 1.5 ASD. A conductive metal layer is formed on the inner wall of the through hole, and the hole wall metallized board is obtained. Step 4: Perform resin plugging treatment on the metallized hole wall plate. Fill the guide hole with resin, the plugging pressure is 4 kg / cm2, and the plugging speed is 1 m / min. After resin filling, perform segmented curing. The first stage curing temperature is 80℃ for 30 min, the second stage curing temperature is 120℃ for 60 min, and the third stage curing temperature is 150℃ for 30 min to obtain the resin-filled plate. Step 5: Perform stress pretreatment on the resin-filled plate. Heat the resin-filled plate to 130℃ and hold for 10 minutes. Then cool it to room temperature at a rate of 1℃ / min to release the internal stress of the plugging resin and obtain the stress-pretreated plate. Step 6: Perform surface flattening treatment on the stress-pretreated plate using a ceramic grinding plate. The grinding speed is 1.5 m / min and the grinding brush current is 1.5 A. After grinding, control the copper reduction to 2 μm, remove the resin overflowing onto the plate surface and flatten the plate surface to obtain a flattened plate. Step 7: Perform shadowing on the planarized board. The activation temperature for shadowing is 25℃, and the activation time is 15s. After shadowing, perform a second board electrical treatment. The current density for the second board electrical treatment is 1.5ASD. After the second board electrical treatment, perform outer layer circuit fabrication, which includes exposure and development. The exposure energy is 60mJ / cm2, and the development time is 50s. After outer layer circuit fabrication, perform surface treatment, which includes solder mask fabrication and tin plating. The tin temperature for tin plating is 230℃, and the immersion time is 2s. This forms a conductive cap layer on the resin surface inside the vias and completes the surface treatment of the outer layer circuit and the finished product, resulting in a POFV type printed circuit board with an interface stress buffer structure, denoted as A1.

[0020] Example 2: This embodiment 2 provides a fabrication process for a POFV type printed circuit board with interface stress buffering, the process including the following steps: Step 1: Cut the copper-clad laminate (CCL) into blanks and bake it at 170℃ for 5 hours. Coat the surface of the CCL with a wet film, controlling the thickness of the wet film to be 25μm. Expose and develop the board after coating the wet film to form the inner layer circuit pattern. Then, etch the developed board to remove the copper layer not covered by the wet film, forming the inner layer circuit. Brown the board at 45℃ for 90 seconds. After browning, perform lamination. The lamination process includes a preheating section, a heating section, and a curing section. The preheating section has a temperature of 120℃, a pressure of 3.5kg / cm2, and a time of 60min. The heating section has a temperature of 180℃, a pressure of 14.0kg / cm2, and a time of 60min. The curing section has a temperature of 220℃, a pressure of 35.0kg / cm2, and a time of 120min, resulting in a multilayer laminated board. Step 2: Drill through holes at the pad positions of the multilayer laminated board. The drill bit speed is 100,000 rpm, the feed rate is 8.0 m / min, and the diameter of the through hole is 0.50 mm. Make the through hole located in the pad position area to obtain a board with a hole-in-pad structure. Step 3: Perform copper plating on the board with the hole-in-the-pan structure. The desmearing rate of the copper plating is 0.35 mg / cm2, and the backlight level of the hole wall after copper plating is 10. After copper plating, perform the first board electroplating treatment. The current density of the first board electroplating treatment is 2.5 ASD. A conductive metal layer is formed on the inner wall of the via, resulting in a board with metallized hole walls. Step 4: Perform resin plugging treatment on the metallized hole wall plate. Fill the through hole with resin, the plugging pressure is 10 kg / cm2, and the plugging speed is 2 m / min. After resin filling, perform two-stage curing. The first stage curing temperature is 110℃ for 30 min, and the second stage curing temperature is 150℃ for 60 min to obtain the resin-filled plate. Step 5: Perform stress pretreatment on the resin-filled plate. Heat the resin-filled plate to 170℃ and hold for 60 minutes. Then cool it to room temperature at a rate of 5℃ / min to release the internal stress of the plugging resin and obtain the stress-pretreated plate. Step 6: Perform surface flattening treatment on the stress-pretreated plate using a ceramic grinding plate. The grinding speed is 4.0 m / min and the grinding brush current is 2.5 A. After grinding, control the copper reduction to 5 μm, remove the resin overflowing onto the plate surface and flatten the plate surface to obtain a flattened plate. Step 7: Perform shadowing on the planarized board. The activation temperature for shadowing is 35℃, and the activation time is 35s. After shadowing, perform a second board electrical treatment. The current density for the second board electrical treatment is 2.5ASD. After the second board electrical treatment, perform outer layer circuit fabrication, which includes exposure and development. The exposure energy is 150mJ / cm2, and the development time is 60s. After outer layer circuit fabrication, perform surface treatment, which includes solder mask fabrication and tin plating. The tin temperature for tin plating is 265℃, and the immersion time is 5s. This forms a conductive cap layer on the resin surface inside the vias and completes the surface treatment of the outer layer circuit and the finished product, resulting in a POFV type printed circuit board with an interface stress buffer structure, denoted as A2.

[0021] Example 3: This embodiment 3 provides a fabrication process for a POFV type printed circuit board with interface stress buffering, the process including the following steps: Step 1: Cut the copper-clad laminate (CCL) into blanks and bake it at 140℃ for 3 hours. Coat the surface of the CCL with a wet film, controlling the thickness of the wet film to 18μm. Expose and develop the board after coating the wet film to form the inner layer circuit pattern. Then etch the developed board to remove the copper layer not covered by the wet film, forming the inner layer circuit. Brown the board at 36℃ for 65 seconds. After browning, perform lamination. The lamination process includes a preheating section, a heating section, and a curing section. The preheating section has a temperature of 100℃, a pressure of 1.9kg / cm2, and a time of 45min. The heating section has a temperature of 150℃, a pressure of 10.5kg / cm2, and a time of 45min. The curing section has a temperature of 200℃, a pressure of 28.0kg / cm2, and a time of 90min, resulting in a multilayer laminated board. Step 2: Drill through holes at the pad positions of the multilayer laminated board. The drill bit speed is 65000 rpm, the feed rate is 4.8 m / min, and the diameter of the through hole is 0.33 mm. Make the through hole located in the pad position area to obtain a board with a hole-in-pad structure. Step 3: Perform copper plating on the board with the hole-in-the-pan structure. The desmearing rate of the copper plating is 0.25 mg / cm2, and the backlight level of the hole wall after copper plating is 9.5. After copper plating, perform the first board electroplating treatment. The current density of the first board electroplating treatment is 2.0 ASD. A conductive metal layer is formed on the inner wall of the via, resulting in a board with metallized hole walls. Step 4: Perform resin plugging treatment on the metallized hole wall plate. Fill the through hole with resin, the plugging pressure is 7 kg / cm2, and the plugging speed is 1.5 m / min. After resin filling, perform constant temperature curing at 130℃ for 75 min to obtain the resin-filled plate. Step 5: Perform stress pretreatment on the resin-filled plate. Heat the resin-filled plate to 150℃ and hold for 35 minutes. Then cool it to room temperature at a rate of 3℃ / min to release the internal stress of the plugging resin and obtain the stress-pretreated plate. Step 6: Perform surface flattening treatment on the stress-pretreated plate using a ceramic grinding plate. The grinding speed is 2.8 m / min, the grinding brush current is 2.0 A, and the copper reduction is controlled to be 3.5 μm after grinding. Remove the resin overflowing onto the plate surface and flatten the plate surface to obtain a flattened plate. Step 7: Perform shadowing on the planarized board. The activation temperature for shadowing is 30℃, and the activation time is 25s. After shadowing, perform a second board electrical treatment. The current density for the second board electrical treatment is 2.0ASD. After the second board electrical treatment, perform outer layer circuit fabrication, which includes exposure and development. The exposure energy is 105mJ / cm2, and the development time is 55s. After outer layer circuit fabrication, perform surface treatment, which includes solder mask fabrication and tin spraying. The tin temperature for tin spraying is 248℃, and the immersion time is 3.5s. This forms a conductive cap layer on the resin surface inside the vias and completes the surface treatment of the outer layer circuit and the finished product, resulting in a POFV type printed circuit board with an interface stress buffer structure, denoted as A3.

[0022] Comparative Example 1: Drilling: Drilling through holes on a PCB board; Chemical copper plating: Applying copper plating to the board after drilling to form a conductive layer on the hole walls; First electroplating: The first electroplating is performed on the board after copper plating, and the plating thickness is controlled at 20-40μm; Resin plugging: Filling the guide hole with resin; Resin grinding: Remove the resin that has overflowed from the hole by grinding; Second copper plating: The polished board is subjected to copper plating treatment again; Secondary electroplating: A second electroplating process is performed on the sheet metal. Pattern Transfer: Outer layer circuitry is fabricated. A PCB board, denoted as D1, is obtained by controlling the resin via filling fullness and thermal stress after one and two electroplating processes.

[0023] Comparative Example 2: S1. Drill holes on the PCB board; S2. The first electroplating of copper on the whole board metallizes the PCB board surface and the inner wall of the hole to form a copper plating layer. S3. Fill the copper-plated holes with resin. S4. Grind the resin outside the overflow hole clean; S5. Etch the resin surface inside the hole so that the resin plane is lower than the board surface after the first copper plating. S6. Micro-etch and roughen the copper exposed in the hole wall after etching. S7. Second copper plating for full-board metallization. This yields a PCB board with highly reliable POFV vias, denoted as D2.

[0024] Comparative Example 3: S1, Previous process; S2. Drilling: Drilling holes on the PCB board; S3, Plating Copper 1: Plating copper on the PCB board to form a copper layer on the surface of the PCB board and the surface of the hole walls; S4, VCP electroplating: Using VCP equipment to electroplat the PCB board to thicken the copper layer on the surface of the PCB board and the surface of the hole walls; S5. Resin plugging: Fill the copper-plated holes with resin plugging oil. Do not add thinner to the resin plugging oil. S6. Ceramic Grinding Plate: After the resin plugging oil has cured, use a PCB grinding machine with ceramic rollers to grind the plate and clean the resin that has overflowed from the holes. S7, Plating Copper II: A second plating copper process is performed on the PCB board to form a copper layer on the surface of the via-filling resin, while also thickening the copper layer on the surface of the PCB board. S8. Electroplating of the board surface: A second electroplating is performed on the PCB board to thicken the resin surface of the vias and the copper layer on the surface of the PCB board. S9, Dry Film: Transferring circuit patterns from film to the PCB board surface through lamination, exposure, and development; S10, Acid Etching: Etching the outer layer circuitry onto the PCB board using an acidic solution; S11. Post-processing. A high-reliability POFV board, denoted as D3, is obtained.

[0025] Comparative Example 4: Step 1: Drill through holes on the printed circuit board for resin plugging, and electroplate copper onto the printed circuit board after drilling to form a continuous copper layer between the surface of the printed circuit board and the inside of the holes. Step 2: Plug the through holes with resin, bake to fully cure the resin inside the holes, and then use a brush to remove the excess resin from the surface of the printed circuit board. Step 3: Treat the surface of the printed circuit board to create a depression in the resin relative to the surface of the printed circuit board; Step 4: Electroplat copper onto the printed circuit board to fill the depressions formed by the via-filling resin, so that the printed circuit board has a flat copper surface layer. Step 5: Create the outer layer pattern to form a through-hole structure containing solder pads. The resulting printed circuit board with the through-hole structure containing solder pads is denoted as D4.

[0026] To verify the difference in preparation process between the present invention and existing technologies, experimental samples were prepared according to the processes of Comparative Examples 1 to 4 and the present invention 2. All samples used the same type of FR-4 (TG170) copper-clad laminate as the substrate, with a finished board thickness of 1.6 mm ± 0.10 mm, a copper thickness of 35 μm, a via diameter of 0.30 mm, and the same type of epoxy resin for plugging the vias. Ten parallel samples (10 PNL per group) were taken from each group. After preparation and before each test, all samples were conditioned for at least 24 hours at a temperature of 23℃ ± 2℃ and a relative humidity of 50% ± 10% to ensure the accuracy and repeatability of the test results. The experimental details are as follows: (a) Test of resin indentation depth in POFV pores Metallographic sections were prepared according to standard IPC-TM-650 2.1.1: Three POFV holes at different locations were taken from each test board (located in the central, edge, and corner areas of the board surface, respectively). After sampling, they were cold-mounted with epoxy resin, followed by coarse grinding (sandpaper #400-#800), fine grinding (sandpaper #1200-#2000), and polishing (polishing cloth with diamond polishing fluid, with the particle size decreasing from 3μm to 1μm). Finally, ammonium persulfate solution was used for micro-etching for 10-15 seconds to clearly display the interface morphology. The prepared sections were observed and measured under a 500x metallographic microscope. The vertical distance between the lowest point of the copper layer at each POFV hole opening and the copper layer on the board surface was measured as the recess depth value. Three different locations were measured for each section, and the average value was calculated. Measurements were performed on each group of samples at five temperatures: 20℃, 25℃, 30℃, 35℃, and 40℃.

[0027] (ii) POFV porosity test Metallographic sections were prepared according to standard IPC-TM-650 2.1.1 (sampling location, section preparation and observation method are the same as for the indentation depth test), and the presence of void areas in the POFV holes was observed under a 500x metallographic microscope. The void ratio in each POFV hole was calculated according to formula (1): void ratio = void area / total cross-sectional area in the hole × 100%.

[0028] The samples in each group were tested at five different temperatures: 20℃, 25℃, 30℃, 35℃, and 40℃. The average value of 10 parallel samples in each group was taken as the final result.

[0029] (III) Interfacial Crack Rate Test after Thermal Shock According to standard JESD22-A104, thermal shock tests were conducted on each group of samples using a two-chamber thermal shock test chamber. The low temperature was set to -55℃±3℃ and the high temperature was set to +125℃±3℃. The residence time of the samples in each temperature zone was 30 minutes (based on the sample surface temperature reaching the set value), and the temperature transition time between the high and low temperatures did not exceed 5 minutes. The samples were taken out after 200, 400, 600, 800 and 1000 cycles, respectively. After each cycle, metallographic sections were prepared according to standard IPC-TM-650 2.1.1, and the cracking of the interface between the cap copper layer and the plugging resin was observed under a 500x metallographic microscope. The interface crack rate of each POFV hole was calculated according to formula (2): Interface crack rate = crack length / total interface length × 100%.

[0030] (iv) Test of flatness change after multiple reflow soldering According to standard IPC / JEDEC J-STD-020, lead-free reflow soldering simulation tests were conducted on each group of samples using a 10-zone reflow oven. The peak reflow temperature was set to 260℃±5℃, the peak temperature was maintained for 20 to 30 seconds, and the liquidus temperature (above 217℃) was maintained for 60 to 150 seconds. Measurements were taken after 1, 2, 3, and 6 reflow soldering cycles, and the samples were allowed to cool naturally at 23℃±2℃ for at least 2 hours after each reflow soldering. The flatness (i.e., the depth of depression) of the POFV pad surface was measured using a 3D microscope or a laser confocal microscope. The change in flatness of each POFV hole was calculated according to formula (3): Change in flatness = Depth of depression after reflow soldering - Depth of depression before reflow soldering.

[0031] (v) POFV orifice interface microcrack density test After each group of samples underwent 1000 thermal shock cycles, metallographic sections were prepared according to standard IPC-TM-650 2.1.1, and the microstructure of the interface between the copper layer at the POFV orifice and the plugging resin was observed at high magnification using a scanning electron microscope (SEM). The observation area was divided into three locations: the orifice corner area (stress concentration area), the middle area of ​​the orifice wall, and the area near the bottom of the orifice. The microcrack density of each observation area was calculated according to formula (4): microcrack density = number of microcracks / interface length.

[0032] like Figure 2As shown, Comparative Example 3 exhibits the highest indentation depth under all temperature conditions, and its growth rate increases the fastest with increasing temperature (from 22.8 μm to 36.2 μm). This is because Comparative Example 3 only uses a ceramic grinding plate for physical cleaning of the resin, without taking any stress management measures for the resin used to plug the holes. The mismatch in the coefficient of thermal expansion (CTE) between the resin and the substrate is most prominent at high temperatures, resulting in the most severe resin deformation and rebound. Comparative Example 1, through optimization of electroplating parameters, controls the resin Z-axis expansion value to some extent, achieving an indentation depth superior to Comparative Example 3 but inferior to Comparative Examples 2 and 4. Comparative Example 2, due to its grooved inlay structure, provides more stable support for the cap copper layer. Comparative Example 4 improves surface smoothness through a secondary electroplating filling method after resin indentation. The indentation depths of both are similar and superior to Comparative Example 1.

[0033] The indentation depths of this invention were 9.6 μm, 7.8 μm, 10.2 μm, 11.7 μm and 13.6 μm at temperatures ranging from 20°C to 40°C, respectively. The increase with increasing temperature was the smallest (approximately 4.0 μm increase from 20°C to 40°C). This is because the stress pretreatment allowed the pore-filling resin to undergo a controlled thermal expansion and contraction cycle before grinding. The shrinkage stress generated inside the resin due to curing was fully released before entering the leveling process. The leveling process further eliminated residual stress through the micro-compression effect of the brush on the resin surface. The "pre-release + post-guidance" stress management chain formed by the two processes enabled the resin to maintain a relatively stable dimensional state under subsequent high-temperature conditions.

[0034] like Figure 3 As shown, Comparative Example 3 exhibited the highest void ratio under all temperature conditions, reaching 7.6% at 40℃. This is primarily because Comparative Example 3 did not undergo any stress pretreatment step. During curing, the shrinkage stress and microcracks formed within the resin further expanded under high-temperature conditions, resulting in visible void defects. Comparative Example 1 had a void ratio of 6.3% at 40℃, exceeding the 5% limit specified in the IPC-6012 Class 3 standard, as optimization of electroplating parameters alone could not eliminate internal resin stress at its source. Comparative Example 2 had a void ratio of 4.1% at 40℃, and Comparative Example 4 had a void ratio of 5.4%, with Comparative Example 4 slightly exceeding the IPC standard limit at 40℃. The void ratio of this invention meets the IPC-6012 Class 3 standard requirements (2.9% at 40℃) under various temperature conditions. Because the stress pretreatment in step 5 fully releases the internal stress of the resin, it avoids the expansion of microcracks or voids caused by stress concentration during curing. The smoothing treatment in step 6 does not cause additional damage to the internal structure of the resin, thus keeping the void ratio at a low level at various temperatures.

[0035] like Figure 4As shown, Comparative Example 1 exhibited a high interface crack rate of 41.3% after 1000 cycles, primarily due to the fact that Comparative Example 1 only adjusted the resin's Z-axis expansion value by controlling electroplating parameters, without any reinforcement treatment at the interface between the resin and the cap copper. Comparative Example 3 showed a crack rate of 37.2% after 1000 cycles, with the most prominent risk of blistering and delamination caused by the mismatch between the resin and copper layer CTE. Comparative Example 2 significantly outperformed Comparative Examples 1 and 3 at all cycle counts (18.3% after 1000 cycles). Its grooved inlay structure shifted the stress point of the cap copper from the interface corner to the inside of the groove, effectively dispersing the interface stress generated during thermal shock. Comparative Example 4 showed a crack rate of 25.8% after 1000 cycles, as it only improved the appearance smoothness through a filling method without addressing stress management. The present invention has a crack rate of only 9.8% after 1000 cycles. This is because the stress pretreatment in step 5 allows the internal stress of the plugging resin to be fully released before thermal shock, and the smoothing treatment in step 6 further eliminates residual stress. The synergistic stress management chain formed by the two results in the stress level accumulated at the interface being much lower than that of each comparative example.

[0036] like Figure 5 As shown, Comparative Example 3 exhibited the largest change in flatness (20.3 μm) after 6 reflow soldering cycles. This was primarily due to the significant difference in thermal expansion coefficients between the via-filling resin and the copper layer used in Comparative Example 3. Repeated expansion and contraction of the resin during the 260℃ peak high-temperature process led to continuous deterioration of flatness. Comparative Example 1 showed a flatness change of 16.3 μm after 6 reflow soldering cycles. While optimizing the electroplating parameters to control the resin's Z-axis expansion value had some effect, it was limited. Comparative Example 4, due to its secondary electroplating filling method, only improved the appearance flatness without addressing the stress issue, resulting in a change of 12.7 μm after 6 reflow soldering cycles. Comparative Example 2, with its grooved inlay structure providing more stable mechanical support to the cap copper, showed a change of 9.7 μm after 6 reflow soldering cycles. The smoothness change after 6 reflow soldering cycles was 6.3 μm. The main reason for this is that the stress pretreatment in step 5 ensured that the resin was in a stable low-stress state before reflow soldering, and the resin had minimal deformation and rebound after multiple high-temperature reflow soldering cycles.

[0037] The present invention also includes a comparative experiment on the microcrack density at the POFV orifice interface of various processes after 1000 thermal shock cycles, as shown in Table 1: Table 1: Comparison of POFV orifice interface microcrack density for each process after 1000 thermal shock cycles (unit: cracks / mm).

[0038] As shown in Table 1, Comparative Example 1 exhibits the highest microcrack density (10.7 cracks / mm) at the orifice corner. Since no reinforcement or stress management measures were implemented at the resin-cap copper interface in Comparative Example 1, stress concentration was most significant during thermal shock. Comparative Example 3 shows a microcrack density of 9.4 cracks / mm at the orifice corner, indicating the highest interfacial stress due to CTE mismatch. Comparative Example 4 shows a microcrack density of 6.4 cracks / mm at the orifice corner, suggesting that its secondary electroplating filling method has limited improvement on interfacial adhesion. Comparative Example 2 shows a microcrack density of 4.2 cracks / mm at the orifice corner, demonstrating that the grooved inlay structure effectively improves the stress distribution of the cap copper during thermal shock. The present invention has a microcrack density of only 2.4 cracks / mm in the orifice corner area, with an average of only 1.6 cracks / mm. This is because the stress pretreatment in step 5 reduces the initiation source of interface microcracks from the source, and the smoothing treatment in step 6 further eliminates residual stress through micro-compression, thereby fundamentally improving the microstructural integrity of the POFV orifice interface.

[0039] It should be understood that although the steps in the flowcharts of the various embodiments of the present invention are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the various embodiments may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps.

[0040] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0041] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A fabrication process for a POFV-type printed circuit board with interface stress buffering, characterized in that, The process includes the following steps: Step 1: The copper-clad laminate is sequentially cut, inner layer circuit fabrication, browning and lamination processes are performed to obtain a multi-layer laminated board. Step 2: Drill through holes at the pad positions of the multilayer laminated board, so that the through holes are within the pad position area, to obtain a board with a hole-in-pad structure; Step 3: Perform copper plating and first board electroplating on the board with the through hole structure in sequence to form a conductive metal layer on the inner wall of the through hole, and obtain a board with metallized hole wall. Step 4: Perform resin plugging treatment on the metallized hole wall plate, fill the through hole with resin and cure it to obtain resin-filled plate; Step 5: Perform stress pretreatment on the resin-filled plate to release the internal stress of the cured plugging resin before subsequent processing, and obtain the stress-pretreated plate. Step 6: Perform a surface flattening treatment on the prestressed plate to remove the resin that has overflowed onto the plate surface and make the plate surface flat, thus obtaining a flattened plate. Step 7: Perform shadow processing, second board electrical processing, outer layer circuit fabrication and surface treatment on the planarized board in sequence, so that a conductive cap layer is formed on the resin surface inside the through hole and the outer layer circuit and finished surface treatment are completed to obtain a POFV type printed circuit board with interface stress buffer structure.

2. The fabrication process of the POFV type printed circuit board with interface stress buffering according to claim 1, characterized in that, In step 1, during the process of obtaining the multi-layer pressed board, the material cutting process also includes a baking process, in which the baking temperature is 110℃-170℃ and the baking time is 1h-5h.

3. The fabrication process of the POFV type printed circuit board with interface stress buffering according to claim 2, characterized in that, The inner layer circuit fabrication includes: coating a wet film on the surface of the copper-clad laminate, with the wet film thickness controlled between 12μm and 25μm; sequentially exposing and developing the board after coating the wet film to form the inner layer circuit pattern, resulting in a developed board; and etching the developed board to remove the copper layer not covered by the wet film, thus forming the inner layer circuit.

4. The fabrication process of the POFV type printed circuit board with interface stress buffering according to claim 3, characterized in that, The browning treatment temperature is 28℃-45℃, and the browning time is 40s-90s; the pressing treatment includes a preheating section, a heating section, and a curing section; The preheating section temperature is 80℃-120℃, the pressure is 0.35kg / cm2~3.5kg / cm2, and the time is 30min-60min; The temperature in the heating section is 120℃-180℃, the pressure is 7.0kg / cm2~14.0kg / cm2, and the time is 30min-60min; The curing temperature is 180℃-220℃, the pressure is 21.0kg / cm2~35.0kg / cm2, and the time is 60min-120min.

5. The fabrication process of the POFV type printed circuit board with interface stress buffering according to claim 4, characterized in that, In step 2, during the process of obtaining the plate with the hole-in-the-disk structure, the drill bit speed for drilling the through hole is 30,000 rpm-100,000 rpm, and the feed rate is 1.5 m / min-8.0 m / min; the diameter of the through hole is 0.15 mm-0.50 mm.

6. The fabrication process of the POFV type printed circuit board with interface stress buffering according to claim 5, characterized in that, In step 3, during the process of obtaining the metallized hole wall board, the desmearing rate of the copper plating treatment is 0.15mg / cm2-0.35mg / cm2; the backlight level of the hole wall after copper plating treatment is ≥9; and the current density of the first board electroplating treatment is 1.5ASD-2.5ASD.

7. The fabrication process of the POFV type printed circuit board with interface stress buffering according to claim 6, characterized in that, In step 4, during the process of obtaining the resin-filled plate, the plugging pressure of the resin plugging treatment is 4 kg / cm2-10 kg / cm2, and the plugging speed is 1 m / min-2 m / min; the curing is segmented curing or constant temperature curing. Segmented curing includes first-stage curing, second-stage curing, and third-stage curing; The curing process involves three stages: the first stage is cured at 80℃ for 30 minutes; the second stage is cured at 120℃ for 60 minutes; and the third stage is cured at 150℃ for 30 minutes. The temperature for constant temperature curing is 110℃-150℃, and the time is 60min-90min.

8. The fabrication process of the POFV type printed circuit board with interface stress buffer according to claim 7, characterized in that, In step 5, during the process of obtaining the stress-pretreated plate, the stress pretreatment is as follows: the resin-filled plate is heated to 130℃-170℃ and held at that temperature for 10min-60min, and then cooled to room temperature at a rate of 1℃ / min-5℃ / min to release the internal stress of the pore-filling resin.

9. The fabrication process of the POFV type printed circuit board with interface stress buffer according to claim 8, characterized in that, In step 6, during the process of obtaining the flattened plate, the plate surface flattening treatment is a ceramic grinding process, with a grinding speed of 1.5m / min-4.0m / min and a grinding brush current of 1.5A-2.5A; after grinding, the copper reduction is controlled to be within 2μm-5μm.

10. The fabrication process of the POFV type printed circuit board with interface stress buffering according to claim 9, characterized in that, In step 7, during the process of obtaining the POFV type printed circuit board with an interface stress buffer structure, the activation temperature of the shadow treatment is 25℃-35℃, and the activation time is 15s-35s; the current density of the second board electrical treatment is 1.5ASD-2.5ASD; the outer layer circuit fabrication includes exposure and development processes. The exposure energy is 60mJ / cm2-150mJ / cm2, and the development time is 50s-60s. The surface treatment includes solder resist fabrication and tin spraying. The tin temperature for tin spraying is 230℃-265℃, and the immersion time is 2s-5s.

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