A method for manufacturing a blind via in an inner-outer layer circuit splicing and uncovering area and a circuit board thereof

Abstract

The application belongs to the technical field of FPC circuit splicing and blind hole making, and discloses an inner and outer layer circuit splicing and blind hole making method and a circuit board, which provides an inner layer FPC, the inner layer FPC comprises a non-splicing area and a splicing area, the non-splicing area is formed with an inner layer circuit, the splicing area is reserved with exposed inner layer copper, and the surface of the inner layer copper is not formed with a selective copper plating layer; an outer layer single copper is provided, and the position of the outer layer single copper corresponding to the splicing area is hollowed out; the outer layer single copper is laminated and combined with the inner layer FPC, so that the exposed inner layer copper of the splicing area is directly exposed to the surface of the outer layer through the hollowing; the blind hole making, selective plating of the splicing area and the blind hole making, selective plating of the uncovering area are simultaneously performed on the outer layer; the uncovering area is not made with a blind hole on the inner layer and is not selectively plated with copper; the outer layer circuit is made on the surface of the outer layer single copper and the surface of the exposed inner layer copper, so that the outer layer circuit is electrically connected with the exposed inner layer copper.

Description

Technical Field

[0001] This application relates to the field of FPC line splicing and blind via technology, and more specifically, to a method for splicing inner and outer layer lines and fabricating blind vias in the uncovered area, and a circuit board thereof. Background Technology

[0002] In existing multilayer flexible circuit board manufacturing technology, when it is necessary to expose specific areas of the inner layer circuitry to the outer layer to form interlayer splicing or electrical interconnection, the usual process path is to complete the PAD fabrication in the inner layer, expose it to the outer layer, and then perform drilling and copper plating.

[0003] However, this approach is limited by factors such as thermal expansion and contraction of multilayer materials, mechanical alignment accuracy, and electroplating uniformity, making it prone to selective plating misalignment, holes, and positional deviations between selectively plated PADs and circuit PADs. Furthermore, these defects are difficult to correct through subsequent processes on flexible substrates. In addition, traditional designs for the uncovered area often require pre-fabrication of laser-drilled blind vias in the inner layer and the execution of selective copper plating to create interlayer conductivity or uncovering boundaries.

[0004] This inner layer blind hole process not only increases the investment in independent equipment and operation steps, but also extends the overall production cycle and increases the cumulative error rate of multi-layer alignment, resulting in severe challenges to the yield and cost of multi-layer FPCs in high-end applications.

[0005] Therefore, this application proposes a method for splicing inner and outer layer circuits and fabricating blind holes in the uncovered area, as well as a circuit board thereof, to solve the aforementioned problems.

[0006] Application content

[0007] To address the aforementioned issues, this application provides a method for splicing inner and outer layer circuits and fabricating blind vias in the uncovered area, along with a circuit board thereof.

[0008] This application provides a method for splicing inner and outer layer circuits and fabricating blind vias in the uncovered area, and the circuit board thereof adopts the following technical solution:

[0009] A method for splicing inner and outer layer circuits and fabricating blind holes in the uncovered area includes the following steps:

[0010] An inner layer FPC is provided, the inner layer FPC including a non-splicing area and a splicing area, the non-splicing area having inner layer circuitry formed thereon, the splicing area having exposed inner layer copper, and the inner layer copper surface not having a selectively plated copper layer formed thereon.

[0011] An outer single copper layer is provided, and the position of the outer single copper layer corresponding to the splicing area is hollowed out;

[0012] The outer single copper layer is laminated with the inner FPC layer, so that the exposed inner copper layer in the splicing area is directly exposed to the outer surface through the cutout.

[0013] Simultaneously, through-holes and selective plating are performed in the splicing area and the uncovered area on the outer layer; wherein, no through-holes are made and no copper is selectively plated in the inner layer of the uncovered area;

[0014] An outer layer circuit is fabricated on the outer single copper surface and the exposed inner copper surface, so that the outer layer circuit is electrically connected to the exposed inner copper.

[0015] A circuit board, manufactured based on the above method, includes:

[0016] The inner FPC includes a non-splicing area and a splicing area. The non-splicing area has inner layer circuitry, and the splicing area retains exposed inner layer copper, and the surface of the inner layer copper does not have a selectively plated copper layer.

[0017] An outer single copper layer is laminated onto the surface of the inner FPC layer. The outer single copper layer has a hollow structure at the position corresponding to the splicing area. The hollow structure allows the exposed inner copper layer of the splicing area to be directly exposed to the outer surface of the multilayer FPC.

[0018] The through-blind hole structure includes a first through-blind hole located in the splicing area and a second through-blind hole located in the uncovering area. Both the first through-blind hole and the second through-blind hole are formed only by synchronous fabrication and selective plating of the outer layer.

[0019] The outer layer circuitry is formed on the outer single copper surface and electrically connected to the exposed inner copper layer.

[0020] The uncovered area does not have blind holes or selective copper plating in the inner layer.

[0021] Furthermore, the hollowed-out shape of the outer single copper layer matches the shape of the inner copper layer in the splicing area, and the edge of the hollowed-out layer has a preset alignment overlap with the edge of the inner copper layer.

[0022] The above technical solution enables precise bonding between the outer layer circuitry and the inner copper layer. Simultaneously, the through-hole structure in the uncovered area is entirely formed synchronously with the outer layer, eliminating blind holes and selective copper plating layers in the inner layer. This fundamentally solves the problems of selective plating misalignment and hole breakage, and achieves process merging and layer simplification in the product structure.

[0023] Furthermore, the hollowed-out shape of the outer single copper layer matches the shape of the inner copper layer in the splicing area, and the edge of the hollowed-out layer has a preset alignment overlap with the edge of the inner copper layer.

[0024] By using the above technical solution, and by pre-setting the alignment overlap between the outer single copper cutout edge and the inner copper edge, the deviation caused by thermal expansion and contraction of materials and mechanical alignment can be absorbed and compensated during the lamination process. This ensures that the boundary between the exposed inner copper layer and the outer cutout area is precisely matched, avoiding insufficient copper layer exposure or edge lifting due to misalignment. This improves the reliability of the splicing area and the outer circuit connection, and reduces the probability of hole breakage during subsequent blind via fabrication.

[0025] Furthermore, the uncovered area retains only the substrate in the inner layer, without forming conductive patterns, blind holes, or selective copper plating.

[0026] The above technical solution simplifies the inner structure of this area to the greatest extent, completely eliminating all the processes required for inner layer blind vias and selective copper plating layers in traditional designs. Simultaneously, it avoids alignment interference between the inner layer selective copper plating layer and the outer layer blind vias, providing a clean interlayer interface for the one-time fabrication of the outer layer's exposed blind vias, and reducing structural stress after lamination.

[0027] Furthermore, before laminating the outer single copper layer with the inner FPC, the exposed inner copper surface of the splicing area of ​​the inner FPC is covered with a peelable protective layer. After lamination, the peelable protective layer is removed to expose the inner copper layer.

[0028] The above technical solution effectively isolates air and mechanical contact during lamination and subsequent transfer processes, preventing copper surface oxidation, scratches, or contamination by foreign matter. After lamination, the protective layer is removed, resulting in a clean copper bonding surface. This ensures the quality of electrical connection between the outer layer circuitry and the inner copper layer, and reduces plating defects and reduced adhesion caused by copper surface contamination.

[0029] Furthermore, the first through-hole penetrates the outer copper layer and extends to the exposed inner copper layer surface, and the second through-hole penetrates the outer copper layer and extends to the substrate surface of the inner FPC.

[0030] The above technical solution enables reliable vertical conductivity between the outer layer circuitry and the inner layer copper through the copper layer inside the via, forming the required interlayer connection in the uncovered area. Furthermore, since the inner layer does not have blind vias or optional copper plating, both types of through-holes can be completed solely through outer layer processing, simplifying the interlayer structure and standardizing the via design.

[0031] Furthermore, the exposed inner copper layer and the outer circuit are electrically connected through a copper layer formed by synchronous selective plating on the outer layer. The copper layer formed by synchronous selective plating simultaneously covers the hole walls of the first through-hole and the second through-hole.

[0032] The above technical solution enables the conductive connection between the splicing area and the uncovered area to be completed in the same electroplating process. This avoids the problems of uneven plating thickness and potential differences caused by step-by-step plating, and ensures the uniformity and density of the copper layer on the hole walls of the two areas, thereby improving the overall electrical performance and long-term reliability of the circuit board.

[0033] Furthermore, when the blind holes are fabricated simultaneously on the outer layer, the first blind hole and the second blind hole are processed in one go using the same laser drilling parameters and electroplating parameters.

[0034] The above technical solution ensures a high degree of consistency in the diameter, depth, and coating quality of the through-holes in the splicing area and the uncovering area. This avoids differences in process windows and repeated equipment adjustments caused by step-by-step processing, while reducing waiting time and material turnover due to process transfers, significantly improving production cycle time and reducing process control complexity.

[0035] Furthermore, the outer single copper layer completely covers the uncovered area, the second through-hole extends from the surface of the outer single copper layer to the substrate of the inner FPC, and there is no additional conductive layer on the inner surface below the uncovered area.

[0036] The above technical solution eliminates the need for an additional conductive layer on the inner surface beneath the uncovering area, allowing the desired electrical functions or mechanical uncovering characteristics to be achieved through the outer blind via. This structural design fully utilizes the integrity of the outer copper layer, avoids material waste caused by additional inner layer pattern fabrication, and provides a clear interlayer separation interface for subsequent selective uncovering.

[0037] Furthermore, at the junction of the exposed inner copper layer and the outer circuit in the splicing area, an integrated copper connection layer is formed by synchronous selective plating of the outer layer. The integrated copper connection layer covers the interface of the junction and the wall of the first through-hole.

[0038] The above technical solution transforms the electrical connection between the inner copper layer and the outer circuitry from a simple planar press-fit contact into a three-dimensional, encapsulated metallurgical bonding structure. This significantly improves the mechanical strength and conductive cross-sectional area of ​​the connection, and effectively suppresses the occurrence of microcracks and electrochemical migration.

[0039] In summary, this application includes at least one of the following beneficial technical effects:

[0040] (1) By transferring all the inner layer splicing lines and blind holes in the uncovered area to the outer layer for synchronous processing, the interlayer processing logic of multilayer FPCs has been completely reconstructed. This not only fundamentally eliminates the quality defects inherent in the traditional inner layer selective plating process, such as alignment misalignment, broken holes, and PAD misalignment, but also achieves significant simplification of the workflow and effective compression of the production cycle by eliminating the independent laser blind hole and selective copper plating process in the inner layer.

[0041] (2) By realizing the direct exposure of the inner layer splicing copper and the inner layer without graphic design of the uncovered area at the product structure level, this solution greatly reduces the interlayer processing complexity and material loss rate of multilayer FPC while ensuring the reliability of electrical connection. Attached Figure Description

[0042] Figure 1 This is a step-by-step schematic diagram of the splicing of inner and outer layer circuits and the fabrication process of through-holes in this application;

[0043] Figure 2 This is a schematic diagram of the method flow of this application;

[0044] Figure 3 This is a plan view of the circuit and hole positions of the L1 to L4 layers of the FPC four-layer board in this application;

[0045] Figure 4 This is a schematic diagram of the interlayer cross-sectional structure of various through holes / blind holes in the four-layer FPC board of this application;

[0046] Figure 5 Microscopic images of defective via pads in existing FPC technology. Detailed Implementation

[0047] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0048] Example:

[0049] The following is in conjunction with the appendix Figure 1 -5 provides further details regarding this application.

[0050] This application discloses a method for splicing inner and outer layer circuits and fabricating blind vias in the uncovered area, including the following steps:

[0051] An inner FPC is provided, which includes a non-splicing area and a splicing area. The non-splicing area forms the inner layer circuit, and the splicing area retains the exposed inner layer copper, and the inner layer copper surface does not form an optional copper plating layer.

[0052] Provide an outer single copper layer, and hollow out the corresponding splicing area of ​​the outer single copper layer;

[0053] The outer single copper layer is laminated with the inner FPC layer, so that the exposed inner copper layer in the splicing area is directly exposed to the outer surface by hollowing out.

[0054] The blind holes in the splicing area and the copper plating in the uncovered area are manufactured and plated simultaneously on the outer layer; however, no blind holes are manufactured and no copper plating is performed on the inner layer of the uncovered area.

[0055] Outer layer circuitry is fabricated on the outer single copper surface and the exposed inner copper surface, so that the outer layer circuitry is electrically connected to the exposed inner copper.

[0056] A circuit board, manufactured based on the above method, includes:

[0057] The inner FPC includes non-splicing areas and splicing areas. The non-splicing areas form inner layer circuits, while the splicing areas retain exposed inner layer copper, and no selective copper plating layer is formed on the surface of the inner layer copper.

[0058] The outer single copper layer is laminated on the surface of the inner FPC. The outer single copper layer has a hollow structure at the position corresponding to the splicing area. The hollow structure allows the exposed inner copper layer in the splicing area to be directly exposed to the outer surface of the multilayer FPC.

[0059] The through-blind hole structure includes a first through-blind hole located in the splicing area and a second through-blind hole located in the uncovering area. Both the first and second through-blind holes are formed only by synchronous fabrication and selective plating of the outer layer.

[0060] The outer layer circuitry is formed on the outer single copper surface and electrically connected to the exposed inner copper layer.

[0061] The uncovered area does not have blind holes or selective copper plating on the inner layer.

[0062] See Figure 1 and Figure 3 The hollowed-out shape of the outer single copper layer matches the shape of the inner copper layer in the splicing area, and the edges of the hollowed-out layer and the edges of the inner copper layer have a preset alignment overlap; this allows the outer layer circuitry to achieve precise overlap with the inner copper layer. At the same time, the through-hole structure in the uncovered area is entirely formed synchronously with the outer layer, and the inner layer no longer retains blind holes or selective copper plating layers, fundamentally solving the problems of selective plating misalignment and hole breakage, and realizing process merging and interlayer simplification in product structure.

[0063] See Figure 1 and Figure 5The hollowed-out shape of the outer single copper layer matches the shape of the inner copper layer in the splicing area, and the edge of the hollowed-out layer has a preset alignment overlap with the edge of the inner copper layer. By presetting the alignment overlap between the edge of the hollowed-out outer single copper layer and the edge of the inner copper layer, the deviation caused by thermal expansion and contraction of materials and mechanical alignment can be absorbed and compensated during the lamination process. This ensures that the boundary between the exposed inner copper layer and the hollowed-out outer area is accurately matched, avoiding insufficient copper layer exposure or edge lifting due to misalignment. This improves the reliability of the splicing area and the outer circuit connection and reduces the probability of hole breakage during subsequent blind via fabrication.

[0064] See Figure 3 and Figure 4 In this design, the uncovered area retains only the substrate in the inner layer, without forming conductive patterns, blind vias, or selective copper plating. This simplifies the inner layer structure to the greatest extent, completely eliminating all the processes required for inner layer blind vias and selective copper plating layers in traditional designs. Simultaneously, it avoids alignment interference between the inner layer selective copper plating layer and the outer layer through-holes, providing a clean interlayer interface for the outer layer to complete the fabrication of through-holes in the uncovered area in one step, and reducing structural stress after lamination.

[0065] See Figure 1 and Figure 2 Before laminating the outer copper layer with the inner FPC layer, the exposed inner copper surface in the splicing area of ​​the inner FPC is covered with a peelable protective layer. After lamination, the peelable protective layer is removed to expose the inner copper. This effectively isolates the copper surface from air and mechanical contact during lamination and subsequent transfer processes, preventing oxidation, scratches, or contamination. Removing the protective layer after lamination directly yields a clean copper bonding surface, ensuring the quality of the electrical connection between the outer circuitry and the inner copper layer, and reducing plating defects and reduced adhesion caused by copper surface contamination.

[0066] See Figure 3 and Figure 4 The first blind via penetrates the outer copper layer and extends to the exposed inner copper surface, while the second blind via penetrates the outer copper layer and extends to the substrate surface of the inner FPC. This allows for reliable vertical conductivity between the outer layer circuitry and the inner copper layer through the copper layer within the via, forming the required interlayer connection in the uncovered area. Furthermore, since the inner layer does not have blind vias or optional copper plating, both types of blind vias can be fabricated solely through the outer layer, simplifying the interlayer structure and standardizing the via design.

[0067] See Figure 1 and Figure 4The exposed inner copper layer and the outer circuitry are electrically connected through a copper layer formed by simultaneous selective plating on the outer layer. This copper layer simultaneously covers the walls of both the first and second through-holes, ensuring that the conductive connection between the splicing area and the uncovered area is completed in the same electroplating process. This avoids the uneven plating thickness and potential differences caused by step-by-step selective plating, and ensures the uniformity and density of the copper layer on the hole walls in both areas, thereby improving the overall electrical performance and long-term reliability of the circuit board.

[0068] See Figure 2 and Figure 3 When fabricating through-holes simultaneously on the outer layer, the first and second through-holes are processed in one go using the same laser drilling and electroplating parameters. This ensures a high degree of consistency in hole diameter, depth, and plating quality between the splicing and uncovering areas. This avoids process window differences and repeated equipment adjustments caused by step-by-step processing, while also reducing waiting time and material turnover due to process transfers, significantly improving production cycle time and reducing process control complexity.

[0069] See Figure 3 and Figure 4 The outer copper layer completely covers the uncovered area, and the second blind via extends from the surface of the outer copper layer to the substrate of the inner FPC layer. Furthermore, there is no additional conductive layer on the inner layer surface below the uncovered area. This allows the required electrical functions or mechanical uncovering characteristics to be achieved through the outer blind via without the need for an additional conductive layer on the inner layer surface below the uncovered area. This structural design fully utilizes the integrity of the outer copper layer, avoids material waste caused by additional pattern fabrication of the inner layer, and provides a clear interlayer separation interface for subsequent selective uncovering.

[0070] See Figure 1 and Figure 4 In the splicing area, the exposed inner copper layer overlaps with the outer circuitry, forming an integrated copper bonding layer through synchronous selective plating of the outer layer. This integrated copper bonding layer covers the interface of the overlap and the wall of the first through-hole. This transforms the electrical connection between the inner copper layer and the outer circuitry from a simple planar press-fit contact into a three-dimensional, encapsulated metallurgical bond structure. This significantly improves the mechanical strength and conductive cross-sectional area of ​​the connection, and effectively suppresses the occurrence of microcracks and electrochemical migration.

[0071] The implementation principle of the method for splicing inner and outer layer circuits and fabricating blind vias in the uncovered area, as described in this application embodiment, is as follows:

[0072] By retaining only the circuit pattern of the non-splicing area in the inner layer, and exposing the copper surface of the splicing area directly to the outer layer in a bare state, and completely eliminating the inner layer blind vias and optional copper plating design in the uncovered area, the laser drilling and electroplating optional plating processes that originally needed to be completed independently in the inner layer are completely merged into the outer layer.

[0073] After lamination, the hollowed-out area of ​​the outer single copper layer directly forms the external interface of the inner copper layer, while the uncovered area relies on the complete copper surface of the outer layer to perform one-time blind hole fabrication and selective plating. This achieves the simultaneous completion of the splicing of the inner and outer layer circuits and the interlayer connection of the uncovered area within the same process window of the outer layer.

[0074] It breaks through the traditional layer-by-layer barrier of processing blind holes and selective copper plating in multi-layer FPCs.

[0075] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.

Claims

1. A method for splicing inner and outer layer circuits and fabricating blind holes in the uncovered area, characterized in that: Includes the following steps: An inner layer FPC is provided, the inner layer FPC including a non-splicing area and a splicing area, the non-splicing area having inner layer circuitry formed thereon, the splicing area having exposed inner layer copper, and the inner layer copper surface not having a selectively plated copper layer formed thereon. An outer single copper layer is provided, and the position of the outer single copper layer corresponding to the splicing area is hollowed out; The outer single copper layer is laminated with the inner FPC layer, so that the exposed inner copper layer in the splicing area is directly exposed to the outer surface through the cutout. Simultaneously, through-holes and selective plating are performed in the splicing area and the uncovered area on the outer layer; wherein, no through-holes are made and no copper is selectively plated in the inner layer of the uncovered area; An outer layer circuit is fabricated on the outer single copper surface and the exposed inner copper surface, so that the outer layer circuit is electrically connected to the exposed inner copper.

2. A circuit board, manufactured based on the method of claim 1, characterized in that: include: The inner FPC includes a non-splicing area and a splicing area. The non-splicing area has inner layer circuitry, and the splicing area retains exposed inner layer copper, and the surface of the inner layer copper does not have a selectively plated copper layer. An outer single copper layer is laminated onto the surface of the inner FPC layer. The outer single copper layer has a hollow structure at the position corresponding to the splicing area. The hollow structure allows the exposed inner copper layer of the splicing area to be directly exposed to the outer surface of the multilayer FPC. The through-blind hole structure includes a first through-blind hole located in the splicing area and a second through-blind hole located in the uncovering area. Both the first through-blind hole and the second through-blind hole are formed only by synchronous fabrication and selective plating of the outer layer. The outer layer circuitry is formed on the outer single copper surface and electrically connected to the exposed inner copper layer. The uncovered area does not have blind holes or optional copper plating in the inner layer.

3. The method or circuit board according to claim 1 or 2, characterized in that: The hollowed-out shape of the outer single copper layer matches the shape of the inner copper layer in the splicing area, and the edge of the hollowed-out layer has a preset alignment overlap with the edge of the inner copper layer.

4. The method or circuit board according to claim 1 or 2, characterized in that: The uncovered area retains only the substrate in the inner layer, without forming conductive patterns, blind holes, or optional copper plating.

5. The method according to claim 1, characterized in that: Before the outer single copper layer is laminated with the inner FPC, the exposed inner copper surface of the splicing area of ​​the inner FPC is covered with a peelable protective layer. After lamination, the peelable protective layer is removed to expose the inner copper layer.

6. The circuit board according to claim 2, characterized in that: The first through-hole penetrates the outer copper layer and extends to the exposed inner copper layer surface, and the second through-hole penetrates the outer copper layer and extends to the substrate surface of the inner FPC.

7. The method or circuit board according to claim 1 or 2, characterized in that: The exposed inner copper layer and the outer circuit are electrically connected through a copper layer formed by synchronous selective plating on the outer layer. The copper layer formed by synchronous selective plating simultaneously covers the hole walls of the first through-hole and the second through-hole.

8. The method according to claim 1, characterized in that: When the blind holes are fabricated synchronously on the outer layer, the first blind hole and the second blind hole are processed in one go using the same laser drilling parameters and electroplating parameters.

9. The circuit board according to claim 2, characterized in that: The outer single copper layer completely covers the uncovered area, the second through-hole extends from the surface of the outer single copper layer to the substrate of the inner FPC, and there is no additional conductive layer on the inner surface below the uncovered area.

10. The method or circuit board according to claim 1 or 2, characterized in that: The exposed inner copper layer of the splicing area overlaps with the outer circuitry to form an integrated copper connection layer through synchronous selective plating of the outer layer. The integrated copper connection layer covers the interface of the overlap and the wall of the first through-hole.

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