Semiconductor structure and method of manufacturing the same, electronic device

Abstract

Embodiments of the present disclosure provide a semiconductor structure and a preparation method thereof, and an electronic device; wherein the semiconductor structure comprises: a substrate; the substrate comprises a first wire group, a contact wire and a second wire group which are arranged at intervals along a first direction; the first wire group and the second wire group are misaligned on the projection of the contact wire; a first transistor and a second transistor which extend along the first direction; the first transistor is connected with the contact wire and the first wire group in sequence, and the second transistor is connected with the contact wire and the second wire group in sequence; the first transistor and the second transistor have no overlapping part on the projection of the contact wire.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and includes, but is not limited to, a semiconductor structure and its fabrication method, and electronic devices. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of the devices.

[0003] Since the advent of Moore's Law, the industry has proposed various chip design and process optimizations in order to reduce chip costs as much as possible while making as many device units as possible on a limited substrate, thereby meeting the demand for chips. Summary of the Invention

[0004] In view of the above, this disclosure provides a semiconductor structure, a method for fabricating the same, and an electronic device.

[0005] In a first aspect, embodiments of this disclosure provide a semiconductor structure, the semiconductor structure comprising: a substrate; the substrate comprising a first wire group, a contact wire group, and a second wire group arranged at intervals along a first direction; the projections of the first wire group and the second wire group onto the contact wire group being misaligned; a first transistor and a second transistor extending along the first direction; the first transistor being sequentially connected to the contact wire group and the first wire group, and the second transistor being sequentially connected to the contact wire group and the second wire group; the projections of the first transistor and the second transistor onto the contact wire group having no overlapping portion; the first direction being perpendicular to the plane containing the substrate.

[0006] In some embodiments, the first conductor group includes a first conductor and a second conductor spaced apart along the first direction; the first conductor and the second conductor extend along a second direction and a third direction, respectively; the second conductor group includes a third conductor and a fourth conductor spaced apart along the first direction; the third conductor and the fourth conductor extend along the second direction and the third direction, respectively; the contact conductor extends along a fourth direction; in the first direction, the projection of the first end of the contact conductor is located at the intersection of the projections of the first conductor and the second conductor, and the intersection of the projections of the third conductor and the fourth conductor is located at the second end of the contact conductor; wherein the second direction and the third direction are perpendicular to and parallel to the plane where the substrate is located; the fourth direction is parallel to the plane where the substrate is located, and the angle between the fourth direction and the second direction is an acute angle.

[0007] In some embodiments, the semiconductor structure further includes: a first isolation structure; the first wire and the second wire located in the first isolation structure; a second isolation structure located at least on the surface of the first isolation structure; the contact wire located in the second isolation structure; a third isolation structure located at least on the surface of the second isolation structure; and the third wire and the fourth wire located in the third isolation structure.

[0008] In some embodiments, the first transistor includes at least a first channel structure and a first gate structure located on the inner surface of the first channel structure; the first gate structure includes a first gate oxide layer and a first gate metal layer, and the top surface of the first channel structure and the first gate oxide layer is lower than the bottom surface of the contact wire; the second transistor includes at least a second channel structure and a second gate structure located on the inner surface of the second channel structure; the second gate structure includes a second gate oxide layer and a second gate metal layer, and the top surface of the second channel structure and the second gate oxide layer is lower than the bottom surface of the fourth wire.

[0009] In some embodiments, the first gate metal layer includes a first sub-gate metal layer and a second sub-gate metal layer; the top surface of the first sub-gate metal layer extends beyond the bottom surface of the contact wire, and the second sub-gate metal layer is located in the gap between the first sub-gate metal layer and the contact wire; the second gate metal layer includes a third sub-gate metal layer and a fourth sub-gate metal layer; the top surface of the third sub-gate metal layer extends beyond the bottom surface of the fourth wire, and the fourth sub-gate metal layer is located in the gap between the third sub-gate metal layer and the fourth wire.

[0010] In some embodiments, the semiconductor structure further includes: a first insulating structure located above the first channel structure and the top surface of the first gate oxide layer; the top surface of the first insulating structure does not exceed the bottom surface of the contact wire; a second insulating structure located above the second channel structure and the top surface of the second gate oxide layer; the top surface of the second insulating structure does not exceed the bottom surface of the fourth wire.

[0011] In some embodiments, the semiconductor structure further includes: a third insulating structure located above the top surface of the first transistor; the top surface of the third insulating structure being flush with the top surface of the third isolation structure; and a fourth insulating structure located above the top surface of the second transistor; the top surface of the fourth insulating structure being flush with the top surface of the third isolation structure.

[0012] In a second aspect, embodiments of this disclosure provide a method for fabricating a semiconductor structure, the method comprising: providing a substrate; the substrate including a first set of conductive wires, a contact wire, and a second set of conductive wires arranged at intervals along a first direction; the projections of the first set of conductive wires and the second set of conductive wires on the contact wires being misaligned; forming a first transistor and a second transistor extending along the first direction; the first transistor being sequentially connected to the contact wires and the first set of conductive wires, and the second transistor being sequentially connected to the contact wires and the second set of conductive wires; the projections of the first transistor and the second transistor on the contact wires having no overlapping portions; the first direction being perpendicular to the plane in which the substrate is located.

[0013] In some embodiments, the first conductor group includes a first conductor and a second conductor spaced apart along the first direction; the first conductor group is formed by the following steps: providing a first isolation structure; in the first isolation structure, the first conductor and the second conductor are formed sequentially; the first conductor and the second conductor extend along a second direction and a third direction, respectively; wherein the second direction and the third direction are perpendicular to and parallel to the plane in which the substrate is located.

[0014] In some embodiments, the contact wire is formed by the following steps: forming a second isolation structure at least on the surface of the first isolation structure; forming the contact wire extending along a fourth direction in the second isolation structure; wherein, in the first direction, the projection of a first end of the contact wire is located at the intersection of the projections of the first wire and the second wire; the fourth direction is parallel to the plane of the substrate and forms an acute angle with the second direction.

[0015] In some embodiments, the second conductor group includes a third conductor and a fourth conductor spaced apart along the first direction; the second conductor group is formed by the following steps: forming a third isolation structure at least on the surface of the second isolation structure; forming the third conductor and the fourth conductor sequentially in the third isolation structure; the third conductor and the fourth conductor extending along the second direction and the third direction, respectively; wherein, in the first direction, the intersection point of the projections of the third conductor and the fourth conductor is located at the second end of the contact conductor.

[0016] In some embodiments, forming a first transistor and a second transistor extending along the first direction includes: etching the substrate to form a first trench and a second trench extending along the first direction; the first trench exposing a first end of the contact conductor and the first wire assembly; the second trench exposing the second wire assembly and a second end of the contact conductor; forming the first transistor in the first trench; and forming the second transistor in the second trench.

[0017] In some embodiments, etching the substrate to form a first trench and a second trench extending along the first direction includes: etching the third isolation structure, and the fourth conductor and the third conductor located in the third isolation structure, until the second end of the contact conductor is exposed, forming the second trench; filling the second trench with a first sacrificial structure; etching the third isolation structure, the contact conductor, the second isolation structure, the first isolation structure, and the second conductor located in the first isolation structure, until the first conductor is exposed, forming the first trench; and removing the first sacrificial structure located in the second trench to expose the second trench.

[0018] In some embodiments, the first transistor includes at least a first channel structure and a first gate structure, the first gate structure including a first gate oxide layer and a first gate metal layer; forming the first transistor in the first trench includes: sequentially forming an initial first channel structure, an initial first gate oxide layer, and an initial first gate metal layer on the exposed surface of the first trench; the initial first gate metal layer filling the first trench; etching the initial first gate metal layer to form a first sub-gate metal layer; the top surface of the first sub-gate metal layer exceeding the bottom surface of the contact wire; etching the initial first channel structure and the initial first gate oxide layer until the top surfaces of the initial first channel structure and the initial first gate oxide layer are lower than the bottom surface of the contact wire, forming the first channel structure and the first gate oxide layer; forming a second sub-gate metal layer in the gap between the first sub-gate metal layer and the contact wire; the first sub-gate metal layer and the second sub-gate metal layer constituting the first gate metal layer.

[0019] In some embodiments, prior to forming the second sub-gate metal layer, the method further includes: forming a first insulating structure located above the first channel structure and the top surface of the first gate oxide layer; the top surface of the first insulating structure does not exceed the bottom surface of the contact wire.

[0020] In some embodiments, the second transistor includes at least a second channel structure and a second gate structure, the second gate structure including a second gate oxide layer and a second gate metal layer; forming the second transistor in the second trench includes: sequentially forming an initial second channel structure, an initial second gate oxide layer, and an initial second gate metal layer on the exposed surface of the second trench; the initial second gate metal layer filling the second trench; etching the initial second gate metal layer to form a third sub-gate metal layer; the top surface of the third sub-gate metal layer exceeding the bottom surface of the fourth conductor; etching the initial second channel structure and the initial second gate oxide layer until the top surfaces of the initial second channel structure and the initial second gate oxide layer are lower than the bottom surface of the fourth conductor to form the second channel structure and the second gate oxide layer; forming a fourth sub-gate metal layer in the gap between the third sub-gate metal layer and the fourth conductor; the third sub-gate metal layer and the fourth sub-gate metal layer constituting the second gate metal layer.

[0021] In some embodiments, before forming the fourth sub-gate metal layer, the method further includes: forming a second insulating structure located above the top surface of the second channel structure and the second gate oxide layer; the top surface of the second insulating structure does not exceed the bottom surface of the fourth conductor.

[0022] In some embodiments, after forming the first transistor and the second transistor, the method for fabricating the semiconductor structure further includes: filling the remaining first trench with a third insulating structure and filling the remaining second trench with a fourth insulating structure.

[0023] Thirdly, this disclosure provides an electronic device, including: the semiconductor structure described in the above embodiments, or a semiconductor structure prepared by the method described in the above embodiments.

[0024] This disclosure provides a semiconductor structure, its fabrication method, and an electronic device. The semiconductor structure includes: a substrate; the substrate includes a first set of conductive wires, a contact wire, and a second set of conductive wires arranged at intervals along a first direction; the projections of the first set of conductive wires and the second set of conductive wires on the contact wires are misaligned; a first transistor and a second transistor extend along the first direction; the first transistor is sequentially connected to the contact wires and the first set of conductive wires, and the second transistor is sequentially connected to the contact wires and the second set of conductive wires; the projections of the first transistor and the second transistor on the contact wires have no overlapping portion. Here, because the projections of the first set of conductive wires and the second set of conductive wires on the contact wires are misaligned, the projections of the first transistor and the second transistor on the contact wires have no overlapping portion, that is, the first transistor and the second transistor are arranged alternately in the first direction; thus, the first transistor and the second transistor can be formed after the first set of conductive wires, the contact wire, and the second set of conductive wires are formed; therefore, the high temperature generated during the formation of the conductive wires will not damage the transistors, thereby allowing the materials constituting the transistors to maintain their original stability, and thus ensuring the performance of the semiconductor structure. Attached Figure Description

[0025] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0026] Figure 1A and Figure 1B A schematic diagram of a semiconductor structure provided for related technologies;

[0027] Figure 2 This is a schematic diagram of the fabrication process of the semiconductor structure provided in the embodiments of this disclosure;

[0028] Figure 3 to Figure 27 This is a schematic diagram of the semiconductor structure fabrication process provided in the embodiments of this disclosure;

[0029] Figure 28 This is a schematic diagram of a semiconductor structure provided in an embodiment of this disclosure.

[0030] Figure 29 This is a schematic diagram of the circuit composition of the semiconductor structure provided in the embodiments of this disclosure.

[0031] Figure 30 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0032] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0033] In the following description, numerous details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0034] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0035] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0036] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0037] Currently, the channel structure in semiconductor structures (i.e., memory cells) can be made of metal oxide materials such as indium gallium zinc oxide (IGZO). This reduces channel leakage while providing good scalability. However, because metal oxide materials such as IGZO are not resistant to high-temperature processes, high-temperature processes (such as CMP) during semiconductor structure formation can cause material deformation or even crystallization in the channel structure, leading to the failure of the entire semiconductor structure.

[0038] For related technologies, please refer to Figure 1A and Figure 1B The semiconductor structure 10 employs a vertical channel structure and a dual-transistor capacitor-free design; this structure allows for further reduction in the size of the memory cell (as shown by the dashed area in Figure 1). Referring again to Figure 1, the semiconductor structure 10 includes a read transistor 11, a write transistor 12, a read bit line 13a, a read word line 13b, a memory node contact 13c, a write word line 13e, and a write bit line 13d; wherein, the read transistor 11 is connected to the read bit line 13a, the read word line 13b, and the memory node contact 13c, and the write transistor 12 is connected to the memory node contact 13c, the write word line 13e, and the write bit line 13d, and the write transistor 12 is located above the surface of the read transistor 11.

[0039] Further, referring to Figure 1, the fabrication process of semiconductor structure 10 is as follows: First, read bit line 13a and read word line 13b are formed sequentially; next, read transistor 11, memory node contact 13c, and write bit line 13d are formed sequentially; finally, write transistor 12 and write word line 13e are formed sequentially. During the fabrication of the metal wires (including 13a to 13e), high-temperature processes (e.g., CMP) generate high temperatures, causing material degradation or even crystallization of the channel structure in read transistor 11 and write transistor 12, leading to the failure of semiconductor structure 10. Furthermore, due to the small size of semiconductor structure 10, the growth time and process cost for forming each structure (e.g., channel structure and gate structure) in read transistor 11 and write transistor 12 are high, thus affecting the overall process time and cost during production.

[0040] The semiconductor structure, its fabrication method, and the electronic device in the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0041] Before introducing the embodiments of this disclosure, let's define four directions that may be used in the following embodiments to describe the three-dimensional structure. These four directions may include the X-axis, Y-axis, Z-axis, and U-axis. The X-axis is a direction perpendicular to the plane containing the substrate; the Y-axis and Z-axis are two perpendicular directions on the plane containing the substrate, wherein the Y-axis may be the direction in which the first conductor extends; the U-axis is a direction on the plane containing the substrate that forms an acute angle with the Y-axis. In this disclosure, the first direction is defined as the X-axis, the second direction as the Y-axis, the third direction as the Z-axis, and the fourth direction as the U-axis.

[0042] This disclosure provides a method for fabricating a semiconductor structure. Figure 2 This is a schematic diagram of the fabrication process of the semiconductor structure provided in the embodiments of this disclosure, such as... Figure 2 As shown, the fabrication process of the semiconductor structure includes the following steps:

[0043] Step S110, providing a substrate; the substrate includes a first set of conductors, a contact conductor, and a second set of conductors arranged at intervals along the X-axis; the projections of the first set of conductors and the second set of conductors on the contact conductor are misaligned.

[0044] In this embodiment of the disclosure, the substrate includes at least a substrate, which may be a silicon substrate, a germanium substrate, a silicon germanide substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc.

[0045] In this embodiment of the disclosure, the first conductor group, the contact conductor, and the second conductor group being arranged at intervals in the X-axis direction means that the first conductor group, the contact conductor, and the second conductor group are not in contact with each other and are located sequentially on different layers in the X-axis direction. The term "interval arrangement" appearing in the following description can be understood with reference to the above explanation.

[0046] Furthermore, the first conductor group includes a first conductor and a second conductor arranged at intervals along the X-axis; wherein the first conductor may extend along the Y-axis and the second conductor may extend along the Z-axis. Similarly, the second conductor group includes a third conductor and a fourth conductor arranged at intervals along the X-axis; wherein the third conductor may extend along the Y-axis and the fourth conductor may extend along the Z-axis; in other embodiments, the third conductor may extend along the Z-axis and the fourth conductor may extend along the Y-axis.

[0047] In this embodiment, the misalignment of the projections of the first and second wire groups on the contact wire means that the projections of the first and second wire groups on the contact wire may not overlap completely or may partially overlap. Specifically, the intersection of the projections of the second and first wires (i.e., the first wire group) is located at the first end of the contact conductor, and the intersection of the projections of the third and fourth wires (i.e., the second wire group) is located at the second end of the contact wire. Here, since the projections of the first and second wire groups are located at the first and second ends of the contact wire, respectively, the first and second wire groups are staggered in the X-axis direction, thereby causing the subsequently formed first and second transistors to be staggered in the X-axis direction. This allows the first and second transistors to be formed simultaneously in subsequent processes, reducing the overall process time and cost during production.

[0048] In this embodiment of the disclosure, the materials of the second wire, the first wire, the contact wire, the third wire, and the fourth wire can be any one of the following conductive materials: metals such as cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), tungsten (W), platinum (Pt), and palladium (Pd), or their alloys, oxides, etc.

[0049] In step S120, a first transistor and a second transistor extending along the X-axis are formed; the first transistor is connected to the contact wire and the first wire group in sequence, and the second transistor is connected to the contact wire and the second wire group in sequence; the projections of the first transistor and the second transistor on the contact wire have no overlapping portion.

[0050] In this embodiment of the disclosure, a transistor (i.e., a first transistor and a second transistor) refers to a device that includes at least three terminals: a gate, a source, and a drain. The transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and the gate can control the conductivity of the channel region, thereby enabling current to flow between the source, the channel region, and the drain based on gate control.

[0051] In this embodiment, the first transistor and the second transistor are electrically connected via contact wires, enabling them to form a 2TOC structure. Specifically, the first transistor can function as a read transistor, and the second transistor as a write transistor. The source of the second transistor is connected to the gate of the first transistor via contact wires. This allows control over the switching on and off of the second transistor, as well as the control over the gate capacitance of the first transistor to be in a high-resistance or low-resistance state, thus enabling the reading and writing of "0" and "1". Because the first transistor and the second transistor can form a 2TOC structure, the size of the semiconductor structure 100 (i.e., the memory cell) is reduced, thereby increasing the storage density.

[0052] In this embodiment, since the first and second transistors are formed after the first wire group, contact wires, and second wire group are formed, the high temperatures generated during wire formation will not damage the transistors. This allows the materials constituting the transistors to maintain their original stability, thereby ensuring the performance of the semiconductor structure. Furthermore, since the projections of the first and second transistors onto the contact wires do not overlap, the first and second transistors are arranged alternately in the X-axis direction, allowing them to be formed simultaneously.

[0053] Figure 3~ Figure 27 The following is a schematic diagram of the semiconductor structure fabrication process provided in the embodiments of this disclosure, with reference to Figures 3-4. Figure 27 The fabrication process of the semiconductor structure provided in the embodiments of this disclosure will be described in detail. In particular, to facilitate illustrating the positional relationship between the first wire, the second wire, the contact wire, the fourth wire, and the third wire, Figures 6A to 18A All are perspective views.

[0054] In this embodiment of the disclosure, step S110 is performed to provide a substrate; the substrate includes a first wire group, a contact wire, and a second wire group arranged at intervals along the X-axis direction; the projections of the first wire group and the second wire group on the contact wire are misaligned.

[0055] In some embodiments, step S110 includes steps S111 to S113.

[0056] Step S111, forming as follows Figure 7A and Figure 7B The first conductor group 120 is shown.

[0057] In this embodiment of the disclosure, please refer to Figure 3A and Figure 3B A substrate 110 is provided. The substrate 110 can be an SOI substrate, a silicon substrate, a germanium substrate, a silicon germanide substrate, a GOI substrate, etc. It can also be a substrate containing other devices, circuits, or conductive structures, and this application does not limit it in this regard.

[0058] In some embodiments, the first conductor group 120 includes, as follows: Figure 7A and Figure 7B The first conductor 121 and the second conductor 122 are arranged at intervals along the X-axis direction. The first conductor group 120 is formed by the following steps: providing a first isolation structure 123; forming the first conductor 121 and the second conductor 122 in sequence in the first isolation structure 123; the first conductor 121 and the second conductor 122 extend in the Y-axis direction and the Z-axis direction, respectively.

[0059] In implementation, the first isolation structure 123 may include a first sub-isolation structure and a second sub-isolation structure. Forming the first conductive line 121 in the first isolation structure 123 includes: forming a conductive line 121 on the surface of the substrate 110 as shown in the image. Figure 4A and Figure 4B The first sub-isolation structure 123a is shown; the first sub-isolation structure 123a is etched to form a first etched groove (not shown) extending along the Y-axis direction; the first etched groove is filled with a first wire material to form a first etched groove as shown. Figure 5A and Figure 5B The first conductor 121 extends along the Y-axis direction as shown.

[0060] It should be noted that during the process of filling the first etched groove with the first conductive material to form the first conductive line 121, some of the first conductive material is often also deposited on the surface of the first sub-isolation structure 123a. This material is then subjected to chemical mechanical polishing (CMP) to ensure the first conductive line 121 has a neat shape, ensuring that it is located only within the first etched groove, which helps reduce leakage current. CMP processing can be performed during subsequent conductor formation processes (including bit lines, word lines, and contact lines). Please refer to the above process for understanding; further details will not be provided hereafter.

[0061] Furthermore, forming the second conductor 122 in the first isolation structure 123 includes: forming, on the surfaces of the first sub-isolation structure 123a and the first conductor 121, as shown in the figure. Figure 6A and Figure 6BThe second sub-isolation structure 123b is shown; the second sub-isolation structure 123b is etched to form a second etched groove (not shown) extending along the Z-axis direction, wherein the dimension of the second etched groove in the X-axis direction is smaller than the dimension of the second sub-isolation structure 123b in the X-axis direction, so that the subsequently formed second wire 122 and the first wire 121 can be isolated by a portion of the second sub-isolation structure 123b; the second etched groove is filled with second wire material to form as shown. Figure 7A and Figure 7B The second conductor 122 extends along the Z-axis direction as shown. Step S112, forming as shown... Figure 9A and Figure 9B The contact wire 130 is shown.

[0062] In some embodiments, the contact wire 130 can be formed by the following steps: at least on the surface of the first isolation structure 123, forming a... Figure 8A and Figure 8B The second isolation structure 131 is shown; in the second isolation structure 131, a shape extending along the U-axis direction is formed as shown. Figure 9A and Figure 9B The contact wire 130 shown; wherein, in the X-axis direction, the projection of the first end A of the contact wire 130 is located at the intersection of the projections of the first wire 121 and the second wire 122.

[0063] In implementation, a structure such as the first isolation structure 123 (i.e., the second sub-isolation structure 123b) and the exposed surfaces of the second conductor 122 can be formed. Figure 8A and Figure 8B The second isolation structure 131 is shown; the second isolation structure 131 is etched to form a third etched groove (not shown) extending along the U-axis direction, wherein the dimension of the third etched groove in the X-axis direction is smaller than the dimension of the second isolation structure 131 in the X-axis direction, so that the contact wire 130 and the second wire 122 formed subsequently can be isolated by a portion of the second isolation structure 131; the contact wire material is filled in the third etched groove to form a... Figure 9A and Figure 9B The contact wire 130 is shown.

[0064] In this embodiment of the disclosure, the size of the formed semiconductor structure (i.e., the memory cell) is 4F. 2 In this case, the angle between the U-axis and the Y-axis can be 45°, thus maximizing the distance between the subsequently formed first and second transistors and reducing leakage current. Simultaneously, to prevent the contact wire 130 from extending into adjacent semiconductor structures, the dimension of the contact wire 130 along the U-axis direction does not exceed [a certain value]. Where F represents the process feature dimension; in other embodiments, the U-axis direction can also be other feasible directions. In this case, the dimension of the contact wire 130 along the U-axis direction does not exceed 2F / cosθ, where θ is the angle between the U-axis direction and the Y-axis direction which is less than 45°, and F represents the process feature dimension; for example, a direction with an angle of 30° with the Y-axis direction, in which case the dimension of the contact wire 130 along the U-axis direction does not exceed

[0065] Step S112, forming as follows Figure 14A and Figure 14B The second conductor group 140 is shown.

[0066] In some embodiments, the second conductor group 140 includes, for example, Figure 14A and Figure 14B The third conductor 141 and the fourth conductor 142 are arranged at intervals along the X-axis direction. The second conductor group 140 can be formed by the following steps: forming a third isolation structure 143 at least on the surface of the second isolation structure 131; forming the third conductor 141 and the fourth conductor 142 sequentially in the third isolation structure 143; the third conductor 141 and the fourth conductor 142 extend along the Y-axis direction and the Z-axis direction, respectively; wherein, in the X-axis direction, the intersection point of the projections of the third conductor 141 and the fourth conductor 142 is located at the second end B of the contact conductor 130.

[0067] In implementation, the third isolation structure 143 may include a third sub-isolation structure and a fourth sub-isolation structure. Forming the third conductor 141 in the third isolation structure 143 includes: forming a conductor 141 on the surface of the second isolation structure 131 as shown in the image. Figure 10A and Figure 10B The third sub-isolation structure 143a is shown; the third sub-isolation structure 143a is etched to form a fourth etched groove (not shown) extending along the Y-axis direction, wherein the dimension of the fourth etched groove in the X-axis direction is smaller than that of the third sub-isolation structure 143a, so that the subsequently formed third wire 141 and contact wire 130 can be isolated by a portion of the third sub-isolation structure 143a; the fourth etched groove is filled with third wire material to form as shown. Figure 11A and Figure 11B The third conductor 141 extends along the Y-axis direction as shown; wherein the projection of the third conductor 141 in the X-axis direction is located on the second end B of the contact conductor 130.

[0068] Furthermore, forming a fourth conductor 142 in the third isolation structure 143 includes: forming a surface on the third sub-isolation structure 143a and the third conductor 141 as shown in the figure. Figure 12A and Figure 12BThe fourth sub-isolation structure 143b is shown; the fourth sub-isolation structure 143b is etched to form a fifth etched groove (not shown) extending along the Z-axis direction, wherein the dimension of the fifth etched groove in the X-axis direction is smaller than that of the fourth sub-isolation structure 143b, so that the subsequently formed fourth wire 142 and third wire 141 can be isolated by a portion of the fourth sub-isolation structure 143b; the fifth etched groove is filled with fourth wire material to form as shown. Figure 13A and Figure 13B The fourth conductor 142 extends along the Z-axis direction as shown; wherein the projection of the fourth conductor 142 in the X-axis direction is located on the second end B of the contact conductor 130. Here, since the projections of the third conductor 141 and the fourth conductor 142 in the X-axis direction are both located on the second end B of the contact conductor 130, the intersection of the projections of the third conductor 141 and the fourth conductor 142 in the X-axis direction is located on the second end B of the contact conductor 130.

[0069] In this embodiment of the disclosure, the third isolation structure 143 may further include a fifth sub-isolation structure. After forming the fourth conductive line 142, the method for fabricating the semiconductor structure further includes: forming a structure on the surface of the fourth sub-isolation structure 143b and the fourth conductive line 142. Figure 14A and Figure 14B The fifth sub-isolation structure 143c shown prevents leakage of the fourth conductor 142.

[0070] It should be noted that, as Figure 14A and Figure 14B The structure shown can also be formed by other suitable fabrication methods, and this disclosure is not limited thereto. For example, it can be formed by depositing conductive material on the side of each sub-isolation structure away from the substrate along the X direction, performing patterned etching to form wires, and depositing insulating material on the surface of the wires away from the substrate to prepare other sub-isolation structures.

[0071] In this embodiment, the first conductor material, the second conductor material, the contact conductor material, the fourth conductor material, and the third conductor material can be any suitable conductive material, such as any one of cobalt, titanium, tantalum, nickel, tungsten, platinum, and palladium, or their nitride materials, such as titanium nitride. The materials of the first sub-isolation structure 123a, the second sub-isolation structure 123b, the second isolation structure 131, the third sub-isolation structure 143a, the fourth sub-isolation structure 143b, and the fifth sub-isolation structure 143c can be any insulating material, such as silicon oxide or silicon oxynitride.

[0072] The formation processes involved in the embodiments of this disclosure include deposition processes and growth processes. The deposition processes include, but are not limited to: Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Sputtering, Metal Organic Chemical Vapor Deposition (MOCVD), Atomic Layer Deposition (ALD), and combinations thereof. The growth processes include, but are not limited to: Vapor Phase Epitaxy (VPE), Liquid Phase Epitaxy (LPE), Molecular Beam Epitaxy (MBE), Ion Beam Epitaxy, Solid Phase Epitaxy, and combinations thereof.

[0073] The etching (removal) processes involved in the embodiments of this disclosure include, but are not limited to: dry etching, wet etching, and combinations thereof.

[0074] In this embodiment, since the contact wire 130 extends along the U-axis direction and the dimension of the contact wire 130 along the U-axis direction does not exceed 2F / cosθ, the size of the semiconductor structure is equal to or less than 4F. 2 This results in a higher storage density in the semiconductor structure. In addition, since the first wire group 120, contact wire 130 and the second wire group 140 are formed first, the high temperature generated during the fabrication of the first wire group 120, contact wire 130 and the second wire group 140 (such as the high temperature generated during CMP) will not affect the subsequent processes, thus ensuring the performance of the semiconductor structure.

[0075] In this embodiment of the present disclosure, step S120 is performed to form a first transistor and a second transistor extending along the X-axis direction; the first transistor is sequentially connected to a contact wire and a first wire group, and the second transistor is sequentially connected to a contact wire and a second wire group; the projections of the first transistor and the second transistor on the contact wire have no overlapping portion.

[0076] In some embodiments, step S120 includes steps S121 and S122.

[0077] Step S121, etch the substrate to form as shown Figure 18A and Figure 18BThe first groove 151 and the second groove 152 extend along the X-axis direction as shown; the first groove 151 exposes the first end A of the contact wire 130 and the first wire group 120; the second groove 152 exposes the second wire group 140 and part of the second end B of the contact wire 130.

[0078] Here, since the dimensions of the first groove 151 and the second groove 152 are different along the X-axis, it is necessary to form the first groove 151 and the second groove 152 separately. Next, we will take the example of forming the second groove 152 first and then the first groove 151 as an example; in other embodiments, the first groove 151 may be formed first and then the second groove 152 may be formed.

[0079] In some embodiments, step S121 specifically includes: etching the third isolation structure 143, and the fourth wire 142 and the third wire 141 located in the third isolation structure 143, until the second end of the contact wire 130 is exposed, forming a second trench 152; filling the second trench 152 with a first sacrificial structure 152a; etching the third isolation structure 143, the contact wire 130, the second isolation structure 131, the first isolation structure 123, and the second wire 122 located in the first isolation structure 123, until the first wire 121 is exposed, forming a first trench 151; and removing the first sacrificial structure 152a located in the second trench 152.

[0080] During implementation, the fifth sub-isolation structure 143c, the fourth wire 142, the fourth sub-isolation structure 143b, the third wire 141, and the third sub-isolation structure 143a are etched sequentially until the second end B of the contact wire 130 is exposed, forming a structure as shown in the figure. Figure 15A and Figure 15B The second trench 152 is shown. In this way, the second trench 152 exposes the fourth wire 142, the third wire 141 and the contact wire 130, which facilitates the subsequent connection of the second transistor with the fourth wire 142, the third wire 141 and the contact wire 130.

[0081] Furthermore, to avoid damage to the second trench 152 during the process of forming the first trench 151, sacrificial material is filled into the second trench 152 before forming the first trench 151, forming a shape as follows: Figure 16A and Figure 16B The first sacrificial structure 152a is shown. Next, the third isolation structure 143 (including the fifth sub-isolation structure 143c, the fourth sub-isolation structure 143b, and the third sub-isolation structure 143a), the contact wire 130, the second isolation structure 131, the second wire 122, and the second sub-isolation structure 123b are etched sequentially until the first wire 121 is exposed, forming a structure as shown. Figure 17A and Figure 17BThe first trench 151 is shown. In this way, the first trench 151 exposes the contact wire 130, the second wire 122 and the first wire 121, which facilitates the subsequent connection of the first transistor with the contact wire 130, the second wire 122 and the first wire 121.

[0082] Finally, the first sacrificial structure 152a located in the second trench 152 is removed to form a shape as shown in the image. Figure 18A and Figure 18B The second trench 152 is exposed as shown.

[0083] Step S122, forming the first trench 151 as shown Figure 27 The first transistor 160 shown, and the second trench 152 formed as shown Figure 27 The second transistor 170 is shown.

[0084] In this embodiment of the present disclosure, the first transistor 160 includes at least a first channel structure 161 and a first gate structure, the first gate structure including a first gate oxide layer 162 and a first gate metal layer 163; the second transistor 170 includes at least a second channel structure 171 and a second gate structure, the second gate structure including a second gate oxide layer 172 and a second gate metal layer 173.

[0085] It should be noted that the first wire 121 connected to the region of the first transistor 160 can serve as the source of the first transistor 160, and the second wire 122 connected to the region of the first transistor 160 can serve as the drain of the first transistor 160. The third wire 141 connected to the region of the second transistor 170 can serve as the source of the second transistor 170, and the contact wire 130 connected to the region of the second transistor 170 can serve as the drain of the second transistor 170.

[0086] Here, the first transistor 160 and the second transistor 170 can be formed simultaneously. For example, the materials for each structure in the first transistor 160 and the second transistor 170 can be deposited simultaneously. This reduces the growth time and process cost of the transistors, and reduces the overall process time and cost during production. The simultaneous formation of the first transistor 160 and the second transistor 170 will be used as an example for explanation. In other embodiments, the first transistor 160 and the second transistor 170 can also be formed separately. For example, the first transistor 160 can be formed first, followed by the second transistor 170.

[0087] In some embodiments, step S122 specifically includes steps S1221a to S1224a, and steps S1221b to S1224c.

[0088] In step S1221a, on the exposed surface of the first trench 151, the following are sequentially formed: Figure 20The initial first channel structure 161a, initial first gate oxide layer 162a, and initial first gate metal layer 163a are shown; the initial first gate metal layer 163a fills the first trench 151. And, in step S1221b, on the exposed surface of the second trench 152, as shown... Figure 20 The initial second channel structure 171a, the initial second gate oxide layer 172a, and the initial second gate metal layer 173a are shown; the initial second gate metal layer 173a fills the second trench 152.

[0089] During implementation, in cases such as Figure 18A and Figure 18B The exposed surfaces of the structure shown (including the exposed surfaces of the first trench 151 and the second trench 152, and the surface of the fifth sub-isolation structure 143c) are sequentially deposited with channel material, gate oxide layer material, and gate metal layer material to form a structure as shown in the figure. Figure 19 The channel material layer 161a', gate oxide material layer 162a', and first gate metal material layer 163a' are shown; next, as Figure 20 As shown, the channel material layer 161a', gate oxide material layer 162a' and first gate metal material layer 163a' located on the surface of the fifth sub-isolation structure 143c are removed to form a first channel structure 161a, an initial first gate oxide layer 162a and an initial first gate metal layer 163a located sequentially on the exposed surface of the first trench 151, and an initial second channel structure 171a, an initial second gate oxide layer 172a and an initial second gate metal layer 173a located sequentially on the exposed surface of the second trench 152.

[0090] In this embodiment, the channel material can be indium gallium zinc oxide (IGZO); in other embodiments, the channel material can also be indium tin oxide (ITO), tungsten tin oxide (TTO), zinc oxide, indium oxide, titanium oxide, tin oxide, or other metal oxide materials. Due to the inherent characteristics of metal oxide semiconductors (low electron mobility), using metal oxides as the channel material can reduce the leakage current in the subsequent formation of the first and second transistors, thereby reducing the rate of charge loss on the storage capacitor, extending the data retention time of the semiconductor structure, and reducing the power consumption of the semiconductor structure.

[0091] In this embodiment of the disclosure, the gate oxide layer material can be silicon oxide or other suitable materials; the gate metal layer material can be any material with good conductivity, such as any one of titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), tungsten (W), cobalt (Co), platinum (Pt), palladium (Pd), ruthenium (Ru), and copper (Cu).

[0092] Step S1222a: Etch the initial first gate metal layer 163a to form Figure 22 The first sub-gate metal layer 163b is shown; wherein the top surface of the first sub-gate metal layer 163b extends beyond the bottom surface of the contact wire 130. And, in step S1222b, the initial second gate metal layer 173a is etched to form... Figure 22 The third sub-gate metal layer 173b is shown; wherein the top surface of the third sub-gate metal layer 173b extends beyond the bottom surface of the fourth conductor.

[0093] It is understood that the top surface of the first sub-gate metal layer 163b refers to the surface of the first sub-gate metal layer 163b away from the substrate along the X direction, and the bottom surface of the contact wire 130 refers to the surface of the contact wire 130 close to the substrate along the X direction. Similarly, in the following text, the top surface of each structure refers to the surface away from the substrate along the X direction, and the bottom surface refers to the surface close to the substrate along the X direction.

[0094] Here, the initial first gate metal layer 163a and the second gate metal layer 173a are etched to different dimensions along the X-axis, so steps S1222a and S1222b can be executed separately. Next, we will describe an example where step S1222b is executed first, followed by step S1222a; in other embodiments, step S1222a can also be executed first, followed by step S1222b.

[0095] Please refer to the following when implementing: Figure 21 The initial second gate metal layer 173a is etched, and the remaining initial second gate metal layer 173a constitutes the third sub-gate metal layer 173b; wherein, the top surface of the third sub-gate metal layer 173b exceeds the bottom surface of the fourth conductor 142 (for example, the top surface of the initial second gate metal layer 173a is flush with the top surface of the fourth conductor 142). Here, since the top surface of the third sub-gate metal layer 173b exceeds the bottom surface of the fourth conductor 142, it is convenient to electrically connect the third sub-gate metal layer 173b and the fourth conductor 142 in subsequent processes.

[0096] Furthermore, to avoid damage to the third sub-gate metal layer 173b during the etching process of the initial first gate metal layer 163a, a sacrificial material can be filled into the groove above the surface of the third sub-gate metal layer 173b before etching the initial first gate metal layer 163a to form a second sacrificial structure (not shown). Next, please refer to... Figure 22 The initial first gate metal layer 163a is etched, and the remaining initial first gate metal layer 163a constitutes the first sub-gate metal layer 163b; wherein, the top surface of the first sub-gate metal layer 163b extends beyond the bottom surface of the contact wire 130 (for example, the top surface of the initial first gate metal layer 163a is flush with the top surface of the contact wire 130). Here, since the top surface of the first sub-gate metal layer 163b extends beyond the bottom surface of the contact wire 130, it is convenient to electrically connect the first sub-gate metal layer 163b and the contact wire 130 in subsequent processes. Finally, the second sacrificial structure is removed to form a structure as shown in the image. Figure 22 The structure shown.

[0097] Step S1223a: Etch the initial first channel structure 161a and the initial first gate oxide layer 162a until the top surface of the initial first channel structure 161a and the initial first gate oxide layer 162a is lower than the bottom surface of the contact wire 130, forming a structure as shown in the figure. Figure 23 The first channel structure 161 and the first gate oxide layer 162 are shown. In step S1223b, the initial second channel structure 171a and the initial second gate oxide layer 172a are etched until the top surfaces of the initial second channel structure 171a and the initial second gate oxide layer 172a are lower than the bottom surface of the fourth conductive line 142, forming a structure as shown. Figure 23 The second channel structure 171 and the second gate oxide layer 172 are shown.

[0098] Here, the top surface of the first channel structure 161 and the first gate oxide layer 162 being lower than the bottom surface of the contact wire 130 means that the top surface of the formed first channel structure 161 and the first gate oxide layer 162 can be located between the bottom surface of the contact wire 130 and the bottom surface of the second wire 122; in this way, the first channel structure 161 is not connected to the contact wire 130, reducing the generation of leakage current, while ensuring that the first channel structure 161 is connected to the second wire 122.

[0099] Similarly, the top surfaces of the initial second channel structure 171a and the initial second gate oxide layer 172a being lower than the bottom surface of the fourth conductor 142 means that the top surfaces of the formed second channel structure 171 and the second gate oxide layer 172 can be located between the bottom surfaces of the third conductor 141 and the fourth conductor 142. This ensures that the second channel structure 171 is not connected to the fourth conductor 142, reducing leakage current while ensuring that the second channel structure 171 is connected to the third conductor 141.

[0100] It should be noted that steps S1223a and S1223b can be executed simultaneously or separately. Furthermore, in this embodiment, the top surface and bottom surface are respectively the top surface and bottom surface along the X-axis direction.

[0101] In some embodiments, such as Figure 24 As shown, after performing step S1223a, the method for fabricating the semiconductor structure further includes: forming a first insulating structure 181 located above the surfaces of the first channel structure 161 and the first gate oxide layer 162; the top surface of the first insulating structure 181 does not exceed the bottom surface of the contact wire 130. And, after performing step S1223b, the method for fabricating the semiconductor structure further includes: forming a second insulating structure 182 located above the surfaces of the second channel structure 171a and the second gate oxide layer 172; the top surface of the second insulating structure 182 does not exceed the bottom surface of the fourth wire 142.

[0102] Here, the first insulating structure 181 and the second insulating structure 182 can be formed simultaneously; in practice, it can be done as follows: Figure 23 An insulating material is deposited on the exposed surface of the structure shown to form a first initial insulating structure (not shown); the first initial insulating structure is etched to form a structure as shown. Figure 24 The first insulating structure 181 and the second insulating structure 182 are shown. In other embodiments, the first insulating structure 181 and the second insulating structure 182 can be formed separately. For example, the first insulating structure 181 can be formed first and then the second insulating structure 182 can be formed.

[0103] It should be noted that the first insulating structure 181 is disposed around the outer side of the first sub-gate metal layer 163b, and the second insulating structure 182 is disposed around the outer side of the third sub-gate metal layer 173b. The insulating material can be silicon oxide or silicon oxynitride, etc.

[0104] In this embodiment of the present disclosure, by providing a first insulating structure 181, the connection between the first gate structure and the first channel structure 161 can be prevented, thereby improving the performance of the first transistor; similarly, by providing a second insulating structure 182, the connection between the second gate structure and the second channel structure 171 can be prevented, thereby improving the performance of the second transistor.

[0105] In step S1224a, a second sub-gate metal layer 163c is formed in the gap between the first sub-gate metal layer 163b and the contact wire 130; the first sub-gate metal layer 163b and the second sub-gate metal layer 163c are configured as follows: Figure 25 The first gate metal layer 163 is shown. And, in step S1224b, a fourth sub-gate metal layer 173c is formed in the gap between the third sub-gate metal layer 173b and the fourth wire 142; the third sub-gate metal layer 173b and the fourth sub-gate metal layer 173c constitute as shown. Figure 25 The second gate metal layer 173 is shown.

[0106] During implementation, it can be done in the following ways: Figure 24 A gate metal layer material is deposited on the exposed surface of the structure shown to form a second gate metal material layer (not shown); the second gate metal material layer at least fills the space between the first sub-gate metal layer 163b and the contact wire 130; subsequently, the second gate metal material layer is etched to form a structure as shown. Figure 25 The second sub-gate metal layer 163c and the fourth sub-gate metal layer 173c are shown.

[0107] In this embodiment, the second sub-gate metal layer 163c can extend beyond the top surface of the first sub-gate metal layer 163b. This does not alter the performance of the first transistor 160, while simultaneously reducing the complexity of the fabrication process and lowering the manufacturing cost of the semiconductor structure. Similarly, the fourth sub-gate metal layer 173c can extend beyond the top surface of the third sub-gate metal layer 173b. This does not alter the performance of the second transistor 170, while simultaneously reducing the complexity of the fabrication process and lowering the manufacturing cost of the semiconductor structure.

[0108] In addition, the top surfaces of the first gate metal layer 163 and the second gate metal layer 173 do not exceed the top surface of the fifth sub-isolation structure 143c. This facilitates the formation of an insulating structure above the exposed surfaces of the first gate metal layer 163 and the second gate metal layer 173, thereby preventing transistor leakage.

[0109] Please refer to the embodiments disclosed herein. Figure 26 and Figure 27 After forming the first transistor 160 and the second transistor 170, the method for fabricating the semiconductor structure further includes filling the remaining first trench 151 with a third insulating structure 191 and filling the remaining second trench 152 with a fourth insulating structure 192.

[0110] During implementation, it can be done in the following ways: Figure 25An insulating material is deposited on the exposed surface of the structure to form a second initial insulating structure (not shown), wherein the second initial insulating structure fills the remaining first trench 151 and the remaining second trench 152; next, the second initial insulating structure located on the surface of the fifth sub-isolation structure 143c is removed to form a structure as shown in the figure. Figure 26 and Figure 27 The third insulation structure 191 and the fourth insulation structure 192 are shown.

[0111] In this embodiment of the disclosure, since the third insulating structure 191 covers the first transistor 160 and the fourth insulating structure 192 covers the second transistor 170, leakage current in the first transistor 160 and the second transistor 170 can be prevented, thereby improving the performance of the semiconductor structure.

[0112] In this embodiment, since the first transistor 160 and the second transistor 170 can be formed simultaneously—that is, the channel structure and gate structure of the two transistors are formed simultaneously through a deposition process—the growth time of each structure in the two transistors is reduced, thereby reducing the process cost and time cost during production. It also reduces the process alignment issues between the upper and lower layers of devices (i.e., transistors).

[0113] In addition, since the wires (including the first wire 121, the second wire 122, the contact wire 130, the third wire 141, and the fourth wire 142) are formed first, the high temperature generated during the formation of the wires will not damage the transistor, thereby allowing the materials constituting the transistor to maintain their original stability and thus ensuring the performance of the semiconductor structure.

[0114] In addition, please continue to refer to Figure 28 This disclosure also provides a semiconductor structure 100, comprising: a substrate; the substrate including a first wire group 120, a contact wire 130 and a second wire group 140 arranged at intervals along the X-axis direction; in the X-axis direction, the projection of the first wire group 120 is located at a first end A of the contact wire 130, and the projection of the second wire group 140 is located at a second end B of the contact wire 130; a first transistor 160 and a second transistor 170 extending along the X-axis direction; the first transistor 160 is connected to the first end A of the contact wire 130 and the first wire group 120, and the second transistor 170 is connected to the second end B of the contact wire 130 and the second wire group 140.

[0115] Please refer to the embodiments disclosed herein. Figure 28 The first conductor group 120 includes a first conductor 121 and a second conductor 122 arranged at intervals along the X-axis; the second conductor group 140 includes a third conductor 141 and a fourth conductor 142 arranged at intervals along the X-axis.

[0116] In this embodiment, because the projections of the first wire group and the second wire group on the contact wire are misaligned, the projections of the first transistor and the second transistor on the contact wire do not overlap. In other words, the first transistor and the second transistor are arranged alternately in the first direction. Thus, the first transistor and the second transistor can be formed after the first wire group, the contact wire, and the second wire group are formed. Therefore, the high temperature generated during the wire formation process will not damage the transistor, thereby allowing the materials constituting the transistor to maintain their original stability and ensuring the performance of the semiconductor structure.

[0117] Next, the semiconductor structure 100 provided in the embodiments of this disclosure will be described in detail.

[0118] In some embodiments, please refer to Figure 26 and Figure 27 The first conductor 121 and the second conductor 122 extend along the Y-axis and Z-axis directions, respectively; the third conductor 141 and the fourth conductor 142 extend along the Y-axis and Z-axis directions, respectively; the contact conductor 130 extends along the U-axis direction; in the X-axis direction, the first end A of the contact conductor 130 (position please refer to...) Figure 18B The projection is located at the intersection of the projections of the first conductor 121 and the second conductor 122. The intersection of the projections of the third conductor 141 and the fourth conductor 142 is located at the second end B of the contact conductor 130 (please refer to the location). Figure 18B )superior.

[0119] In this embodiment of the disclosure, the size of the semiconductor structure (i.e., the memory cell) is 4F. 2 In this case, the angle between the U-axis and the Y-axis can be 45°, thus maximizing the distance between the first transistor 160 and the second transistor 170 and reducing leakage current. Simultaneously, to prevent the contact wire 130 from extending into adjacent semiconductor structures, the dimension of the contact wire 130 along the U-axis direction does not exceed [a certain value]. Where F represents the process feature dimension; in other embodiments, the U-axis direction can also be other feasible directions. In this case, the dimension of the contact wire 130 along the U-axis direction does not exceed 2F / cosθ, where θ is the angle between the U-axis direction and the Y-axis direction which is less than 45°, and F represents the process feature dimension; for example, a direction with an angle of 30° with the Y-axis direction, in which case the dimension of the contact wire 130 along the U-axis direction does not exceed This allows for smaller semiconductor structures and increases their storage density.

[0120] In some embodiments, please refer to Figure 26 and Figure 27The semiconductor structure 100 further includes: a first isolation structure 123, a second isolation structure 131, and a third isolation structure 143; wherein, the first wire 121 and the second wire 122 are located in the first isolation structure 123; the second isolation structure 131 is located on the surface of the first isolation structure 123, and the contact wire 130 is located in the second isolation structure 131; the third isolation structure 143 is located on the surface of the second isolation structure 131, and the third wire 141 and the fourth wire 142 are located in the third isolation structure 143.

[0121] In this embodiment of the disclosure, please continue to refer to Figure 26 and Figure 27 The first isolation structure 123 may include a first sub-isolation structure 123a and a second sub-isolation structure 123b stacked sequentially along the X-axis; wherein, the first wire 121 is located in the first sub-isolation structure 123a, and the second wire 122 is located in the second sub-isolation structure 123b. In this way, leakage current can be prevented between the first wire 121 and the second wire 122.

[0122] In this embodiment of the disclosure, please continue to refer to Figure 26 and Figure 27 The second isolation structure 131 includes a third sub-isolation structure 143a, a fourth sub-isolation structure 143b, and a fifth sub-isolation structure 143c stacked sequentially along the X-axis; wherein the third conductor 141 is located in the third sub-isolation structure 143a, and the fourth conductor 142 is located in the fourth sub-isolation structure 143b. This prevents leakage current from the third conductor 141 and the fourth conductor 142.

[0123] In some embodiments, please refer to Figure 26 and Figure 27 The first transistor 160 includes at least a first channel structure 161 and a first gate structure located on the inner surface of the first channel structure 161. The first gate structure includes a first gate oxide layer 162 and a first gate metal layer 163. The top surfaces of the first channel structure 161 and the first gate oxide layer 162 are lower than the bottom surface of the contact wire 130. This avoids contact between the first channel structure 161 and the contact wire 130, improving the performance of the first transistor 160.

[0124] In some embodiments, please refer to Figure 26 and Figure 27 The second transistor 170 includes at least a second channel structure 171 and a second gate structure located on the inner surface of the second channel structure 171. The second gate structure includes a second gate oxide layer 172 and a second gate metal layer 173. The top surfaces of the second channel structure 171 and the second gate oxide layer 172 are lower than the bottom surface of the fourth conductive line 142. This avoids contact between the second channel structure 171 and the fourth conductive line 142, improving the performance of the second transistor 170.

[0125] In some embodiments, please refer to Figure 26 and Figure 27 The first gate metal layer 163 includes a first sub-gate metal layer 163b and a second sub-gate metal layer 163c; wherein the top surface of the first sub-gate metal layer 163b extends beyond the bottom surface of the contact wire 130, and the second sub-gate metal layer 163c is located in the gap between the first sub-gate metal layer 163b and the contact wire 130, thereby electrically connecting the first gate structure to the contact wire 130. The second gate metal layer 173 includes a third sub-gate metal layer 173b and a fourth sub-gate metal layer 173c; wherein the top surface of the third sub-gate metal layer 173b extends beyond the bottom surface of the fourth wire 142, and the fourth sub-gate metal layer 173c is located in the gap between the third sub-gate metal layer 173b and the fourth wire 142, thereby electrically connecting the second gate structure to the fourth wire 142.

[0126] In some embodiments, please refer to Figure 26 and Figure 27 The semiconductor structure 100 further includes a first insulating structure 181 located above the top surface of the first channel structure 161 and the first gate oxide layer 162; the top surface of the first insulating structure 181 does not exceed the bottom surface of the contact wire 130. Thus, the first insulating structure 181 can isolate the first channel structure 161 and the contact wire 130.

[0127] In some embodiments, please refer to Figure 26 and Figure 27 The semiconductor structure 100 further includes a second insulating structure 182 located above the top surface of the second channel structure 171 and the second gate oxide layer 172; the top surface of the second insulating structure 182 does not exceed the bottom surface of the fourth conductive line 142. Thus, the second insulating structure 182 can isolate the second channel structure 171 and the fourth conductive line 142.

[0128] In some embodiments, please refer to Figure 26 and Figure 27 The semiconductor structure 100 further includes: a third insulating structure 191 located above the top surface of the first transistor 160; the top surface of the third insulating structure 191 is flush with the top surface of the third isolation structure 143; and a fourth insulating structure 192 located above the top surface of the second transistor 170; the top surface of the fourth insulating structure 192 is flush with the top surface of the third isolation structure 143. Here, since the third insulating structure 191 covers the first transistor 160 and the fourth insulating structure 192 covers the second transistor 170, leakage current in the first transistor 160 and the second transistor 170 can be prevented, thereby improving the performance of the semiconductor structure.

[0129] The semiconductor structure provided in this disclosure is similar to the semiconductor structure in the above embodiments in terms of preparation method. For technical features not disclosed in detail in this disclosure, please refer to the above embodiments for understanding. Here, they will not be repeated.

[0130] Figure 29 The schematic diagram of the circuit composition of the semiconductor structure provided in the embodiments of this disclosure is only used to illustrate the working principle of the semiconductor structure (i.e., memory cell) in the embodiments of this disclosure. The first transistor 160 can be used as a read transistor, and the second transistor 170 can be used as a write transistor. The gate of the first transistor 160 is connected to the drain of the second transistor 170. By changing the charge in the gate capacitance of the first transistor 160 through the second transistor 170, the resistance state between the source and drain of the first transistor 160 is affected, thereby achieving the distinction between "0" and "1". The specific principle is as follows.

[0131] During the "1" writing process, the second transistor 170 is turned on, and a positive voltage is applied to the source of the second transistor 170 (i.e., the write bit line WBL, corresponding to the third wire 141 in the above embodiment) to inject charge into the gate capacitance of the first transistor 160. After the charge injection, the gate voltage and source voltage of the second transistor 170 are removed, and the "1" state is preserved.

[0132] In the process of reading "1", a reading voltage is applied to the drain of the first transistor 160 (i.e., the read bit line RBL, corresponding to the second wire 122 in the above embodiment). Since there is a certain charge in the gate capacitor, the first transistor 160 is in a low resistance state and obtains a large current. After being amplified and identified by the peripheral circuit, the process of reading "1" is completed.

[0133] During the "0" writing process, the second transistor 170 is turned on, and a negative voltage is applied to the source of the second transistor 170 (i.e., the bit line WBL, corresponding to the third wire 141 in the above embodiment) to draw charge from the gate capacitance of the first transistor 160. After the charge is drawn, the gate voltage and source voltage of the second transistor 170 are removed, and the "0" state is preserved.

[0134] During the process of reading "0", a reading voltage is applied to the drain of the first transistor 160 (i.e., the read bit line RBL, corresponding to the second wire 122 in the above embodiment). Since there is no charge in the gate capacitor, the first transistor 160 is in a high resistance state and obtains a small current. After being amplified and identified by the peripheral circuit, the process of reading "0" is completed.

[0135] In addition, this disclosure also provides an electronic device 200, which may be a storage device, smartphone, computer, tablet computer, artificial intelligence, wearable device, or smart mobile terminal. For example, it may be a dynamic random access memory (DRAM). Please refer to [link to previous document]. Figure 30The electronic device 200 includes at least one semiconductor structure (as described in the above embodiments) arranged along the Z-axis and Y-axis directions. Figure 30 (9 are shown).

[0136] Please continue reading Figure 26 , Figure 27 and Figure 30 Each semiconductor structure 100 includes a second transistor 170 and a first transistor 160, with the first drain of the second transistor 170 and the first gate structure of the first transistor 160 electrically connected by a contact wire 130.

[0137] In this embodiment of the disclosure, the first transistor 160 in the semiconductor structure 100 can serve as a read transistor, and the second transistor 170 can serve as a write transistor. The source of the second transistor 170 is connected to the write bit line (i.e., the third wire 141), and the second gate structure of the second transistor 170 is connected to the write word line (i.e., the fourth wire 142). The drain of the first transistor 160 is connected to the read bit line (i.e., the second wire 122), and the source of the first transistor 160 is connected to the read word line (i.e., the first wire 121). By applying different voltages to the first, second, third, and fourth wires, the second transistor 170 can be turned on or off, and the gate capacitance of the first transistor 160 can be controlled to present a high-resistance state or a low-resistance state to achieve the process of reading and writing "0" and "1".

[0138] Furthermore, due to the contact wire 130 in this embodiment (please refer to...) Figure 27 The size of the gate is larger than that of the storage node contact 13c (see Figure 1), thereby increasing the gate capacitance. This allows the semiconductor structure 100 in this embodiment to store more charge and improve the data retention capability of the semiconductor structure.

[0139] In the several embodiments provided in this disclosure, it should be understood that the disclosed structures and methods can be implemented in a non-target manner. The structural embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the various components shown or discussed are coupled to each other or directly coupled.

[0140] The features disclosed in the several method or structural embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or structural embodiments.

[0141] The above are merely some embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: Base; The substrate includes a first group of conductors, a contact conductor, and a second group of conductors arranged at intervals along a first direction; The projections of the first wire group and the second wire group on the contact wire are misaligned; A first transistor and a second transistor extending along the first direction; the first transistor is sequentially connected to the contact wire and the first wire group, and the second transistor is sequentially connected to the contact wire and the second wire group; the projections of the first transistor and the second transistor on the contact wire have no overlapping portion; The first direction is perpendicular to the plane in which the base lies.

2. The semiconductor structure according to claim 1, characterized in that, The first conductor group includes a first conductor and a second conductor arranged at intervals along the first direction; the first conductor and the second conductor extend along the second direction and the third direction, respectively; The second conductor group includes a third conductor and a fourth conductor arranged at intervals along the first direction; the third conductor and the fourth conductor extend along the second direction and the third direction, respectively; The contact wire extends in the fourth direction; In the first direction, the projection of the first end of the contact wire is located at the intersection of the projections of the first wire and the second wire, and the intersection of the projections of the third wire and the fourth wire is located at the second end of the contact wire. The second direction is perpendicular to the third direction and parallel to the plane containing the base; the fourth direction is parallel to the plane containing the base and forms an acute angle with the second direction.

3. The semiconductor structure according to claim 2, characterized in that, The semiconductor structure also includes: A first isolation structure; the first wire and the second wire are located within the first isolation structure; A second isolation structure is located at least on the surface of the first isolation structure; the contact wire is located in the second isolation structure. A third isolation structure is located at least on the surface of the second isolation structure; the third wire and the fourth wire are located within the third isolation structure.

4. The semiconductor structure according to claim 3, characterized in that, The first transistor includes at least a first channel structure and a first gate structure located on the inner surface of the first channel structure; the first gate structure includes a first gate oxide layer and a first gate metal layer, and the top surface of the first channel structure and the first gate oxide layer is lower than the bottom surface of the contact wire; The second transistor includes at least a second channel structure and a second gate structure located on the inner surface of the second channel structure; the second gate structure includes a second gate oxide layer and a second gate metal layer, and the top surface of the second channel structure and the second gate oxide layer is lower than the bottom surface of the fourth conductor.

5. The semiconductor structure according to claim 4, characterized in that, The first gate metal layer includes a first sub-gate metal layer and a second sub-gate metal layer; the top surface of the first sub-gate metal layer extends beyond the bottom surface of the contact wire, and the second sub-gate metal layer is located in the gap between the first sub-gate metal layer and the contact wire; The second gate metal layer includes a third sub-gate metal layer and a fourth sub-gate metal layer; the top surface of the third sub-gate metal layer extends beyond the bottom surface of the fourth conductor, and the fourth sub-gate metal layer is located in the gap between the third sub-gate metal layer and the fourth conductor.

6. The semiconductor structure according to claim 4, characterized in that, The semiconductor structure also includes: A first insulating structure located above the first channel structure and the top surface of the first gate oxide layer; the top surface of the first insulating structure does not exceed the bottom surface of the contact wire; A second insulating structure located above the second channel structure and the top surface of the second gate oxide layer; the top surface of the second insulating structure does not exceed the bottom surface of the fourth conductor.

7. The semiconductor structure according to claim 3, characterized in that, The semiconductor structure also includes: A third insulating structure located above the top surface of the first transistor; the top surface of the third insulating structure is flush with the top surface of the third isolation structure; A fourth insulating structure located above the top surface of the second transistor; the top surface of the fourth insulating structure is flush with the top surface of the third insulating structure.

8. A method for fabricating a semiconductor structure, characterized in that, The method includes: A substrate is provided; the substrate includes a first group of conductors, a contact conductor, and a second group of conductors arranged at intervals along a first direction; the projections of the first group of conductors and the second group of conductors on the contact conductor are misaligned; A first transistor and a second transistor are formed extending along the first direction; the first transistor is sequentially connected to the contact wire and the first wire group, and the second transistor is sequentially connected to the contact wire and the second wire group; the projections of the first transistor and the second transistor on the contact wire have no overlapping portion; the first direction is perpendicular to the plane where the substrate is located.

9. The method according to claim 8, characterized in that, The first conductor group includes a first conductor and a second conductor arranged at intervals along the first direction; the first conductor group is formed by the following steps: Provide the first isolation structure; In the first isolation structure, the first wire and the second wire are formed sequentially; the first wire and the second wire extend along the second direction and the third direction, respectively. The second direction and the third direction are perpendicular to and parallel to the plane in which the base is located.

10. The method according to claim 9, characterized in that, The contact wire is formed by the following steps: A second isolation structure is formed at least on the surface of the first isolation structure; In the second isolation structure, the contact wire extending in the fourth direction is formed; In the first direction, the projection of the first end of the contact wire is located at the intersection of the projections of the first wire and the second wire; the fourth direction is parallel to the plane where the base is located and forms an acute angle with the second direction.

11. The method according to claim 10, characterized in that, The second conductor group includes a third conductor and a fourth conductor arranged at intervals along the first direction; the second conductor group is formed by the following steps: At least on the surface of the second isolation structure, a third isolation structure is formed; In the third isolation structure, the third conductor and the fourth conductor are formed sequentially; the third conductor and the fourth conductor extend along the second direction and the third direction, respectively; In the first direction, the intersection of the projections of the third conductor and the fourth conductor is located at the second end of the contact conductor.

12. The method according to claim 11, characterized in that, Forming a first transistor and a second transistor extending along the first direction includes: The substrate is etched to form a first trench and a second trench extending along the first direction; the first trench exposes the first end of the contact conductor and the first wire group; the second trench exposes the second wire group and the second end of the contact wire. The first transistor is formed in the first trench, and the second transistor is formed in the second trench.

13. The method according to claim 12, characterized in that, Etching the substrate to form a first trench and a second trench extending along the first direction includes: The third isolation structure, as well as the fourth and third wires located in the third isolation structure, are etched until the second end of the contact wire is exposed, forming the second trench; The second trench is filled with a first sacrificial structure; The third isolation structure, the contact wire, the second isolation structure, the first isolation structure, and the second wire located in the first isolation structure are etched until the first wire is exposed, forming the first trench; Remove the first sacrificial structure located in the second trench to expose the second trench.

14. The method according to claim 12, characterized in that, The first transistor includes at least a first channel structure and a first gate structure, wherein the first gate structure includes a first gate oxide layer and a first gate metal layer; Forming the first transistor in the first trench includes: On the exposed surface of the first trench, an initial first channel structure, an initial first gate oxide layer, and an initial first gate metal layer are sequentially formed; the initial first gate metal layer fills the first trench. The initial first gate metal layer is etched to form a first sub-gate metal layer; the top surface of the first sub-gate metal layer extends beyond the bottom surface of the contact wire. The initial first channel structure and the initial first gate oxide layer are etched until the top surface of the initial first channel structure and the initial first gate oxide layer is lower than the bottom surface of the contact wire, thereby forming the first channel structure and the first gate oxide layer; A second sub-gate metal layer is formed in the gap between the first sub-gate metal layer and the contact wire; the first sub-gate metal layer and the second sub-gate metal layer constitute the first gate metal layer.

15. The method according to claim 14, characterized in that, Before forming the second sub-gate metal layer, the method further includes: A first insulating structure is formed above the first channel structure and the top surface of the first gate oxide layer; the top surface of the first insulating structure does not exceed the bottom surface of the contact wire.

16. The method according to claim 12, characterized in that, The second transistor includes at least a second channel structure and a second gate structure, the second gate structure including a second gate oxide layer and a second gate metal layer; forming the second transistor in the second trench includes: On the exposed surface of the second trench, an initial second channel structure, an initial second gate oxide layer, and an initial second gate metal layer are sequentially formed; the initial second gate metal layer fills the second trench. The initial second gate metal layer is etched to form a third sub-gate metal layer; the top surface of the third sub-gate metal layer extends beyond the bottom surface of the fourth conductor. The initial second channel structure and the initial second gate oxide layer are etched until the top surface of the initial second channel structure and the initial second gate oxide layer is lower than the bottom surface of the fourth conductor, thereby forming the second channel structure and the second gate oxide layer; A fourth sub-gate metal layer is formed in the gap between the third sub-gate metal layer and the fourth wire; the third sub-gate metal layer and the fourth sub-gate metal layer constitute the second gate metal layer.

17. The method according to claim 16, characterized in that, Before forming the fourth sub-gate metal layer, the method further includes: A second insulating structure is formed above the second channel structure and the top surface of the second gate oxide layer; the top surface of the second insulating structure does not exceed the bottom surface of the fourth conductor.

18. The method according to claim 12, characterized in that, After forming the first transistor and the second transistor, the method for fabricating the semiconductor structure further includes: The remaining first trench is filled with a third insulating structure, and the remaining second trench is filled with a fourth insulating structure.

19. An electronic device, characterized in that, include: The semiconductor structure as described in any one of claims 1 to 7, or a semiconductor structure made by a method comprising the semiconductor structure as described in any one of claims 8 to 12.

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