Memory device and method of manufacturing the same

Abstract

Embodiments of the present disclosure provide a memory device and a manufacturing method thereof. The memory device includes a stack structure including a plurality of levels arranged in a first direction; the stack structure includes an array region and a first step region disposed at one side of the array region; wherein in each level, the array region includes a plurality of word lines arranged at intervals in a second direction and extending in a third direction, and the first step region includes a plurality of first connection structures and a plurality of first conductive structures, the first conductive structures being coupled to the word lines through the first connection structures; wherein the first connection structures and the word lines have the same size in the first direction, and any two of the first direction, the second direction and the third direction intersect.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, including but not limited to a memory device and a method for manufacturing the same. Background Technology

[0002] With the development of semiconductor technology, in order to further pursue the miniaturization of memory device structures, the process has shifted from planar to three-dimensional, that is, the arrangement of each memory cell and related signal lines in three-dimensional space in memory devices has become the main development direction of current memory device structure research.

[0003] For example, a 3D Dynamic Random Access Memory (3DDRAM) device may include a horizontal bit line stacking (BL Stacking) architecture and a horizontal word line stacking (WL Stacking) architecture. The horizontal word line stacking architecture includes local word lines (Local WL) extending in the horizontal direction and bit lines extending in the vertical direction. The local word lines can be coupled to a common word line (Common WL) through a connection structure, and then coupled to a step structure. The step structure includes multiple steps so that the local word lines can be electrically connected through the corresponding steps and contact structures and word line driving circuits disposed on the steps.

[0004] However, as storage density continues to increase, the layout of local word lines, connection structures, common word lines, and step structures faces challenges. Summary of the Invention

[0005] In view of the above, embodiments of the present disclosure provide a memory device and a method for manufacturing the same.

[0006] In a first aspect, embodiments of this disclosure provide a memory device, the memory device comprising: a stacked structure including multiple layers stacked along a first direction; the stacked structure including an array region and a first step region disposed on one side of the array region; wherein, in each layer, the array region includes multiple word lines spaced apart along a second direction and extending along a third direction, the first step region including multiple first connection structures and multiple first conductive structures, the first conductive structures being coupled to the word lines through the first connection structures; wherein, the first connection structures and the word lines have the same dimensions along the first direction, and any two of the first direction, the second direction, and the third direction intersect.

[0007] In some embodiments, the stacking structure further includes: a second step region, wherein the first step region and the second step region are respectively disposed on opposite sides of the array region; wherein, in each layer, the second step region includes a plurality of second connection structures and a plurality of second conductive structures, wherein the first conductive structure is coupled to a first word line among the plurality of word lines through the first connection structure, and the second conductive structure is coupled to a second word line among the plurality of word lines through the second connection structure; wherein, the first connection structure and the first word line have the same dimensions along the first direction, and the second connection structure and the second word line have the same dimensions along the first direction.

[0008] In some embodiments, the first connecting structure and the first character line coupled thereto are integrally formed structures, and the second connecting structure and the second character line coupled thereto are integrally formed structures.

[0009] In some embodiments, the projection shape of the first connecting structure on a plane perpendicular to the first direction includes an arc-shaped edge, and the projection shape of the second connecting structure on a plane perpendicular to the first direction includes an arc-shaped edge.

[0010] In some embodiments, the first step region further includes a first step structure, the first step structure being coupled to the first connection structure via the first conductive structure; the second step region further includes a second step structure, the second step structure being coupled to the second connection structure via the second conductive structure.

[0011] In some embodiments, in each level, the plurality of character lines includes a plurality of character line groups spaced apart along the second direction, each character line group including the first character line and the second character line.

[0012] In some embodiments, the plurality of character line groups include a first character line group and a second character line group arranged adjacent to each other; wherein, the distance between the first character line in the first character line group and the first character line in the second character line group is less than the distance between the second character line in the first character line group and the second character line group, and the first character line in the first character line group and the first character line in the second character line group are coupled to the same first conductive structure; or, the distance between the second character line in the first character line group and the second character line in the second character line group is less than the distance between the first character line in the first character line group and the second character line in the second character line group, and the second character line in the first character line group and the second character line in the second character line group are coupled to the same second conductive structure.

[0013] In some embodiments, the array region further includes: a bit line group disposed between the first word line and the second word line in the same word line group, each bit line group including multiple bit lines spaced apart along the third direction, each bit line extending along the first direction and passing through the multiple layers.

[0014] In some embodiments, the array region further includes: a plurality of memory cells, each memory cell being coupled to a corresponding bit line and a corresponding first word line or a second word line; wherein each memory cell includes an access transistor and a data storage element, the access transistor being coupled to a corresponding bit line and a corresponding first word line or a second word line, and the data storage element being coupled to the access transistor.

[0015] In some embodiments, the plurality of storage cells include a first storage cell and a second storage cell, the first storage cell and the second storage cell being coupled to a first word line and a second word line in the same word line group, respectively, and the first storage cell and the second storage cell sharing the same bit line.

[0016] In some embodiments, the data storage element includes a capacitor, the capacitor including a first electrode, a second electrode, and a dielectric layer disposed between the first electrode and the second electrode, the first electrode being coupled to the access transistor; the plurality of memory cells include a third memory cell and a fourth memory cell, the third memory cell and the fourth memory cell being coupled to two first word lines or two second word lines in two adjacent word line groups, and the third memory cell and the fourth memory cell sharing the second electrode.

[0017] In a second aspect, embodiments of this disclosure provide a method for manufacturing a memory device. The method includes: providing an initial stacked structure, including a semiconductor layer and a sacrificial layer alternately stacked along a first direction, the initial stacked structure including an array region and a first step region and a second step region disposed on opposite sides of the array region; etching the initial stacked structure disposed in the array region to form a first etch hole group and a second etch hole group alternately arranged along a second direction, the first etch hole group including a plurality of first etch holes spaced apart along a third direction, and the second etch hole group including a plurality of second etch holes spaced apart along the third direction; removing the sacrificial layer disposed in the array region, the first step region, and the second step region through the first etch holes and the second etch holes to form gaps; wherein any two of the first direction, the second direction, and the third direction intersect.

[0018] In some embodiments, the method further includes: sequentially forming a first dielectric layer, a second dielectric layer, and a first filling layer in the space formed by the first etched hole, the second etched hole, and the gap; wherein the first dielectric layer and the second dielectric layer are disposed in the gap, and the first dielectric layer, the second dielectric layer, and the first filling layer are disposed in the first etched hole and the second etched hole.

[0019] In some embodiments, the method further includes: removing the first filling layer in the first etched hole; removing a portion of the first dielectric layer and a portion of the semiconductor layer along the second direction through the first etched hole to form a first groove and a second groove, wherein the first etched hole is disposed between the first groove and the second groove, the first etched hole, the first groove and the second groove are connected, and the size of the removed portion of the first dielectric layer along the second direction is larger than the size of the removed portion of the semiconductor layer along the second direction; and sequentially forming a third dielectric layer and a second filling layer in the space formed by the first etched hole, the first groove and the second groove.

[0020] In some embodiments, the method further includes: removing the first filling layer in the second etched hole; removing a portion of the first dielectric layer disposed in the array region through the second etched hole along the second direction to form a third groove and a fourth groove; and removing a portion of the first dielectric layer disposed in the first step region and the second step region through the second etched hole to form a fifth groove and a sixth groove, respectively; the second etched hole is disposed between the third groove and the fourth groove, the second etched hole, the third groove and the fourth groove are connected, and a plurality of the third grooves and the fifth grooves arranged along the third direction are connected, and along the third direction... The plurality of fourth and sixth grooves are connected; conductive material is filled in the third, fourth, fifth, and sixth grooves through the second etched holes to form an initial word line structure in the third and fourth grooves, a first connection structure in the fifth groove, and a second connection structure in the sixth groove; a portion of the initial word line structure is removed to divide the remaining initial word line structure into a first word line and a second word line, both the first and second word lines extending along the third direction, the first word line being coupled to the first connection structure, and the second word line being coupled to the second connection structure.

[0021] In some embodiments, the method further includes: sequentially forming a fourth dielectric layer and a bit line in the second etched hole, and correspondingly forming a bit line group in the second etched hole group, each bit line group including multiple bit lines spaced apart along the third direction, each bit line extending along the first direction.

[0022] In some embodiments, the method further includes: removing the first dielectric layer and the semiconductor layer from the first step region and the second step region to form a seventh groove in the first step region exposing the first connection structure, and forming an eighth groove in the second step region exposing the second connection structure; filling the seventh groove and the eighth groove with conductive material to form a first conductive structure in the seventh groove and a second conductive structure in the eighth groove; wherein the first conductive structure is coupled to the first word line through the first connection structure, and the second conductive structure is coupled to the second word line through the second connection structure.

[0023] This disclosure provides a memory device and a method for manufacturing the same. In this embodiment, an array region includes word lines, and a first stepped region located on one side of the array region includes a first connection structure and a first conductive structure. The word lines are coupled to the first conductive structure via the first connection structure. The first connection structure and the word lines have the same dimensions along a first direction, which solves the interconnection problem between the word lines in the array region and the first conductive structure in the first stepped region, thereby improving the reliability of the memory device. Attached Figure Description

[0024] Figure 1 Schematic diagrams of the layout structure of memory devices provided for some examples;

[0025] Figure 2 Schematic diagram of partial side view of memory device during manufacturing process for some examples. Figure 1 ;

[0026] Figure 3 Schematic diagram of partial side view of memory device during manufacturing process for some examples. Figure 2 ;

[0027] Figure 4 Partial top view of a memory device provided for some examples;

[0028] Figure 5 A partial cross-sectional schematic diagram of a memory device provided for some examples;

[0029] Figure 6 This is a top view of a memory device provided in an embodiment of the present disclosure;

[0030] Figure 7 This is a partially enlarged top view of the memory device provided in an embodiment of the present disclosure;

[0031] Figure 8 This is a partially enlarged cross-sectional view of a memory device provided in an embodiment of the present disclosure;

[0032] Figure 9 A schematic diagram of the arrangement of memory cells in a memory device. Figure 1 ;

[0033] Figure 10 A schematic diagram of the arrangement of memory cells in a memory device. Figure 2 ;

[0034] Figure 11 A schematic flowchart illustrating a method for manufacturing a memory device according to an embodiment of this disclosure;

[0035] Figures 12 to 24 This is a schematic diagram of the structure of the memory device during the manufacturing process provided in the embodiments of this disclosure;

[0036] Figure 25 A block diagram of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0037] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0038] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0039] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0040] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0041] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0042] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0043] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0044] Here, we first define the directions that may be involved in this article. The stacking direction of the stacked structure is defined as the first direction (i.e., the Z direction). In the plane intersecting the first direction, the intersecting second direction (i.e., the X direction) and the third direction (i.e., the Y direction) are defined. In some embodiments, any two of the X, Y, and Z directions intersect. The following explanation uses the example where any two of the X, Y, and Z directions are perpendicular to each other.

[0045] refer to Figure 1 , Figure 1 Schematic diagrams of the layout structure of memory devices are provided for some examples. For example... Figure 1 As shown, the memory device 100 includes an array area 102 and a first staircase area 104 and a second staircase area 106 disposed on opposite sides of the array area 102 along the Y direction.

[0046] refer to Figure 2 , Figure 2 Schematic diagram of partial side view of memory device during manufacturing process for some examples. Figure 1 .like Figure 2 As shown, forming Figure 1 The schematic memory device 100 has an initial stacked structure 108 including a semiconductor layer 110 and a sacrificial layer 112 that are alternately stacked along the Z direction. The initial stacked structure 108 includes an array region 102 and a first step region 104 and a second step region 106 located on opposite sides of the array region 102 along the Y direction.

[0047] refer to Figure 3 , Figure 3 Schematic diagram of partial side view of memory device during manufacturing process for some examples. Figure 2 .like Figure 3As shown, for the initial stacked structure 108, the initial stacked structure 108 disposed in the array region 102 can be etched to form an etch hole 114. The etch hole 114 can be, for example, an etch hole forming a bit line or an etch hole forming a capacitor. The sacrificial layer 112 disposed in the array region 102 is removed through the etch hole 114 to form a first gap. A first silicon nitride layer 116, a first silicon oxide layer 118 and a polysilicon layer 120 are sequentially formed in the space formed by the etch hole 114 and the first gap. The sacrificial layer 112 disposed in the first step region 104 and the second step region 106 is removed to form a second gap. A second silicon oxide layer 122 and a second silicon nitride layer 124 are sequentially formed in the second gap. Therefore, in the first gap, the first silicon nitride layer 116 surrounds the first silicon oxide layer 118; in the etched hole 114, the first silicon nitride layer 116, the first silicon oxide layer 118 and the polysilicon layer 120 are sequentially included in the radially inward direction; in the first step region 104 (or, the second step region 106), the second silicon oxide layer 122 surrounds the second silicon nitride layer 124; a sidewall is formed between the array region 102 and the first step region 104 (or, the second step region 106), which will increase the process difficulty in the subsequent replacement with conductive materials.

[0048] refer to Figure 4 and Figure 5 , Figure 4 Partial top view schematic diagram of the memory device provided for some examples. Figure 5 A partial cross-sectional structural diagram of a memory device is provided for some examples. For example... Figure 4 and Figure 5 As shown, array region 102 is provided with local word lines 126 (e.g. Figure 4 (As shown in the dashed box), the first step area 104 includes a common character line 128 and a step structure 130. A connection structure is also provided between the local character line 126 and the common character line 128 to achieve interconnection between them. Among these, due to... Figure 3 The diagram illustrates the presence of sidewalls between array region 102 and the first step region 104 (or, the second step region 106). During the subsequent replacement of conductive material in array region 102 to form local word lines 126 and in the replacement of conductive material in the first step region 104 to form connection structures and common word lines 128, a "neck region" exists in the connection structure between local word lines 126 and common word lines 128. (Refer to...) Figure 5 The enlarged structural diagram shown in the dashed box shows that the dimension of the connecting structure along the Z direction is smaller than the dimension of the local word line 126 along the Z direction, which reduces the reliability of the interconnection between the local word line 126 and the step structure 130.

[0049] In the horizontal word line stacking architecture of 3D DRAM, the local word line 126 needs to be laterally connected to the stepped structure 130 to achieve interconnection with the word line driving circuitry. However, the interconnection between the local word line 126 and the stepped structure 130 is particularly difficult, leading to a decrease in the reliability of the memory device 100.

[0050] In view of this, in order to solve at least one of the above-mentioned technical problems, this disclosure provides a memory device and a method for manufacturing the same.

[0051] refer to Figure 6 and Figure 7 , Figure 6 This is a top view of the memory device provided in an embodiment of the present disclosure. Figure 7 This is a partially enlarged top view of the memory device provided in an embodiment of this disclosure. Figure 6 and Figure 7 As shown, in a first aspect, embodiments of this disclosure provide a memory device 200, which includes: a stacked structure comprising multiple layers stacked along the Z direction; the stacked structure includes an array region 202, a first step region 204 disposed on one side of the array region 202, and a second step region 206 disposed on the other side of the array region 202. That is, the first step region 204 and the second step region 206 are respectively disposed on opposite sides of the array region 202 along the Y direction. Figure 6 The schematic top view of the structure can be regarded as a structural diagram of a certain level in the stacked structure.

[0052] It should be noted that, since the memory device 200 includes multiple memory cells along the X, Y and Z directions, for the sake of simplification, the memory device 200 is divided into multiple layers stacked along the Z direction. The memory cells in each layer are arranged in the same way. Each layer includes multiple memory cells arranged along the X and Y directions. The technical features of the memory device 200 can be determined by defining the technical features of each layer and the relationship between different layers.

[0053] refer to Figure 8 , Figure 8 This is a partially enlarged cross-sectional view of a memory device provided in an embodiment of this disclosure. (In conjunction with...) Figure 6 , Figure 7 and Figure 8 As shown in this embodiment, in each layer, the array region 202 includes multiple word lines 208 spaced apart along the X direction and extending along the Y direction, and the first step region 204 includes multiple first connection structures 216 and multiple first conductive structures 220 (e.g., ...). Figure 6 (As shown in the solid box in the middle), the first conductive structure 220 is coupled to the word line 208 through the first connection structure 216; wherein, reference Figure 8 As shown, the first connecting structure 216 and the word line 208 have the same dimensions along the Z direction.

[0054] Here, in the memory device 200, memory cells are arranged in an array along the X, Y, and Z directions. Word lines 208 extend along the Y direction and are spaced apart along both the X and Z directions. The gates of the access transistors in the plurality of memory cells spaced apart along the Y direction are coupled to the same word line 208.

[0055] In this embodiment, the first connection structure 216 is disposed between the array region 202 and the first conductive structure 220. The first connection structure 216 and the word line 208 are formed in the same manufacturing process. The portion of the first connection structure 216 in contact with the word line 208 has the same Z-direction dimension as the word line 208. The portion of the first connection structure 216 in contact with the word line 208 does not have a "neck region". This can solve the interconnection problem between the word line 208 in the array region 202 and the first conductive structure 220 in the first step region 204, and improve the reliability of the memory device 200.

[0056] In some embodiments, in each level, the plurality of word lines 208 include a plurality of word line groups 210 spaced apart along the X direction (e.g., ...). Figure 6 (As shown in the dashed box in the middle), each character line group 210 includes a first character line 212 and a second character line 214 arranged at intervals along the X direction.

[0057] Here, the multiple character lines 208 can be divided into multiple character line groups 210. Each character line group 210 may include a first character line 212 and a second character line 214 arranged adjacent to each other along the X direction. In two character line groups 210 arranged adjacent to each other along the X direction, the first character line 212 is located on different sides of the second character line 214, that is, in some character line groups, the first character line is located to the left of the second character line, and in some character line groups, the first character line is located to the right of the second character line.

[0058] In some embodiments, in each layer, the second step region 206 includes a plurality of second connection structures 218 and a plurality of second conductive structures 222 (e.g., ...). Figure 6 (As shown in the solid box in the middle), the multiple word lines 208 include a first word line 212 and a second word line 214. A first conductive structure 220 is coupled to the first word line 212 of the multiple word lines 208 through a first connecting structure 216, and a second conductive structure 222 is coupled to the second word line 214 of the multiple word lines 208 through a second connecting structure 218. The first connecting structure 216 and the first word line 212 have the same dimensions along the Z direction, and the second connecting structure 218 and the second word line 214 have the same dimensions along the Z direction.

[0059] Here, the first connection structure 216 is disposed between the array region 202 and the first conductive structure 220, and the second connection structure 218 is disposed between the array region 202 and the second conductive structure 222. Among the multiple word lines 208, the first word line 212 is coupled to the first conductive structure 220 through the first connection structure 216 in the first step region 204 for signal output, and the second word line 214 is coupled to the second conductive structure 222 through the second connection structure 218 in the second step region 206 for signal output. That is, the first word line 212 outputs its signal through the first step region 204 located on one side of the array region 202 along the Y direction, and the second word line 214 outputs its signal through the second step region 206 located on the other side of the array region 202 along the Y direction.

[0060] In this embodiment, the dimension of the first connection structure 216 in contact with the first word line 212 along the Z direction is the same as the dimension of the first word line 212 along the Z direction, and the dimension of the second connection structure 218 in contact with the second word line 214 along the Z direction is the same as the dimension of the second word line 214 along the Z direction. This solves the interconnection problem between the first word line 212 in the array region 202 and the first conductive structure 220 in the first step region 204, as well as the interconnection problem between the second word line 214 in the array region 202 and the second conductive structure 222 in the second step region 206, thereby improving the reliability of the memory device 200. In other words, this embodiment can improve the reliability of the interconnection between the first word line 212 and the first conductive structure 220, and can also improve the reliability of the interconnection between the second word line 214 and the second conductive structure 222, thereby reducing the interconnection area and consequently reducing the resistance and parasitic capacitance of the interconnection structure.

[0061] In some embodiments, the first connecting structure 216 and its coupled first character line 212 are integrally formed, and the second connecting structure 218 and its coupled second character line 214 are integrally formed.

[0062] Here, the first connection structure 216 and its coupled first word line 212 are formed in the same manufacturing process, that is, the first connection structure 216 and its coupled first word line 212 are integrally formed, which can reduce the short-circuit risk in the process of forming the first word line 212 and the first connection structure 216 in stages in the memory device 200. The second connection structure 218 and its coupled second word line 214 are formed in the same manufacturing process, that is, the second connection structure 218 and its coupled second word line 214 are integrally formed, which can reduce the short-circuit risk in the process of forming the second word line 214 and the second connection structure 218 in stages in the memory device 200. In some embodiments, the first word line 212, the second word line 214, the first connection structure 216 and the second connection structure 218 may be formed in the same manufacturing process.

[0063] In some embodiments, the projection shape of the first connecting structure 216 on a plane perpendicular to the Z direction includes an arc-shaped edge, and the projection shape of the second connecting structure 218 on a plane perpendicular to the Z direction includes an arc-shaped edge.

[0064] Here, the groove forming the first connection structure 216 is formed by wet etching. Therefore, the projection shape of the first connection structure 216 on the XY plane includes curved edges, for example, a fan shape or a semicircle. Similarly, the space forming the second connection structure 218 is also formed by wet etching. Therefore, the projection shape of the second connection structure 218 on the XY plane includes curved edges, for example, a fan shape or a semicircle.

[0065] Here, the first connecting structure 216 faces the first character line 212, and the second connecting structure 218 faces the second character line 214. The first connecting structure 216 and the second connecting structure 218 are respectively located on opposite sides of the character line group 210 along the Y direction.

[0066] It should be noted that, in some embodiments, a support structure may also be provided in the first step region 204 and the second step region 206, and the morphology of the first connecting structure 216 and the second connecting structure 218 will be affected by the support structure, resulting in an irregular morphology. The projection shape of such an irregular morphology of the first connecting structure 216 and the second connecting structure 218 on the XY plane includes at least a portion of the curved edge.

[0067] In some embodiments, the first step region 204 further includes a first step structure 224, which is coupled to the first connection structure 216 via a first conductive structure 220; the second step region 206 further includes a second step structure 226, which is coupled to the second connection structure 218 via a second conductive structure 222.

[0068] Here, the first step structure 224 is coupled to two first connecting structures 216 via a first conductive structure 220, and then coupled to two first word lines 212 arranged adjacently along the X direction; the second step structure 226 is coupled to two second connecting structures 218 via a second conductive structure 222, and then coupled to two second word lines 214 arranged adjacently along the X direction. In a specific embodiment, the first conductive structure 220 and the second conductive structure 222 can be, for example, a ring-shaped conductive structure.

[0069] refer to Figure 7 As shown, in some embodiments, the plurality of character line groups 210 include a first character line group 238 and a second character line group 240 arranged adjacent to each other along the X direction. In the first character line group 238, the second character line 214 is located on the left and the first character line 212 is located on the right; in the second character line group 240, the first character line 212 is located on the left and the second character line 214 is located on the right. That is, in the first character line group 238 and the second character line group 240 arranged adjacent to each other along the X direction, the second character line 214, the first character line 212, the first character line 212, and the second character line 214 are arranged sequentially along the X direction. The distance between the first character line 212 in the first character line group 238 and the first character line 212 in the second character line group 240 is less than the distance between the second character line 214 in the first character line group 238 and the second character line 214 in the second character line group 240. The first word line 212 in the first word line group 238 and the first word line 212 in the second word line group 240 are respectively coupled to different first connection structures 216, and then coupled to the same first conductive structure 220 through different first connection structures 216.

[0070] In other embodiments, the multiple word line groups include a first word line group and a second word line group arranged adjacent to each other along the X direction. In the first word line group, the first word line is located on the left and the second word line is located on the right; in the second word line group, the second word line is located on the left and the first word line is located on the right. That is, in the first and second word line groups arranged adjacent to each other along the X direction, the first word line, the second word line, the second word line, and the first word line are arranged sequentially along the X direction. The distance between the second word line in the first word line group and the second word line in the second word line group is less than the distance between the first word line in the first word line group and the first word line in the second word line group. The second word line in the first word line group and the second word line in the second word line group are respectively coupled to different second connection structures, and then coupled to the same second conductive structure through different second connection structures.

[0071] In some embodiments, the array region 202 further includes: a bit line group 230 disposed between a first word line 212 and a second word line 214 in the same word line group 210 (e.g., Figure 6 (As shown in the dashed circle in the middle), each bit line group 230 includes multiple bit lines 228 spaced apart along the Y direction, and each bit line 228 extends along the Z direction and passes through multiple layers.

[0072] Here, in the memory device 200, bit line groups 230 are spaced apart along the X direction, and the bit line groups 230 are located between the first word line 212 and the second word line 214 of the same word line group 210. Bit lines 228 extend along the Z direction and are spaced apart along both the X and Y directions. The sources (or drains) of the access transistors in the plurality of memory cells spaced apart along the Z direction are coupled to the same bit line 228.

[0073] In some embodiments, the array region 202 further includes: a plurality of storage cells (such as...) Figure 7 (As shown in the dashed circle in the middle), each memory cell 232 is coupled to the corresponding bit line 228 and the corresponding first word line 212 or second word line 214; wherein, each memory cell 232 includes an access transistor 234 and a data storage element 236, the access transistor 234 is coupled to the corresponding bit line 228 and the corresponding first word line 212 or second word line 214, and the data storage element 236 is coupled to the access transistor 234.

[0074] Here, the access transistor 234 includes an active structure extending along the X direction, a gate electrode layer coupled to the active structure, and a gate dielectric layer disposed between the active structure and the gate electrode layer. The active structure includes a source, a drain, and a channel disposed between the source and the drain along the X direction. The gate electrode layer of the access transistor 234 is coupled to the corresponding first word line 212 or second word line 214. The source (or drain) of the access transistor 234 is coupled to the bit line 228, and the drain (or source) of the access transistor 234 is coupled to the data storage element 236. A portion of the first word line 212 or a portion of the second word line 214 can serve as the gate electrode layer of the access transistor 234.

[0075] In some embodiments, the access transistor 234 may be formed as a transistor with dual gates, wherein the gate electrode layer located above the active structure may be referred to as the upper gate, and the gate electrode layer located below the active structure may be referred to as the lower gate. In other embodiments, the access transistor 234 may also be formed as a gate-all-around (GAA) transistor.

[0076] Here, the data storage element 236 includes a capacitor, which includes a first electrode, a second electrode, and a dielectric layer disposed between the first electrode and the second electrode. The first electrode can be coupled to the drain (or source) of the access transistor, and the second electrode of the plurality of capacitors stacked along the Z direction can be coupled to a common terminal to form a common electrode.

[0077] refer to Figure 9 , Figure 9 A schematic diagram of the arrangement of memory cells in a memory device. Figure 1 .like Figure 9 As shown, in some embodiments, Figure 9 The dashed boxes in the middle illustrate the first memory cell 242 and the second memory cell 244, respectively. The first memory cell 242 and the second memory cell 244 are respectively coupled to the first word line 212 and the second word line 214 in the same word line group 210 at the same level. For example, the gate electrode layer of the access transistor in the first memory cell 242 can be coupled to the first word line 212, and the gate electrode layer of the access transistor in the second memory cell 244 can be coupled to the second word line 214.

[0078] The first memory cell 242 and the second memory cell 244 share the same bit line 228, meaning that the source (or drain) of the access transistor in the first memory cell 242 and the access transistor in the second memory cell 244 can be coupled to the same bit line 228. It is understood that the first memory cell 242 and the second memory cell 244 can be any two memory cells from a plurality of memory cells that satisfy the above coupling relationship.

[0079] refer to Figure 10 , Figure 10 A schematic diagram of the arrangement of memory cells in a memory device. Figure 2 .like Figure 10 As shown, in some embodiments, Figure 10 The dashed boxes in the middle illustrate the third memory cell 246 and the fourth memory cell 248, respectively. The third memory cell 246 and the fourth memory cell 248 are respectively coupled to two first word lines 212 in two adjacent word line groups, or they are respectively coupled to two second word lines 214 in two adjacent word line groups. For example, the gate electrode layer of the access transistor in the third memory cell 246 can be coupled to the first word line 212 in the first word line group 238, and the gate electrode layer of the access transistor in the fourth memory cell 248 can be coupled to the first word line 212 in the second word line group 240.

[0080] The third storage cell 246 and the fourth storage cell 248 share a second electrode, meaning that the data storage elements in the third storage cell 246 and the fourth storage cell 248 can share the same capacitor via. Thus, the capacitors in the third storage cell 246 and the fourth storage cell 248 can share the second electrode. It is understood that the third storage cell 246 and the fourth storage cell 248 can be any two storage cells from a plurality of storage cells that satisfy the above coupling relationship.

[0081] Here, the active structure can include any suitable semiconductor material, such as single-crystal silicon, polycrystalline silicon, amorphous silicon, metal oxide semiconductor materials, etc. The metal oxide semiconductor material can include, but is not limited to, indium gallium zinc oxide (IGZO).

[0082] Here, the first word line 212, the second word line 214, the bit line 228, the first connection structure 216, the second connection structure 218, the first conductive structure 220, the second conductive structure 222, the first step structure 224, the second step structure 226, the first electrode, and the second electrode may include any suitable conductive material, such as titanium nitride, tantalum nitride, tungsten, molybdenum, metal silicide, or any combination thereof.

[0083] In some embodiments, the first character line 212, the second character line 214, the first connecting structure 216, and the second connecting structure 218 may be made of the same material, and these components may be formed in the same manufacturing process. In some embodiments, the first conductive structure 220 and the second conductive structure 222 may be made of the same material, and these components may be formed in the same manufacturing process. In some embodiments, the first step structure 224 and the second step structure 226 may be made of the same material, and these components may be formed in the same manufacturing process.

[0084] Here, the materials of the gate dielectric layer disposed between the active structure and the gate electrode layer, and the dielectric layer disposed between the first electrode and the second electrode, can include any suitable dielectric layer material. For example, silicon oxide, silicon nitride, high-k dielectric materials, or any combination thereof. For example, high-k dielectric materials can include, but are not limited to, hafnium dioxide or zirconium oxide.

[0085] It should be noted that, Figure 6 , Figure 7 , Figure 9 and Figure 10 The illustrated memory device is not the final product structure; data storage elements still need to be formed between two adjacent word line groups along the X direction. Figure 7 The illustration of data storage element 236 is only for illustrative purposes to show that the location of data storage element 236 is between the first word line group 238 and the second word line group 240, and cannot be used to illustrate the structure of data storage element.

[0086] refer to Figure 11 , Figure 11 This is a schematic flowchart illustrating a method for manufacturing a memory device according to an embodiment of this disclosure. Figure 11As shown, in a second aspect, embodiments of this disclosure provide a method for manufacturing a memory device, the method comprising:

[0087] Step S310: Provide an initial stacked structure, including semiconductor layers and sacrificial layers alternately stacked along the Z direction. The initial stacked structure includes an array region and a first step region and a second step region disposed on opposite sides of the array region.

[0088] Step S320: Etch the initial stacked structure in the array region to form a first etched hole group and a second etched hole group arranged alternately along the X direction. The first etched hole group includes a plurality of first etched holes arranged at intervals along the Y direction, and the second etched hole group includes a plurality of second etched holes arranged at intervals along the Y direction.

[0089] Step S330: Remove the sacrificial layer in the array region, the first step region, and the second step region through the first etch hole and the second etch hole to form a gap.

[0090] refer to Figures 12 to 24 , Figures 12 to 24 This is a schematic diagram illustrating the structure of a memory device during the manufacturing process, as provided in the embodiments of this disclosure. The following will be combined with… Figure 11 as well as Figures 12 to 24 The present disclosure provides a detailed description of the manufacturing method of the memory device provided in the embodiments.

[0091] In step S310, the initial stacked structure 250 includes semiconductor layers 252 and sacrificial layers alternately stacked along the Z direction. The initial stacked structure 250 includes an array region 202 and a first step region 204 and a second step region 206 disposed on opposite sides of the array region 202 along the Y direction. For ease of explanation, Figure 12 Only a partial structural diagram of the array region 202 and the first step region 204 is shown.

[0092] Here, the semiconductor layer 252 can include any suitable semiconductor material, such as silicon. Subsequent etching of the semiconductor layer 252 can then form an active structure.

[0093] Here, the sacrificial layer may include, for example, silicon-germanium materials.

[0094] In step S320, the initial stacked structure 250 disposed in the array region 202 is etched to form a first group of etched holes 254 arranged alternately along the X direction (e.g., ...). Figure 12 (as shown by the dashed circle in the middle) and the second etched hole group 258 (as shown in the middle dashed circle) Figure 12(As shown in the dashed box in the middle), the first etched hole group 254 includes a plurality of first etched holes 256 spaced apart along the Y direction, and the second etched hole group 258 includes a plurality of second etched holes 260 spaced apart along the Y direction. The sidewalls of the first etched holes 256 and the sidewalls of the second etched holes 260 expose semiconductor layers 252 and sacrificial layers that are alternately stacked along the Z direction.

[0095] like Figure 12 As shown, in step S330, the sacrificial layer disposed in the array region 202, the first step region 204, and the second step region 206 is removed through the first etch hole 256 and the second etch hole 260 to form a gap 262 disposed between adjacent semiconductor layers 252. Since the sacrificial layer disposed in the array region 202, the first step region 204, and the second step region 206 is removed in the same manufacturing process, the gaps disposed in the array region 202, the first step region 204, and the second step region 206 are connected. That is to say, there are no sidewalls between the array region 202 and the first step region 204, and between the array region 202 and the second step region 206, which reduces the difficulty of the process.

[0096] Here, the process for removing the sacrificial layer can include, for example, a wet etching process.

[0097] like Figure 13 As shown, in some embodiments, the method further includes: sequentially forming a first dielectric layer 264, a second dielectric layer 266, and a first filling layer 268 in the space formed by the first etching hole 256, the second etching hole 260, and the gap 262; wherein the first dielectric layer 264 and the second dielectric layer 266 are disposed in the gap 262, and the first dielectric layer 264, the second dielectric layer 266, and the first filling layer 268 are disposed in the first etching hole 256 and the second etching hole 260.

[0098] Here, in the gap 262, the first dielectric layer 264 surrounds the second dielectric layer 266, meaning that the first dielectric layer 264 and the second dielectric layer 266 can fill the gap 262. In the first etched hole 256 and the second etched hole 260, the first dielectric layer 264, the second dielectric layer 266, and the first filler layer 268 are sequentially included in the radially inward direction. The material of the first dielectric layer 264 can be, for example, silicon nitride, the material of the second dielectric layer 266 can be, for example, silicon oxide, and the material of the first filler layer 268 can be, for example, polysilicon.

[0099] In some embodiments, the projection shapes of the first etched hole 256 and the second etched hole 260 on the XY plane may include, but are not limited to, circles, ellipses, squares or other shapes.

[0100] In some embodiments, the process for forming the first dielectric layer 264, the second dielectric layer 266, and the first filler layer 268 may include, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0101] like Figure 14 As shown, in some embodiments, the method further includes removing the first fill layer 268 in the first etched hole 256, i.e., opening the first etched hole 256. Here, the first etched hole 256 can be used to form a data storage element, such as a capacitor.

[0102] like Figure 15 As shown, in some embodiments, the method further includes: removing a portion of the first dielectric layer 264 and a portion of the semiconductor layer 252 along the X direction through the first etched hole 256 to form a first groove 272 and a second groove 274. The first etched hole 256 is disposed between the first groove 272 and the second groove 274. The remaining semiconductor layer 252 can form an active structure extending along the X direction. The first etched hole 256, the first groove 272, and the second groove 274 are connected. (Reference) Figure 15 The enlarged structure shown in the dashed box has a larger dimension along the X direction than the removed portion of the first dielectric layer 264.

[0103] Here, the first groove 272 and the second groove 274 are arranged along the X, Y, and Z directions, and the plurality of first grooves 272 and the plurality of second grooves 274 arranged along the Z direction are connected through the first etched hole 256. The first groove 272 is formed between adjacent second dielectric layers 266 along the Z direction, and the dimension of the first groove 272 along the X direction at the height position of the first dielectric layer 264 is larger than the dimension of the first groove 272 along the X direction at the height position of the semiconductor layer 252. The second groove 274 is formed between adjacent second dielectric layers 266 along the Z direction, and the dimension of the second groove 274 along the X direction at the height position of the first dielectric layer 264 is larger than the dimension of the second groove 274 along the X direction at the height position of the semiconductor layer 252.

[0104] like Figure 16As shown, in some embodiments, the method further includes: sequentially forming a third dielectric layer 276 and a second filler layer 278 in the space formed by the first etched hole 256, the first groove 272, and the second groove 274. The third dielectric layer 276 and the second filler layer 278 are disposed in the first etched hole 256, the first groove 272, and the second groove 274. Here, the third dielectric layer 276 and the second filler layer 278 occupy the first etched hole 256 to facilitate the subsequent formation of word lines and bit lines using the second etched hole.

[0105] Here, in the first groove 272 and the second groove 274, the third dielectric layer 276 surrounds the second filler layer 278. The material of the third dielectric layer 276 may be, for example, silicon nitride, and the material of the second filler layer 278 may be, for example, polysilicon.

[0106] Here, the process for forming the third dielectric layer 276 and the second filler layer 278 may include, but is not limited to, CVD, PVD, ALD or any combination thereof.

[0107] like Figure 17 As shown, in some embodiments, the method further includes removing the first filler layer 268 in the second etched hole 260, i.e., opening the second etched hole 260. Here, the second etched hole 260 can be used to form bit lines.

[0108] like Figure 18 As shown, in some embodiments, the method further includes: removing a portion of the first dielectric layer 264 disposed in the array region 202 along the X direction through the second etching hole 260 to form a third groove 280 and a fourth groove 282; and removing a portion of the first dielectric layer 264 disposed in the first step region 204 and the second step region 206 through the second etching hole 260 to form a fifth groove 284 and a sixth groove, respectively. Figure 18 (The second groove located in the second step area is omitted from the diagram); the second etched hole 260 is located between the third groove 280 and the fourth groove 282. The second etched hole 260, the third groove 280 and the fourth groove 282 are connected. The multiple third grooves 280 and the fifth groove 284 arranged along the Y direction are connected. The multiple fourth grooves 282 and the sixth groove arranged along the Y direction are connected.

[0109] Here, the third groove 280 and the fourth groove 282 are arranged along the X and Z directions, respectively. Multiple third grooves 280 and multiple fourth grooves 282 arranged along the Z direction are connected through the second etching hole 260. The fifth groove 284 is formed by removing a portion of the first dielectric layer 264 in the first step region 204 using a wet etching process. The projection shape of the fifth groove 284 on the XY plane includes an arc-shaped edge. The sixth groove is formed by removing a portion of the first dielectric layer 264 in the second step region 206 using a wet etching process. The projection shape of the sixth groove on the XY plane includes an arc-shaped edge. The fifth groove 284 and the sixth groove are respectively located on opposite sides of the third groove 280 and the fourth groove 282 along the Y direction.

[0110] It should be noted that supporting structures can also be formed in the first step region 204 and the second step region 206, for example... Figure 18 The columnar support structure is illustrated. During the process of removing part of the first dielectric layer 264 provided in the first step region 204 and the second step region 206, the shapes of the fifth groove 284 and the sixth groove will be affected by the columnar support structure. Therefore, the shapes of the fifth groove 284 and the sixth groove may include irregular morphologies.

[0111] like Figure 19 As shown, in some embodiments, the method further includes: filling conductive material into the third groove 280, the fourth groove 282, the fifth groove 284, and the sixth groove through the second etched hole 260 to form an initial word line structure 286 in the third groove 280 and the fourth groove 282, a first connection structure 216 in the fifth groove 284, and a second connection structure in the sixth groove. Figure 18 (The second connecting structure located in the second step area is omitted from the diagram).

[0112] Here, the initial character line structure 286, the first connecting structure 216, and the second connecting structure 218 are formed in the same manufacturing process. The orthographic projection of the initial character line structure 286 on the XY plane is a plurality of interconnected ring structures, and the two opposite sides of the initial character line structure 286 along the Y direction are respectively coupled to the first connecting structure 216 and the second connecting structure 218.

[0113] Here, the material forming the initial word line structure 286, the first connecting structure 216, and the second connecting structure 218 can be, for example, titanium nitride.

[0114] Here, the process for forming the initial word line structure 286, the first connection structure 216 and the second connection structure 218 may include, but is not limited to, CVD, PVD, ALD or any combination thereof.

[0115] like Figure 20As shown, in some embodiments, the method further includes: removing a portion of the initial word line structure 286 to divide the remaining initial word line structure 286 into a first word line 212 and a second word line 214, both the first word line 212 and the second word line 214 extending along the Y direction, the first word line 212 being coupled to the first connecting structure 216, and the second word line 214 being coupled to the second connecting structure 218. Figure 20 (The second connecting structure is omitted in the diagram) Coupling. Here, an initial word line structure 286 can correspond to a word line group. The initial word line structure 286 is divided into a first word line 212 and a second word line 214 arranged at intervals along the X direction. The first word line 212 is coupled to a first connecting structure 216 located on one side of it along the Y direction, and the second word line 214 is coupled to a second connecting structure 218 located on the other side of it along the Y direction.

[0116] like Figure 21 As shown, in some embodiments, the method further includes: sequentially forming a fourth dielectric layer 288 and a bit line 228 in the second etched hole 260, and correspondingly forming a bit line group 230 in the second etched hole group 258, each bit line group 230 including multiple bit lines 228 spaced apart along the Y direction, each bit line 228 extending along the Z direction. (See reference...) Figure 21 The enlarged structure shown in the dashed box indicates that the fourth dielectric layer 288 can be disposed between the first word line 212 and the bit line 228 to isolate the first word line 212 and the bit line 228. The fourth dielectric layer 288 can also be disposed between the second word line 214 and the bit line 228 to isolate the second word line 214 and the bit line 228.

[0117] Here, the fourth dielectric layer 288 can be, for example, silicon nitride. The bit line 228 can include a conductive material, such as a conductive metal. In one specific embodiment, the bit line 228 can sequentially include a titanium silicide layer, a titanium nitride layer, and a tungsten layer.

[0118] The above Figure 21 A top view of the structure of line 228 is shown. Figure 22 This illustrates the cross-sectional structure of character line 208. More specifically, Figure 22 A cross-sectional view of the first character line 212 and the first connecting structure 216 is shown. The dimensions of the first character line 212 along the Z direction are the same as those of the first connecting structure 216 along the Z direction. Figure 23 This illustrates the second connection structure 218 coupled to the second character line 214.

[0119] like Figure 24As shown, in some embodiments, the method further includes: removing the first dielectric layer 264 and the semiconductor layer 252 from the first step region 204 and the second step region 206 to form a seventh groove in the first step region 204 exposing the first connection structure 216, and an eighth groove in the second step region 206 exposing the second connection structure 218; filling the seventh groove and the eighth groove with conductive material to form a first conductive structure 220 in the seventh groove and a second conductive structure 222 in the eighth groove; wherein the first conductive structure 220 is coupled to the first word line 212 through the first connection structure 216, and the second conductive structure 222 is coupled to the second word line 214 through the second connection structure 218.

[0120] Here, a second dielectric layer 266 is provided between adjacent first conductive structures 220 along the Z direction, and a second dielectric layer 266 is provided between adjacent second conductive structures 222 along the Z direction. In this way, the coupling capacitance between adjacent first conductive structures 220 and adjacent second conductive structures 222 can be reduced.

[0121] It should be noted that, Figure 24 The illustrated memory device is not the final product structure; the first etched hole still needs to be opened to form the data storage element. For example, a first electrode, a dielectric layer, and a second electrode can be formed sequentially.

[0122] refer to Figure 25 , Figure 25 A block diagram of an electronic device provided in an embodiment of this disclosure. (As shown) Figure 25 As shown, this disclosure also provides an electronic device 400, which includes a memory device 200 and a processor 402 coupled to the memory device 200.

[0123] In some embodiments, processor 402 may include, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), etc. Memory device 200 may be configured to store data to be processed by processor 402 and / or data processed by processor 402.

[0124] In some embodiments, the electronic device 400 includes, but is not limited to, mobile phones, tablets, smart bracelets, wearable smart devices, virtual reality devices, augmented reality devices, in-vehicle devices, servers, and workstations.

[0125] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0126] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A memory device, characterized in that, The memory device includes: A stacked structure includes multiple layers stacked along a first direction; the stacked structure includes an array region and a first step region disposed on one side of the array region. In each level, the array region includes multiple word lines spaced apart along a second direction and extending along a third direction. The first step region includes multiple first connection structures and multiple first conductive structures. The first conductive structures are coupled to the word lines through the first connection structures. The first connection structures and the word lines have the same dimensions along the first direction, and any two of the first direction, the second direction, and the third direction intersect.

2. The memory device according to claim 1, characterized in that, The stacked structure further includes: The second step region, the first step region and the second step region are respectively located on opposite sides of the array region; In each level, the second step region includes multiple second connecting structures and multiple second conductive structures. The first conductive structure is coupled to a first word line among the multiple word lines through the first connecting structure, and the second conductive structure is coupled to a second word line among the multiple word lines through the second connecting structure. The first connecting structure and the first word line have the same dimensions along the first direction, and the second connecting structure and the second word line have the same dimensions along the first direction.

3. The memory device according to claim 2, characterized in that, The first connecting structure and the first character line coupled thereto are integrally formed, and the second connecting structure and the second character line coupled thereto are integrally formed.

4. The memory device according to claim 2, characterized in that, The projection shape of the first connecting structure on a plane perpendicular to the first direction includes an arc-shaped edge, and the projection shape of the second connecting structure on a plane perpendicular to the first direction also includes an arc-shaped edge.

5. The memory device according to claim 2, characterized in that, The first step region further includes a first step structure, which is coupled to the first connection structure through the first conductive structure; the second step region further includes a second step structure, which is coupled to the second connection structure through the second conductive structure.

6. The memory device according to claim 2, characterized in that, In each level, the plurality of character lines include a plurality of character line groups arranged at intervals along the second direction, and each character line group includes the first character line and the second character line.

7. The memory device according to claim 6, characterized in that, The plurality of character line groups include a first character line group and a second character line group arranged adjacent to each other; Wherein, the distance between the first character line in the first character line group and the first character line in the second character line group is less than the distance between the second character lines in the first character line group and the second character line group; and the first character line in the first character line group and the first character line in the second character line group are coupled to the same first conductive structure; or... The distance between the second character line in the first character line group and the second character line in the second character line group is less than the distance between the first character line in the first character line group and the first character line in the second character line group. The second character line in the first character line group and the second character line in the second character line group are coupled to the same second conductive structure.

8. The memory device according to claim 6, characterized in that, The array region also includes: A bit line group is provided between the first word line and the second word line in the same word line group. Each bit line group includes multiple bit lines spaced apart along the third direction. Each bit line extends along the first direction and passes through the multiple layers.

9. The memory device according to claim 8, characterized in that, The array region also includes: A plurality of memory cells, each memory cell being coupled to a corresponding bit line and a corresponding first word line or a second word line; wherein each memory cell includes an access transistor and a data storage element, the access transistor being coupled to a corresponding bit line and a corresponding first word line or a second word line, and the data storage element being coupled to the access transistor.

10. The memory device according to claim 9, characterized in that, The plurality of storage cells include a first storage cell and a second storage cell, wherein the first storage cell and the second storage cell are respectively coupled to the first word line and the second word line in the same word line group, and the first storage cell and the second storage cell share the same bit line.

11. The memory device according to claim 9, characterized in that, The data storage element includes a capacitor, the capacitor including a first electrode, a second electrode, and a dielectric layer disposed between the first electrode and the second electrode, the first electrode being coupled to the access transistor; The plurality of storage units include a third storage unit and a fourth storage unit. The third storage unit and the fourth storage unit are respectively coupled to two first word lines or two second word lines in two adjacent word line groups. The third storage unit and the fourth storage unit share the second electrode.

12. A method for manufacturing a memory device, characterized in that, The method includes: An initial stacked structure is provided, comprising semiconductor layers and sacrificial layers alternately stacked along a first direction, the initial stacked structure comprising an array region and a first step region and a second step region disposed on opposite sides of the array region; The initial stacked structure disposed in the array region is etched to form a first etch hole group and a second etch hole group arranged alternately along a second direction. The first etch hole group includes a plurality of first etch holes spaced apart along a third direction, and the second etch hole group includes a plurality of second etch holes spaced apart along the third direction. The sacrificial layer disposed in the array region, the first step region, and the second step region is removed through the first etch hole and the second etch hole to form a gap; wherein any two of the first direction, the second direction, and the third direction intersect.

13. The manufacturing method according to claim 12, characterized in that, The method further includes: A first dielectric layer, a second dielectric layer, and a first filling layer are sequentially formed in the space formed by the first etched hole, the second etched hole, and the gap; wherein the first dielectric layer and the second dielectric layer are disposed in the gap, and the first dielectric layer, the second dielectric layer, and the first filling layer are disposed in the first etched hole and the second etched hole.

14. The manufacturing method according to claim 13, characterized in that, The method further includes: Remove the first filling layer from the first etched hole; A portion of the first dielectric layer and a portion of the semiconductor layer are removed along the second direction through the first etch hole to form a first groove and a second groove. The first etch hole is disposed between the first groove and the second groove. The first etch hole, the first groove, and the second groove are connected. The size of the portion of the first dielectric layer removed along the second direction is larger than the size of the portion of the semiconductor layer removed along the second direction. A third dielectric layer and a second filling layer are sequentially formed in the space formed by the first etched hole, the first groove, and the second groove.

15. The manufacturing method according to claim 14, characterized in that, The method further includes: Remove the first filler layer from the second etched hole; A portion of the first dielectric layer disposed in the array region is removed through the second etching hole along the second direction to form a third groove and a fourth groove, and a portion of the first dielectric layer disposed in the first step region and the second step region is removed through the second etching hole to form a fifth groove and a sixth groove, respectively; the second etching hole is disposed between the third groove and the fourth groove, the second etching hole, the third groove and the fourth groove are connected, a plurality of third grooves and fifth grooves arranged along the third direction are connected, and a plurality of fourth grooves and sixth grooves arranged along the third direction are connected; Conductive material is filled into the third, fourth, fifth, and sixth grooves through the second etched hole to form an initial word line structure in the third and fourth grooves, a first connection structure in the fifth groove, and a second connection structure in the sixth groove. A portion of the initial character line structure is removed to divide the remaining initial character line structure into a first character line and a second character line. Both the first character line and the second character line extend along the third direction. The first character line is coupled to the first connecting structure, and the second character line is coupled to the second connecting structure.

16. The manufacturing method according to claim 15, characterized in that, The method further includes: A fourth dielectric layer and a bit line are sequentially formed in the second etched hole, and a bit line group is correspondingly formed in the second etched hole group. Each bit line group includes multiple bit lines spaced apart along the third direction, and each bit line extends along the first direction.

17. The manufacturing method according to claim 16, characterized in that, The method further includes: The first dielectric layer and the semiconductor layer in the first step region and the second step region are removed to form a seventh groove in the first step region that exposes the first connection structure, and an eighth groove in the second step region that exposes the second connection structure. Conductive material is filled in the seventh and eighth grooves to form a first conductive structure in the seventh groove and a second conductive structure in the eighth groove; wherein the first conductive structure is coupled to the first word line through the first connection structure, and the second conductive structure is coupled to the second word line through the second connection structure.

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