Semiconductor device and method of manufacturing the same

Abstract

The disclosure provides a semiconductor device and a preparation method thereof, and belongs to the technical field of semiconductor. The semiconductor device comprises a first semiconductor structure. The first semiconductor structure comprises a semiconductor body, a first storage structure and a second storage structure. The semiconductor body extends along a first direction and is arranged at intervals along a second direction. Along the first direction, the semiconductor body is located between the first storage structure and the second storage structure, and the first storage structure and the second storage structure are staggered along the second direction. The semiconductor body comprises a first semiconductor body and a second semiconductor body adjacent along the second direction. The first semiconductor body is coupled with the first storage structure, and the second semiconductor body is coupled with the second storage structure. The first direction intersects the second direction.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for fabricating a semiconductor device. Background Technology

[0002] Planar memory cells have been scaled down to smaller sizes through improvements in process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches its lower limit, planar processes and manufacturing technologies become challenging and costly. As a result, the storage density of planar memory cells is nearing its upper limit. Three-dimensional (3D) memory architectures can address the density limitations of planar memory cells. Summary of the Invention

[0003] According to one aspect of this disclosure, a semiconductor device is provided, including a first semiconductor structure. The first semiconductor structure includes a semiconductor body, a first memory structure, and a second memory structure. The semiconductor bodies extend along a first direction and are spaced apart along a second direction. Along the first direction, the semiconductor bodies are located between the first memory structure and the second memory structure, and the first memory structure and the second memory structure are staggered along the second direction. The semiconductor bodies include adjacent first semiconductor bodies and second semiconductor bodies along the second direction. The first semiconductor body is coupled to the first memory structure, and the second semiconductor body is coupled to the second memory structure. The first direction intersects the second direction.

[0004] According to another aspect of this disclosure, a method for fabricating a semiconductor device is provided, comprising: providing a first semiconductor structure, wherein the first semiconductor structure includes a semiconductor body, a first memory structure, and a second memory structure; the semiconductor body extends along a first direction and is arranged along a second direction; along the first direction, the semiconductor body is located between the first memory structure and the second memory structure, and the first memory structure and the second memory structure are arranged alternately along the second direction; the semiconductor body includes a first semiconductor body and a second semiconductor body adjacent to each other along the second direction; the first semiconductor body is coupled to the first memory structure, and the second semiconductor body is coupled to the second memory structure; the first direction and the second direction intersect. Attached Figure Description

[0005] Figure 1 A schematic diagram of a semiconductor device according to some embodiments of the present disclosure is shown.

[0006] Figure 2 A schematic diagram of a semiconductor device according to some other embodiments of the present disclosure is shown.

[0007] Figure 3 It shows Figure 2 A partially enlarged schematic diagram of the memory cell of the semiconductor device shown.

[0008] Figure 4 A schematic diagram of a semiconductor device according to yet another embodiment of the present disclosure is shown.

[0009] Figure 5 A top view of a first semiconductor structure according to some embodiments of the present disclosure is shown.

[0010] Figure 6 A bottom view of a first semiconductor structure according to some embodiments of the present disclosure is shown.

[0011] Figure 7 It shows Figure 5 and Figure 6 The first semiconductor structure shown is a cross-sectional view along the BB direction.

[0012] Figure 8 It shows Figure 5 and Figure 6 The first semiconductor structure shown is a cross-sectional view along the CC direction.

[0013] Figure 9 A schematic cross-sectional view of a semiconductor device according to some embodiments of the present disclosure is shown.

[0014] Figure 10 Another schematic cross-sectional view of a semiconductor device according to some embodiments of the present disclosure is shown.

[0015] Figure 11 A flowchart illustrating a method for fabricating a semiconductor device according to some embodiments of the present disclosure is shown.

[0016] Figures 12-30 A schematic diagram of a semiconductor device at a certain stage of fabrication according to various embodiments of the present disclosure is shown.

[0017] Figure 31 A schematic diagram of a capacitor structure according to some embodiments of the present disclosure is shown.

[0018] Figure 32 A schematic diagram of a capacitor structure according to some other embodiments of the present disclosure is shown.

[0019] Figure 33 A schematic diagram of a memory system according to some embodiments of the present disclosure is shown.

[0020] Figure 34 A schematic diagram of a memory card according to an embodiment of the present disclosure is shown.

[0021] Figure 35 A schematic diagram of a solid-state drive (SSD) according to an embodiment of the present disclosure is shown. Detailed Implementation

[0022] Although specific configurations and arrangements have been discussed, it should be understood that they are for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this disclosure. It will be apparent to those skilled in the art that this disclosure can also be used in a variety of other applications.

[0023] It should be noted that the use of terms such as "an embodiment," "an embodiment," "an exemplary embodiment," and "some embodiments" in the specification indicates that the described embodiment may include a specific feature, structure, or characteristic, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, implementing that feature, structure, or characteristic in conjunction with other embodiments (whether explicitly described or not) should be within the knowledge of those skilled in the art.

[0024] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term “one or more” as used herein can be used to describe a feature, structure, or characteristic in a singular sense, or a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as “a” or “the” can be understood to convey either a singular or a plural use.

[0025] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest manner, such that “on” means not only “directly on” something but also includes something with an intervening feature or layer, and that “above” or “on top of” means not only “above” or “on top of” something but also includes something “above” or “on top of” without an intervening feature or layer (i.e., directly on something).

[0026] Furthermore, spatially related terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein for convenience to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the accompanying drawings. Spatially relative terms are intended to cover different orientations in the use or operation of the device other than those depicted in the accompanying drawings. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted similarly accordingly.

[0027] As used herein, the terms "substrate," "base plate," or "base" refer to a material on which subsequent material is added or otherwise disposed. The substrate or base plate itself may be patterned. Material disposed on the substrate or base plate (e.g., on top) may be patterned or may remain unpatterned. Furthermore, the substrate or base plate may comprise a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate or base plate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0028] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer may extend over the entirety of a structure below or above, or may have a extent smaller than that of the structure below or above. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than that of the continuous structure. Layers may extend horizontally, vertically, and / or along inclined surfaces. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, a stacked layer may include one or more conductor and contact layers (where contacts, interconnects, and / or vias are formed) and one or more dielectric layers.

[0029] As used herein, the term "nominal / nominally" refers to the expected or target value of a characteristic or parameter for the operation of a component or process, set during the design phase of production or process, and the range of values ​​higher and / or lower than the expected value. The range of values ​​may be due to slight variations in the manufacturing process or tolerances. As used herein, the term "about" indicates the value of a given quantity that can vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "about" can indicate the value of a given quantity that varies, for example, within 10%–30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0030] As used herein, the terms “horizontal / horizontally / laterally” mean nominally parallel to the lateral surface of the substrate or base plate, and the terms “vertical” or “perpendicularly” mean nominally perpendicular to the lateral surface of the substrate or base plate.

[0031] As used herein, a "semiconductor device" can specifically refer to a 3D memory device. A 3D memory device includes a memory cell array and peripheral circuitry for facilitating the operation of the memory cell array. In an exemplary embodiment, the 3D memory device can be Dynamic Random Access Memory (DRAM).

[0032] Transistors are used as switches or selection devices in memory cells of some semiconductor devices, such as DRAM. In a 1-transistor-1-capacitor (1T1C) DRAM structure, data is stored in the capacitor structure. While single-crystal silicon can be used as the channel material for transistors, this disclosure is not limited to this; alternative channel materials with lower leakage, such as metal-oxide-semiconductor materials (e.g., IGZO (Indium Gallium Zinc Oxide)), can also be employed. Furthermore, as DRAM continues to scale up, the unit size of each capacitor structure is decreasing, and the etch aspect ratio of the capacitor structure is increasing, posing significant challenges to the manufacturing process and increasing product costs.

[0033] The semiconductor body of the transistor in this embodiment extends along a vertical direction (i.e., the first direction, the Y direction), therefore the transistor can also be called a vertical transistor or a vertical channel transistor (VCT). VCT breaks the limitation of traditional horizontal transistor arrangement by arranging the conductive channels vertically. By arranging the transistors vertically, VCT DRAM can reduce the cell area, thereby achieving higher storage capacity per unit chip area. Furthermore, the vertical channel structure helps reduce leakage current and interference, improving the stability and reliability of the DRAM.

[0034] In some embodiments, the capacitor structure can be formed before the transistors in the 1T1C DRAM structure. Since the capacitor structure fabrication process requires high temperatures, and the semiconductor substrate used in the vertical transistor, such as IGZO, is temperature-sensitive and degrades at certain temperatures, in some embodiments, by fabricating the capacitor structure first and then the vertical transistor, the high temperatures during the capacitor structure fabrication process can prevent material degradation of the semiconductor substrate in the vertical transistor. However, this disclosure is not limited to this. In other embodiments, the temperature can be reduced by improving the capacitor structure fabrication process, thus allowing the vertical transistor to be fabricated first, followed by the capacitor structure. Alternatively, by improving the material properties of the semiconductor substrate, such as IGZO, to reduce its susceptibility to temperature, the vertical transistor can also be fabricated first, followed by the capacitor structure. By using novel designs and corresponding novel fabrication methods for transistors and capacitor structures in DRAM, the disclosed semiconductor device can have high storage density while further reducing cell size. By applying the disclosed manufacturing process, the manufacturing difficulty of the disclosed semiconductor device is reduced. Compared with related methods, the disclosed manufacturing process can have a simplified procedure, thereby reducing product costs.

[0035] According to some embodiments of this disclosure, each vertical transistor includes a semiconductor body extending in a vertical direction and a gate structure adjacent to the semiconductor body. In some implementations, word lines and bit lines connected to the vertical transistors are arranged along a second direction (X direction, also referred to as the word line direction or WL (Word Line) direction) and a third direction (Z direction, also referred to as the bit line direction or BL (Bit Line) direction), respectively. Each semiconductor body of the corresponding vertical transistor extends in a vertical direction. By using such a design, the efficiency of the memory region can be improved. Furthermore, the memory cell array and peripheral circuitry can be formed on different wafers, so that the fabrication processes of the memory cell array and the peripheral circuitry do not interfere with each other, thereby further improving the efficiency of the memory region.

[0036] This disclosure provides a novel VCT structure that can be applied to DRAM memory. DRAM is a semiconductor memory used for random access storage in computer systems. It includes a number of memory cells, each capable of storing one or more bits of data. DRAM can be capacitor-based, with each memory cell containing a capacitor and a transistor (e.g., a vertical transistor). The capacitor stores charge, representing one bit of binary data. To read data, the DRAM controller accesses specific row and column addresses, activates the corresponding transistor, and then detects the amount of charge on the capacitor to determine whether the stored data is 0 or 1.

[0037] Figure 1 A schematic diagram of a semiconductor device 100 according to some aspects of this disclosure is shown. For example... Figure 1 As shown, the semiconductor device 100 may include a second semiconductor structure 104, a first semiconductor structure 102, and a third semiconductor structure 103 stacked sequentially along a first direction (Y direction).

[0038] For example, components of a semiconductor device (e.g., a memory cell array, a first peripheral circuit, and a second peripheral circuit) can be formed on different wafers and then connected to form a bonded chip. According to some embodiments, a first semiconductor structure 102 and a second semiconductor structure 104 are bonded at a first bonding interface 106 between them. The first semiconductor structure 102 and a third semiconductor structure 103 are bonded at a second bonding interface 108 between them. The second semiconductor structure 104 may include a second substrate ( Figure 1 (Not shown in the image). The third semiconductor structure 103 may include a third substrate (…). Figure 1(Not shown in the image). The second and third substrates may include silicon (e.g., single-crystal silicon, c-Si), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. The second semiconductor structure 104 may include a first peripheral circuit on the second substrate. The third semiconductor structure 103 may include a second peripheral circuit on the third substrate. In some implementations, the first and second peripheral circuits include multiple transistors (e.g., planar transistors and / or semiconductor transistors). Trench isolation (e.g., shallow trench isolation (STI)) and doped regions (e.g., the well, source, and drain of a transistor) may also be formed on or in the second substrate, or on or in the third substrate.

[0039] like Figure 2 As shown, the first semiconductor structure 102 includes a memory cell array 1021. The second semiconductor structure 104 includes a first peripheral circuit 1041 coupled to the memory cell array 1021. The third semiconductor structure 103 includes a second peripheral circuit 1031 coupled to the memory cell array 1021. Exemplarily, the first peripheral circuit 1041 and the second peripheral circuit 1031 may be located on opposite sides of the memory cell array 1021 along a first direction (Y direction).

[0040] like Figure 2 As shown, the memory cell array 1021 may include memory cells 208. The memory cells 208 may be arranged in a two-dimensional (2D) array having rows and columns. The first peripheral circuitry 1041 and the second peripheral circuitry 1031 may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of the memory cell array 1021. For example, the first peripheral circuitry 1041 and the second peripheral circuitry 1031 may include page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion (e.g., sub-circuits) of the aforementioned functional circuitry, or one or more of any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitor structures). According to some embodiments, the first peripheral circuitry 1041 and the second peripheral circuitry 1031 utilize complementary metal-oxide-semiconductor (CMOS) technology.

[0041] like Figure 2 and Figure 3As shown, the semiconductor device 100 may include word lines 204 coupling the first peripheral circuitry 1041 and the second peripheral circuitry 1031 to the memory cell array 1021 for controlling the on and off states of vertical transistors 210 in memory cells 208 located in rows; and bit lines 206 coupling the first peripheral circuitry 1041 and the second peripheral circuitry 1031 to the memory cell array 1021 for sending data to and / or receiving data from memory cells 208 located in columns. That is, each word line 204 is coupled to a corresponding row of memory cells 208, and each bit line 206 is coupled to a corresponding column of memory cells 208. The first peripheral circuitry 1041 and the second peripheral circuitry 1031 may be coupled to the memory cell array 102 via bit lines 206, word lines 204, and any other suitable metal wiring. As described above, the first peripheral circuit 1041 and the second peripheral circuit 1031 may include any suitable circuitry for facilitating the operation of the memory cell array 102 by applying and sensing voltage and / or current signals to each memory cell 208 via word line 204 and bit line 206. The first peripheral circuit 1041 and the second peripheral circuit 1031 may include various types of peripheral circuitry formed using CMOS technology.

[0042] The vertical transistor 210 in this embodiment, such as a vertical metal-oxide-semiconductor field-effect transistor (MOSFET), can replace the conventional planar transistor as the transfer transistor of the memory cell 208, thereby reducing the area occupied by the transfer transistor and reducing the complexity of the coupling capacitor structure and interconnect wiring.

[0043] refer to Figure 3 As shown, the memory cell array 1021 can be any suitable memory cell array. Each memory cell 208 includes a vertical transistor 210 and a memory cell 10 coupled to the vertical transistor 210. In some implementations, the memory cell array 1021 is a DRAM cell array. A DRAM cell array includes DRAM cells arranged in an array. The memory cell 10 is a capacitor structure for storing charge as binary information stored by the individual DRAM cells.

[0044] like Figure 3 As shown, unlike planar transistors where the active region is formed in the substrate, the vertical transistor 210 includes the active region in the substrate ( Figure 3 A semiconductor body 124 extends vertically (along the Y direction) above (not shown). That is, the semiconductor body 124 can extend above the top surface of the substrate, exposing not only the top surface of the semiconductor body 124 but also one or more of its side surfaces. For example, as... Figure 3As shown, the semiconductor body 124 can have a cuboid shape exposing four sides. It should be understood that the semiconductor body 124 can take any suitable shape, such as a polyhedral or cylindrical shape. That is, the cross-section of the semiconductor body 124 in a planar view (e.g., in the XZ plane) can have a square, rectangular (or trapezoidal), circular (or elliptical) shape, or any other suitable shape. It should be understood that a semiconductor body 124 having a circular or elliptical cross-section in a planar view can still be considered to have multiple sides, thereby allowing the gate structure to couple with multiple sides of the semiconductor body 124.

[0045] like Figure 3 As shown, the vertical transistor 210 may further include a gate structure 216 coupled to one or more sides of the semiconductor body 124, i.e., in one or more planes on the side surface of the active region. In other words, the active region of the vertical transistor 210, i.e., the semiconductor body 124, may be at least partially surrounded by the gate structure 216. Exemplarily, the gate structure 216 includes a gate dielectric layer 126 and a gate electrode 114. The gate dielectric layer 126 is located between the semiconductor body 124 and the gate electrode 114. The gate dielectric layer 126 may be coupled to one or more side surfaces of the semiconductor body 124. For example, as... Figure 3 As shown, the gate dielectric layer 126 is coupled to the four side surfaces of the semiconductor body 124. In some embodiments, the gate electrode 114 is coupled to the gate dielectric layer 126. The gate dielectric layer 126 may comprise any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. The gate electrode 114 may comprise any suitable conductive and / or semiconductor material, such as one or more of polysilicon, metals (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), metal compounds (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or silicides.

[0046] When the voltage applied to the gate electrode 114 of the gate structure 216 exceeds the threshold voltage of the vertical transistor 210, one or more channels (not shown) in the vertical transistor 210 can be vertically formed in the semiconductor body 124. In some embodiments, such as Figure 3 As shown, the vertical transistor 210 is a multi-gate transistor. This means that the gate structure 216 can be connected to more than one side of the semiconductor body 124 (e.g., Figure 3 The four sides of the semiconductor body 124 are coupled to form more than one gate electrode 114, thereby allowing multiple channels to be formed between the source and drain of the semiconductor body 124 during operation. Unlike planar transistors that include only a single planar gate (resulting in a single planar channel), the semiconductor body 124 and the gate structure 216 surrounding the multiple sides of the semiconductor body 124... Figure 3The vertical transistor 210 shown may include multiple vertical gate electrodes 114 on multiple sides of the semiconductor body 124. Compared to planar transistors, Figure 3 The vertical transistor 210 shown can have a larger gate control area, thereby enabling better channel control with a smaller subthreshold swing. During the off-state, the leakage current of the vertical transistor 210 can also be significantly reduced because the channel is fully depleted. Multi-gate vertical transistors can include dual-gate vertical transistors (e.g., dual-side-gate vertical transistors, with gate structure 216 surrounding two sides of semiconductor body 124), tri-gate vertical transistors (e.g., gate structure 216 surrounding three sides of semiconductor body 124), and GAA (Gate-All-Around) vertical transistors (e.g., gate structure 216 surrounding four sides of semiconductor body 124).

[0047] Although Figure 3 The vertical transistor 210 is shown as a multi-gate vertical transistor, but it should be understood that the vertical transistor in embodiments of this disclosure may also include a single-gate vertical transistor. That is, the gate structure 216 may be coupled to one side of the semiconductor body 124 to increase transistor and memory cell density.

[0048] like Figure 3 As shown, memory cell 10 can be coupled to the source or drain of vertical transistor 210. Memory cell 10 can include any device capable of storing binary data (e.g., 0 and 1), including but not limited to capacitor structures for DRAM cells and FRAM (Ferroelectric Random Access Memory) cells, and PCM elements for PCM (Phase Change Memory) cells.

[0049] In some embodiments, the second semiconductor structure 104 further includes a third interconnect layer (not shown) located above the first peripheral circuit 1041 for transmitting electrical signals with the first peripheral circuit 1041. The third interconnect layer may include multiple third interconnects (also referred to as “contacts”), including lateral interconnects and vertical interconnect access (VIA) contacts. As used herein, the term “interconnect” can broadly include any suitable type of interconnect, such as middle-end (MEOL) interconnects and back-end (BEOL) interconnects. The third interconnect layer may also include one or more inter-layer dielectric (ILD) layers (also referred to as “inter-metal dielectric (IMD) layers”) in which interconnects and via contacts can be formed. That is, the third interconnect layer may include interconnects and via contacts in multiple ILD layers. In some implementations, the first peripheral circuit 1041 is coupled to each other via third interconnects in the third interconnect layer.

[0050] The second semiconductor structure 104 may further include a third bonding layer located at the first bonding interface 106 and above the third interconnect layer and the first peripheral circuit 1041. The third bonding layer may include a plurality of third bonding contacts and a dielectric that electrically isolates the third bonding contacts. The surrounding dielectric in the third bonding contacts and the third bonding layer may be used for hybrid bonding.

[0051] For example, the first semiconductor structure 102 may further include a first bonding layer located at the first bonding interface 106 and above the third bonding layer. The first bonding layer may include a plurality of first bonding contacts and a dielectric that electrically isolates the first bonding contacts. The first bonding contacts in the first bonding layer and the surrounding dielectric may be used for hybrid bonding. According to some embodiments, the first bonding contacts are coupled to the third bonding contacts at the first bonding interface 106.

[0052] The first semiconductor structure 102 can be bonded face-to-face to the top of the second semiconductor structure 104 at the first bonding interface 106. In some embodiments, the first bonding interface 106 is disposed between the first and third bonding layers due to hybrid bonding (also known as "metal / dielectric hybrid bonding"), which is a direct bonding technique. For example, surface-to-surface bonding is formed without the use of intermediate layers (such as solder or adhesive), and metal-to-metal bonding and dielectric-to-dielectric bonding can be obtained simultaneously. In some embodiments, the first bonding interface 106 is where the first and third bonding layers meet and bond. In practice, the first bonding interface 106 can be a layer of a certain thickness, comprising the top surface of the third bonding layer of the second semiconductor structure 104 and the bottom surface of the first bonding layer of the first semiconductor structure 102.

[0053] In some embodiments, the first semiconductor structure 102 further includes a first interconnect layer, which includes a first bit line located above the first bonding layer for transmitting electrical signals. The first interconnect layer may include multiple first interconnects, such as MEOL interconnects and BEOL interconnects. In some implementations, the first interconnects in the first interconnect layer also include local interconnects, such as bit line contacts, word line contacts, and capacitor structure contacts. The first interconnect layer may also include one or more ILD layers, in which interconnect lines and via contacts may be formed.

[0054] In some embodiments, the third semiconductor structure 103 further includes a fourth interconnect layer (not shown) located below the second peripheral circuit 1031 for transmitting electrical signals with the second peripheral circuit 1031. The fourth interconnect layer may include multiple fourth interconnects (also referred to as "contacts"), including lateral interconnects and vertical interconnect access (VIA) contacts. Examples include middle-end line (MEOL) interconnects and back-end line (BEOL) interconnects. The fourth interconnect layer may also include one or more interlayer dielectric (ILD) layers, in which interconnects and via contacts can be formed. That is, the fourth interconnect layer may include interconnects and via contacts in multiple ILD layers. In some implementations, the second peripheral circuit 1031 is coupled to each other through the fourth interconnects in the fourth interconnect layer.

[0055] The third semiconductor structure 103 may further include a fourth bonding layer located at the second bonding interface 108 and below the fourth interconnect layer and the second peripheral circuitry 1031. The fourth bonding layer may include a plurality of fourth bonding contacts and a dielectric material that electrically isolates the fourth bonding contacts. The surrounding dielectric material in the fourth bonding contacts and the fourth bonding layer may be used for hybrid bonding.

[0056] For example, the first semiconductor structure 102 may further include a second bonding layer located at the first bonding interface 108 and above the fourth bonding layer. The second bonding layer may include a plurality of second bonding contacts and a dielectric that electrically isolates the second bonding contacts. The second bonding contacts in the second bonding layer and the surrounding dielectric may be used for hybrid bonding. According to some embodiments, the second bonding contacts are coupled to the fourth bonding contact at the second bonding interface 108.

[0057] The third semiconductor structure 103 can be bonded face-to-face to the top of the first semiconductor structure 102 at the second bonding interface 108. In some embodiments, due to hybrid bonding, the second bonding interface 108 is disposed between the second and fourth bonding layers, which is a direct bonding technique. In some embodiments, the second bonding interface 108 is the location where the second and fourth bonding layers meet and bond. In practice, the second bonding interface 108 can be a layer of a certain thickness, comprising the top surface of the second bonding layer of the first semiconductor structure 102 and the bottom surface of the fourth bonding layer of the third semiconductor structure 103.

[0058] In some embodiments, the first semiconductor structure 102 further includes a second interconnect layer, which includes second bit lines located below the second bonding layer for transmitting electrical signals. The second interconnect layer may include multiple second interconnects, such as MEOL interconnects and BEOL interconnects. In some implementations, the second interconnects in the second interconnect layer also include local interconnects, such as bit line contacts, word line contacts, and capacitor structure contacts. The second interconnect layer may also include one or more ILD layers, in which interconnect lines and via contacts can be formed.

[0059] For example, the first interconnect, second interconnect, third interconnect, and fourth interconnect may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. For example, the ILD layer may be formed using a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. For example, the first bonding contact, second bonding contact, third bonding contact, and fourth bonding contact may include conductive materials such as copper. The remaining regions of the first bonding contact, second bonding contact, third bonding contact, and fourth bonding contact may be formed using a dielectric material such as silicon oxide.

[0060] In some embodiments, the first semiconductor structure 102 includes a DRAM device, wherein memory cells are disposed above the first interconnect layer and the first bonding layer in the form of a DRAM cell array. That is, the first interconnect layer including a first bit line can be disposed between the first bonding layer and the DRAM cell array. The memory cells are disposed below the second interconnect layer and the second bonding layer in the form of a DRAM cell array. That is, the second interconnect layer including a second bit line can be disposed between the second bonding layer and the DRAM cell array. It should be understood that the cross-section of the semiconductor device can be formed along the bit line direction (Z direction), and a second bit line in the second interconnect layer extending laterally in the Z direction can be coupled to a row of DRAM cells, and a first bit line in the first interconnect layer extending laterally in the Z direction can also be coupled to a row of DRAM cells.

[0061] In some implementations, such as Figure 4 As shown, each DRAM cell 302 in the DRAM cell array may include a vertical transistor 304 and a capacitor structure 306 coupled to the vertical transistor 304. The DRAM cell 302 may be a 1T1C cell consisting of one transistor and one capacitor structure. It should be understood that DRAM cells may have any suitable configuration, such as 2T1C cells, 3T1C cells, etc.

[0062] In some embodiments, the capacitor structure includes a first capacitor structure (which can be an example of a first storage structure) and a second capacitor structure (which can be an example of a second storage structure). The first capacitor structure and the second capacitor structure are two adjacent capacitor structures along a second direction. The vertical transistor may include a first vertical transistor and a second vertical transistor. The first vertical transistor and the second vertical transistor are two adjacent vertical transistors along a second direction.

[0063] The first vertical transistor is vertically disposed between the first capacitor structure and the first bonding interface 106. That is, the first vertical transistor can be closer to the first peripheral circuitry 1041 of the second semiconductor structure 104 and the first bonding interface 106 than the first capacitor structure. According to some implementations, a first bit line (as part of the first interconnect layer) is vertically disposed between the first vertical transistor and the first bonding interface 106. Since the first bit line and the first capacitor structure are coupled to opposite ends of the first vertical transistor along a first direction (Y direction), the first interconnect layer including the first bit line can be arranged close to the first bonding interface 106 to reduce wiring distance and interconnect complexity.

[0064] The second vertical transistor is vertically disposed between the second capacitor structure and the second bonding interface 108. That is, the second vertical transistor can be closer to the second peripheral circuitry 1031 of the third semiconductor structure 103 and the second bonding interface 108 than the second capacitor structure. According to some implementations, a second bit line (as part of the second interconnect layer) is vertically disposed between the second vertical transistor and the second bonding interface 108. Since the second bit line and the second capacitor structure are coupled to opposite ends of the second vertical transistor along the first direction (Y direction), the second interconnect layer including the second bit line can be arranged close to the second bonding interface 108 to reduce wiring distance and interconnect complexity.

[0065] In some embodiments, the third semiconductor structure 103 may further include a solder interconnect layer. The solder interconnect layer may include interconnects in one or more ILD layers, such as contact pads. In some embodiments, the interconnects in the solder interconnect layer may transmit electrical signals between the semiconductor device and external circuitry, for example, for soldering purposes. In some embodiments, the third semiconductor structure 103 also includes one or more contacts extending through a portion of the solder interconnect layer. The second peripheral circuitry 1031 may be coupled to a DRAM cell (e.g., a DRAM cell including a second vertical transistor) via the fourth interconnect layer and the second interconnect layer, as well as the fourth bonding layer and the second bonding layer. The first peripheral circuitry 1041 may be coupled to a DRAM cell (e.g., a DRAM cell including a first vertical transistor) via the first interconnect layer and the third interconnect layer, as well as the first bonding layer and the third bonding layer. The first peripheral circuitry, the second peripheral circuitry, and the DRAM cell may be coupled to external circuitry via contacts and the solder interconnect layer. Contact pads and contacts may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In one example, the contact pads may include Al, and the contacts may include W.

[0066] This disclosure provides a semiconductor device (such as the semiconductor device 100 described above), including a first semiconductor structure 102. The first semiconductor structure 102 includes a semiconductor body (also referred to as an active region, and therefore hereinafter referred to as AA).

[0067] The semiconductor bodies extend along a first direction (Y direction) and are spaced apart along a second direction (X direction). The X and Y directions intersect, for example, the X and Y directions are orthogonal, but this disclosure is not limited thereto.

[0068] For example, such as Figure 5 As shown, the semiconductor body includes a first semiconductor body AA1 and a second semiconductor body AA2. Along the X direction, the first semiconductor body AA1 and the second semiconductor body AA2 are arranged alternately and intermittently. For example, in the same row along the X direction, from left to right, they are sequentially the first semiconductor body AA1, the second semiconductor body AA2, the first semiconductor body AA1, the second semiconductor body AA2, and so on. In the same column along the Y direction, all are either the first semiconductor body AA1 or all are the second semiconductor body AA2.

[0069] Continue to refer to Figure 5 Along the X direction, an isolation structure 402 is provided between adjacent first semiconductor bodies AA1 and second semiconductor bodies AA2. That is, the isolation structure 402 separates adjacent first semiconductor bodies AA1 and second semiconductor bodies AA2. The isolation structure 402 extends along the Z direction and is distributed at intervals along the X direction.

[0070] like Figure 5As shown, the semiconductor device also includes a partition structure 401. The partition structure 401 extends along the X direction and is spaced apart along the Z direction. That is, a partition structure 401 is provided between two adjacent first semiconductor bodies AA1 along the Z direction, and a corresponding partition structure 401 is also provided between two adjacent second semiconductor bodies AA2 along the Z direction.

[0071] For example, the isolation structure 402 extending along the Z direction is interrupted by the partition structures 401 distributed at intervals along the Z direction, that is, the isolation structure 402 extending along the Z direction is divided into segments by the partition structures 401.

[0072] In some embodiments, both the isolation structure 402 and the separation structure 401 can be formed of dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, or any combination thereof.

[0073] Figure 5 This is a top view of the semiconductor device, i.e., viewed from above. The second conductive structure BL2 is visible on the separator structure 401. The second conductive structure BL2 extends along the Z direction and is spaced apart along the X direction. For example, the second conductive structure BL2 is coupled to the second semiconductor body AA2 in the same column along the Z direction, but is not coupled to the first semiconductor body AA1 in the same column along the Z direction.

[0074] Figure 6 This is a bottom view of the semiconductor device, i.e., looking from below, showing the first conductive structure BL1 located under the partition structure 401. The first conductive structure BL1 extends along the Z direction and is spaced apart along the X direction. For example, the first conductive structure BL1 is coupled to the first semiconductor body AA1 in the same column along the Z direction, but is not coupled to the second semiconductor body AA2 in the same column along the Z direction. This allows for an alternating arrangement of the first conductive structure BL1 and the second conductive structure BL2, increasing the distance between them and reducing their coupling capacitance.

[0075] like Figure 5 and Figure 6 As shown, at least one end of the first conductive structure BL1 and the second conductive structure BL2 can be led out along the Z direction, so that the first conductive structure BL1 is connected to the first peripheral circuit 1041 in the second semiconductor structure 104, and the second conductive structure BL2 is connected to the second peripheral circuit 1031 in the third semiconductor structure 103 (which can be combined with the following). Figure 9 and Figure 10This shortens the connection length between the first conductive structure and the first peripheral circuit, and also shortens the connection length between the second conductive structure and the second peripheral circuit, simplifying the wiring design of semiconductor devices.

[0076] It should be noted that, Figure 5 Top view and Figure 6 The bottom view does not take into account the interconnect layer, coupling layer and dielectric that may cover the first conductive structure BL1 and the second conductive structure BL2 in the actual first semiconductor structure 102. Its purpose is to clearly show the positional relationship between the first conductive structure BL1 and the second conductive structure BL2.

[0077] In some embodiments, the conductive structure (including a first conductive structure and a second conductive structure) comprises a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polycrystalline silicon, silicides, or any combination thereof. In some embodiments, the conductive structure comprises multiple conductive layers, such as a W layer on a TiN layer.

[0078] The following is combined with Figure 7 An example of the first semiconductor structure 102 is provided. Figure 7 for Figure 5 or Figure 6 The diagram shows a cross-sectional view of the semiconductor device along the BB direction. Figure 7 As shown, the semiconductor body includes a first semiconductor body AA1 and a second semiconductor body AA2. The first semiconductor body AA1 and the second semiconductor body AA2 are arranged alternately along the X-direction. That is, the projections of the first semiconductor body AA1 and the second semiconductor body AA2 in the Y-direction towards the same direction (e.g., downwards or upwards) do not completely overlap; they are offset by a certain distance. The first semiconductor body AA1 and the second semiconductor body AA2 are arranged at intervals along the X-direction. For example, from left to right along the X-direction, if the first semiconductor body is the first semiconductor body AA1, then the second semiconductor body is the second semiconductor body AA2, the third semiconductor body is the first semiconductor body AA1, the fourth semiconductor body is the second semiconductor body AA2, and so on. The first semiconductor body AA1 and the second semiconductor body AA2 are two adjacent semiconductor bodies along the X-direction.

[0079] Continue to refer to Figure 7The first semiconductor structure 102 further includes a first memory structure 61 and a second memory structure 62. Along the Y-direction, the semiconductor body is located between the first memory structure 61 and the second memory structure 62, meaning the first memory structure 61 and the second memory structure 62 are located on opposite sides of the semiconductor body along the Y-direction. For example, the first memory structure 61 and the second memory structure 62 are staggered along the X-direction. For instance, from left to right along the X-direction, if the first memory structure is the first memory structure 61, then the second memory structure is the second memory structure 62, the third memory structure is the first memory structure 61, the fourth memory structure is the second memory structure 62, and so on. The first memory structure 61 and the second memory structure 62 are two adjacent memory structures along the X-direction. The first semiconductor body AA1 is coupled to the first memory structure 61, and the second semiconductor body AA2 is coupled to the second memory structure 62.

[0080] The semiconductor device provided in this disclosure provides a first storage structure and a second storage structure arranged in an alternating manner on opposite sides of the semiconductor body. On the one hand, compared with the related art in which all storage structures are located on the same side of the semiconductor body, the area of ​​the storage structure can be increased, thereby increasing the amount of charge that the storage structure can store.

[0081] For example, the vertical transistor containing the first semiconductor body AA1 may be referred to as the first transistor or the first vertical transistor 2101. The vertical transistor containing the second semiconductor body AA2 may be referred to as the second transistor or the second vertical transistor 2102.

[0082] In some embodiments, the vertical transistor may be a MOSFET for switching a corresponding DRAM cell. In some embodiments, the vertical transistor includes a semiconductor body extending vertically (in the Y direction) (i.e., an active region in which multiple channels may be formed), and a gate structure coupled to one or more sides of the semiconductor body. In some embodiments, the semiconductor body may include a metal-oxide-semiconductor material or single-crystal silicon, etc. For example, the semiconductor body may be indium gallium zinc oxide (In... x Ga y Zn z Indium gallium silicon oxide (IGZO) is a compound of indium gallium silicon oxide (In). x Ga y Si z O), Indium tin zinc oxide (In x Sn y Zn z O), indium zinc oxide (In x Zn y O), zinc oxide (Zn) x O), zinc tin oxide (Zn) x Sn yO), Zinc nitrogen oxide (Zn) x O y N), Zirconium zinc tin oxide (Zr) x Zn y Sn z O), tin oxide (Sn) x O), hafnium indium zinc oxide (Hf) x In y Zn z O), gallium zinc tin oxide (Ga) x Zn y Sn z O), aluminum zinc tin oxide (Al) x Zn y Sn z O), ytterbium gallium zinc oxide (Yb x Ga y Zn z O), Indium gallium oxide (In x Ga y One or more of O, etc. The values ​​of x, y, z can be determined according to the actual situation, and this disclosure does not limit them.

[0083] For example, continue to refer to Figure 7 The semiconductor device may further include a first conductive structure BL1 and a second conductive structure BL2. Both the first and second conductive structures are made of conductive materials. For example, the first conductive structure can be a first bit line, and the second conductive structure can be a second bit line. Both the first conductive structure BL1 and the second conductive structure BL2 extend along a third direction (Z direction). The first conductive structure BL1 and the second conductive structure BL2 are spaced apart along a second direction (X direction). For example, assuming that along the X direction from left to right, the first conductive structure is the first conductive structure BL1, then the second conductive structure is the second conductive structure BL2; the third conductive structure is the first conductive structure BL1, then the fourth conductive structure is the second conductive structure BL2, and so on. Simultaneously, the first conductive structure BL1 and the second conductive structure BL2 are staggered along the second direction (X direction). That is, the projections of the first conductive structure BL1 and the second conductive structure BL2 in the Y direction towards the same direction (e.g., downwards or upwards) do not completely overlap; they are offset by a certain distance.

[0084] In this embodiment of the disclosure, the third direction (Z direction) intersects the first direction (Y direction) and the second direction (X direction), respectively. For example, the Z direction, Y direction, and X direction are mutually perpendicular to each other, but this disclosure is not limited to this.

[0085] In this embodiment of the present disclosure, by placing the first conductive structure and the second conductive structure on opposite sides of the semiconductor body along the Y direction, and by arranging the first conductive structure and the second conductive structure alternately along the X direction, the distance between adjacent first conductive structures and second conductive structures can be increased, and the coupling capacitance between adjacent first conductive structures and second conductive structures can be reduced.

[0086] For example, continue to refer to Figure 7 Along the Y direction, the first semiconductor body AA1 includes a first end AA1-1 (e.g., upper end) and a second end AA1-2 (e.g., lower end) opposite each other; the second semiconductor body AA2 includes a first end AA2-1 (e.g., upper end) and a second end AA2-2 (e.g., lower end) opposite each other.

[0087] In some embodiments, the first end AA1-1 of the first semiconductor body AA1 can serve as the source or drain of the first vertical transistor; the second end AA1-2 of the first semiconductor body AA1 can serve as the drain or source of the first vertical transistor. In some embodiments, the first end AA2-1 of the second semiconductor body AA2 can serve as the drain or source of the second vertical transistor; the second end AA2-2 of the second semiconductor body AA2 can serve as the source or drain of the second vertical transistor.

[0088] In an exemplary embodiment, the first storage structure 61 is coupled to the first end AA1-1 of the first semiconductor body AA1. The first conductive structure BL1 is coupled to the second end AA1-2 of the first semiconductor body AA1. That is, the first storage structure 61 and the first conductive structure BL1 are located on opposite sides of the first semiconductor body AA1 along the Y direction, and are respectively connected to the source and drain of the first vertical transistor. This increases the distance between the first conductive structures BL1 and simplifies the structural layout of the semiconductor device.

[0089] In an exemplary embodiment, the second storage structure 62 is coupled to the second end AA2-2 of the second semiconductor body AA2. The second conductive structure BL2 is coupled to the first end AA2-1 of the second semiconductor body AA2. That is, the second storage structure 62 and the second conductive structure BL2 are located on opposite sides of the second semiconductor body AA2 along the Y direction, and are respectively connected to the source and drain of the second vertical transistor. This increases the distance between the second conductive structure BL2 and the second storage structure 62, simplifying the structural layout of the semiconductor device.

[0090] The semiconductor device provided in this disclosure, on the one hand, increases the distance between the conductive structure (including a first conductive structure and a second conductive structure) and the memory structure (including a first memory structure and a second memory structure) by placing them on opposite sides of the semiconductor body (including a first semiconductor body and a second semiconductor body) along the Y direction, thus simplifying the layout of the conductive and memory structures in the semiconductor device. On the other hand, by altering the orientation of the first memory structure and the first conductive structure and the second conductive structure connected to the source and drain of adjacent first semiconductor bodies and second semiconductor bodies along the Y direction—for example, if the first memory structure connected to the first semiconductor body is located at the upper end of the first semiconductor body, then the second memory structure connected to the second semiconductor body is located at the lower end of the second semiconductor body; correspondingly, the first conductive structure connected to the first semiconductor body is located at the lower end of the first semiconductor body, and the second conductive structure connected to the second semiconductor body is located at the upper end of the second semiconductor body—this increases the distance between adjacent first conductive structures and second conductive structures, reduces the coupling capacitance between the first conductive structures and second conductive structures, and also allows the first memory structure and the second memory structure to have a larger area, thereby storing more charge.

[0091] For example, such as Figure 7 As shown, the first storage structure 61 includes a first electrode 611 (also referred to as an internal electrode). The second storage structure 62 includes a first electrode 621 (also referred to as an internal electrode). The first end AA1-1 of the first semiconductor body AA1 is coupled to the first electrode 611 of the first storage structure 61. That is, the first end AA1-1 and the second end AA1-2 of the first semiconductor body AA1 are coupled to the first electrode 611 of the first storage structure 61 and the first conductive structure BL1, respectively. The second end AA2-2 of the second semiconductor body AA2 is coupled to the first electrode 621 of the second storage structure 62. That is, the first end AA2-1 and the second end AA2-2 of the second semiconductor body AA2 are coupled to the second conductive structure BL2 and the first electrode 621 of the second storage structure 62, respectively.

[0092] For example, along the X direction, the first electrodes 611 of the adjacent first storage structure 61 and the first electrodes 621 of the second storage structure 62 are spaced apart. For instance, along the X direction from left to right, the first electrodes 611 of the first storage structure 61, the first electrodes 621 of the second storage structure 62, the first electrodes 611 of the first storage structure 61, the first electrodes 621 of the second storage structure 62, and so on are spaced apart.

[0093] For example, along the X direction, the first electrodes 611 of adjacent first storage structures 61 and the first electrodes 621 of adjacent second storage structures 62 are staggered. That is, when projected along the Y direction in the same direction (e.g., upward or downward), the projections of the first electrodes 611 of adjacent first storage structures 61 and the first electrodes 621 of adjacent second storage structures 62 do not overlap at least partially.

[0094] In some embodiments, the first memory structure 61 in the semiconductor device further includes a second electrode (external electrode), and the second electrodes of multiple first memory structures 61 are all connected to a common electrode or connected together as a common electrode (e.g., common ground), so that no charge accumulates between the second electrodes of two adjacent first memory structures 61. In this way, the electrical coupling between the first semiconductor bodies of two adjacent first vertical transistors can be greatly reduced.

[0095] In some embodiments, the second memory structure 62 in the semiconductor device further includes a second electrode (external electrode), and the second electrodes of multiple second memory structures 62 are all connected to another common electrode or connected together as another common electrode (e.g., common ground), so that no charge accumulates between the second electrodes of two adjacent second memory structures 62. In this way, the electrical coupling between the second semiconductor bodies of two adjacent second vertical transistors can be greatly reduced.

[0096] In some embodiments, the capacitor structure (which may be a first storage structure or a second storage structure) includes a first electrode, a second electrode, and a capacitor dielectric located between the first electrode and the second electrode. For example, the capacitor structure may be a vertical capacitor, wherein the first electrode, the second electrode, and the capacitor dielectric are stacked vertically (in the Y direction), and the capacitor dielectric may be sandwiched between the first electrode and the second electrode.

[0097] In some embodiments, the first electrode and / or the second electrode may include a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polycrystalline silicon, silicides, or any combination thereof. In some embodiments, the first electrode and / or the second electrode comprises a multilayer structure, each layer of which includes one of TiN, TaN, carbon, polycrystalline silicon, metal, metal compound, and silicide. In some embodiments, the capacitor dielectric includes a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al₂O₃, HfO₂, Ta₂O₅, ZrO₂, TiO₂, or any combination thereof.

[0098] In some implementations, each vertical transistor (including a first vertical transistor and a second vertical transistor) may include a drain and a source, respectively disposed at both ends (upper and lower ends) of the semiconductor body (including a first semiconductor body and a second semiconductor body) in the vertical direction (Y direction). In some implementations, one of the source and drain is coupled to a capacitor structure, while the other of the source and drain is coupled to a bit line (including a first bit line and a second bit line). This increases the contact area between the capacitor structure and the vertical transistor, and the contact resistance can be significantly reduced due to the increased contact area. In this case, the source node contact between the capacitor structure and the vertical transistor can be omitted. The source or drain of the coupled bit line extends laterally (X direction), forming the top or bottom wall of the semiconductor body. The bit line can be directly formed on the laterally extending source or drain of the vertical transistor, simplifying the manufacturing process.

[0099] refer to Figure 7 Along the X direction, there is an isolation structure 402 between adjacent first semiconductor bodies AA1 and second semiconductor bodies AA2.

[0100] Figure 8 Is it like this? Figure 5 or Figure 6 The diagram shows a cross-sectional view of the semiconductor device along the CC direction. (As shown...) Figure 8 As shown, the first semiconductor structure 102 also includes a gate structure WL. The gate structures WL extend along the X direction and are spaced apart along the Z direction. Along the Y direction, the gate structures WL are located between the partition structures 401. That is, the upper and lower surfaces of the gate structures WL along the Y direction are covered by the partition structures 401.

[0101] For example, the gate structure coupled to the first semiconductor body AA1 is referred to as the first gate structure, and the gate structure coupled to the second semiconductor body AA2 is referred to as the second gate structure. The same gate structure WL can therefore be divided into first gate structures and second gate structures that are alternately distributed along the X direction.

[0102] For example, along the third direction (Z direction), the first gate structure is located on at least one side of the first semiconductor body AA1 and coupled to the first semiconductor body AA1, and the second gate structure is located on at least one side of the second semiconductor body AA2 and coupled to the second semiconductor body AA2.

[0103] For example, along the third direction (Z direction), the first gate structure is located on both sides of the first semiconductor body AA1, and the second gate structure WL2 is located on both sides of the second semiconductor body AA2. In the following example of the fabrication method, the example is given with the first gate structure located on two sides of the first semiconductor body AA1 along the Z direction and the second gate structure located on two sides of the second semiconductor body AA2 along the Z direction, i.e., a dual-gate vertical transistor is used as an example, but this disclosure is not limited to this.

[0104] For example, the first semiconductor structure 102 further includes a separator structure 401 located between adjacent first gate structures and second gate structures. For example, as... Figure 5 As shown, the same partition structure 401 along the Z direction includes two first gate structures. The partition structure 401 not only covers the upper and lower surfaces of these two first gate structures but also fills the space between them to electrically insulate these adjacent first gate structures. Similarly, the same partition structure 401 along the Z direction includes two second gate structures. The partition structure 401 not only covers the upper and lower surfaces of these two second gate structures but also fills the space between them to electrically insulate these adjacent second gate structures.

[0105] For example, such as Figure 9 As shown, the semiconductor device may further include a second semiconductor structure 104 and a third semiconductor structure 103. The second semiconductor structure 104, the first semiconductor structure 102, and the third semiconductor structure 103 are stacked sequentially along a first direction (Y direction). The second semiconductor structure 104 includes a first peripheral circuit 1041. The third semiconductor structure 103 includes a second peripheral circuit 1031. A portion of the semiconductor body in the first semiconductor structure 102 is coupled to the first peripheral circuit 1041 in the second semiconductor structure 104. Another portion of the semiconductor body in the first semiconductor structure 102 is coupled to the second peripheral circuit 1031 in the third semiconductor structure 103. For example, the first semiconductor body AA1 or the first vertical transistor is coupled to the first peripheral circuit 1041 in the second semiconductor structure 104, and the second semiconductor body AA2 or the second vertical transistor is coupled to the second peripheral circuit 1031 in the third semiconductor structure 103.

[0106] This embodiment of the present disclosure provides a second semiconductor structure and a third semiconductor structure coupled to opposite sides of a first semiconductor structure along the Y direction, and couples the first semiconductor body AA1 or the first vertical transistor to the first peripheral circuit 1041 in the second semiconductor structure 104, and the second semiconductor body AA2 or the second vertical transistor to the second peripheral circuit 1031 in the third semiconductor structure 103. This reduces the wiring complexity between the vertical transistors in the first semiconductor structure and the peripheral circuits, reduces the wiring length, and simplifies the manufacturing process.

[0107] In an exemplary embodiment, combined with Figure 7 and Figure 9 In this embodiment, along the Y direction, the first storage structure 61 is located between the first semiconductor body AA1 and the third semiconductor structure 103, that is, the first storage structure 61 is closer to the third semiconductor structure 103 than the first semiconductor body AA1; the second storage structure 62 is located between the second semiconductor body AA2 and the second semiconductor structure 102, that is, the second storage structure 62 is closer to the second semiconductor structure 104 than the second semiconductor body AA2.

[0108] For example, such as Figure 8 and Figure 10 As shown, the semiconductor device also includes a gate structure WL, which extends along a second direction (X direction) and is spaced apart along a third direction (Z direction). In this embodiment, the gate structure coupled to the first semiconductor body AA1 is referred to as the first gate structure, and the gate structure coupled to the second semiconductor body AA2 is referred to as the second gate structure. For the same gate structure WL extending along the X direction, since the first semiconductor body AA1 and the second semiconductor body AA2 are spaced apart along the X direction, the same gate structure WL is divided into a spaced-apart first gate structure and a second gate structure along the X direction. The first gate structure is coupled to the first peripheral circuit 1041 in the second semiconductor structure 104 through a second contact structure 701. Alternatively, the second gate structure is coupled to the second peripheral circuit 1031 in the third semiconductor structure 103 through a fourth contact structure 702. The semiconductor device provided by this embodiment makes the interconnection between the gate structure and the peripheral circuit more flexible, and the gate structure can be connected to the first peripheral circuit or the second peripheral circuit according to actual wiring requirements.

[0109] Continue to refer to Figure 10The second semiconductor structure 104 further includes a second substrate 1043, and the first peripheral circuit 1041 is located on the second substrate 1043, or partially located on the second substrate 1043 and partially located within the second substrate 1043. The second semiconductor structure 104 also includes a third interconnect layer, which includes a third interconnect 1044. The third interconnect 1044 can be connected to the second contact structure 701 to realize the connection between the first gate structure and the first peripheral circuit 1041.

[0110] like Figure 10 As shown, the third semiconductor structure 103 further includes a third substrate 1033, and the second peripheral circuit 1031 is located under the third substrate 1033, or partially located under the third substrate 1033 and partially located within the third substrate 1033. The third semiconductor structure 103 also includes a fourth interconnect layer, which includes a fourth interconnect 1034. The fourth interconnect 1034 can be connected to the fourth contact structure 702 to realize the connection between the second gate structure and the second peripheral circuit 1031.

[0111] The embodiments disclosed herein employ vertical transistors, that is, a semiconductor body along the Y direction and a gate structure in contact with it form a vertical transistor. Some vertical transistors are controlled by the upper peripheral circuit (e.g., the second peripheral circuit), and some vertical transistors are controlled by the lower peripheral circuit (e.g., the first peripheral circuit).

[0112] The gate structure (including a first gate structure and a second gate structure) in this disclosure includes a gate dielectric layer and a gate electrode. The gate dielectric layer is located between the semiconductor body and the gate electrode. The gate dielectric layer includes a dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to aluminum oxide (Al₂O₃), hafnium oxide (HfO₂), tantalum oxide (Ta₂O₅), zirconium oxide (ZrO₂), titanium oxide (TiO₂), or any combination thereof. The gate electrode includes a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polycrystalline silicon, silicides, or any combination thereof. In some embodiments, the gate electrode includes a conductive layer and a gate, for example, the conductive layer is a TiN layer and the gate is a W layer located on the TiN layer. In some embodiments, the gate may include doped polycrystalline silicon, and the gate dielectric layer includes silicon oxide. In other embodiments, the gate dielectric layer includes a high-k dielectric, and the gate includes a metal.

[0113] When DRAM technology is applied to actual production, the pursuit of increased capacity (increased storage density) and lower costs has led to increasingly smaller pitches (metal line spacing). This reduction in pitch results in two main problems: firstly, the physical size of the IC capacitors within memory cells decreases, leading to reduced charge storage and shorter data retention time; secondly, the reduced spacing between bit lines increases the coupling capacitance, further worsening the sense margin and increasing read / write error rates. This is a significant issue for DRAM scaling. One approach is to reduce the coupling capacitance between bit lines by adding black line shielding. However, reducing the coupling capacitance through black line shielding increases the total black line capacitance (BL).

[0114] The semiconductor device provided in this embodiment employs three wafers: two CMOS wafers (i.e., the second semiconductor structure and the third semiconductor structure) and one DRAM cell wafer (i.e., the first semiconductor structure). Adjacent first bit lines and second bit lines are alternately staggered, as are adjacent first capacitor structures and second capacitor structures. The first bit lines and second bit lines are located on opposite sides of the semiconductor body, and the first capacitor structures and second capacitor structures are located on opposite sides of the semiconductor body. On one hand, this reduces the spacing between bit lines, lowering the coupling capacitance between them without increasing the total capacitance of the bit lines. On the other hand, it increases the physical size of the capacitor structures in the memory cell, providing sufficient area to increase the 1C capacitance value and enabling further scaling of the DRAM.

[0115] The semiconductor device provided in this disclosure can serve as a novel 4F2 DRAM structure, improving the signal-to-noise ratio. Through vertical integration of three wafers and a staggered design of bit lines and capacitor structures, the capacitance value and signal integrity are optimized while reducing the DRAM cell size.

[0116] like Figure 11 As shown in the embodiments of this disclosure, a method for fabricating a semiconductor device is also provided, including the following steps.

[0117] In S110, a first semiconductor structure is provided, comprising a semiconductor body, a first memory structure, and a second memory structure; the semiconductor body extends along a first direction and is arranged along a second direction; along the first direction, the semiconductor body is located between the first memory structure and the second memory structure, and the first memory structure and the second memory structure are staggered along the second direction; the semiconductor body includes adjacent first semiconductor bodies and second semiconductor bodies along the second direction; the first semiconductor body is coupled to the first memory structure, and the second semiconductor body is coupled to the second memory structure; the first direction and the second direction intersect.

[0118] For example, the method provided in this disclosure further includes: providing a second semiconductor structure and a third semiconductor structure, such that the second semiconductor structure, the first semiconductor structure and the third semiconductor structure are stacked sequentially along the first direction.

[0119] The second semiconductor structure and the third semiconductor structure respectively include a first peripheral circuit and a second peripheral circuit; a portion of the semiconductor body in the first semiconductor structure is coupled to the first peripheral circuit; and another portion of the semiconductor body in the first semiconductor structure is coupled to the second peripheral circuit.

[0120] For example, a first semiconductor structure is provided, including: providing a first gate structure and a second gate structure, such that the first gate structure is coupled to the first peripheral circuit; or, the second gate structure is coupled to the second peripheral circuit.

[0121] For example, a first semiconductor structure is provided, further comprising: forming a third contact structure and a fourth contact structure respectively coupled to the first gate structure and the second gate structure.

[0122] The provision includes a second semiconductor structure and a third semiconductor structure, comprising: forming a third interconnect coupled to the first peripheral circuit, such that the third interconnect is coupled to the third contact structure; and forming a fourth interconnect coupled to the second peripheral circuit, such that the fourth interconnect is coupled to the fourth contact structure.

[0123] For example, a first semiconductor structure is provided, comprising: forming a first semiconductor body and a second semiconductor body extending along a first direction, wherein the first semiconductor body and the second semiconductor body each include a first end and a second end opposite to each other along the first direction; forming a second conductive structure coupled to the first end of the second semiconductor body; forming a first conductive structure coupled to the second end of the first semiconductor body, wherein the first conductive structure and the second conductive structure both extend along a third direction, and the first conductive structure and the second conductive structure are staggered along a second direction, wherein the third direction intersects the first direction and the second direction respectively; forming a first memory structure coupled to the first end of the first semiconductor body; and forming a second memory structure coupled to the second end of the second semiconductor body.

[0124] For example, a first semiconductor structure is provided, comprising: providing a substrate, the substrate including a first surface and a second surface opposite to each other along a first direction; forming an isolation structure in the substrate from the first surface of the substrate, the isolation structure extending along a third direction and spaced apart along a second direction, the third direction intersecting the first direction and the second direction respectively; forming a first gate structure and a second gate structure in the substrate, the first gate structure and the second gate structure both extending along the second direction and spaced apart along the third direction, so as to form the first semiconductor body and the second semiconductor body in the substrate respectively through the first gate structure, the second gate structure and the isolation structure.

[0125] For example, the first semiconductor body and the second semiconductor body respectively include a first end and a second end along the first direction.

[0126] For example, a first semiconductor structure is provided, further comprising: forming a second conductive structure coupled to a first end of a second semiconductor body; forming a first conductive structure coupled to a second end of the first semiconductor body, wherein the first conductive structure and the second conductive structure both extend along a third direction, and the first conductive structure and the second conductive structure are staggered along the second direction; forming a first memory structure coupled to the first end of the first semiconductor body; and forming a second memory structure coupled to the second end of the second semiconductor body.

[0127] For example, forming the first gate structure and the second gate structure in the substrate includes: forming word line trenches in the substrate from a first surface of the substrate, the word line trenches extending along a second direction and spaced apart along the third direction; forming the first gate structure and the second gate structure in the word line trenches, the first gate structure being coupled to the first semiconductor body, the second gate structure being coupled to the second semiconductor body, and both the first gate structure and the second gate structure including a first side and a second side opposite to each other along the first direction; exposing the second side of the first gate structure and the second gate structure on a second surface of the substrate; forming a separation structure, through which the first semiconductor body and the second semiconductor body are formed in the substrate respectively.

[0128] For example, both the first gate structure and the second gate structure include a gate dielectric layer and a gate electrode.

[0129] For example, forming the first gate structure and the second gate structure in the word line trench includes: forming the gate dielectric layer on the sidewall of the word line trench; and forming the gate electrode on the sidewall of the gate dielectric layer.

[0130] The semiconductor device fabrication method provided in this disclosure involves dividing the conductive structure into upper and lower layers (such as a first conductive structure and a second conductive structure) in a mid-layer DRAM cell wafer. These layers are arranged through different metal layers (such as a first interconnect layer and a second interconnect layer). Adjacent conductive structures are not on the same plane, reducing lateral coupling, and are vertically staggered by a certain spacing. This staggered layout increases the physical spacing between adjacent conductive structures, reduces the coupling capacitance between them, and avoids occupying additional lateral area, maintaining a 4F2 cell density. The transistors (1T) and capacitor structures (1C) of each memory cell are stacked vertically. The first and second conductive structures are connected to the source / drain of adjacent memory cells, respectively, reducing wiring complexity. The aspect ratio of the capacitor structure is expanded using vertical space (such as a cylindrical or finned structure), increasing the capacitance value and enhancing data retention capability.

[0131] The following is combined with Figures 12 to 30 The methods for fabricating semiconductor devices provided in the embodiments of this disclosure are illustrated by way of example. It is understood that this disclosure is not limited thereto. Any method for fabricating a semiconductor device with the above structure is within the scope of protection of this disclosure. Figures 12 to 30 This refers to the fabrication process of DRAM cell wafers, i.e., the first semiconductor structure. Two CMOS wafers can be fabricated using relevant technologies. Figures 12 to 30This section primarily introduces the manufacturing process of DRAM memory cells that include vertical transistors, where bit lines and capacitor structures are staggered.

[0132] like Figure 12 As shown, a substrate 91 is provided. The substrate 91 includes a first surface 911 (upper surface) and a second surface 912 (lower surface) opposite each other along the Y direction. A WELL implantation process is then performed on the substrate 91. If a P-type silicon substrate is used, N-well implantation is performed, i.e., N-type impurities such as phosphorus (P) or arsenic (As) are implanted into the P-type substrate to form a high-concentration N-type region. If an N-type silicon substrate is used, P-well implantation is performed, i.e., P-type impurities such as boron (B) are implanted into the N-type substrate or epitaxial layer to form a P-type region.

[0133] like Figure 13 As shown, an isolation structure 402 is formed in the substrate 91 from the first surface 911. The isolation structure 402 extends along the Z direction and is spaced apart along the X direction. The Z direction intersects the X and Y directions, for example, orthogonally. For example, an oxide layer can be formed in the well area to prevent leakage by using LOCOS (Local Oxide Isolation) or STI (Shallow Trench Isolation) processes.

[0134] like Figure 14 The top view shown shows word line trenches 110 formed in the substrate 91 from its first surface 911. The word line trenches 110 extend along the X direction and are spaced apart along the Z direction. During the formation of the word line trenches 110, a portion of the isolation structure 402 is removed, that is, the isolation structure 402 extending along the Z direction is divided into multiple segments. At this time, the intersecting word line trenches 110 and the isolation structure 402 separate the well regions, forming a first semiconductor body AA1 and a second semiconductor body AA2.

[0135] Figure 15 yes Figure 14 The diagram shows a cross-sectional view of the first semiconductor structure along the DD or EE direction. When the cross-sectional view is along the DD direction, Figure 15 The semiconductor body AA in the diagram is the first semiconductor body AA1. When the view is a cross-sectional view along the EE direction, Figure 15 The semiconductor body AA in the figure is the second semiconductor body AA2.

[0136] like Figure 15 As shown, the character line groove 110 includes two side walls 110-1 and 110-2 along the Z direction.

[0137] like Figure 16As shown, a gate dielectric layer 126 is formed on the left and right sidewalls 110-1 and 110-2 of the word line groove 110. The gate dielectric layer 126 does not completely fill the word line groove 110, and the gate dielectric layer 126 includes the left and right sidewalls 126-1 and 126-2 along the Z direction.

[0138] like Figure 17 As shown, gate electrodes 114 are formed on the left and right sidewalls 126-1 and 126-2 of the gate dielectric layer 126 along the Z direction. The gate electrodes 114 do not fill the word line trench 110, and the gate electrodes 114 include the left and right sidewalls 114-1 and 114-2 along the Z direction. Then, the mutually coupled gate electrodes 114 and gate dielectric layer 126 are combined into a gate structure. For example, the sidewalls 114-1 of the gate electrode 114 and 126-1 of the gate dielectric layer 126 are combined into a gate structure (when the cross-sectional view is along the DD direction, a first gate structure is formed; when the cross-sectional view is along the EE direction, a second gate structure is formed). The sidewalls 114-2 of the gate electrode 114 and 126-2 of the gate dielectric layer 126 are combined into another gate structure (when the cross-sectional view is along the DD direction, another first gate structure is formed; when the cross-sectional view is along the EE direction, another second gate structure is formed). The first gate structure is coupled to the first semiconductor body AA1, and the second gate structure is coupled to the second semiconductor body AA2. Both the first gate structure and the second gate structure include a first side 216-1 and a second side 216-2 that are opposite each other along the Y direction.

[0139] like Figure 18 As shown, along the first surface 911 of the substrate 91, a portion of the gate structure is etched back to remove it, so that its upper surface in the Y direction is lower than the upper surface of the semiconductor body AA. The second surface 912 of the substrate 91 is then thinned until the lower surface of the semiconductor body AA and the second side 216-2 of the gate structure are exposed. Then, a portion of the second side 216-2 of the gate structure is etched back along the back surface, so that the second side 216-2 in the Y direction is recessed inward relative to the lower surface of the semiconductor body AA, i.e., along the Y direction, the upper and lower surfaces of the gate structure WL are both located between the upper and lower surfaces of the semiconductor body AA. A separator structure 401 is then filled between two gate structures WL located between adjacent semiconductor bodies, so that the separator structure 401 covers the space between the two gate structures WL, as well as the upper and lower surfaces of the two gate structures WL. This forms a gate structure that is substantially symmetrical vertically in the Y direction, and along the Z direction, each semiconductor body has two gate structures on both sides in contact with it, thus forming a dual-gate vertical transistor, increasing the gate control area and improving gate control capability.

[0140] like Figure 19The diagram shows a cross-sectional view along the YZ direction. The first end of the semiconductor body AA is processed using an LDD (Lightly Doped Drain) process to form the first end AA-1 of the semiconductor body AA. When the cross-sectional view is along the DD direction, the first end AA-1 of the semiconductor body AA along the Y direction is the first end AA1-1 of the first semiconductor body AA1; when the cross-sectional view is along the EE direction, the opposite first end AA-1 of the semiconductor body AA along the Y direction is the first end AA2-1 of the second semiconductor body AA2.

[0141] like Figure 20 The diagram shows a cross-sectional view along the XY direction. A second conductive structure BL2 is formed on the first end AA2-1 of the second semiconductor body AA2, and the second conductive structure BL2 is connected to the first end AA2-1 of the second semiconductor body AA2. The second conductive structure BL2 extends along the Z direction and is spaced apart along the X direction. No second conductive structure BL2 is formed on the first end AA1-1 of the first semiconductor body AA1.

[0142] Figure 21 This is a top view of the first semiconductor structure. Figure 20 for Figure 21 Cross-sectional view along the FF direction.

[0143] like Figure 22 As shown, Figure 20 Flip along the Y direction, i.e., flip up and down. Then, perform LDD process on the second end AA1-2 of the first semiconductor body AA1 and the second end AA2-2 of the second semiconductor body AA2 to form the second end AA1-2 of the first semiconductor body AA1 and the second end AA2-2 of the second semiconductor body AA2.

[0144] like Figure 23 The diagram shows a cross-sectional view along the XY direction. A first conductive structure BL1 is formed on the second end AA1-2 of the first semiconductor body AA1, and the first conductive structure BL1 is connected to the second end AA1-2 of the first semiconductor body AA1. The first conductive structure BL1 extends along the Z direction and is spaced apart along the X direction. The first conductive structure BL1 is not formed on the second end AA2-2 of the second semiconductor body AA2.

[0145] Figure 24 This is a bottom view of the first semiconductor structure. Figure 23 for Figure 24 Cross-sectional view along the FF direction.

[0146] like Figure 25As shown, a first dielectric layer 221 is formed on the first conductive structure BL1, the second end AA2-2 of the second semiconductor body AA2, and the isolation structure 402. The first dielectric layer 221 may include one or more layers of insulating material.

[0147] like Figure 26 As shown, a first capacitor hole 231 is formed through the first dielectric layer 221 to expose the second end AA2-2 of the second semiconductor body AA2 and the partial isolation structure 402.

[0148] like Figure 27 As shown, a first electrode 621 of the second storage structure 62 is formed on the sidewall and bottom wall of the first capacitor hole 231. The first electrode 621 of the second storage structure 62 is in contact with the second end AA2-2 of the second semiconductor body AA2.

[0149] like Figure 28 As shown, a first capacitor dielectric 251 is formed on the upper surface of the first electrode 621 and the remaining first dielectric layer 221 of the second storage structure.

[0150] like Figure 29 As shown, a second electrode 261 of the second storage structure 62 is formed on the first capacitor dielectric 251. Optionally, an insulating material 291 may also be formed within the first capacitor hole 231.

[0151] like Figure 30 As shown, Figure 29 The first semiconductor structure shown is flipped over so that the second conductive structure BL2 is located above the first conductive structure BL1. Then, a second dielectric layer 271 is formed on the second conductive structure BL2, the first end AA1-1 of the first semiconductor body AA1, and the isolation structure 402. The second dielectric layer 271 may include one or more layers of insulating material. A second capacitor hole is formed through the second dielectric layer 271 to expose the first end AA1-1 of the first semiconductor body AA1 and part of the isolation structure 402. A first electrode 611 of the first storage structure 61 is formed on the sidewalls and bottom wall of the second capacitor hole. The first electrode 611 of the first storage structure is in contact with the first end AA1-1 of the first semiconductor body AA1. A second capacitor dielectric 272 is formed on the first electrode 611 of the first storage structure and the upper surface of the remaining second dielectric layer 271. A second electrode 273 of the first storage structure 61 is formed on the second capacitor dielectric 272. Optionally, an insulating material 301 may also be formed within the second capacitor hole.

[0152] In some embodiments, the first and second capacitor dielectrics comprise dielectric materials such as silicon oxide, silicon nitride, or high-k dielectrics, including but not limited to Al₂O₃, HfO₂, Ta₂O₅, ZrO₂, TiO₂, or any combination thereof. It should be noted that the first and second capacitor dielectrics have materials different from the substrate or base plate. The capacitor dielectrics (including the first and second capacitor dielectrics) of the capacitor structure can be formed by one or more thin-film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. In some embodiments, the first electrode may comprise a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polycrystalline silicon, silicides, or any combination thereof. In some embodiments, the capacitor dielectrics and the first electrode can be formed by a series of manufacturing processes, including thin-film deposition processes (e.g., CVD, PVD, ALD, etc.) and patterning processes (e.g., photolithography, dry etching, wet etching, cleaning, chemical mechanical polishing (CMP), etc.). Note that the manufacturing process and / or sequence for forming the capacitor dielectric and the first electrode can vary depending on whether the process is front-side or back-side.

[0153] exist Figure 30 Other process steps can then be performed to form, for example... Figure 9 and Figure 10 The semiconductor device shown.

[0154] It should be understood that the operations shown in the method are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously or in a different order than those shown.

[0155] It should be noted that in the semiconductor devices provided in this disclosure, it is sufficient to form staggered capacitor structures on opposite sides of the semiconductor body extending along the Y direction perpendicular to the transistor; the shape and structure of the capacitor structures are not limited. For example, the above... Figures 25 to 30 The example used is a cap-shaped capacitor, but in other embodiments, other structures such as columnar capacitors can also be used.

[0156] The capacitor structure (including the first storage structure and the second storage structure) in the embodiments of this disclosure can be a planar capacitor or a vertical capacitor, and this disclosure does not limit this to either. In some embodiments, the vertical capacitor can be a cylindrical capacitor. In other embodiments, the vertical capacitor can be a cup-shaped capacitor.

[0157] Figure 31 A schematic diagram of a cylindrical capacitor structure is shown. Figure 31As shown, a first electrode 23 (e.g., TiN) is formed in a first hole 11, and the first hole 11 is filled with a filler material 16 (e.g., polysilicon, dielectric material). The filler material 16 covers the first electrode 23. The first electrodes 23 are arranged and recessed within the first hole 11 to establish a relatively uniform material layer within the first hole 11, but the first hole 11 can also be filled in different ways. For example, depending on the configuration of the vertical capacitor, the first electrodes 23 can be partially arranged or partially filled in the first hole 11. Different first holes 11 can also be filled in different ways as needed. A mask (not shown) is applied on top of the filler material 16. The mask includes circular spacer holes (not shown) aligned with the first hole 11. The spacer holes and the periphery of the mask can be etched to pattern various features. The spacer holes of the mask are used as guides to etch a second hole 71. An isolation layer 15 (e.g., a high-k dielectric material) is deposited on the first electrode 23. Specifically, the isolation layer 15 is deposited into the etched second hole 71 and covers the first electrode 13. Alternatively, the isolation layer 15 can also be laterally deposited around the first via etched periphery of the capacitor structure. The isolation layer 15 can also be deposited on other exposed surfaces, such as on top of the filler material 16 remaining in the first via 11 and on the second dielectric material layers 42-1, 42-2, and 42-3. The second electrode 14 is then formed on the isolation layer 15 in a similar manner, for example, by deposition through etched second via 71 and / or by lateral deposition through etched periphery. Exemplarily, the second electrode 14 consists of two different conductive material layers 14-1 and 14-2, which may include, for example, TiN and SiGe, respectively. The second electrode 14 can also consist of a single layer of conductive material, such as TiN or SiGe. The first electrode 23 is separated from the second electrode 14 by the isolation layer 15, thereby forming a columnar capacitor 90. Due to the vertical geometry of the columnar capacitor 90 and the high dielectric constant of the isolation layer 15, the columnar capacitor 90 generally exhibits higher quality, such as higher capacitance and / or reduced wafer area consumption, compared to planar capacitors and / or capacitors manufactured using other methods.

[0158] Due to various etching processes, material removal, and deposition steps, the columnar capacitor 90 has a relatively complex three-dimensional configuration. For example, a columnar capacitor 90 includes a region defined vertically by two layers of second dielectric material 42-1 and 42-2. This region is laterally defined by two first electrodes 23 adjacent to first holes 11. An insulating layer 15 is supported by a continuous surface supported by the two layers of second dielectric material 42-1 and 42-2 and the two first electrodes 23. A shared second electrode 14 occupies the space defined by this continuous surface, such that a conductive material layer 14-1 is deposited on the insulating layer 15, and a conductive material layer 14-2 fills the remaining space. The columnar capacitor 90 can be interpreted as two capacitors corresponding to two first electrodes 13, which share a central second electrode 14.

[0159] Figure 32 A schematic diagram of a cup-shaped capacitor structure is shown. A first electrode 23 (e.g., TiN) is formed in a first hole 11, and the first hole 11 is filled with a sacrificial material (not shown, e.g., carbon) to (at least partially) cover the first electrode 23. The first electrodes 23 are arranged and recessed within the first hole 11 to establish a relatively uniform material layer within the first hole 11, but the first hole 11 can also be filled in a different manner. The first dielectric material layers 41-1, 41-2 and the second dielectric material layers 42-1, 42-2, 42-3 can be the same material. An isolation layer 15 (e.g., a high-k dielectric material) is then deposited in the first hole 11 on the first electrode 23. A second electrode 14 (e.g., TiN) is formed on the isolation layer 15. The second electrode 14 fills the first hole 11 and forms a layer on the isolation layer 15. The first electrode 23 is separated from the second electrode 14 by the isolation layer 15, thereby forming a cup-shaped capacitor 320. Due to the vertical geometry of the cup capacitor 320 and the high dielectric constant of the isolation layer 15, the cup capacitor 320 has higher quality, such as higher capacitance and / or reduced wafer area consumption, compared to planar capacitors and / or capacitors manufactured using other methods.

[0160] Furthermore, this disclosure also provides a memory system. The memory system includes at least one semiconductor device as described in any of the above embodiments, and a controller electrically connected to the semiconductor device. The controller is also connected to an external host, which can transmit user instructions and stored data to the controller. The user instructions may include write instructions, erase instructions, and read instructions, etc. The controller can determine which storage location in the semiconductor device to write, erase, and read based on these instructions.

[0161] For example, Figure 33 This is a block diagram of a memory system provided for an embodiment of this disclosure. The memory system 2100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory therein. Figure 33As shown, the memory system 2100 may include a host 2104 and a memory subsystem 2102. The memory subsystem 2102 includes one or more memories 2102B and a controller 2102A. The memories 2102B include an array of memory cells and multiple page buffers. The host 2104 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 2104 may be configured to send data to or receive data from the memories 2102B.

[0162] The semiconductor device disclosed herein is memory 2102B, or a portion thereof. According to some embodiments, controller 2102A is coupled to memory 2102B and host 2104 and is configured to control the memory. Controller 2102A can manage data stored in memory 2102B and communicate with host 2104. Controller 2102A can be configured to control operations of memory 2102B, such as read, erase, and program operations. Controller 2102A can also be configured to manage various functions relating to data stored or to be stored in memory 2102B, including but not limited to bad block management, garbage collection, logic-to-physical address translation, wear leveling, etc. In some embodiments, controller 2102A is also configured to process error correction codes (ECC) relating to data read from or written to memory 2102B. Controller 2102A can also perform any other suitable function, such as formatting memory 2102B. Controller 2102A can communicate with external devices (e.g., host 2104) according to a specific communication protocol. For example, controller 2102A can communicate with external devices through at least one of various interface protocols.

[0163] The controller 2102A and one or more memories 2102B can be integrated into various types of storage devices. That is, the storage subsystem 2102 can be implemented and packaged into different types of end electronic products.

[0164] Figure 34 This is a schematic diagram of a memory card provided according to an embodiment of the present disclosure. Figure 34 In one example shown, controller 2102A and a single memory 2102B can be integrated into memory card 2200. Memory card 2200 can include PC card, CF card, smart media (SM) card, memory stick, multimedia card, SD card, etc. Memory card 2200 can also include a connection between memory card 2200 and host computer (e.g., Figure 33 The memory card connector 2202 is coupled to the host 2104.

[0165] Figure 35 This is a schematic diagram of a solid-state drive (SSD) provided for an embodiment of this disclosure. (See diagram below.) Figure 35 As shown, controller 2102A and multiple memory units 2102B can be integrated into SSD 2300. SSD 2300 may also include components for connecting SSD 2300 to a host computer (e.g., ...). Figure 33 The SSD connector 2302 is coupled to the host 2104. In some embodiments, the storage capacity and / or operating speed of the SSD 2300 is greater than that of the memory card 2200.

[0166] The memory structure described above is merely an exemplary structure. Other types of memory, or memory structures, are also applicable to the operation methods of this disclosure.

Claims

1. A semiconductor device, characterized in that, Includes a first semiconductor structure; wherein, The first semiconductor structure includes a semiconductor body, a first memory structure, and a second memory structure; The semiconductor bodies extend along a first direction and are spaced apart along a second direction; Along the first direction, the semiconductor body is located between the first memory structure and the second memory structure, and the first memory structure and the second memory structure are staggered along the second direction; The semiconductor body includes a first semiconductor body and a second semiconductor body that are adjacent to each other along the second direction; The first semiconductor body is coupled to the first memory structure, and the second semiconductor body is coupled to the second memory structure; The first direction intersects with the second direction.

2. The semiconductor device according to claim 1, characterized in that, It also includes a second semiconductor structure and a third semiconductor structure; among which, The second semiconductor structure, the first semiconductor structure, and the third semiconductor structure are stacked sequentially along the first direction; The second semiconductor structure and the third semiconductor structure respectively include a first peripheral circuit and a second peripheral circuit; A portion of the semiconductor body in the first semiconductor structure is coupled to the first peripheral circuit; another portion of the semiconductor body in the first semiconductor structure is coupled to the second peripheral circuit.

3. The semiconductor device according to claim 2, characterized in that, The first storage structure is located between the first semiconductor body and the third semiconductor structure; The second memory structure is located between the second semiconductor body and the second semiconductor structure.

4. The semiconductor device according to claim 2, characterized in that, The first semiconductor structure further includes a first gate structure and a second gate structure; The first gate structure is coupled to the first peripheral circuit through a second contact structure; or, the second gate structure is coupled to the second peripheral circuit through a fourth contact structure.

5. The semiconductor device according to claim 1, characterized in that, The first semiconductor structure further includes a first conductive structure and a second conductive structure; Both the first conductive structure and the second conductive structure extend along a third direction, and the first conductive structure and the second conductive structure are arranged alternately along the second direction; The third direction intersects with the first direction and the second direction, respectively.

6. The semiconductor device according to claim 5, characterized in that, The first semiconductor body and the second semiconductor body respectively include a first end and a second end along the first direction; The first memory structure is coupled to a first end of the first semiconductor body; the second memory structure is coupled to a second end of the second semiconductor body. The first conductive structure is coupled to the second end of the first semiconductor body; the second conductive structure is coupled to the first end of the second semiconductor body.

7. The semiconductor device according to claim 6, characterized in that, Both the first memory structure and the second memory structure include a first electrode; The first end of the first semiconductor body is coupled to the first electrode of the first memory structure; The second end of the second semiconductor body is coupled to the first electrode of the second memory structure.

8. The semiconductor device according to claim 1, characterized in that, The first semiconductor structure further includes a gate structure that extends along the second direction and is spaced apart along a third direction; the third direction intersects the first direction and the second direction respectively. The gate structure includes a first gate structure and a second gate structure; Along the third direction, the first gate structure is located on at least one side of the first semiconductor body and coupled to the first semiconductor body; the second gate structure is located on at least one side of the second semiconductor body and coupled to the second semiconductor body.

9. The semiconductor device according to claim 8, characterized in that, Along the third direction, the first gate structure is located on both sides of the first semiconductor body, and the second gate structure is located on both sides of the second semiconductor body; The first semiconductor structure further includes: a separator structure located between adjacent first gate structures and between adjacent second gate structures.

10. A method for fabricating a semiconductor device, characterized in that, include: A first semiconductor structure is provided, wherein the first semiconductor structure includes a semiconductor body, a first memory structure, and a second memory structure; The semiconductor body extends along a first direction and is arranged along a second direction; along the first direction, the semiconductor body is located between the first memory structure and the second memory structure, and the first memory structure and the second memory structure are arranged alternately along the second direction; the semiconductor body includes a first semiconductor body and a second semiconductor body that are adjacent to each other along the second direction; The first semiconductor body is coupled to the first memory structure, and the second semiconductor body is coupled to the second memory structure; the first direction and the second direction intersect.

11. The method according to claim 10, characterized in that, Also includes: A second semiconductor structure and a third semiconductor structure are provided, such that the second semiconductor structure, the first semiconductor structure and the third semiconductor structure are stacked sequentially along the first direction; The second semiconductor structure and the third semiconductor structure respectively include a first peripheral circuit and a second peripheral circuit; a portion of the semiconductor body in the first semiconductor structure is coupled to the first peripheral circuit; and another portion of the semiconductor body in the first semiconductor structure is coupled to the second peripheral circuit.

12. The method according to claim 11, characterized in that, A first semiconductor structure is provided, comprising: A first gate structure and a second gate structure are provided, such that the first gate structure is coupled to the first peripheral circuit; or, the second gate structure is coupled to the second peripheral circuit.

13. The method according to claim 12, characterized in that, The first semiconductor structure is provided, and also includes: A third contact structure and a fourth contact structure are respectively formed to be coupled to the first gate structure and the second gate structure; The second semiconductor structure and the third semiconductor structure are provided, including: A third interconnection is formed that is coupled to the first peripheral circuit, such that the third interconnection is coupled to the third contact structure; A fourth interconnect is formed that is coupled to the second peripheral circuit, such that the fourth interconnect is coupled to the fourth contact structure.

14. The method according to claim 10, characterized in that, A first semiconductor structure is provided, comprising: A first semiconductor body and a second semiconductor body are formed extending along the first direction, and both the first semiconductor body and the second semiconductor body include opposing first ends and second ends along the first direction; A second conductive structure is formed that is coupled to a first end of the second semiconductor body; a first conductive structure is formed that is coupled to a second end of the first semiconductor body, wherein the first conductive structure and the second conductive structure both extend along a third direction, and the first conductive structure and the second conductive structure are staggered along the second direction, and the third direction intersects the first direction and the second direction respectively; A first memory structure coupled to a first end of the first semiconductor body is formed; a second memory structure coupled to a second end of the second semiconductor body is formed.

15. The method according to claim 10, characterized in that, A first semiconductor structure is provided, comprising: A substrate is provided, the substrate including a first surface and a second surface opposite to each other along the first direction; An isolation structure is formed in the substrate from a first surface of the substrate, the isolation structure extending along a third direction and spaced apart along the second direction, the third direction intersecting the first direction and the second direction respectively; A first gate structure and a second gate structure are formed in the substrate, both extending along the second direction and spaced apart along the third direction, so that the first semiconductor body and the second semiconductor body are formed in the substrate through the first gate structure, the second gate structure and the isolation structure, respectively.

16. The method according to claim 15, characterized in that, The first semiconductor body and the second semiconductor body respectively include a first end and a second end along the first direction; The first semiconductor structure also includes: A second conductive structure is formed that is coupled to a first end of the second semiconductor body; a first conductive structure is formed that is coupled to a second end of the first semiconductor body, wherein the first conductive structure and the second conductive structure both extend along a third direction, and the first conductive structure and the second conductive structure are arranged alternately along the second direction; A first memory structure coupled to a first end of the first semiconductor body is formed; a second memory structure coupled to a second end of the second semiconductor body is formed.

17. The method according to claim 15, characterized in that, The first gate structure and the second gate structure are respectively formed in the substrate, including: From a first surface of the substrate, word line trenches are formed in the substrate, the word line trenches extending along the second direction and spaced apart along the third direction; The first gate structure and the second gate structure are formed in the word line trench. The first gate structure is coupled to the first semiconductor body, and the second gate structure is coupled to the second semiconductor body. Both the first gate structure and the second gate structure include a first side and a second side that are opposite to each other along the first direction. The second side of the first gate structure and the second gate structure is exposed on the second surface of the substrate; A separation structure is formed, through which the first semiconductor body and the second semiconductor body are respectively formed in the substrate.

18. The method according to claim 17, characterized in that, Both the first gate structure and the second gate structure include a gate dielectric layer and a gate electrode; The formation of the first gate structure and the second gate structure in the word line trench includes: The gate dielectric layer is formed on the sidewall of the word line groove; The gate electrode is formed on the sidewall of the gate dielectric layer.

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