Semiconductor device and method of manufacturing the same, electronic device

Abstract

A semiconductor device, a preparation method thereof, and an electronic device. The semiconductor device comprises a plurality of memory cells, the plurality of memory cells comprising at least one first memory cell and at least one second memory cell; the first memory cell comprises a first transistor and a first capacitor, and the second memory cell comprises a second transistor and a second capacitor, the first transistor and the second transistor are both vertical channel transistors; the first capacitor comprises a first electrode and a shared electrode, and the second capacitor comprises a second electrode and the shared electrode, the first electrode, the shared electrode and the second electrode are arranged in sequence in a direction close to the substrate, and the shared electrode is configured as a common electrode of the first capacitor and the second capacitor. The present application relates to the technical field of semiconductor devices, and the semiconductor device, the preparation method thereof and the electronic device can effectively improve the storage density and production flexibility.

Description

Technical Field

[0001] This article relates to the field of semiconductor device technology, and in particular to a semiconductor device and its fabrication method, and electronic equipment. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking daily, while the types and number of devices contained in a single chip are increasing. This means that even minor differences in the manufacturing process can affect device performance. To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0003] This application provides a semiconductor device including a substrate and a plurality of memory cells disposed on the substrate. The plurality of memory cells include at least one first memory cell and at least one second memory cell, which are arranged in a one-to-one correspondence. The first memory cell is located on the side of the second memory cell away from the substrate. The first memory cell includes a first transistor and a first capacitor, and the second memory cell includes a second transistor and a second capacitor. Both the first transistor and the second transistor are vertical channel transistors. The first capacitor includes a first electrode and a shared electrode, and the second capacitor includes a second electrode and the shared electrode. The first electrode, the shared electrode, and the second electrode are arranged sequentially along a direction close to the substrate, and the shared electrode is configured as a common electrode of the first capacitor and the second capacitor.

[0004] In some exemplary embodiments, the first transistor includes a first semiconductor pillar extending in a direction perpendicular to the substrate, and the second transistor includes a second semiconductor pillar extending in a direction perpendicular to the substrate, wherein the materials of the first semiconductor pillar and the second semiconductor pillar both include oxide semiconductor materials.

[0005] In some exemplary embodiments, the first electrode is provided with a first groove facing the shared electrode; The shared electrode has one end disposed in the first groove in the direction perpendicular to the substrate, and the other end extends out of the first groove and has a second groove with a slot facing the second electrode. The second electrode is disposed within the second groove.

[0006] In some exemplary embodiments, the shared electrode includes a first shared electrode portion and a second shared electrode portion connected to each other. The first shared electrode portion is disposed in the first groove, and the second shared electrode portion is disposed outside the first groove and has a second groove with a slot facing the second electrode.

[0007] In some exemplary embodiments, the orthographic projection of the first electrode on the substrate overlaps with the orthographic projection of the second electrode on the substrate.

[0008] In some exemplary embodiments, the first capacitor further includes a first dielectric located between the first electrode and the shared electrode, wherein the first dielectric is configured as a groove with its opening facing the second electrode; The second capacitor further includes a second dielectric material located between the second electrode and the shared electrode, wherein the second dielectric material is configured as a groove with its opening facing away from the first electrode.

[0009] In some exemplary embodiments, the first memory cell is provided in a plurality of such cells, and the plurality of first memory cells are arranged at intervals along a first direction, the first direction being parallel to the substrate; The second storage unit is provided in multiple ways, and the multiple second storage units are arranged at intervals along the first direction; The semiconductor device further includes a plurality of first bit lines and a plurality of second bit lines, wherein the first bit lines and the second bit lines extend along the first direction and are spaced apart in a direction perpendicular to the substrate. A plurality of the first memory cells arranged along the first direction are connected to the same first bit line; A plurality of second memory cells arranged along the first direction are connected to the same second bit line.

[0010] In some exemplary embodiments, one end of the first transistor is connected to the first electrode of the first capacitor, and the other end is connected to the first bit line; One end of the second transistor is connected to the second electrode of the second capacitor, and the other end is connected to the second bit line.

[0011] In some exemplary embodiments, the first transistor further includes a first contact portion and a second contact portion, the first contact portion and the second contact portion being located at opposite ends of the first semiconductor pillar in a direction perpendicular to the substrate, the first semiconductor pillar being connected to the first electrode of the first capacitor through the first contact portion, and the first semiconductor pillar being connected to the first bit line through the second contact portion; The second transistor further includes a third contact portion and a fourth contact portion, which are respectively located at both ends of the second semiconductor pillar in the direction perpendicular to the substrate. The second semiconductor pillar is connected to the second electrode of the second capacitor through the third contact portion, and the second semiconductor pillar is connected to the second bit line through the fourth contact portion.

[0012] In some exemplary embodiments, the first contact portion and the second contact portion are configured as grooves with opposing slots, and the first contact portion and the second contact portion respectively cover the two ends of the first semiconductor pillar in the direction perpendicular to the substrate; The third contact portion and the fourth contact portion are configured as grooves with opposite openings, and the third contact portion and the fourth contact portion respectively cover the two ends of the second semiconductor pillar in the direction perpendicular to the substrate.

[0013] In some exemplary embodiments, the system further includes a plurality of first word lines and a plurality of second word lines extending along a second direction parallel to the substrate; The first storage unit is provided in multiple ways, and the multiple first storage units are arranged at intervals in the second direction; The second storage unit is provided in multiple units, and the multiple second storage units are arranged at intervals in the second direction; The first transistor further includes a first gate, which is insulatedly disposed on the outer periphery of the first semiconductor pillar; The second transistor further includes a second gate, which is insulatedly disposed on the outer periphery of the second semiconductor pillar; The first word line and the first gate of the first transistor of the plurality of first memory cells arranged along the second direction are integral structures; The second word line and the second gate of the second transistor of the plurality of second memory cells arranged along the second direction are integrally formed.

[0014] This application provides a method for fabricating a semiconductor device, including: A first dielectric thin film is deposited on a base substrate to form a first dielectric layer; Multiple conductive films are deposited on the first dielectric layer and each conductive film is patterned to form a first electrode, a shared electrode, and a second electrode arranged sequentially in a direction away from the first dielectric layer. A second transistor is formed on the side of the second electrode away from the base substrate; A substrate is covered on the side of the second transistor away from the base substrate to form an intermediate structure, and the intermediate structure is flipped over and the base substrate is removed. The first dielectric layer is located on the side of the first electrode away from the substrate. A first transistor is formed on the first dielectric layer.

[0015] In some exemplary embodiments, the step of depositing multiple conductive films on the first dielectric layer and patterning each conductive film to form a first electrode, a shared electrode, and a second electrode arranged sequentially in a direction away from the first dielectric layer includes: A third groove is etched on the first dielectric layer, the third groove penetrating the first dielectric layer; A first conductive film is deposited on the first dielectric layer, and the first conductive film is patterned to form a first electrode pattern. The first electrode pattern includes the first electrode, and the first electrode covers the groove wall of the third groove. A first insulating film is deposited to form a first insulating layer; A second conductive film is deposited, which covers the first insulating layer to form a first shared electrode portion, which fills the third groove. A second dielectric film is deposited, which covers the second conductive film to form a second dielectric layer; A fourth groove is etched on the second dielectric layer, the fourth groove penetrating the second dielectric layer in a direction perpendicular to the base substrate, and the orthographic projection of the fourth groove on the base substrate overlaps with the orthographic projection of the first electrode on the base substrate; A third conductive film is deposited, and the third conductive film is patterned to form a shared electrode pattern, the shared electrode pattern including a second shared electrode portion covering the groove wall of the fourth groove; A second insulating film is deposited to form a second insulating layer; A fourth conductive film is deposited in the fourth groove to form the second electrode, and the second electrode fills the fourth groove.

[0016] In some exemplary embodiments, forming a second transistor on the side of the second electrode away from the base substrate includes: Deposit at least one dielectric thin film to form a first intermediate dielectric layer; A first trench is etched on the first intermediate dielectric layer and a conductive thin film is deposited in the first trench to form a second gate and a second word line. Deposit at least one dielectric thin film to form a fifth dielectric layer; A first via is etched on the fifth dielectric layer. The first via penetrates the first intermediate dielectric layer and the fifth dielectric layer in a direction perpendicular to the base substrate. The orthogonal projection of the first via on the base substrate is located within the orthogonal projection of the second electrode on the base substrate. Semiconductor material is deposited within the first via to form a second semiconductor pillar.

[0017] In some exemplary embodiments, the deposition of at least one dielectric thin film to form a first intermediate dielectric layer includes: A third dielectric thin film is deposited to form a third dielectric layer; A fifth groove is etched on the third dielectric layer. The fifth groove penetrates the third dielectric layer in a direction perpendicular to the base substrate to expose the second electrode. The orthographic projection of the fifth groove on the base substrate is located within the orthographic projection of the second electrode on the base substrate. A fifth conductive film is deposited in the fifth groove, and the fifth conductive film covers the groove wall of the fifth groove to form a third contact portion; A fourth dielectric film is deposited, which covers the third contact and the third dielectric layer to form a fourth dielectric layer. The third dielectric layer and the fourth dielectric layer constitute the first intermediate dielectric layer.

[0018] In some exemplary embodiments, etching to form a first trench on the first intermediate dielectric layer and depositing a conductive thin film within the first trench to form a second gate and a second word line includes: The first trench is etched on the fourth dielectric layer to form the first trench. The orthographic projection of the first trench on the base substrate does not overlap with the orthographic projection of the second semiconductor pillar on the base substrate. The orthographic projection of the first trench on the base substrate is located on the outer periphery of the orthographic projection of the second semiconductor pillar on the base substrate. A conductive thin film is deposited in the first trench and fills the first trench to form the second gate and the second word line.

[0019] In some exemplary embodiments, the step of depositing semiconductor material within the first via to form a second semiconductor pillar includes: Semiconductor material is deposited in the first through-hole, and the semiconductor material fills the first through-hole to form a first pillar; A sixth annular groove is etched into the fifth dielectric layer, the sixth groove surrounding the first pillar; The end of the first pillar away from the base substrate is etched to form a first notch; A sixth conductive film is deposited in the sixth groove and the first notch to form a fourth contact portion.

[0020] In some exemplary embodiments, forming the second transistor on the side of the second electrode away from the base substrate further includes: A dielectric film is deposited on the fifth dielectric layer to form a first top dielectric layer; A second trench is etched on the first top dielectric layer, and the orthographic projection of the second trench on the base substrate overlaps with the orthographic projection of the second semiconductor pillar on the base substrate; A conductive thin film is deposited in the second trench to form a second bit line.

[0021] In some exemplary embodiments, forming the first transistor on the first dielectric layer includes: Thin the first dielectric layer to expose the end face of the first electrode away from the second electrode; Deposit at least one dielectric thin film to form a second intermediate dielectric layer; A third trench is etched on the second intermediate dielectric layer and a conductive thin film is deposited in the third trench to form a first gate and a first word line; Deposit the eighth dielectric thin film to form the eighth dielectric layer; A second via is etched on the eighth dielectric layer. The second via penetrates the second intermediate dielectric layer and the eighth dielectric layer in a direction perpendicular to the substrate. The orthogonal projection of the second via on the substrate is located within the orthogonal projection of the first electrode on the substrate. Semiconductor material is deposited in the second via to form a first semiconductor pillar.

[0022] In some exemplary embodiments, the deposition of at least one dielectric thin film to form a second intermediate dielectric layer includes: Deposit a sixth dielectric thin film to form a sixth dielectric layer; A seventh groove is etched on the sixth dielectric layer. The seventh groove penetrates the sixth dielectric layer in a direction perpendicular to the substrate to expose the first electrode. The orthogonal projection of the seventh groove on the substrate is located within the orthogonal projection of the first electrode on the substrate. A seventh conductive film is deposited in the seventh groove, and the seventh conductive film covers the groove wall of the seventh groove to form a second contact portion; A seventh dielectric film is deposited, which covers the second contact portion and the sixth dielectric layer to form a seventh dielectric layer. The sixth dielectric layer and the seventh dielectric layer constitute the second intermediate dielectric layer.

[0023] In some exemplary embodiments, the step of etching a third trench on the second intermediate dielectric layer and depositing a conductive thin film within the third trench to form a first gate and a first word line includes: A third trench is etched on the seventh dielectric layer. The orthographic projection of the third trench on the substrate does not overlap with the orthographic projection of the first semiconductor pillar on the base substrate. The orthographic projection of the third trench on the base substrate is located on the outer periphery of the orthographic projection of the first semiconductor pillar on the substrate. A conductive thin film is deposited in the third trench and the third trench is filled to form a first gate and a first word line.

[0024] In some exemplary embodiments, the step of depositing semiconductor material within the second via to form the first semiconductor pillar includes: Semiconductor material is deposited in the second via, and the semiconductor material fills the second via to form a second pillar; An annular eighth groove is etched in the second intermediate dielectric layer, the eighth groove surrounding the second pillar; The end of the second pillar furthest from the substrate is etched to form a second notch; An eighth conductive film is deposited in the eighth groove and the second notch to form a first contact portion.

[0025] In some exemplary embodiments, forming the first transistor on the first dielectric layer further includes: A dielectric film is deposited on the eighth dielectric layer to form a second top dielectric layer; A fourth trench is etched on the second top dielectric layer, and the orthographic projection of the fourth trench on the substrate overlaps with the orthographic projection of the first semiconductor pillar on the substrate; A conductive thin film is deposited in the fourth trench to form the first line.

[0026] This application provides an electronic device, including the semiconductor device described above, or a semiconductor device obtained by the method for preparing the semiconductor device described above.

[0027] The semiconductor device of this application embodiment has two memory cells (i.e., the first memory cell and the second memory cell) stacked in the direction perpendicular to the substrate, which have a common electrode (i.e., a shared electrode), and can effectively improve the storage density without increasing the storage area. The semiconductor device of this application embodiment uses an oxide semiconductor material as the channel material, which can reduce the thermal budget in the fabrication process of vertical channel transistors and increase the flexibility of the process.

[0028] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings. Attached Figure Description

[0029] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0030] Figure 1 A schematic diagram of a semiconductor device according to an exemplary embodiment of this invention; Figure 2 for Figure 1 Schematic diagram of the AA-direction section; Figure 3 for Figure 1 Schematic diagram of the BB-direction section in the middle; Figure 4 for Figure 2 A magnified view of part a in the diagram; Figure 5 for Figure 2 A magnified view of section b in the diagram; Figure 6 for Figure 2 A magnified view of part c in the diagram; Figure 7 This is a schematic diagram of a method for fabricating a semiconductor device according to an exemplary embodiment of the present invention; Figure 8 This is a first fabrication schematic diagram of a semiconductor device according to an exemplary embodiment of the present invention; Figure 9 This is a second fabrication schematic diagram of a semiconductor device according to an exemplary embodiment of the present invention; Figure 10 for Figure 9 Schematic diagram of the CC-direction section in the middle; Figure 11 This is a third fabrication schematic diagram of the semiconductor device according to this exemplary embodiment; Figure 12 This is a fourth fabrication schematic diagram of the semiconductor device according to this exemplary embodiment; Figure 13 This is a fifth fabrication schematic diagram of the semiconductor device according to this exemplary embodiment; Figure 14 This is a sixth fabrication schematic diagram of a semiconductor device according to this exemplary embodiment; Figure 15 This is a seventh fabrication schematic diagram of a semiconductor device according to an exemplary embodiment of the present invention; Figure 16 This is an eighth fabrication schematic diagram of a semiconductor device according to an exemplary embodiment of the present invention; Figure 17 This is a ninth fabrication schematic diagram of the semiconductor device according to this exemplary embodiment; Figure 18 A tenth fabrication schematic diagram of the semiconductor device according to this exemplary embodiment; Figure 19 This is an eleventh fabrication schematic diagram of the semiconductor device according to this exemplary embodiment; Figure 20 This is a schematic diagram illustrating the twelfth fabrication step of the semiconductor device according to this exemplary embodiment; Figure 21 This is a thirteenth schematic diagram of the fabrication of a semiconductor device according to this exemplary embodiment; Figure 22 for Figure 21 Schematic diagram of the DD-direction section; Figure 23 This is a fourteenth fabrication schematic diagram of the semiconductor device according to this exemplary embodiment; Figure 24 This is a fifteenth schematic diagram of the fabrication of a semiconductor device according to this exemplary embodiment; Figure 25 This is a sixteenth schematic diagram illustrating the fabrication of a semiconductor device according to this exemplary embodiment; Figure 26 This is a seventeenth fabrication schematic diagram of the semiconductor device according to this exemplary embodiment; Figure 27 This is an eighteenth fabrication schematic diagram of the semiconductor device according to this exemplary embodiment; Figure 28 This is a nineteenth schematic diagram illustrating the fabrication of a semiconductor device according to this exemplary embodiment; Figure 29 This is a twentieth schematic diagram illustrating the fabrication of a semiconductor device according to this exemplary embodiment; Figure 30 This is the twenty-first fabrication schematic diagram of the semiconductor device according to this exemplary embodiment; Figure 31 This is a twenty-second schematic diagram illustrating the fabrication of a semiconductor device according to this exemplary embodiment; Figure 32 This is a twenty-third schematic diagram illustrating the fabrication of a semiconductor device according to this exemplary embodiment; Figure 33 This is the twenty-fourth schematic diagram of the fabrication of a semiconductor device according to this exemplary embodiment; Figure 34 This is a twenty-fifth schematic diagram of the fabrication of a semiconductor device according to this exemplary embodiment; Figure 35 This is a twenty-sixth schematic diagram illustrating the fabrication of a semiconductor device according to this exemplary embodiment; Figure 36 This is the twenty-seventh schematic diagram of the fabrication of a semiconductor device according to this exemplary embodiment; Figure 37 This is a twenty-eighth schematic diagram of the fabrication of a semiconductor device according to this exemplary embodiment; Figure 38This is the twenty-ninth schematic diagram of the fabrication of a semiconductor device according to this exemplary embodiment; Figure 39 This is a thirtieth fabrication schematic diagram of the semiconductor device according to this exemplary embodiment; Figure 40 This is the thirty-first schematic diagram illustrating the fabrication of a semiconductor device according to this exemplary embodiment; Figure 41 This is the thirty-second schematic diagram of the fabrication of a semiconductor device according to this exemplary embodiment; Figure 42 This is the thirty-third schematic diagram illustrating the fabrication of a semiconductor device according to this exemplary embodiment; Figure 43 This is the thirty-fourth fabrication schematic diagram of a semiconductor device according to this exemplary embodiment; Figure 44 This is the thirty-fifth schematic diagram of the fabrication of a semiconductor device according to this exemplary embodiment. Detailed Implementation

[0031] This application describes several embodiments, but these descriptions are exemplary and not restrictive, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0032] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application can also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this application can be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes can be made within the scope of the appended claims.

[0033] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0034] With the continuous miniaturization of memory devices and the increasing density of storage, vertical channel transistors (VCTs) have seen significant development. The channel direction of a VCT is perpendicular to the substrate, allowing for higher integration density on a smaller chip area compared to traditional planar transistors. Silicon-based VCTs are a novel transistor structure based on silicon, featuring a vertical channel design that enables higher integration density and performance optimization. However, the applicant has found limitations in silicon-based VCTs. Their manufacturing process requires ion implantation, and the thermal annealing process of ion implantation results in a large thermal budget, which can even affect capacitor performance. Therefore, the vertical transistor is often fabricated first, followed by the capacitor, limiting the flexibility of the manufacturing process. Furthermore, to save area, capacitors are typically formed on top of the transistors, stacked vertically to form a 1T1C structure. However, this storage structure still cannot meet the ever-increasing demand for high storage density.

[0035] Figure 1 This is a schematic diagram of a semiconductor device according to an exemplary embodiment. Figure 2 for Figure 1 Schematic diagram of the AA-direction section. Figure 3 for Figure 1 The schematic diagram of the BB-direction section in this exemplary embodiment provides a semiconductor device, such as... Figures 1 to 3As shown, the semiconductor device includes a substrate 1 and a plurality of memory cells 2 disposed on the substrate 1. The plurality of memory cells 2 include at least one first memory cell 3 and at least one second memory cell 4, arranged in a one-to-one correspondence. The first memory cell 3 is located on the side of the second memory cell 4 away from the substrate 1. The first memory cell 3 includes a first transistor 5 and a first capacitor 6, and the second memory cell 4 includes a second transistor 8 and a second capacitor 7. Both the first transistor 5 and the second transistor 8 are vertical channel transistors. The first capacitor 6 includes a first electrode 18 and a shared electrode 20, and the second capacitor 7 includes a second electrode 21 and a shared electrode 20. The first electrode 18, the shared electrode 20, and the second electrode 21 are arranged sequentially along the direction close to the substrate 1, and the shared electrode 20 is configured as the common electrode of the first capacitor 6 and the second capacitor 7. Thus, in this exemplary embodiment of the semiconductor device, two memory cells have a common electrode, which effectively increases the storage density without increasing the storage area.

[0036] In some exemplary embodiments, such as Figures 1 to 3 As shown, both the first and second directions are parallel to the substrate 1. Multiple first storage cells 3 and multiple second storage cells 4 are present. The multiple first storage cells 3 are arranged in an array on the plane formed by the first and second directions. The multiple first storage cells 3 can be arranged at equal intervals along the first direction to form a row of first storage cells 3, or at equal intervals along the second direction to form a column of first storage cells 3. Similarly, the multiple second storage cells 4 are arranged in an array on the plane formed by the first and second directions. The multiple second storage cells 4 can be arranged at equal intervals along the first direction to form a row of second storage cells 4, or at equal intervals along the second direction to form a column of second storage cells 4. The multiple first storage cells 3 and multiple second storage cells 4 can be arranged one-to-one in a third direction (i.e., perpendicular to the substrate 1), meaning each first storage cell 3 can be connected to a second storage cell 4, and the first storage cell 3 is located on the side of the second storage cell 4 connected to it that is away from the substrate 1. The vertical channel transistor can be one in which the semiconductor material forming the channel is perpendicular to the substrate 1.

[0037] Figure 4 for Figure 2 A magnified view of part a in the diagram. Figure 5 for Figure 2 A magnified view of point b in the diagram. Figure 6 for Figure 2 A partially enlarged schematic diagram at point c in the diagram, as shown in some exemplary embodiments, such as Figure 2 , Figure 4 and Figure 5As shown, the first transistor 5 is located on the side of the first capacitor 6 away from the second memory cell 4, and the second transistor 8 is located on the side of the second capacitor 7 away from the first memory cell 3. The first transistor 5 includes a first semiconductor pillar 13 extending along a direction perpendicular to the substrate 1 (i.e., the third direction), and the second transistor 8 includes a second semiconductor pillar 23 extending along a direction perpendicular to the substrate 1. The materials of both the first semiconductor pillar 13 and the second semiconductor pillar 23 include oxide semiconductor materials. The oxide semiconductor material may include, but is not limited to, indium gallium zinc oxide (InGaZnO, i.e., IGZO), and may be any one or more of the following: indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (I Materials such as nWO3, IWO3, titanium dioxide (TiO2), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO) can be used, as long as the leakage current of the transistor meets the requirements. Specific adjustments can be made based on actual conditions. The transistor in this example uses oxide semiconductor materials as the channel material, which reduces the thermal budget in the fabrication of vertical channel transistors and increases the flexibility of the process.

[0038] In some exemplary embodiments, such as Figure 2 and Figure 5 As shown, the first capacitor 6 further includes a first dielectric 19, which may be located between the first electrode 18 and the shared electrode 20, such that the first electrode 18 and the shared electrode 20 do not contact each other. The second capacitor 8 further includes a second dielectric 22, which may be located between the second electrode 21 and the shared electrode 20, such that the second electrode 21 and the shared electrode 20 do not contact each other. The second dielectric 22 may be formed in a groove shape. The materials of the second dielectric 22 and the first dielectric 19 may include hafnium oxide (HfO2), but are not limited to this. For example, the materials of the second dielectric 22 and the first dielectric 19 may be other high dielectric constant materials.

[0039] In some exemplary embodiments, such as Figure 2 and Figure 5As shown, the first electrode 18 has a first groove 29 with its opening facing the shared electrode 20. The first electrode 18 may be groove-shaped, and the first electrode 18 surrounds the first groove 29. The first dielectric 19 may cover the side of the first electrode 18 away from the groove wall of the first groove 29, and the first dielectric 19 may be groove-shaped. The shared electrode 20 may include a first shared electrode portion 31 and a second shared electrode portion 34 that are connected. The first shared electrode portion 31 is disposed in the first groove 29 and covers the side of the first dielectric 19 away from the groove wall of the first groove 29. In some exemplary embodiments, adjacent first shared electrode portions 31 in a plurality of first storage cells 3 are connected. The second shared electrode portion 34 is disposed outside the first groove 29. The second shared electrode portion 34 is groove-shaped and surrounds a second groove 35, and the opening of the second groove 35 faces away from the first shared electrode portion 31. Thus, one end of the shared electrode 20 in the direction perpendicular to the substrate 1 (i.e., the third direction) is disposed in the first groove 29, and the other end extends out of the first groove 29 and has a second groove 35 with its opening facing the second electrode 21. The second dielectric 22 may cover the wall of the second groove 35, and the second electrode 21 is disposed within the second groove 35 and covers the side of the second dielectric 22 away from the wall of the second groove 35. The first electrode 18, the second electrode 21, and the shared electrode 20 are made of the same material and all include titanium nitride (TiN), but are not limited to this. For example, the first electrode 18, the second electrode 21, and the shared electrode 20 may be made of other metal materials. The first electrode 18, the shared electrode 20, and the second electrode 21 are arranged sequentially in a third direction, with the shared electrode 20 located between the first electrode 18 and the second electrode 21, and can serve as a common electrode.

[0040] In some exemplary embodiments, such as Figures 2 to 6As shown, the first transistor 5 further includes a first gate 14, a first gate insulating layer 15, a first contact portion 17, and a second contact portion 16. The first gate insulating layer 15 and the first gate 14 are disposed on the outer periphery of the first semiconductor pillar 13, with the first gate 14 located on the side of the first gate insulating layer 15 away from the first semiconductor pillar 13. The portion of the first semiconductor pillar 13 covered by the first gate insulating layer 15 forms the channel of the first transistor 5, and the two ends of the first semiconductor pillar 13 in a third direction respectively constitute the source and drain of the first transistor 5. The first contact portion 17 and the second contact portion 16 are respectively located at the two ends of the first semiconductor pillar 13 in a third direction. The first contact portion 17 covers the end of the first semiconductor pillar 13 away from the first capacitor 6, and the second contact portion 16 covers the end of the first semiconductor pillar 13 close to the first capacitor 6. The first semiconductor pillar 13 is connected to the first electrode 18 through the second contact portion 16. The material of the first gate 14 may include TiN or indium zinc oxide (IZO), but is not limited to these. For example, it may be any one or more of the following different types of materials: such as metals containing tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing the aforementioned metals; it may also be a metal oxide, metal nitride, metal silicide, metal carbide, etc., such as highly conductive metal oxide materials like indium tin oxide (ITO) and indium oxide (InO); such as metal nitride materials like tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN); of course, it may also be a polycrystalline silicon material; it may also be a conductive material doped with a semiconductor material, such as conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.; other materials that exhibit conductivity, etc. The material of the first gate insulating layer 15 may include one or more layers of High-K dielectric material, or Low-K dielectric material, or contain two or more regions with different dielectric constants K. Low-K materials, such as silicon oxide. High-K materials, such as dielectric materials with a dielectric constant K ≥ 3.9. In some embodiments, oxides of one or more of hafnium, aluminum, lanthanum, zirconium, etc., may be included. Exemplarily, for example, it may include, but is not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), etc. The materials of the first contact portion 17 and the second contact portion 16 may be the same and both include copper, but are not limited thereto; for example, other metallic materials may be used.

[0041] In some exemplary embodiments, such as Figures 2 to 6As shown, the second transistor 8 further includes a second gate 24, a second gate insulating layer 25, a third contact portion 39, and a fourth contact portion 49. The second gate insulating layer 25 and the second gate 24 are disposed on the outer periphery of the second semiconductor pillar 23, with the second gate 24 located on the side of the second gate insulating layer 25 away from the second semiconductor pillar 23. The portion of the second semiconductor pillar 23 covered by the second gate insulating layer 25 forms the channel of the second transistor 8, and the two ends of the second semiconductor pillar 23 in a third direction respectively constitute the source and drain of the second transistor 8. The third contact portion 39 and the fourth contact portion 49 are located at the two ends of the second semiconductor pillar 23 in a third direction, respectively. The third contact portion 39 covers the end of the second semiconductor pillar 23 near the second capacitor 7, and the fourth contact portion 49 covers the end of the second semiconductor pillar 23 away from the second capacitor 7. The second semiconductor pillar 23 is connected to the second electrode 21 through the third contact portion 39. The material of the second gate 24 may include TiN or indium zinc oxide (IZO), but is not limited to these. For example, it may be any one or more of the following different types of materials: such as metals containing tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing the aforementioned metals; it may also be a metal oxide, metal nitride, metal silicide, metal carbide, etc., such as highly conductive metal oxide materials like indium tin oxide (ITO) and indium oxide (InO); such as metal nitride materials like tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN); of course, it may also be a polycrystalline silicon material; it may also be a conductive material doped with a semiconductor material, such as conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.; other materials that exhibit conductivity, etc. The material of the second gate insulating layer 25 may contain one or more layers of High-K dielectric material, or Low-K dielectric material, or contain two or more regions with different dielectric constants K. Low-K materials, such as silicon oxide. High-K materials, such as dielectric materials with a dielectric constant K ≥ 3.9. In some embodiments, oxides of one or more of hafnium, aluminum, lanthanum, zirconium, etc., may be included. Exemplarily, for example, it may include, but is not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), etc. The materials of the third contact portion 39 and the fourth contact portion 49 may be the same and both include copper, but are not limited thereto; for example, they may be other metallic materials.

[0042] In some exemplary embodiments, such as Figures 2 to 6As shown, the semiconductor device also includes multiple first bit lines 9 and multiple second bit lines 11. Both the first bit lines 9 and the second bit lines 11 extend along a first direction. The multiple first bit lines 9 are spaced apart in a second direction, and the multiple second bit lines 11 are also spaced apart in the second direction. The first bit lines 9 and the second bit lines 11 correspond one-to-one, meaning each first bit line 9 has a second bit line 11 located on the side of the first bit line 9 closest to the substrate 1, and the orthographic projections of the first bit line 9 and the corresponding second bit line 11 on the substrate 1 overlap. One end of the first semiconductor pillar 13 is connected to the first bit line 9 via a second contact portion 16, and one end of the second semiconductor pillar 23 is connected to the second bit line 11 via a fourth contact portion 49. The materials of the first bit lines 9 and the second bit lines 11 may both include copper (Cu), but are not limited to this. For example, they may include any one or more of other metallic materials with similar properties, such as tungsten, molybdenum, and cobalt. They may also be single-layer or multi-layer structures, for example, a multi-layer structure formed of titanium (Ti), titanium nitride (TiN), and tungsten (W).

[0043] In some exemplary embodiments, such as Figures 2 to 6 As shown, the semiconductor device also includes a first word line 10 and a second word line 12 extending along a second direction. The first word line 10 may be formed by connecting the first gates 14 of the first transistors 5 of a plurality of first memory cells 3 arranged along the second direction, and the second word line 12 may be formed by connecting the second gates 24 of the second transistors 8 of a plurality of second memory cells 4 arranged along the second direction. The materials for the first letter 10 and the second letter 12 may include TiN or indium zinc oxide (IZO), but are not limited to these. For example, they may be any one or more of the following different types of materials: for example, containing metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; metal alloys containing the aforementioned metals; metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as highly conductive metal oxide materials like indium tin oxide (ITO) and indium oxide (InO); metal nitride materials such as tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN); of course, they may also be polycrystalline silicon; they may also be conductive materials doped with semiconductor materials, such as conductive doped silicon, conductive doped germanium, and conductive doped silicon-germanium; and other materials that exhibit conductivity.

[0044] Figure 7 This is a schematic diagram of a method for fabricating a semiconductor device according to an exemplary embodiment of the present invention, as shown below. Figure 7 As shown, a method for fabricating a semiconductor device can be applied to the fabrication of devices such as... Figures 1 to 6 The semiconductor device shown is fabricated using the following methods: S1: Deposit a first dielectric thin film on a base substrate to form a first dielectric layer.

[0045] Figure 8This is a first fabrication schematic diagram of a semiconductor device according to an exemplary embodiment. In some exemplary embodiments, such as Figure 8 As shown, a first dielectric thin film is deposited on a base substrate to form a first dielectric layer, comprising: A first dielectric film is deposited on a base substrate 26. The material of the first dielectric film may include silicon oxide (SiO2), but is not limited to it. For example, the material of the first dielectric film may include silicon nitride (SiN), etc. The first dielectric film forms a first dielectric layer 27, and the base substrate 26 may be parallel to the substrate 1.

[0046] S2: A third groove is formed by etching the first dielectric layer, and the third groove penetrates the first dielectric layer.

[0047] Figure 9 This is a second fabrication schematic diagram of the semiconductor device according to this exemplary embodiment. Figure 10 for Figure 9 The schematic diagram of the CC-direction section in some exemplary embodiments, such as Figure 9 and Figure 10 As shown, a third groove is etched in the first dielectric layer, the third groove penetrating the first dielectric layer, and includes: A plurality of third grooves 28 are etched into the first dielectric layer 27. The plurality of third grooves 28 are arranged in an array in the plane formed by the first direction and the second direction, for example, two third grooves 28 are arranged at intervals in the first direction. The third grooves 28 are recessed into the base substrate 26 from the end face away from the base substrate 26, and the third grooves 28 penetrate the first dielectric layer 27 in the direction perpendicular to the base substrate 26 (i.e., the third direction). The third grooves 28 can be rectangular grooves, but are not limited thereto; for example, the third grooves 28 can be circular grooves.

[0048] S3: Deposit a first conductive thin film on the first dielectric layer to form a first electrode.

[0049] Figure 11 This is a third schematic diagram of the fabrication of a semiconductor device according to an exemplary embodiment. In some exemplary embodiments, such as Figure 10 and Figure 11 As shown, a first conductive thin film is deposited on the first dielectric layer to form a first electrode, comprising: A first conductive film is deposited on the first dielectric layer 27 having a third groove 28. The material of the first conductive film may include titanium nitride (TiN), but is not limited to it; for example, the material of the first conductive film may be other metallic materials. The first conductive film may cover the first dielectric layer 27 and the groove wall of the third groove 28. The first conductive film covering the first dielectric layer 27 is then etched away, leaving the first conductive film covering the groove wall of the third groove 28, to form a first electrode 18. The first electrode 18 is groove-shaped, forming a first groove 29.

[0050] S4: Deposit the first insulating film to form the first insulating layer.

[0051] Figure 12 This is a fourth schematic diagram of the fabrication of a semiconductor device according to this exemplary embodiment. In some exemplary embodiments, such as Figure 11 and Figure 12 As shown, a first insulating film is deposited to form a first insulating layer, comprising: A first insulating film is deposited on the structure obtained in the above steps. The material of the first insulating film may include, but is not limited to, hafnium oxide (HfO2). For example, the material of the first insulating film may be other high dielectric constant materials. The first insulating film covers the first dielectric layer 27 and also covers the side face of the first electrode 18 facing away from the first dielectric layer 27 and the base substrate 26, forming a first insulating layer 30. The portion of the first insulating layer 30 covering the side face of the first electrode 18 facing away from the first dielectric layer 27 and the base substrate 26 constitutes the first dielectric 19.

[0052] S5: Deposit a second conductive thin film to form a first shared electrode portion.

[0053] Figure 13 This is a fifth schematic diagram of the fabrication of a semiconductor device according to an exemplary embodiment. In some exemplary embodiments, such as Figure 12 and Figure 13 As shown, a second conductive thin film is deposited to form a first shared electrode portion, including: A second conductive film is deposited on the structure obtained in the above steps. The second conductive film covers the first insulating layer 30 and fills the third groove 28, forming the first shared electrode portion 31. The material of the second conductive film may include titanium nitride (TiN), but is not limited to it. For example, the material of the second conductive film may be other metal materials. A planarization process is then performed so that the end face of the first shared electrode portion 31 away from the base substrate 26 is parallel to the base substrate 26.

[0054] S6: Deposit the second dielectric film to form the second dielectric layer.

[0055] Figure 14 This is a sixth schematic diagram of the fabrication of a semiconductor device according to an exemplary embodiment. In some exemplary embodiments, such as Figure 13 and Figure 14 As shown, a second dielectric thin film is deposited to form a second dielectric layer, comprising: A second dielectric film is deposited on the structure obtained in the above steps. The second dielectric film covers the end face of the first shared electrode portion 31 away from the base substrate 26, forming a second dielectric layer 32. The material of the second dielectric film may include silicon oxide (SiO2), but is not limited thereto. For example, the material of the second dielectric film may include silicon nitride (SiN), etc.

[0056] S7: The fourth groove is etched on the second dielectric layer.

[0057] In some exemplary embodiments, such as Figure 13 and Figure 14 As shown, a fourth groove is etched on the second dielectric layer, including: A fourth groove 33 is formed on the second dielectric layer 32. The fourth groove 33 penetrates the second dielectric layer 32 in a direction perpendicular to the base substrate 26 (i.e., the third direction). The orthogonal projection of the fourth groove 33 on the base substrate 26 overlaps with the orthogonal projection of the first electrode 18 on the base substrate 26.

[0058] S8: Deposit a third conductive film and perform a patterning process on the third conductive film to form a shared electrode pattern.

[0059] Figure 15 This is a seventh schematic diagram of the fabrication of a semiconductor device according to this exemplary embodiment. In some exemplary embodiments, such as Figure 14 and Figure 15 As shown, a third conductive film is deposited, and a patterning process is performed on the third conductive film to form a shared electrode pattern, including: A third conductive film is deposited on the structure obtained in the above steps, and the third conductive film is patterned to form a shared electrode pattern. The shared electrode pattern includes a second shared electrode portion 34 covering the trench wall of the fourth groove 33. The material of the third conductive film may include titanium nitride (TiN), but is not limited to this; for example, the material of the third conductive film may be other metallic materials. The second shared electrode portion 34 is groove-shaped and may surround a second groove 35. The second shared electrode portion 34 and the first shared electrode portion 31 together constitute the shared electrode 20.

[0060] S9: Deposit a second insulating film to form a second insulating layer.

[0061] Figure 16 This is an eighth schematic diagram of the fabrication of a semiconductor device according to this exemplary embodiment. In some exemplary embodiments, such as Figure 15 and Figure 16 As shown, a second insulating film is deposited to form a second insulating layer, comprising: A second insulating film is deposited on the structure obtained in the above steps. The second insulating film covers the second dielectric layer 32 and the second shared electrode portion 34 to form a second insulating layer 36. The material of the second insulating film may include hafnium oxide (HfO2), but is not limited to it. For example, the material of the second insulating film may be other high dielectric constant materials. The second insulating layer 36 includes a second dielectric 22 covering the second shared electrode portion 34.

[0062] S10: A fourth conductive film is deposited in the fourth groove to form a second electrode.

[0063] Figure 17 This is a ninth schematic diagram illustrating the fabrication of a semiconductor device according to this exemplary embodiment. In some exemplary embodiments, such as... Figure 16 and Figure 17 As shown, a fourth conductive thin film is deposited in the fourth groove to form a second electrode, including: A fourth conductive film is deposited on the structure obtained in the above steps, and a planarization process is performed so that the fourth groove 33 is filled with the fourth conductive film, forming the second electrode 21. The material of the fourth conductive film may include titanium nitride (TiN), but is not limited to this; for example, the material of the fourth conductive film may be other metallic materials.

[0064] S11: Deposit the third dielectric film to form the third dielectric layer.

[0065] Figure 18 This is a tenth schematic diagram of the fabrication of a semiconductor device according to this exemplary embodiment. In some exemplary embodiments, such as Figure 17 and Figure 18 As shown, a third dielectric thin film is deposited to form a third dielectric layer, comprising: A third dielectric film is deposited on the structure obtained in the above steps. The third dielectric film covers the second electrode 21 and the second dielectric layer 32 to form a third dielectric layer 37. The material of the third dielectric film may include silicon oxide (SiO2), but is not limited to it. For example, the material of the third dielectric film may include silicon nitride (SiN), etc.

[0066] S12: The fifth groove is etched on the third dielectric layer.

[0067] In some exemplary embodiments, such as Figure 17 and Figure 18 As shown, a fifth groove is etched into the third dielectric layer, including: A fifth groove 38 is etched into the third dielectric layer 37. The fifth groove 38 penetrates the third dielectric layer 37 in a direction perpendicular to the base substrate 26 (i.e., the third direction) to expose the second electrode 21. The orthogonal projection of the fifth groove 38 onto the base substrate 26 lies within the orthogonal projection of the second electrode 21 onto the base substrate 26.

[0068] S13: A third contact portion is formed within the fifth groove.

[0069] Figure 19 This is an eleventh schematic diagram of the fabrication of a semiconductor device according to this exemplary embodiment. In some exemplary embodiments, such as Figure 18 and Figure 19 As shown, a third contact portion is formed within the fifth groove, including: A fifth conductive film is deposited within the fifth groove 38, covering the groove wall of the fifth groove 38 to form a third contact portion 39. The material of the fifth conductive film may include copper (Cu), but is not limited to this; for example, the material of the fifth conductive film may include other metallic materials.

[0070] S14: Deposit the fourth dielectric film to form the fourth dielectric layer.

[0071] Figure 20 This is a schematic diagram illustrating the twelfth fabrication step of a semiconductor device according to an exemplary embodiment. In some exemplary embodiments, such as Figure 19 and Figure 20 As shown, a fourth dielectric thin film is deposited to form a fourth dielectric layer, comprising: A fourth dielectric film is deposited on the structure obtained in the above steps. The fourth dielectric film covers the third contact 39 and the third dielectric layer 37 to form a fourth dielectric layer 40. The third dielectric layer 37 and the fourth dielectric layer 40 constitute a first intermediate dielectric layer 41. The material of the fourth dielectric film may include silicon oxide (SiO2), but is not limited to it. For example, the material of the fourth dielectric film may include silicon nitride (SiN), etc.

[0072] S15: The first trench is formed by etching the first intermediate dielectric layer.

[0073] Figure 21 This is a thirteenth schematic diagram illustrating the fabrication of a semiconductor device according to this exemplary embodiment. Figure 22 for Figure 21 The schematic diagram of the DD-direction section in some exemplary embodiments, such as Figure 20 , Figure 21 and Figure 22 As shown, a first trench is formed by etching the first intermediate dielectric layer, including: A first trench 42 and a first protrusion 43 surrounded by the first trench 42 are etched on the fourth dielectric layer 40. The first trench 42 is configured to extend along a second direction, and the orthographic projection of the first protrusion 43 on the base substrate 26 overlaps with the orthographic projection of the third contact portion 39 on the base substrate 26.

[0074] S16: A second gate insulation layer is formed in the first trench.

[0075] Figure 23 This is a fourteenth schematic diagram of the fabrication of a semiconductor device according to this exemplary embodiment. In some exemplary embodiments, such as Figure 21 , Figure 22 and Figure 23 As shown, a second gate insulating layer is formed within the first trench, comprising: A gate insulating film is deposited around the outer periphery of the first protrusion 43, covering the sidewall of the first protrusion 43 to form a second gate insulating layer 25. The material of the gate insulating film may include one or more layers of High-K dielectric material, or Low-K dielectric material, or two or more regions containing different dielectric constants K. Low-K materials include, for example, silicon oxide. High-K materials include, for example, dielectric materials with a dielectric constant K ≥ 3.9. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, it may include, but is not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), etc., high-K materials.

[0076] S17: Forms the second gate and the second word line.

[0077] In some exemplary embodiments, such as Figure 21 , Figure 22 and Figure 23 As shown, forming the second gate and the second word line includes: A conductive thin film is deposited and fills the first trench 42. The conductive thin film covers the side of the second gate insulating layer 25 away from the first protrusion 43, forming the second gate 24 and the second word line 12. The material of the conductive thin film may include TiN or indium zinc oxide (IZO), but is not limited to these. For example, it may be any one or more of the following different types of materials: such as metals containing tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing the aforementioned metals; it may also be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as highly conductive metal oxide materials like indium tin oxide (ITO) and indium oxide (InO); such as metal nitride materials like tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN); of course, it may also be polycrystalline silicon; it may also be a conductive material doped with a semiconductor material, such as conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.; other materials exhibiting conductivity, etc.

[0078] S18: Forms the fifth dielectric layer.

[0079] Figure 24 This is a fifteenth schematic diagram of the fabrication of a semiconductor device according to this exemplary embodiment. In some exemplary embodiments, such as Figure 23 and Figure 24 As shown, a fifth dielectric layer is formed, including: A fifth dielectric film is deposited on the structure formed in the above steps to form a fifth dielectric layer 44, which covers the end face of the fourth dielectric layer 40 away from the base substrate 26. The material of the fifth dielectric film may include silicon oxide (SiO2), but is not limited to it. For example, the material of the fifth dielectric layer 44 may include silicon nitride (SiN), etc.

[0080] S19: The first via is formed by etching on the fifth dielectric layer.

[0081] In some exemplary embodiments, such as Figure 23 and Figure 24 As shown, a first via is formed by etching on the fifth dielectric layer, including: A first via 45 is etched on the first intermediate dielectric layer 41. The first via 45 penetrates the first intermediate dielectric layer 41 and the fifth dielectric layer 44 along a direction perpendicular to the base substrate 26 (i.e., the third direction). The orthogonal projection of the first via 45 on the base substrate 26 lies within the orthogonal projection of the second electrode 21 on the base substrate 26, exposing the third contact portion 39. Simultaneously, the end face of the second gate insulating layer 25 away from the second gate 10 is exposed. The first via 45 can be a rectangular hole, but is not limited to this; for example, it can be a circular hole, a diamond-shaped hole, etc.

[0082] S20: Deposit semiconductor material in the first through hole to form the first pillar.

[0083] Figure 25 This is a sixteenth schematic diagram of the fabrication of a semiconductor device according to this exemplary embodiment. In some exemplary embodiments, such as Figure 24 and Figure 25 As shown, a semiconductor material is deposited within the first via to form a first pillar, comprising: Semiconductor material is deposited within the first via 45, filling the via 45 to form a first pillar 46. The end face of the first pillar 46 furthest from the base substrate 26 is flush with the end face of the fifth dielectric layer 44. The semiconductor material may include, but is not limited to, indium gallium zinc oxide (InGaZnO, i.e., IGZO), and may be any one or more of the following: indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), and indium tungsten oxide (InW). Materials such as O, IWO, titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO) are all acceptable, as long as the leakage current of the transistor meets the requirements. Specific adjustments can be made based on the actual situation.

[0084] S21: A sixth annular groove is formed by etching the fifth dielectric layer.

[0085] Figure 26 This is a seventeenth schematic diagram of the fabrication of a semiconductor device according to this exemplary embodiment. In some exemplary embodiments, such as Figure 25 and Figure 26 As shown, a sixth annular groove is etched into the fifth dielectric layer, comprising: A sixth annular groove 47 is etched into the fifth dielectric layer 44. The sixth groove 47 is recessed from the fifth dielectric layer 44 into the base substrate 26 and surrounds the first pillar 46.

[0086] S22: Etch the first column to form the first notch.

[0087] Figure 27 This is an eighteenth fabrication schematic diagram of a semiconductor device according to this exemplary embodiment. In some exemplary embodiments, such as Figure 26 and Figure 27 As shown, the first column is etched to form the first notch, including: The end of the first pillar 46 furthest from the base substrate 26 is etched, causing this end to be recessed relative to the end of the fifth dielectric layer 44 furthest from the base substrate 26, forming a first notch 48. The first notch 48 can communicate with the sixth groove 47. After etching, the first pillar 46 forms the second semiconductor pillar 23.

[0088] S23: Formation of the fourth contact area.

[0089] Figure 28 This is a nineteenth schematic diagram of the fabrication of a semiconductor device according to this exemplary embodiment. In some exemplary embodiments, such as Figure 27 and Figure 28 As shown, a fourth contact portion is formed, including: A sixth conductive film is deposited within the sixth groove 47 and the first notch 48, filling both areas and being planarized. The sixth conductive film covers the end of the second semiconductor pillar 23 furthest from the base substrate 26, forming a fourth contact portion 49. The end of the fourth contact portion 49 furthest from the base substrate 26 may be flush with the end of the fifth dielectric layer 44 furthest from the base substrate 26. The material of the sixth conductive film may include copper (Cu), but is not limited to this; for example, the material of the sixth conductive film may include other metallic materials.

[0090] S24: Form the first top dielectric layer.

[0091] Figure 29 This is a twentieth schematic diagram of the fabrication of a semiconductor device according to this exemplary embodiment. In some exemplary embodiments, such as Figure 28 and Figure 29 As shown, a first top dielectric layer is formed, comprising: A dielectric film is deposited on the fifth dielectric layer 44, covering the fifth dielectric layer 44 and the fourth contact portion 49, to form a first top dielectric layer 50. The material of the dielectric film may include, but is not limited to, silicon oxide.

[0092] S25: A second trench is formed on the first top dielectric layer.

[0093] In some exemplary embodiments, such as Figure 28 and Figure 29 As shown, a second trench is formed on the first top dielectric layer, including: A second trench 51 is etched into the first top dielectric layer 50. The second trench 51 is configured to extend along a first direction, and the orthographic projection of the second trench onto the base substrate 26 overlaps with the orthographic projection of the second semiconductor pillar 23 onto the base substrate 26. The second trench 51 penetrates the first top dielectric layer 50 in a third direction, exposing the fourth contact portion 49.

[0094] S26: Form the second position line.

[0095] Figure 30 This is a twenty-first schematic diagram of the fabrication of a semiconductor device according to this exemplary embodiment. In some exemplary embodiments, such as Figure 29 and Figure 30 As shown, the second bit line 11 is formed, including: A conductive thin film is deposited in the second trench 51, filling the second trench 51 to form a second bit line 11, which contacts the fourth contact portion 49. The material of the conductive thin film may include copper (Cu), but is not limited to it. For example, it may include any one or more of other metal materials with similar properties such as tungsten, molybdenum, and cobalt. It may also be a single-layer or multi-layer structure, for example, a multi-layer structure formed of titanium (Ti), titanium nitride (TiN), and tungsten (W).

[0096] S27: Flip.

[0097] Figure 31 This is a twenty-second schematic diagram illustrating the fabrication of a semiconductor device according to this exemplary embodiment. Figure 32 This is a twenty-third schematic diagram of the fabrication of a semiconductor device according to this exemplary embodiment. In some exemplary embodiments, such as Figures 30 to 32 As shown, the flip includes: A substrate 1 is covered on the side of the second bit line 11 away from the base substrate 26 to form an intermediate structure. The intermediate structure includes the base substrate 26, the structure formed on the base substrate 26 in the above steps, and the substrate 1. Subsequently, the intermediate structure is flipped over, and the base substrate 26 is removed, so that the first dielectric layer 27 is located on the side away from the substrate 1.

[0098] S28: Thinning of the first dielectric layer.

[0099] In some exemplary embodiments, such as Figures 30 to 32 As shown, thinning the first dielectric layer includes: The end of the first dielectric layer 27 away from the substrate 1 is etched to expose the end face of the first electrode 18 away from the substrate 1.

[0100] S29: Deposit the sixth dielectric thin film to form the sixth dielectric layer.

[0101] Figure 33 This is a twenty-fourth schematic diagram of the fabrication of a semiconductor device according to this exemplary embodiment. In some exemplary embodiments, such as Figure 32 and Figure 33 As shown, a sixth dielectric thin film is deposited to form a sixth dielectric layer, comprising: A sixth dielectric film is deposited on the structure formed in the above steps. The sixth dielectric film covers the first dielectric layer 27 and the first electrode 18 to form a sixth dielectric layer 52. The material of the sixth dielectric film may include silicon oxide, but is not limited to it; for example, it may be silicon nitride.

[0102] S30: The seventh groove is formed by etching on the sixth dielectric layer.

[0103] In some exemplary embodiments, such as Figure 32 and Figure 33 As shown, a seventh groove is etched into the sixth dielectric layer, including: A seventh groove 53 is etched into the sixth dielectric layer 52. The seventh groove 53 penetrates the sixth dielectric layer 52 in a direction perpendicular to the substrate 1 (i.e., the third direction) to expose the first electrode 18. The orthogonal projection of the seventh groove 53 onto the substrate 1 lies within the orthogonal projection of the first electrode 18 onto the substrate 1.

[0104] S31: Forming the second contact area.

[0105] Figure 34 This is a twenty-fifth schematic diagram of the fabrication of a semiconductor device according to this exemplary embodiment. In some exemplary embodiments, such as Figure 33 and Figure 34 As shown, a second contact portion is formed, including: A seventh conductive film is deposited within the seventh groove 53, covering the groove wall of the seventh groove 53 to form the second contact portion 16. The material of the seventh conductive film may include copper (Cu), but is not limited to this; for example, the material of the seventh conductive film may include other metallic materials.

[0106] S32: Deposit the seventh dielectric thin film to form the seventh dielectric layer.

[0107] Figure 35 This is a twenty-sixth schematic diagram of the fabrication of a semiconductor device according to this exemplary embodiment. In some exemplary embodiments, such as Figure 34 and Figure 35 As shown, a seventh dielectric thin film is deposited to form a seventh dielectric layer, comprising: A seventh dielectric film is deposited on the structure obtained in the above steps. The seventh dielectric film covers the second contact portion 16 and the sixth dielectric layer 52 to form a seventh dielectric layer 55. The material of the seventh dielectric film may include silicon oxide (SiO2), but is not limited to it. For example, the material of the seventh dielectric film may include silicon nitride (SiN). The seventh dielectric layer 55 and the sixth dielectric layer 52 constitute a second intermediate dielectric layer.

[0108] S33: The third trench is formed by etching the seventh dielectric layer.

[0109] Figure 36 This is a twenty-seventh schematic diagram of the fabrication of a semiconductor device according to this exemplary embodiment. In some exemplary embodiments, such as Figure 35 and Figure 36 As shown, a third trench is formed by etching the seventh dielectric layer, including: A third trench 56 and a second protrusion 57 surrounded by the third trench 56 are etched on the seventh dielectric layer 55. The third trench 56 is configured to extend along the second direction, and the orthographic projection of the second protrusion 57 on the substrate 1 overlaps with the orthographic projection of the second contact portion 16 on the bottom 1.

[0110] S34: A first gate insulation layer is formed in the third trench.

[0111] Figure 37 This is a twenty-eighth schematic diagram of the fabrication of a semiconductor device according to this exemplary embodiment. In some exemplary embodiments, such as Figure 36 and Figure 37 As shown, a first gate insulating layer is formed within the third trench, comprising: A gate insulating film is deposited on the outer periphery of the second protrusion 57, covering the sidewall of the second protrusion 57 to form a first gate insulating layer 15. The gate insulating film may comprise one or more layers of High-K dielectric material, or Low-K dielectric material, or two or more regions comprising different dielectric constants K. Low-K materials include, for example, silicon oxide. High-K materials include, for example, dielectric materials with a dielectric constant K ≥ 3.9. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, it may include, but is not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), etc., high-K materials.

[0112] S35: Forms the first gate and the first word line.

[0113] In some exemplary embodiments, such as Figure 36 and Figure 37 As shown, a first gate and a first word line are formed, including: A conductive thin film is deposited and fills the third trench 56. The conductive thin film covers the side of the first gate insulating layer 15 away from the second protrusion 57, forming the first gate 14 and the first word line 10. The material of the conductive thin film may include TiN or indium zinc oxide (IZO), but is not limited to these. For example, it may be any one or more of the following different types of materials: such as metals containing tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing the aforementioned metals; it may also be a metal oxide, metal nitride, metal silicide, metal carbide, etc., such as indium tin oxide (ITO), indium oxide (InO), etc., which are highly conductive metal oxide materials; such as tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), etc.; of course, it may also be polycrystalline silicon; it may also be a conductive material doped with a semiconductor material, such as conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.; other materials that exhibit conductivity, etc.

[0114] S36: Form the eighth dielectric layer.

[0115] Figure 38 This is a twenty-ninth schematic diagram of the fabrication of a semiconductor device according to this exemplary embodiment. In some exemplary embodiments, such as Figure 37 and Figure 38 As shown, an eighth dielectric layer is formed, comprising: An eighth dielectric film is deposited on the structure formed in the above steps to form an eighth dielectric layer 59, which covers the end face of the seventh dielectric layer 55 away from the substrate 1. The material of the eighth dielectric film may include silicon oxide (SiO2), but is not limited to it. For example, the material of the eighth dielectric film may include silicon nitride (SiN), etc.

[0116] S37: Etch the second via on the eighth dielectric layer.

[0117] Figure 39 This is a thirtieth schematic diagram of the fabrication of a semiconductor device according to this exemplary embodiment. In some exemplary embodiments, such as Figure 38 and Figure 39 As shown, etching the second via on the eighth dielectric layer includes: A second via 58 is etched on the eighth dielectric layer 59. The second via 58 sequentially penetrates the eighth dielectric layer 59, the seventh dielectric layer 55, and the sixth dielectric layer 52 along a direction perpendicular to the substrate 1 (i.e., the third direction). The orthogonal projection of the second via 58 on the substrate 1 lies within the orthogonal projection of the first electrode 18 on the substrate 1, thus exposing the second contact portion 16. The second via 58 can be a rectangular hole, but is not limited to this; for example, it can be a circular hole, a diamond-shaped hole, etc.

[0118] S38: Deposit semiconductor material in the second through-hole to form a second pillar.

[0119] Figure 40 This is the thirty-first schematic diagram of the fabrication of a semiconductor device according to this exemplary embodiment. In some exemplary embodiments, such as Figure 39 and Figure 40 As shown, a semiconductor material is deposited within the second via to form a second pillar, comprising: Semiconductor material is deposited within the second via 58, filling the via 58 to form a second pillar 60. The end face of the second pillar 60 furthest from the substrate 1 is flush with the end face of the eighth dielectric layer 59. The semiconductor material may include, but is not limited to, indium gallium zinc oxide (InGaZnO, i.e., IGZO), and may be any one or more of the following: indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), and indium tungsten oxide (InW). Materials such as O, IWO, titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO) are all acceptable, as long as the leakage current of the transistor meets the requirements. Specific adjustments can be made based on the actual situation.

[0120] S39: An annular eighth groove is formed by etching the eighth dielectric layer.

[0121] Figure 41 This is a thirty-second schematic diagram of the fabrication of a semiconductor device according to this exemplary embodiment. In some exemplary embodiments, such as Figure 40 and Figure 41 As shown, an annular eighth groove is formed by etching the eighth dielectric layer, including: An annular eighth groove 61 is formed by etching the eighth dielectric layer 59. The eighth groove 61 is recessed from the eighth dielectric layer 59 toward the substrate 1, and the eighth groove 61 surrounds the second pillar 60 to form an annular eighth groove 61.

[0122] S40: Etch the second column to form the second notch.

[0123] Figure 42 This is a thirty-third schematic diagram of the fabrication of a semiconductor device according to this exemplary embodiment. In some exemplary embodiments, such as Figure 41 and Figure 42 As shown, the second pillar is etched to form the second notch, including: The end of the second pillar 60 furthest from the substrate 1 is etched, causing the end of the second pillar 60 furthest from the substrate 1 to be recessed relative to the end of the eighth dielectric layer 59 furthest from the substrate 1, forming a second notch 62. The second notch 62 can communicate with the eighth groove 61. After etching, the second pillar 60 forms the first semiconductor pillar 13.

[0124] S41: Form the first contact area.

[0125] Figure 43 This is the thirty-fourth schematic diagram of the fabrication of a semiconductor device according to this exemplary embodiment. In some exemplary embodiments, such as Figure 41 , Figure 42 and Figure 43 As shown, a first contact portion is formed, comprising: An eighth conductive film is deposited within the eighth groove 61 and the second notch 62, filling the eighth groove 61 and the second notch 62, and then planarized. The eighth conductive film covers the end of the second semiconductor pillar 23 away from the substrate 1, forming a first contact portion 17. The end of the first contact portion 17 away from the substrate 1 may be flush with the end of the eighth dielectric layer 59 away from the substrate 1. The material of the eighth conductive film may include copper (Cu), but is not limited to this; for example, the material of the eighth conductive film may include other metallic materials.

[0126] S42: Form the second top dielectric layer.

[0127] Figure 44 This is a thirty-fifth schematic diagram of the fabrication of a semiconductor device according to this exemplary embodiment. In some exemplary embodiments, such as Figure 43 and Figure 44 As shown, a second top dielectric layer is formed, comprising: A dielectric film is deposited on the eighth dielectric layer 59, covering the eighth dielectric layer 59 and the second contact 17 to form a second top dielectric layer 63. The material of the dielectric film may include, but is not limited to, silicon oxide.

[0128] S43: A fourth trench is formed on the second top dielectric layer.

[0129] In some exemplary embodiments, such as Figure 43 and Figure 44 As shown, a fourth trench is formed on the second top dielectric layer, including: A fourth trench 64 is etched into the second top dielectric layer 63. The fourth trench 64 is configured to extend along a first direction, and the orthographic projection of the fourth trench 64 onto the substrate 1 overlaps with the orthographic projection of the second semiconductor pillar 23 onto the substrate 1. The fourth trench 64 penetrates the second top dielectric layer 63 in a third direction, thereby exposing the first contact portion 17.

[0130] S44: Form the first line.

[0131] In some exemplary embodiments, such as Figure 44 and Figure 2 As shown, the first line is formed, including: A conductive thin film is deposited in the fourth trench 64, filling the fourth trench 64 to form a first line 99, which contacts the first contact portion 17. The material of the conductive thin film may include copper (Cu), but is not limited to this. For example, it may include any one or more of other metallic materials with similar properties such as tungsten, molybdenum, and cobalt. It may also be a single-layer or multi-layer structure, for example, a multi-layer structure formed of titanium (Ti), titanium nitride (TiN), and tungsten (W).

[0132] In some exemplary embodiments, an electronic device includes the aforementioned semiconductor device, or includes a semiconductor device obtained by the aforementioned semiconductor device fabrication method. The electronic device can be any electronic product with storage functionality, such as a storage device, smartphone, computer, tablet computer, artificial intelligence device, wearable device, or power bank.

[0133] In some exemplary embodiments, a method for fabricating a semiconductor device, include: A first dielectric thin film is deposited on a base substrate to form a first dielectric layer; Multiple conductive films are deposited on the first dielectric layer and each conductive film is patterned to form a first electrode, a shared electrode, and a second electrode arranged sequentially in a direction away from the first dielectric layer. A second transistor is formed on the side of the second electrode away from the base substrate; A substrate is covered on the side of the second transistor away from the base substrate to form an intermediate structure, and the intermediate structure is flipped over and the base substrate is removed. The first dielectric layer is located on the side of the first electrode away from the substrate. A first transistor is formed on the first dielectric layer.

[0134] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0135] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include at least one of those features.

[0136] In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.

[0137] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," "fixing," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0138] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0139] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0140] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A semiconductor device, characterized in that, The device includes a substrate and a plurality of memory cells disposed on the substrate. The plurality of memory cells include at least one first memory cell and at least one second memory cell. The at least one first memory cell and the at least one second memory cell are arranged in a one-to-one correspondence. The first memory cell is located on the side of the second memory cell away from the substrate. The first memory cell includes a first transistor and a first capacitor, and the second memory cell includes a second transistor and a second capacitor. Both the first transistor and the second transistor are vertical channel transistors. The first capacitor includes a first electrode and a shared electrode, and the second capacitor includes a second electrode and the shared electrode. The first electrode, the shared electrode, and the second electrode are arranged sequentially along a direction close to the substrate, and the shared electrode is configured as a common electrode of the first capacitor and the second capacitor.

2. The semiconductor device as claimed in claim 1, characterized in that, The first transistor includes a first semiconductor pillar extending in a direction perpendicular to the substrate, and the second transistor includes a second semiconductor pillar extending in a direction perpendicular to the substrate. Both the first semiconductor pillar and the second semiconductor pillar are made of oxide semiconductor material.

3. The semiconductor device as described in claim 2, characterized in that, The first electrode has a first groove with its opening facing the shared electrode; The shared electrode has one end disposed in the first groove in the direction perpendicular to the substrate, and the other end extends out of the first groove and has a second groove with a slot facing the second electrode. The second electrode is disposed within the second groove.

4. The semiconductor device as described in claim 3, characterized in that, The shared electrode includes a first shared electrode portion and a second shared electrode portion that are connected to each other. The first shared electrode portion is disposed in the first groove, and the second shared electrode portion is disposed outside the first groove and has a second groove with a slot facing the second electrode.

5. The semiconductor device as described in claim 3, characterized in that, The orthographic projection of the first electrode on the substrate overlaps with the orthographic projection of the second electrode on the substrate.

6. The semiconductor device as claimed in claim 3, characterized in that, The first capacitor further includes a first dielectric, which is located between the first electrode and the shared electrode, and the first dielectric is configured as a groove with the opening facing the second electrode; The second capacitor further includes a second dielectric material located between the second electrode and the shared electrode, wherein the second dielectric material is configured as a groove with its opening facing away from the first electrode.

7. The semiconductor device as claimed in claim 2, characterized in that, The first storage cell is provided in multiple ways, and the multiple first storage cells are arranged at intervals along a first direction, the first direction being parallel to the substrate; The second storage unit is provided in multiple ways, and the multiple second storage units are arranged at intervals along the first direction; The semiconductor device further includes a plurality of first bit lines and a plurality of second bit lines, wherein the first bit lines and the second bit lines extend along the first direction and are spaced apart in a direction perpendicular to the substrate. A plurality of the first memory cells arranged along the first direction are connected to the same first bit line; A plurality of second memory cells arranged along the first direction are connected to the same second bit line.

8. The semiconductor device as claimed in claim 7, characterized in that, One end of the first transistor is connected to the first electrode of the first capacitor, and the other end is connected to the first bit line; One end of the second transistor is connected to the second electrode of the second capacitor, and the other end is connected to the second bit line.

9. The semiconductor device as claimed in claim 8, characterized in that, The first transistor further includes a first contact portion and a second contact portion, the first contact portion and the second contact portion being located at opposite ends of the first semiconductor pillar in a direction perpendicular to the substrate, the first semiconductor pillar being connected to the first electrode of the first capacitor through the first contact portion, and the first semiconductor pillar being connected to the first bit line through the second contact portion; The second transistor further includes a third contact portion and a fourth contact portion, which are respectively located at both ends of the second semiconductor pillar in the direction perpendicular to the substrate. The second semiconductor pillar is connected to the second electrode of the second capacitor through the third contact portion, and the second semiconductor pillar is connected to the second bit line through the fourth contact portion.

10. The semiconductor device as claimed in claim 9, characterized in that, The first contact portion and the second contact portion are configured as grooves with opposite openings, and the first contact portion and the second contact portion respectively cover the two ends of the first semiconductor pillar in the direction perpendicular to the substrate; The third contact portion and the fourth contact portion are configured as grooves with opposite openings, and the third contact portion and the fourth contact portion respectively cover the two ends of the second semiconductor pillar in the direction perpendicular to the substrate.

11. The semiconductor device as claimed in claim 2, characterized in that, It also includes a plurality of first word lines and a plurality of second word lines extending along a second direction, the second direction being parallel to the substrate; The first storage unit is provided in multiple ways, and the multiple first storage units are arranged at intervals in the second direction; The second storage unit is provided in multiple units, and the multiple second storage units are arranged at intervals in the second direction; The first transistor further includes a first gate, which is insulatedly disposed on the outer periphery of the first semiconductor pillar; The second transistor further includes a second gate, which is insulatedly disposed on the outer periphery of the second semiconductor pillar; The first word line and the first gate of the first transistor of the plurality of first memory cells arranged along the second direction are integral structures; The second word line and the second gate of the second transistor of the plurality of second memory cells arranged along the second direction are integrally formed.

12. A method for fabricating a semiconductor device, characterized in that, include: A first dielectric thin film is deposited on a base substrate to form a first dielectric layer; Multiple conductive films are deposited on the first dielectric layer and each conductive film is patterned to form a first electrode, a shared electrode, and a second electrode arranged sequentially in a direction away from the first dielectric layer. A second transistor is formed on the side of the second electrode away from the base substrate; A substrate is covered on the side of the second transistor away from the base substrate to form an intermediate structure, and the intermediate structure is flipped over and the base substrate is removed. The first dielectric layer is located on the side of the first electrode away from the substrate. A first transistor is formed on the first dielectric layer.

13. The method for fabricating a semiconductor device as described in claim 12, characterized in that, The step of depositing multiple conductive films on the first dielectric layer and patterning each conductive film to form a first electrode, a shared electrode, and a second electrode arranged sequentially in a direction away from the first dielectric layer includes: A third groove is etched on the first dielectric layer, the third groove penetrating the first dielectric layer; A first conductive film is deposited on the first dielectric layer, and the first conductive film is patterned to form a first electrode pattern. The first electrode pattern includes the first electrode, and the first electrode covers the groove wall of the third groove. A first insulating film is deposited to form a first insulating layer; A second conductive film is deposited, which covers the first insulating layer to form a first shared electrode portion, which fills the third groove. A second dielectric film is deposited, which covers the second conductive film to form a second dielectric layer; A fourth groove is etched on the second dielectric layer, the fourth groove penetrating the second dielectric layer in a direction perpendicular to the base substrate, and the orthographic projection of the fourth groove on the base substrate overlaps with the orthographic projection of the first electrode on the base substrate; A third conductive film is deposited, and the third conductive film is patterned to form a shared electrode pattern, the shared electrode pattern including a second shared electrode portion covering the groove wall of the fourth groove; A second insulating film is deposited to form a second insulating layer; A fourth conductive film is deposited in the fourth groove to form the second electrode, and the second electrode fills the fourth groove.

14. The method for fabricating a semiconductor device as described in claim 13, characterized in that, A second transistor is formed on the side of the second electrode away from the base substrate, including: Deposit at least one dielectric thin film to form a first intermediate dielectric layer; A first trench is etched on the first intermediate dielectric layer and a conductive thin film is deposited in the first trench to form a second gate and a second word line. Deposit at least one dielectric thin film to form a fifth dielectric layer; A first via is etched on the fifth dielectric layer. The first via penetrates the first intermediate dielectric layer and the fifth dielectric layer in a direction perpendicular to the base substrate. The orthogonal projection of the first via on the base substrate is located within the orthogonal projection of the second electrode on the base substrate. Semiconductor material is deposited within the first via to form a second semiconductor pillar.

15. The method for fabricating a semiconductor device as described in claim 14, characterized in that, The deposition of at least one dielectric thin film to form a first intermediate dielectric layer includes: A third dielectric thin film is deposited to form a third dielectric layer; A fifth groove is etched on the third dielectric layer. The fifth groove penetrates the third dielectric layer in a direction perpendicular to the base substrate to expose the second electrode. The orthographic projection of the fifth groove on the base substrate is located within the orthographic projection of the second electrode on the base substrate. A fifth conductive film is deposited in the fifth groove, and the fifth conductive film covers the groove wall of the fifth groove to form a third contact portion; A fourth dielectric film is deposited, which covers the third contact and the third dielectric layer to form a fourth dielectric layer. The third dielectric layer and the fourth dielectric layer constitute the first intermediate dielectric layer.

16. The method for fabricating a semiconductor device as described in claim 15, characterized in that, The step of etching a first trench on the first intermediate dielectric layer and depositing a conductive thin film in the first trench to form a second gate and a second word line includes: A first trench is etched on the fourth dielectric layer, and the orthographic projection of the first trench on the base substrate does not overlap with the orthographic projection of the second semiconductor pillar on the base substrate. The orthographic projection of the first trench on the base substrate is located on the outer periphery of the orthographic projection of the second semiconductor pillar on the base substrate. A conductive thin film is deposited in the first trench and fills the first trench to form the second gate and the second word line.

17. The method for fabricating a semiconductor device as described in claim 14, characterized in that, The step of depositing semiconductor material in the first through-hole to form a second semiconductor pillar includes: A semiconductor material is deposited in the first through-hole, and the semiconductor material fills the first through-hole to form a first pillar; A sixth annular groove is etched into the fifth dielectric layer, the sixth groove surrounding the first pillar; The end of the first pillar away from the base substrate is etched to form a first notch; A sixth conductive film is deposited in the sixth groove and the first notch to form a fourth contact portion.

18. The method for fabricating a semiconductor device as described in claim 14, characterized in that, The method of forming a second transistor on the side of the second electrode away from the base substrate further includes: A dielectric film is deposited on the fifth dielectric layer to form a first top dielectric layer; A second trench is etched on the first top dielectric layer, and the orthographic projection of the second trench on the base substrate overlaps with the orthographic projection of the second semiconductor pillar on the base substrate; A conductive thin film is deposited in the second trench to form a second bit line.

19. The method for fabricating a semiconductor device as described in claim 12, characterized in that, The step of forming the first transistor on the first dielectric layer includes: Thin the first dielectric layer to expose the end face of the first electrode away from the second electrode; Deposit at least one dielectric thin film to form a second intermediate dielectric layer; A third trench is etched on the second intermediate dielectric layer and a conductive thin film is deposited in the third trench to form a first gate and a first word line; Deposit the eighth dielectric thin film to form the eighth dielectric layer; A second via is etched on the eighth dielectric layer. The second via penetrates the second intermediate dielectric layer and the eighth dielectric layer in a direction perpendicular to the substrate. The orthogonal projection of the second via on the substrate is located within the orthogonal projection of the first electrode on the substrate. Semiconductor material is deposited in the second via to form a first semiconductor pillar.

20. The method for fabricating a semiconductor device as described in claim 19, characterized in that, The deposition of at least one dielectric thin film to form a second intermediate dielectric layer includes: Deposit a sixth dielectric thin film to form a sixth dielectric layer; A seventh groove is etched on the sixth dielectric layer. The seventh groove penetrates the sixth dielectric layer in a direction perpendicular to the substrate to expose the first electrode. The orthogonal projection of the seventh groove on the substrate is located within the orthogonal projection of the first electrode on the substrate. A seventh conductive film is deposited in the seventh groove, and the seventh conductive film covers the groove wall of the seventh groove to form a second contact portion; A seventh dielectric film is deposited, which covers the second contact portion and the sixth dielectric layer to form a seventh dielectric layer. The sixth dielectric layer and the seventh dielectric layer constitute the second intermediate dielectric layer.

21. The method for fabricating a semiconductor device as described in claim 20, characterized in that, The step of etching a third trench on the second intermediate dielectric layer and depositing a conductive thin film in the third trench to form a first gate and a first word line includes: A third trench is etched on the seventh dielectric layer. The orthographic projection of the third trench on the substrate does not overlap with the orthographic projection of the first semiconductor pillar on the base substrate. The orthographic projection of the third trench on the base substrate is located on the outer periphery of the orthographic projection of the first semiconductor pillar on the substrate. A conductive thin film is deposited in the third trench and the third trench is filled to form a first gate and a first word line.

22. The method for fabricating a semiconductor device as described in claim 19, characterized in that, The step of depositing semiconductor material in the second via to form the first semiconductor pillar includes: Semiconductor material is deposited in the second via, and the semiconductor material fills the second via to form a second pillar; An annular eighth groove is etched in the second intermediate dielectric layer, the eighth groove surrounding the second pillar; The end of the second pillar furthest from the substrate is etched to form a second notch; An eighth conductive film is deposited in the eighth groove and the second notch to form a first contact portion.

23. The method for fabricating a semiconductor device as described in claim 21, characterized in that, The step of forming the first transistor on the first dielectric layer further includes: A dielectric film is deposited on the eighth dielectric layer to form a second top dielectric layer; A fourth trench is etched on the second top dielectric layer, and the orthographic projection of the fourth trench on the substrate overlaps with the orthographic projection of the first semiconductor pillar on the substrate; A conductive thin film is deposited in the fourth trench to form the first line.

24. An electronic device, characterized in that, It includes the semiconductor device as described in any one of claims 1 to 11, or the semiconductor device obtained by the method of preparing the semiconductor device as described in any one of claims 12 to 23.

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