Semiconductor device

Abstract

A semiconductor device is provided, including a bit line extending in a first direction; a semiconductor pattern spaced apart in the first direction and having one end in a second direction connected to the bit line; a word line extending in a third direction and located on one side in the first direction of each of the semiconductor patterns; and a data storage pattern connected to the other end in the second direction of each of the semiconductor patterns, wherein the bit line includes a core conductive layer and a first oxide semiconductor layer, the first oxide semiconductor layer being located between the core conductive layer and the semiconductor pattern and connected to the semiconductor pattern.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices. Background Technology

[0002] There is a need for a technique to improve the integration density of semiconductor devices. In the case of two-dimensional semiconductor devices, the integration density is primarily determined by the area occupied by a unit memory cell, and this aspect of integration can be affected by the level of fine patterning technology.

[0003] However, the use of fine patterning techniques requires expensive equipment, thus limiting the integration of two-dimensional semiconductor devices despite their increasing integration density. Therefore, a three-dimensional semiconductor memory device with memory cells arranged in three dimensions has been proposed. Summary of the Invention

[0004] The aspects of this disclosure can provide a semiconductor device with low leakage current, which can increase integration density and prevent semiconductor pattern degradation, thereby enhancing operational reliability. The contact area between the bit line and the semiconductor pattern can be increased, thereby reducing the contact resistance between the semiconductor pattern and the bit line, which can improve operating characteristics.

[0005] Embodiments of the present invention provide a semiconductor device comprising: bit lines extending in a first direction; semiconductor patterns spaced apart in the first direction and having one end of the bit lines connected in a second direction different from the first direction; word lines extending upward in a third direction different from the first and second directions and located on one side of each of the semiconductor patterns in the first direction; and data storage patterns connected to the other end of each of the semiconductor patterns in the second direction, wherein the bit lines include a core conductive layer and a first oxide semiconductor layer, the first oxide semiconductor layer being located between the core conductive layer and the semiconductor pattern and connected to the semiconductor pattern.

[0006] Embodiments of this disclosure provide a semiconductor device comprising: bit lines extending in a first direction; semiconductor patterns spaced apart in the first direction and having one end of the bit lines connected in a second direction different from the first direction; word lines extending upward in a third direction different from the first and second directions and located on one side of each of the semiconductor patterns in the first direction; a gate insulating layer located between each of the semiconductor patterns and the word lines, and including a gate insulating pattern layer positioned toward each of the semiconductor patterns and a gate insulating pad positioned toward the word lines; and a data storage pattern connected to the other end of each of the semiconductor patterns in the second direction, wherein the gate insulating pad has a first insulating pad portion located between the word lines and the gate insulating pattern layer and a second insulating pad portion located between the word lines and the data storage pattern.

[0007] Embodiments of this disclosure provide a semiconductor device comprising: a bit line extending in a first direction; a semiconductor structure having one end of the bit line connected in a second direction different from the first direction; a word line extending upward in a third direction different from the first and second directions and located on one side of the semiconductor structure in the first direction; and a data storage pattern connected to the other end of the semiconductor structure in the second direction, wherein the semiconductor structure includes a first portion and a second portion, the first portion overlapping the word line in the first direction, having a connection to the data storage pattern on the other side in the second direction and being spaced apart in the first direction, and the second portion extending in the first direction, connecting to the first portion, and located between the bit line and the first portion.

[0008] Embodiments of this disclosure provide a method for manufacturing a semiconductor device, the method comprising: forming a primary stack on a substrate by alternately stacking a sacrificial pattern and a primary semiconductor pattern, wherein a gate insulating pattern layer is interposed between the sacrificial pattern and the primary semiconductor pattern; forming a first electrode on one side of the primary semiconductor pattern; forming a dielectric layer on the first electrode; forming a second electrode on the dielectric layer to form a data storage pattern; removing the other side of the sacrificial pattern to expose the gate insulating pattern layer, and forming a gate insulating pad on the gate insulating pattern layer to form a gate insulating layer; forming a word line on the gate insulating pad; removing the primary semiconductor pattern and simultaneously forming a semiconductor pattern and a first oxide semiconductor layer; and forming a bit line by forming a core conductive layer on the first oxide semiconductor layer.

[0009] Semiconductor patterns can be formed in the space where the primary semiconductor pattern has been removed, and a first oxide semiconductor layer can be formed on one side of the gate insulating pattern layer and the gate insulating pad, and the first oxide semiconductor layer and the semiconductor pattern can be formed simultaneously in one process.

[0010] When a first oxide semiconductor layer connected to the semiconductor pattern is formed at the same time as the semiconductor pattern is formed, a recessed portion can be formed on the side of the first oxide semiconductor layer facing the core conductive layer, and the recessed portion can be recessed relative to the semiconductor pattern.

[0011] Forming bit lines may include forming a second oxide semiconductor layer on a first oxide semiconductor layer, and forming a core conductive layer on the second oxide semiconductor layer.

[0012] Forming a primary stack may include: alternately stacking a sacrificial layer and an active layer on a substrate, wherein a gate insulating patterning material layer is interposed between the sacrificial layer and the active layer; patterning the sacrificial layer, the active layer, and the gate insulating patterning material layer to form a first trench, the first trench extending in a second direction substantially parallel to the upper surface of the substrate and spaced apart in a third direction different from the second direction; configuring the remaining sacrificial layer as a first sacrificial pattern and configuring the remaining active layer as a first primary semiconductor pattern; forming a first primary fill pattern to fill the first trench; patterning the first sacrificial pattern, the first primary semiconductor pattern, and the gate insulating patterning material layer to form a second trench extending in a third direction and spaced apart in a second direction; configuring the remaining first primary semiconductor pattern as a second primary semiconductor pattern and configuring the remaining gate insulating patterning material layer as a gate insulating pattern layer; and forming a second primary fill pattern to fill the second trench.

[0013] Forming a data storage pattern may include: removing some of the second primary fill pattern to re-expose some of the second trench; removing one side of the first sacrificial pattern exposed by the second trench in a second direction; configuring the remaining first sacrificial pattern as the second sacrificial pattern; forming a first sacrificial insulating pattern in the space where the first sacrificial pattern was removed; forming a second sacrificial insulating pattern on the first sacrificial insulating pattern to fill the space where the first sacrificial pattern was removed; forming a third sacrificial insulating pattern on the first and second sacrificial insulating patterns to form a sacrificial insulating structure; removing one side of the first primary semiconductor pattern and the gate insulating pattern layer in a second direction; configuring the remaining first primary semiconductor pattern as the second primary semiconductor pattern; forming a first electrode in the space where the first primary semiconductor pattern and the gate insulating pattern layer were removed; removing the sacrificial insulating structure; forming a dielectric layer on the first electrode; and forming a second electrode on the dielectric layer and in the space where the sacrificial insulating structure was removed.

[0014] Forming a gate insulating layer may include: exposing a gate insulating pattern layer by removing a second sacrificial pattern on one side in the second direction; forming a gate insulating pad material layer on the gate insulating pattern layer; forming a cover material layer on the gate insulating pad material layer; forming a word line separation material layer on the cover material layer; forming a word line separation layer by removing a portion of the word line separation material layer formed on the other side in the second direction of the second primary semiconductor pattern and the gate insulating pattern layer; forming a cover pattern by exposing one end of the cover material layer in the second direction and removing a portion of the cover material layer from one end in the second direction; and forming a gate insulating pad by removing a portion of the gate insulating pad material layer formed on one side in the second direction of the primary semiconductor pattern and the gate insulating pattern layer.

[0015] Forming a word line may include: forming a primary gate conductive layer in the space where the cover material layer has been removed; removing a portion of the primary gate conductive layer formed on the other side of the second primary semiconductor pattern and the gate insulating pattern layer in the second direction to form a word line; and when removing a portion of the primary gate conductive layer, recessing the other end of the word line in the second direction to form a first spacer in the recessed space of the word line.

[0016] The semiconductor device according to the embodiments may have a semiconductor pattern including an oxide semiconductor material, which may have low leakage current and can increase integration density.

[0017] The gate insulating layer can prevent hydrogen permeation into the semiconductor pattern by including a gate insulating pattern layer and a gate insulating pad, thereby preventing semiconductor pattern degradation and improving operational reliability.

[0018] Bit lines, including those connected to a first oxide semiconductor layer of a semiconductor pattern, can enhance operational characteristics by increasing the contact area between the bit lines and the semiconductor pattern, thereby reducing the contact resistance between the semiconductor pattern and the bit lines.

[0019] Methods for manufacturing semiconductor devices according to other embodiments can form the main components through deposition processes instead of epitaxial growth processes, thereby potentially facilitating the manufacturing process of semiconductor devices.

[0020] By first forming the data storage pattern, then forming the word lines, and subsequently replacing the primary semiconductor pattern with the semiconductor pattern before forming the bit lines, chemical and thermal damage to the semiconductor pattern, including oxide semiconductor materials, can be minimized, and the characteristics of the semiconductor pattern can be improved.

[0021] Because a first oxide semiconductor layer that connects the bit lines to the semiconductor pattern is formed simultaneously with the semiconductor pattern, it can eliminate the disconnection defect between the semiconductor pattern and the bit lines. Attached Figure Description

[0022] Figure 1 This is a perspective view showing a semiconductor device according to an embodiment.

[0023] Figure 2 It is along Figure 1 A cross-sectional view taken from line A-A'.

[0024] Figure 3 It is along Figure 1 The cross-sectional view taken from lines B-B' and C-C'.

[0025] Figure 4 It is along Figure 1 The cross-sectional view taken by line D-D'.

[0026] Figure 5 It is Figure 2 An enlarged cross-sectional view of part P.

[0027] Figure 6 It is along Figure 1 The cross-sectional view taken by line A-A' corresponds to Figure 2 .

[0028] Figure 7 It is Figure 6 An enlarged cross-sectional view of the Q portion.

[0029] Figure 8 It is along Figure 1 The cross-sectional view taken by line A-A' corresponds to Figure 2 .

[0030] Figure 9 It is along Figure 1 The cross-sectional view taken by line D-D' corresponds to Figure 4 .

[0031] Figure 10 It is along Figure 1 The cross-sectional view taken by line A-A' corresponds to Figure 2 .

[0032] Figure 11 It is along Figure 1 The cross-sectional view taken by line A-A' corresponds to Figure 2 .

[0033] Figures 12 to 67 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment, arranged in process order. Detailed Implementation

[0034] In the following, various embodiments of this disclosure will be described in detail with reference to the accompanying drawings, enabling those skilled in the art to readily implement this disclosure. This disclosure may be implemented in many different forms and is not limited to the embodiments set forth herein.

[0035] The accompanying drawings and descriptions are to be considered illustrative rather than restrictive in nature. Throughout the specification, the same reference numerals denote the same elements.

[0036] The dimensions and thicknesses of each constituent element shown in the accompanying drawings are presented randomly for better understanding and ease of description, and this disclosure is not necessarily limited to those shown. In the drawings, the thicknesses of layers, regions, etc., are exaggerated for clarity. Furthermore, in the drawings, the thicknesses of some layers and regions are exaggerated for better understanding and ease of description.

[0037] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element, or there may be intermediate elements present. Conversely, when an element is referred to as being "directly on" another element, there are no intermediate elements present. The terms "on" or "above" mean placed on or below a part of an object, and do not necessarily mean placed on top of the part of the object based on the direction of gravity.

[0038] Furthermore, unless explicitly stated otherwise, the words “including” and variations such as “comprising” will be understood to mean that the said element is included but not excluded any other element.

[0039] Additionally, in this specification, the phrase "on a plane" means the target portion as viewed from above, and the phrase "on a cross section" means the cross section formed by vertically cutting the target portion as viewed from the side.

[0040] Furthermore, throughout the specification, the direction perpendicular to the upper surface of the substrate is described as the first direction D1, and the two directions parallel to the upper surface of the substrate and intersecting each other are described as the second direction D2 and the third direction D3, respectively. For example, the second direction D2 and the third direction D3 can be perpendicular to each other.

[0041] In the following text, see references Figures 1 to 5 The following describes a semiconductor device according to an embodiment.

[0042] Figure 1 This is a perspective view showing a semiconductor device according to an embodiment. Figure 2 It is along Figure 1 A cross-sectional view taken from line A-A'. Figure 3 It is along Figure 1 The cross-sectional view taken by lines B-B' and C-C'. Figure 4 It is along Figure 1 The cross-sectional view taken by line D-D'. Figure 5 It is Figure 2 An enlarged cross-sectional view of part P.

[0043] refer to Figures 1 to 5 The semiconductor device may include memory cells arranged in three dimensions. The memory cells may be arranged in a first direction D1, a second direction D2, and a third direction D3.

[0044] For example, memory cells can be stacked on the first direction D1. Figures 1 to 5 The diagram shows memory cells that are commonly connected to bit line BL and stacked in three layers on the first direction D1, but are not limited to this, as memory cells can be stacked in more layers.

[0045] Furthermore, the memory cells in each layer can be spaced apart in the second direction D2 and the third direction D3. For example, the memory cells can be arranged in a mirror-symmetric manner in the second direction D2. A memory cell and its mirror-symmetric memory cell can form a pair, and the memory cell pair can share the second electrode 330 of the data storage pattern DS, which will be described later.

[0046] Memory cells can be connected to bit lines BL and word lines WL. Bit lines BL can extend along a first direction D1. Individual bit lines BL can be commonly connected to memory cells stacked on the first direction D1. Bit lines BL can be spaced apart and arranged along a third direction D3. Word lines WL can extend along a third direction D3. Individual word lines WL can be commonly connected to memory cells arranged along a third direction D3. Word lines WL can be spaced apart and arranged along the first direction D1.

[0047] For example, the memory cells may be located on substrate 100. Substrate 100 may be, for example, a silicon substrate, a germanium substrate, a silicon-germanium substrate, an insulator substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate.

[0048] In some embodiments, peripheral circuitry for operating the memory cells may be located on the substrate 100. Furthermore, wiring connected to the bit line BL and word line WL may be located above the memory cells, and this wiring may be connected to the peripheral circuitry.

[0049] The bit line BL can be spaced apart from each other in the second direction D2 and the third direction D3, and can extend in the first direction D1. For example, the bit line BL can have a line shape or a column shape extending in the first direction D1.

[0050] Bit line BL may have two sides connected to semiconductor pattern 200 in a second direction D2, the semiconductor pattern 200 being spaced along a first direction D1 and located on both sides of bit line BL in the second direction D2. Bit line BL may be electrically connected to semiconductor pattern 200.

[0051] For example, bit line BL may include a core conductive layer 410 and a first oxide semiconductor layer 420.

[0052] The core conductive layer 410 may extend in the first direction D1. For example, the core conductive layer 410 may have a line shape or a column shape extending in the first direction D1. In addition, the shape of the core conductive layer 410 in the plane may be circular, but is not limited thereto. For example, the shape of the core conductive layer 410 in the plane may be a quadrilateral, a polygon with five or more corners, or an ellipse.

[0053] The core conductive layer 410 may include a conductive material. The conductive material may include, for example, a doped semiconductor material (such as doped silicon or doped germanium), a conductive metal nitride (such as titanium nitride or tantalum nitride), a metal (such as tungsten, titanium, or tantalum), a metal-semiconductor compound (such as tungsten silicide, cobalt silicide, or titanium silicide), or a combination thereof. For example, the core conductive layer 410 may include a core layer extending from a center in a first direction D1 and a barrier layer extending in the first direction D1 on the outer sidewall of the core layer. For example, the barrier layer may be interposed between the core layer and the first oxide semiconductor layer 420. For example, the core layer may include tungsten, and the barrier layer may include at least one of titanium and titanium nitride.

[0054] The first oxide semiconductor layer 420 may be located between the core conductive layer 410 and the semiconductor pattern 200. The first oxide semiconductor layer 420 may extend along the core conductive layer 410 in a first direction D1. The first oxide semiconductor layer 420 may conformally cover the side surface of the core conductive layer 410. In other words, the first oxide semiconductor layer 420 may be a thin film having a uniform thickness along the shape of the side surface of the core conductive layer 410.

[0055] For example, the first oxide semiconductor layer 420 may cover all sides of the core conductive layer 410. For example, the first oxide semiconductor layer 420 may have an annular shape that extends continuously in a plane around the core conductive layer 410. Furthermore, corresponding to the planar shape of the core conductive layer 410, the planar shape of the first oxide semiconductor layer 420 may be a quadrilateral ring, a polygonal ring with five or more corners, a circular ring, or an elliptical ring.

[0056] The first oxide semiconductor layer 420 may conformally cover one side of the semiconductor pattern 200, the gate insulating pattern layer 220 (described later), the gate insulating pad 280, the first spacer 140, and the word line separation layer 150 in the second direction D2.

[0057] The first oxide semiconductor layer 420 can be attached to one side of the semiconductor pattern 200 in the second direction D2. For example, the first oxide semiconductor layer 420 and the semiconductor pattern 200 can constitute a single unit. In other words, the first oxide semiconductor layer 420 and the semiconductor pattern 200 can be combined to form an integral unit.

[0058] As described below, when the primary semiconductor pattern 170 is replaced with the semiconductor pattern 200, a first oxide semiconductor layer 420 connected to the bit line BL of the semiconductor pattern 200 can be formed together. Since the first oxide semiconductor layer 420 and the semiconductor pattern 200 are formed simultaneously in a single process, they can constitute a single entity. In other words, the first oxide semiconductor layer 420 and the semiconductor pattern 200 can comprise oxide semiconductor materials having the same composition, and their boundaries may not be distinguishable.

[0059] Therefore, the disconnection defect between the semiconductor pattern 200 and the bit line BL can be eliminated. Furthermore, the contact area between the bit line BL and the semiconductor pattern 200 can be increased, thereby reducing the contact resistance between the semiconductor pattern 200 and the bit line BL, which can improve the operating characteristics of the semiconductor device.

[0060] The first oxide semiconductor layer 420 may include the same oxide semiconductor material as the semiconductor pattern 200. The oxide semiconductor material may include, but is not limited to, a combination of at least two of In, Ga, Zn, Al, Sn, and Hf. The oxide semiconductor material may further include materials such as Si, Mg, Ta, La, Nd, Ce, Sc, Cr, Co, Nb, Mo, Ba, Gd, Ti, W, Pd, Ru, Ni, or Mn in its composition. For example, the first oxide semiconductor layer 420 may include IGZO (indium gallium zinc oxide), Sn-IGZO (tin-doped indium gallium zinc oxide), ITZO (indium tin zinc oxide), IZO (indium zinc oxide), ZnO (zinc oxide), ZTO (zinc tin oxide), ZnON (zinc nitride oxide), ZZTO (zirconium zinc tin oxide), SnO (tin oxide), HIZO (hafnium indium zinc oxide), GZTO (gallium zinc tin oxide), AZTO (aluminum zinc tin oxide), YGZO (ytterbium gallium zinc oxide), IGO (indium gallium oxide), IWO (indium tungsten oxide), YZO (yttrium zinc oxide), or combinations thereof.

[0061] Bit line spacers can be positioned to space bit lines BL apart in a third direction D3. Bit line spacers can include an insulating material and can space and insulate the bit lines BL apart from each other in the third direction D3. For example, bit line spacers can include a silicon nitride layer, a silicon oxide nitride layer, a carbon-containing silicon oxide layer, a carbon-containing silicon nitride layer, a carbon-containing silicon oxide nitride layer, or a combination thereof.

[0062] In some embodiments, the bit line shielding structure can be positioned spaced apart between bit lines BL in the third direction D3. The bit lines BL and the bit line shielding structure can be spaced apart from each other along the third direction D3 and can be positioned alternately. For example, a bit line shielding structure can be positioned on each side of the bit line BL in the third direction D3. Bit line spacers can be located between the bit lines BL and the bit line shielding structure.

[0063] The word line WL may extend along a third direction D3. The word line WL may have a line shape extending along the third direction D3. The word line WL may include a first word line WL1 and a second word line WL2, the first word line WL1 passing below the semiconductor pattern 200 in the first direction D1, and the second word line WL2 passing above the semiconductor pattern 200 in the first direction D1. In other words, the first word line WL1 and the second word line WL2 may be spaced apart in the first direction D1, with the semiconductor pattern 200 interposed therebetween.

[0064] Each memory cell may include a first word line WL1, a semiconductor pattern 200, and a second word line WL2. When the memory cells are stacked in a first direction D1, the first word line WL1 of one semiconductor pattern 200 may be adjacent to the second word line WL2 of another semiconductor pattern 200 located below the first semiconductor pattern 200 in the first direction D1. In this case, the first word line WL1 of one semiconductor pattern 200 and the second word line WL2 of another semiconductor pattern 200 may be spaced apart in the first direction D1, and the word line separation layer 150, which will be described later, may be located between the first word line WL1 of one semiconductor pattern 200 and the second word line WL2 of another semiconductor pattern 200.

[0065] In some implementations, the word line WL may extend along a third direction D3, and in the region where it does not cross the semiconductor pattern 200, the first word line WL1 and the second word line WL2 may be combined. In this case, the word line WL may surround the semiconductor pattern 200 or a stack including the semiconductor pattern 200 and the gate insulating pattern layer 220, which will be described later.

[0066] The word line (WL) may include a conductive material. For example, a conductive material may include a semiconductor material, a conductive metal nitride, a metal, a metal-semiconductor compound, or a combination thereof.

[0067] The first spacer 140 may be located between the word line WL and the bit line BL. One end of the first spacer 140 in the second direction D2 may be connected to the bit line BL, and the other end of the first spacer 140 in the second direction D2 may be connected to the word line WL.

[0068] The first spacer 140 may include an insulating material and may space the bit line BL and the word line WL in the second direction D2 and insulate them from each other. For example, the first spacer 140 may include a silicon nitride layer, a silicon oxide nitride layer, a carbon-containing silicon oxide layer, a carbon-containing silicon nitride layer, a carbon-containing silicon oxide nitride layer, or a combination thereof.

[0069] The gate insulating layer Gox may be located between the word line WL and the semiconductor pattern 200. The gate insulating layer Gox may also be located between the first spacer 140 and the semiconductor pattern 200. The gate insulating layer Gox may also be located between the overlay pattern 145 described below and the semiconductor pattern 200.

[0070] In some embodiments, the gate insulating layer Gox may surround the word line WL and the first spacer 140. The gate insulating layer Gox may cover the upper, side, and lower sides of the word line WL. The gate insulating layer Gox may cover the upper and lower sides of the first spacer 140.

[0071] The gate insulating layer Gox may include a high-k layer, a silicon oxide layer, a silicon nitride layer, a silicon nitride layer, or a combination thereof. The high-k layer may include, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof.

[0072] The gate insulating layer Gox may include a gate insulating pattern layer 220 and a gate insulating pad 280.

[0073] The gate insulating pattern layer 220 is positioned toward the semiconductor pattern 200 in the first direction D1, and the gate insulating pad 280 may be positioned toward the word line WL in the first direction D1.

[0074] The gate insulating pattern layer 220 may be located on one or both sides of the semiconductor pattern 200 in the first direction D1. For example, the gate insulating layer Gox may include the gate insulating pattern layer 220, one of which is located on one side of the semiconductor pattern 200 in the first direction D1, and the other gate insulating pattern layer 220 may be located on the other side of the semiconductor pattern 200 in the first direction D1.

[0075] The gate insulating pattern layer 220 may extend in the second direction D2. One end of the gate insulating pattern layer 220 in the second direction D2 may be connected to the bit line BL. The other end of the gate insulating pattern layer 220 in the second direction D2 may be connected to the data storage pattern DS.

[0076] The length of the gate insulating pattern layer 220 in the third direction D3 can be equal to or greater than the length of the semiconductor pattern 200 in the third direction D3, and they can be substantially the same. In this case, the semiconductor pattern 200 can be inserted between two gate insulating pattern layers 220 spaced apart along the first direction D1, and the upper and lower surfaces of the semiconductor pattern 200 can be covered by the gate insulating pattern layer 220. At this time, both sides of the semiconductor pattern 200 in the third direction D3 can be exposed, and the exposed sides of the semiconductor pattern 200 in the third direction D3 can be covered by the gate insulating pad 280.

[0077] In some embodiments, the gate insulating pattern layer 220 may be located only on the upper or lower surface of the semiconductor pattern 200. In this case, the upper or lower surface of the semiconductor pattern 200 not covered by the gate insulating pattern layer 220 may be covered by the gate insulating pad 280.

[0078] The gate insulating pad 280 may be located on one or both sides of the semiconductor pattern 200 in the first direction D1 and on both sides in the third direction D3. Alternatively, the gate insulating pad 280 may be located on one side of the gate insulating pattern layer 220 in the first direction D1 and on both sides in the third direction D3. In other words, if the gate insulating layer Gox does not include the gate insulating pattern layer 220, the gate insulating pad 280 may cover the upper and lower surfaces of the semiconductor pattern 200; if the gate insulating pattern layer 220 is located only on the upper or lower surface of the semiconductor pattern 200, the gate insulating pad 280 may cover the upper or lower surface of the semiconductor pattern 200 and the upper or lower surface of the gate insulating pattern layer 220; and if the gate insulating pattern layer 220 is located on both the upper and lower surfaces of the semiconductor pattern 200, the gate insulating pad 280 may cover both the upper and lower surfaces of the gate insulating pattern layer 220. In any case, the gate insulating pad 280 may be located on both sides of the semiconductor pattern 200 and the gate insulating pattern layer 220 on the third-direction D3. In other words, the gate insulating pad 280 may surround the semiconductor pattern 200 or surround a stack including the semiconductor pattern 200 and the gate insulating pattern layer 220.

[0079] The gate insulating pad 280 may have a first insulating pad portion 281 and a second insulating pad portion 282.

[0080] The first insulating pad portion 281 may extend in the second direction D2. One end of the first insulating pad portion 281 in the second direction D2 may be connected to the bit line BL. The other end of the first insulating pad portion 281 in the second direction D2 may be connected to the data storage pattern DS.

[0081] The first insulating pad portion 281 may be located in the first direction D1 between the word line WL and the gate insulating pattern layer 220. The first insulating pad portion 281 may be located in the first direction D1 between the first spacer 140 and the gate insulating pattern layer 220. The first insulating pad portion 281 may be located in the first direction D1 between the overlay pattern 145 and the gate insulating pattern layer 220.

[0082] The first insulating pad portion 281 may be located between the first word line WL1 and the gate insulating pattern layer 220 in the first direction D1, and may also be located between the second word line WL2 and the gate insulating pattern layer 220. The first insulating pad portion 281 may also be located on both sides of the second insulating pad portion 282 in the first direction D1. In other words, the first insulating pad portion 281 located between the first word line WL1 and the gate insulating pattern layer 220, and the first insulating pad portion 281 located between the second word line WL2 and the gate insulating pattern layer 220, may be connected to both sides of a second insulating pad portion 282.

[0083] The first insulating pad portion 281 may extend along the word line WL in the third direction D3. The first insulating pad portion 281 may extend in the third direction D3 and may pass through the semiconductor pattern 200 and the gate insulating pattern layer 220 spaced apart in the third direction D3.

[0084] The second insulating pad portion 282 may extend in the first direction D1.

[0085] The second insulating pad portion 282 may be located in the second direction D2 between the word line WL and the data storage pattern DS. The second insulating pad portion 282 may be located in the second direction D2 between the word line separation layer 150 and the data storage pattern DS. The second insulating pad portion 282 may be located in the second direction D2 between the overlay pattern 145 and the data storage pattern DS.

[0086] The second insulating pad portion 282 may extend long along the letter line WL on the third direction D3.

[0087] For example, the length of the gate insulating pattern layer 220 in the first direction D1 can be greater than the length of the first insulating pad portion 281 of the gate insulating pad 280 in the first direction D1. In other words, the thickness of the gate insulating pattern layer 220 can be greater than the thickness of the first insulating pad portion 281.

[0088] In some embodiments, the gate insulating pad 280 may further have a third insulating pad portion 283. The third insulating pad portion 283 may be located between semiconductor patterns 200 spaced apart in a third direction D3. The third insulating pad portion 283 may extend in a first direction D1 and be connected to the first insulating pad portion 281.

[0089] The first insulating pad portion 281 may be located on one side of the gate insulating pattern layer 220 in the first direction D1. The third insulating pad portion 283 may be located on both sides of the semiconductor pattern 200 in the third direction D3. Alternatively, the third insulating pad portion 283 may be located on both sides of the gate insulating pattern layer 220 in the third direction D3. For example, the first insulating pad portion 281 and the third insulating pad portion 283 may surround the semiconductor pattern 200, or surround a stack including the semiconductor pattern 200 and the gate insulating pattern layer 220.

[0090] By including a gate insulating pattern layer 220 and a gate insulating pad 280, the gate insulating layer Gox can block hydrogen permeation into the semiconductor pattern 200, thereby preventing the semiconductor pattern 200 from deteriorating, which can enhance operational reliability.

[0091] A memory cell may include multiple layers, and a word line separation layer 150 may be located between any two adjacent layers of the memory cell. In other words, a memory cell includes a first word line WL1, a semiconductor pattern 200, and a second word line WL2. When memory cells are stacked in a first direction D1, the first word line WL1 of one semiconductor pattern 200 may be adjacent to the second word line WL2 of another semiconductor pattern located below the semiconductor pattern 200 in the first direction D1. In this case, the first word line WL1 of one semiconductor pattern 200 and the second word line WL2 of another semiconductor pattern may be spaced apart in the first direction D1, and the word line separation layer 150 may be located between the first word line WL1 of one semiconductor pattern 200 and the second word line WL2 of another semiconductor pattern.

[0092] The word line separation layer 150 can extend along the word line WL in the third direction D3.

[0093] One end of the word line separation layer 150 in the second direction D2 can be connected to the bit line BL. The other end of the word line separation layer 150 in the second direction D2 can be connected to the overlay pattern 145.

[0094] The word line separation layer 150 may include an insulating material, such as a silicon nitride layer, a silicon oxide nitride layer, a carbon-containing silicon oxide layer, a carbon-containing silicon nitride layer, or a carbon-containing silicon oxide nitride layer.

[0095] In some embodiments, the word line separation layer 150 may include a separation pad and a separation fill layer located between the separation pads. The separation pad may conformally cover one side of the first word line WL1 and the second word line WL2 located between memory cells in each layer in a first direction D1, and the separation fill layer may fill the space between the separation pads. The separation pad and the separation fill layer may each include an insulating material.

[0096] The overlay pattern 145 may be located on one or both sides of the semiconductor pattern 200 in the first direction D1. The overlay pattern 145 may be located on one or both sides of the gate insulating layer 220 in the first direction D1. The overlay pattern 145 may contact the gate insulating pad 280 in the first direction D1.

[0097] Overlay pattern 145 may be located in the second direction D2 between word line WL and data storage pattern DS. Overlay pattern 145 may also be located in the second direction D2 between word line separation layer 150 and data storage pattern DS.

[0098] The overlay pattern 145 may extend along the word line WL in the third direction D3. The overlay pattern 145 may extend along the word line separation layer 150 in the third direction D3.

[0099] For example, the overlay pattern 145 may have a first overlay portion 146 and a second overlay portion 147.

[0100] The first cover portion 146 may be located in the first direction D1 between the word line separation layer 150 and the first insulating pad portion 281 of the gate insulating pad 280.

[0101] The first cover portion 146 may extend in the second direction D2. The first cover portion 146 may be located in the second direction D2 between the word line WL and the data storage pattern DS. The first cover portion 146 may be located in the second direction D2 between the word line WL and the second insulating pad portion 282 of the gate insulating pad 280.

[0102] The first cover portion 146 may be located at one end of the first word line WL1 in the second direction D2, the first word line WL1 being below a semiconductor pattern 200 in the first direction D1. Additionally, the first cover portion 146 may be located at one end of the second word line WL2 in the second direction D2, the second word line WL2 being above another semiconductor pattern 200 positioned below the semiconductor pattern 200 in the first direction D1. In other words, the first cover portion 146 may be located in the second direction D2 between the first word line WL1 of one semiconductor pattern 200 and the second insulating pad portion 282, and the first cover portion 146 may be located in the second direction D2 between the second word line WL2 of another semiconductor pattern 200 and the second insulating pad portion 282.

[0103] For example, the length of the word line WL in the first direction D1 can be greater than the length of the first covering portion 146 in the first direction D1. In other words, the thickness of the word line WL can be greater than the thickness of the first covering portion 146.

[0104] Therefore, the length of the word line separating layer 150 in the first direction D1 can vary depending on its position in the second direction D2. For example, the length of the word line separating layer 150 located between the first word line WL1 and the second word line WL2 in the first direction D1 can be less than the length of the word line separating layer 150 located between the first covering portion 146 positioned at one end of the first word line WL1 in the second direction D2 and the first covering portion 146 positioned at one end of the second word line WL2 in the second direction D2 in the first direction D1.

[0105] The second cover portion 147 may extend in the first direction D1. The second cover portion 147 may be located in the second direction D2 between the word line separation layer 150 and the data storage pattern DS. The second cover portion 147 may be located in the second direction D2 between the word line separation layer 150 and the second insulating pad portion 282 of the gate insulating pad 280. In other words, one side of the second cover portion 147 in the second direction D2 may contact the word line separation layer 150. The other side of the second cover portion 147 in the second direction D2 may contact the second insulating pad portion 282.

[0106] The first covering portion 146 may be located on both sides of the second covering portion 147 in the first direction D1. In other words, the second covering portion 147 may connect the first covering portion 146 located at one end of the first word line WL1 of one semiconductor pattern 200 in the second direction D2 and the first covering portion 146 located at one end of the second word line WL2 of another semiconductor pattern 200 in the second direction D2.

[0107] The overlay pattern 145 may include an insulating material. The overlay pattern 145 may include, for example, a silicon oxide layer, a silicon oxide nitride layer, a silicon nitride layer, or a combination thereof.

[0108] Semiconductor pattern 200 can be located at each layer of the memory cell.

[0109] One end of the semiconductor pattern 200 in the second direction D2 can be connected to the bit line BL. The other end of the semiconductor pattern 200 in the second direction D2 can be connected to the data storage pattern DS.

[0110] The semiconductor patterns 200 may be spaced apart in a first direction D1 along the extension direction of the bit line BL. Additionally, the semiconductor patterns 200 may be spaced apart in a third direction D3 along the spacing direction of the bit line BL. For example, the semiconductor patterns 200 may have a longer length in the third direction D3 than their length in the first direction D1, and the semiconductor patterns 200 may have a larger spacing distance in the first direction D1 than their spacing distance in the third direction D3.

[0111] Semiconductor pattern 200 may be located between gate insulating pattern layers 220. Semiconductor pattern 200 may be surrounded by gate insulating pad 280. Semiconductor pattern 200 may be spaced apart from word lines WL, with gate insulating layer Gox interposed therebetween. Semiconductor pattern 200 may be located between first word line WL1 and second word line WL2.

[0112] At least a portion of the semiconductor pattern 200 may overlap with the word line WL in the first direction D1. At least a portion of the semiconductor pattern 200 may overlap with the first spacer 140 and the overlay pattern 145 in the first direction D1.

[0113] One side of the semiconductor pattern 200 in the second direction D2 can be connected to the first oxide semiconductor layer 420. For example, the first oxide semiconductor layer 420 and the semiconductor pattern 200 can constitute a single unit. In other words, the first oxide semiconductor layer 420 and the semiconductor pattern 200 can be combined to form an integral unit.

[0114] As described below, when the primary semiconductor pattern 170 is replaced with the semiconductor pattern 200, a first oxide semiconductor layer 420 connected to the semiconductor pattern 200 and the bit line BL can be formed together. Since the first oxide semiconductor layer 420 and the semiconductor pattern 200 are formed simultaneously in one process, they can constitute a single entity. In other words, the first oxide semiconductor layer 420 and the semiconductor pattern 200 can comprise oxide semiconductor materials with the same composition, and their boundaries may not be distinguishable.

[0115] As a result, breakage defects in the semiconductor pattern 200 and bit line BL can be eliminated. Furthermore, the increased contact area between the bit line BL and the semiconductor pattern 200 reduces the contact resistance between them, thereby improving the operating characteristics of the semiconductor device.

[0116] Semiconductor pattern 200 may include the same oxide semiconductor material as the first oxide semiconductor layer 420. The oxide semiconductor material may include, but is not limited to, a combination of at least two of In, Ga, Zn, Al, Sn, and Hf. The oxide semiconductor material may further include materials such as Si, Mg, Ta, La, Nd, Ce, Sc, Cr, Co, Nb, Mo, Ba, Gd, Ti, W, Pd, Ru, Ni, or Mn in its composition. For example, semiconductor pattern 200 may include IGZO (indium gallium zinc oxide), Sn-IGZO (tin-doped indium gallium zinc oxide), ITZO (indium tin zinc oxide), IZO (indium zinc oxide), ZnO (zinc oxide), ZTO (zinc tin oxide), ZnON (zinc nitride oxide), ZZTO (zirconium zinc tin oxide), SnO (tin oxide), HIZO (hafnium indium zinc oxide), GZTO (gallium zinc tin oxide), AZTO (aluminum zinc tin oxide), YGZO (ytterbium gallium zinc oxide), IGO (indium gallium oxide), IWO (indium tungsten oxide), YZO (yttrium zinc oxide), or combinations thereof.

[0117] In some embodiments, the semiconductor pattern 200 may have impurity regions and channel regions between the impurity regions. The impurity regions may correspond to the source / drain regions of a memory cell transistor. The impurity regions may be regions in the semiconductor pattern 200 that are doped with impurities. The impurity regions may have n-type or p-type conductivity. The impurity regions may be positioned adjacent to both ends of the semiconductor pattern 200 in the second direction D2.

[0118] The data storage pattern DS can be electrically connected to the semiconductor pattern 200. The data storage pattern DS is used as a memory element capable of storing data, such as a memory element utilizing a capacitor, a memory element utilizing a magnetic tunnel junction pattern, or a memory element utilizing a variable resistor including a phase change material.

[0119] For example, the data storage pattern DS can be a capacitor. The data storage pattern DS can include a first electrode 310 and a second electrode 330 spaced apart from the first electrode 310, and a dielectric layer 320 located between the first electrode 310 and the second electrode 330.

[0120] The first electrode 310 can be connected to one side of the semiconductor pattern 200 in the second direction D2, the dielectric layer 320 can cover the first electrode 310, and the second electrode 330 can cover the dielectric layer 320.

[0121] For example, in the second direction D2, one side of the first electrode 310 can be connected to one side of the semiconductor pattern 200. The dielectric layer 320 can conformally cover the other side of the first electrode 310 in the second direction D2, the upper and lower surfaces of the first electrode 310, and one and the other side of the first electrode 310 in the third direction D3. A second electrode 330 can cover the first electrode 310, with the dielectric layer 320 interposed therebetween. Alternatively, a second electrode 330 can integrally cover the first electrode 310, with the dielectric layer 320 interposed therebetween. Consequently, data storage patterns DS stacked in the first direction D1 can share a single second electrode 330.

[0122] A second spacer 340 may be filled between the data storage patterns DS. The second spacer 340 may cover the second electrode 330. For example, the second spacer 340 may fill the space defined by the second electrode 330. In other words, the second spacer 340 may fill the space between data storage patterns DS positioned spaced apart in each of the first direction D1, the second direction D2, and the third direction D3. In some embodiments, the space between the data storage patterns DS may be filled with the second electrode 330 instead of the second spacer 340.

[0123] Figures 1 to 5 The illustration shows a first electrode 310 with a cylindrical shape and an internal space filled. In some embodiments, the first electrode 310 may have a cylindrical shape with a hollow internal space. In this case, the dielectric layer 320 and the second electrode 330 may be located on the internal space of the first electrode 310, thereby further increasing the surface area of ​​the data storage pattern DS.

[0124] The first electrode 310 and the second electrode 330 may each include a metallic material such as titanium, tantalum, tungsten, copper or aluminum, a conductive metal nitride such as titanium nitride or tantalum nitride, or a doped semiconductor material such as silicon doped or germanium doped.

[0125] The dielectric layer 320 may include a dielectric, a ferroelectric, an antiferromagnetic, or a combination thereof. The dielectric may include a high-k material. For example, the dielectric may include hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof.

[0126] As described below, a semiconductor device according to one embodiment is manufactured by first forming a data storage pattern DS on one side of a primary semiconductor pattern 170, forming a word line WL on the other side of the primary semiconductor pattern 170, and then replacing the primary semiconductor pattern 170 with a semiconductor pattern 200 before forming a bit line BL.

[0127] Since the data storage pattern DS is formed before the word line WL, the semiconductor pattern 200, and the bit line BL, the gate insulating layer Gox may include a gate insulating pattern layer 220 positioned toward the semiconductor pattern 200 and a gate insulating pad 280 positioned toward the word line WL. Furthermore, the gate insulating pad 280 may have a first insulating pad portion 281 located between the word line WL and the gate insulating pattern layer 220, and a second insulating pad portion 282 located between the word line WL and the data storage pattern DS. Additionally, the cover pattern 145 may have a first cover portion 146 located between the word line separation layer 150 and the first insulating pad portion 281, and a second cover portion 147 located between the word line separation layer 150 and the second insulating pad portion 282.

[0128] In other words, when the data storage pattern DS is first formed, a second insulating pad portion 282 may be needed between the word line WL and the data storage pattern DS to ensure that the word line WL is spaced apart from the second electrode 330 of the data storage pattern DS. Furthermore, as described later, when the first word line WL1 and the second word line WL2 are formed by cutting the primary gate conductive layer PGL after its formation, a second cover portion 147 may be needed between the word line separation layer 150 and the second insulating pad portion 282 because the data storage pattern DS has already been formed and cutting of the primary gate conductive layer PGL is prevented.

[0129] The gate insulating layer Gox may include a gate insulating pattern layer 220 and a gate insulating pad 280 to prevent hydrogen from penetrating the semiconductor pattern 200, thereby preventing the semiconductor pattern 200 from deteriorating, which can improve operational reliability.

[0130] Furthermore, by first forming the data storage pattern DS, then forming the word line WL, and replacing the primary semiconductor pattern 170 with the semiconductor pattern 200 before forming the bit line BL, damage caused by chemicals and heat applied to the semiconductor pattern 200, which includes an oxide semiconductor material, can be minimized, and the characteristics of the semiconductor pattern 200 can be improved.

[0131] For example, when the primary semiconductor pattern 170 is first replaced with semiconductor pattern 200 and then word lines WL and bit lines BL are formed, the semiconductor pattern 200, including oxide semiconductor materials, may be damaged by chemicals, and exposure to heat may degrade the characteristics of the semiconductor pattern 200. For example, when the primary semiconductor pattern 170 is first replaced with semiconductor pattern 200, the semiconductor pattern 200 may be exposed to the outside more than seven times during the process of forming word lines WL and bit lines BL, and may be exposed to three main thermal processes, such as the step of forming gate insulating pad 280 (approximately 150°C), the step of forming word lines WL (300°C to 450°C), and the step of forming bit lines BL (300°C to 450°C).

[0132] On the other hand, if the word line WL is formed first and the primary semiconductor pattern 170 is replaced with a semiconductor pattern 200 before the bit line BL is formed, the semiconductor pattern 200 may be exposed to the outside only once in the process of forming the second oxide semiconductor layer 430, and may be exposed to heat treatment only once in the process of forming the bit line BL (300°C to 450°C).

[0133] Furthermore, when the primary semiconductor pattern 170 is replaced with the semiconductor pattern 200, a first oxide semiconductor layer 420 connected to the semiconductor pattern 200 is formed together with the bit line BL. Since the first oxide semiconductor layer 420 and the semiconductor pattern 200 are formed simultaneously in one process, they can constitute a single entity, thereby eliminating disconnection defects between the semiconductor pattern 200 and the bit line BL. Additionally, as the contact area between the bit line BL and the semiconductor pattern 200 increases, the contact resistance between them can be reduced, thereby improving operating characteristics.

[0134] In the following text, see references Figures 6 to 11 This will describe semiconductor devices according to various implementation methods.

[0135] Figure 6 It is along Figure 1 The cross-sectional view taken by line A-A' corresponds to Figure 2 . Figure 7 It is Figure 6 An enlarged cross-sectional view of the Q portion.

[0136] Figure 6 and Figure 7 The implementation methods shown are the same as Figures 1 to 5 The embodiments shown are essentially the same, therefore explanations of these parts will be omitted, and the differences will be explained primarily. Additionally, the same reference numerals are used for the same components as in the foregoing embodiments.

[0137] refer to Figure 6 and Figure 7 The first oxide semiconductor layer 420 of bit line BL may have a recessed portion 421 on the side facing the core conductive layer 410, and the recessed portion 421 may be recessed relative to the semiconductor pattern 200.

[0138] As described above, when the primary semiconductor pattern 170 is replaced with the semiconductor pattern 200, a first oxide semiconductor layer 420 connected to the semiconductor pattern 200 is formed together with the bit line BL.

[0139] The first oxide semiconductor layer 420 and the semiconductor pattern 200 of the bit line BL can be formed simultaneously in one process. For example, the first oxide semiconductor layer 420 and the semiconductor pattern 200 can be formed of an oxide semiconductor material that conformally covers the surface of the space exposed by the fifth internal region INR5 and the fourth trench TR4, which will be described later. In this case, the surface of the oxide semiconductor material exposed to the fourth trench TR4 at the corner where one side of the gate insulating pattern layer 220 in the second direction D2 meets one side in the first direction D1 (which is the part where the first oxide semiconductor layer 420 and the semiconductor pattern 200 are connected) can have a rounded shape in cross-section. Since the part where the first oxide semiconductor layer 420 and the semiconductor pattern 200 are connected can have a rounded shape in cross-section, the first oxide semiconductor layer 420 can have a recessed portion 421 at each corresponding position in the semiconductor pattern 200. The recessed portion 421 can have a size and shape corresponding to the size and shape on the second direction D2 and the third direction D3 of the semiconductor pattern 200.

[0140] Furthermore, when the semiconductor pattern 200 is formed by filling the fifth internal region INR5 with an oxide semiconductor material, the oxide semiconductor material is grown simultaneously from the lower surface of one gate insulating pattern layer 220 in the first direction D1 and from the upper surface of another gate insulating pattern layer 220 in the first direction D1. When it fills the fifth internal region INR5 and meets at approximately the midpoint of the fifth internal region INR5 in the first direction D1, the semiconductor pattern 200 can have an interface internally. The interface of the semiconductor pattern 200 extends in the second direction D2, and its ends can meet the recessed portion 421. However, this is not a limitation, because the semiconductor pattern 200 comprises the same material, the interface can be indistinguishable.

[0141] Furthermore, as described below, bit lines BL are formed after the formation of the first oxide semiconductor layer 420 by filling the empty spaces between the first oxide semiconductor layers 420 with the core conductive layer 410. Therefore, the core conductive layer 410 may have a first protrusion 411 protruding toward the recessed portion 421 of the first oxide semiconductor layer 420. The core conductive layer 410 may have a first protrusion 411 located at each corresponding position in the recessed portion 421 of the first oxide semiconductor layer 420. The first protrusion 411 may have a size and shape corresponding to the size and shape in the second direction D2 and the third direction D3 of the recessed portion 421.

[0142] By including the recessed portion 421, the first oxide semiconductor layer 420 is more smoothly connected to the semiconductor pattern 200, which can eliminate breakage defects between the semiconductor pattern 200 and the bit line BL. In addition, as the contact area between the bit line BL and the semiconductor pattern 200 increases, the contact resistance between the semiconductor pattern 200 and the bit line BL can be reduced, which can improve operating characteristics.

[0143] Simultaneously, as described below, after forming the first oxide semiconductor layer 420, a portion of the surface of the first oxide semiconductor layer 420 exposed to the fourth trench TR4 can be removed by a cleaning process. For example, the cleaning process can be performed to the extent of removing the recessed portion 421 of the first oxide semiconductor layer 420. When the recessed portion 421 is removed by the cleaning process, the length of the first oxide semiconductor layer 420 in the second direction D2 can be reduced, and as... Figure 2 As shown, the first oxide semiconductor layer 420 may not have the recessed portion 421. Furthermore, if a cleaning process is not performed, then as... Figure 6 As shown, the first oxide semiconductor layer 420 may have a recessed portion 421.

[0144] Figure 8 It is along Figure 1 The cross-sectional view taken by line A-A' corresponds to Figure 2 . Figure 9 It is along Figure 1 The cross-sectional view taken by line D-D' corresponds to Figure 4 .

[0145] Figure 8 and Figure 9 The implementation methods shown are the same as Figures 1 to 5 The embodiments shown are essentially the same, therefore explanations of these parts will be omitted, and the differences will be explained primarily. Additionally, the same reference numerals are used for the same components as in the foregoing embodiments.

[0146] Figure 8 and Figure 9The bit line BL is shown to further include a second oxide semiconductor layer 430.

[0147] The second oxide semiconductor layer 430 may be located between the core conductive layer 410 and the first oxide semiconductor layer 420. The second oxide semiconductor layer 430 may extend along the core conductive layer 410 in a first direction D1. The second oxide semiconductor layer 430 may conformally cover the side surface of the core conductive layer 410. For example, the second oxide semiconductor layer 430 may have an annular shape that extends continuously in a plane around the core conductive layer 410. Moreover, corresponding to the planar shape of the core conductive layer 410, the planar shape of the second oxide semiconductor layer 430 may be a quadrilateral ring, a polygonal ring with five or more corners, a circular ring, or an elliptical ring.

[0148] The second oxide semiconductor layer 430 may include an oxide semiconductor material. The oxide semiconductor material may include, but is not limited to, a combination of at least two of In, Ga, Zn, Al, Sn, and Hf. The oxide semiconductor material may further include materials such as Si, Mg, Ta, La, Nd, Ce, Sc, Cr, Co, Nb, Mo, Ba, Gd, Ti, W, Pd, Ru, Ni, or Mn in its composition. For example, the second oxide semiconductor layer 430 may include IGZO (indium gallium zinc oxide), Sn-IGZO (tin-doped indium gallium zinc oxide), ITZO (indium tin zinc oxide), IZO (indium zinc oxide), ZnO (zinc oxide), ZTO (zinc tin oxide), ZnON (zinc nitride oxide), ZZTO (zirconium zinc tin oxide), SnO (tin oxide), HIZO (hafnium indium zinc oxide), GZTO (gallium zinc tin oxide), AZTO (aluminum zinc tin oxide), YGZO (ytterbium gallium zinc oxide), IGO (indium gallium oxide), IWO (indium tungsten oxide), YZO (yttrium zinc oxide), or combinations thereof.

[0149] However, unlike the first oxide semiconductor layer 420, the second oxide semiconductor layer 430 is not formed together with the first oxide semiconductor layer 420 and the semiconductor pattern 200, but is formed separately in a different process. Therefore, the second oxide semiconductor layer 430 may include an oxide semiconductor material different from the first oxide semiconductor layer 420 and the semiconductor pattern 200. The core conductive layer 410 may be spaced apart from the first oxide semiconductor layer 420 and the semiconductor pattern 200, with the second oxide semiconductor layer 430 interposed therebetween.

[0150] In some embodiments, when the first oxide semiconductor layer 420 is as Figure 6When the recessed portion 421 is shown, the second oxide semiconductor layer 430 may have a second protrusion 431 protruding toward the recessed portion 421 of the first oxide semiconductor layer 420. In this case, the first oxide semiconductor layer 420 may have a recessed portion 421 on the side facing the second oxide semiconductor layer 430. The recessed portion 421 may be recessed relative to the semiconductor pattern 200. The second oxide semiconductor layer 430 may have a second protrusion 431 at a position corresponding to each recessed portion 421 of the first oxide semiconductor layer 420. The second protrusion 431 may have a size and shape corresponding to the size and shape in the second direction D2 and the third direction D3 of the recessed portion 421. In other embodiments, the side of the first oxide semiconductor layer 420 facing the core conductive layer 410 may have, as shown in other embodiments, a second protrusion 431 protruding toward the first oxide semiconductor layer 420. Figure 2 The flat surface shown in the figure, in this case, the second oxide semiconductor layer 430 may have a flat surface to correspond to the flat surface of the first oxide semiconductor layer 420.

[0151] Figure 10 Is with Figure 2 Corresponding, along Figure 1 A cross-sectional view taken from line A-A'.

[0152] Figure 10 The implementation methods shown are the same as Figures 1 to 5 The embodiments shown are essentially the same, therefore explanations of these parts will be omitted, and the differences will be explained primarily. Additionally, the same reference numerals are used for the same components as in the foregoing embodiments.

[0153] exist Figure 2 In this diagram, since the first oxide semiconductor layer 420 and the semiconductor pattern 200 of the bit line BL are formed simultaneously in one process, the first oxide semiconductor layer 420 and the semiconductor pattern 200 constitute a single entity. In other words, the first oxide semiconductor layer 420 and the semiconductor pattern 200 may comprise oxide semiconductor materials having the same composition, and their boundaries may be indistinguishable.

[0154] exist Figure 10 The diagram illustrates the boundary between the first oxide semiconductor layer 420 and the semiconductor pattern 200. In this case, the first oxide semiconductor layer 420 is not formed together with the semiconductor pattern 200 and can be formed separately in a different process. The core conductive layer 410 may be spaced apart from the semiconductor pattern 200, and the first oxide semiconductor layer 420 is interposed therebetween. The first oxide semiconductor layer 420 of the bit line BL may not have a recessed portion 421 that is recessed relative to the semiconductor pattern 200 on the side facing the core conductive layer 410.

[0155] At this time, the first oxide semiconductor layer 420 may include an oxide semiconductor material different from the semiconductor pattern 200. However, it is not limited to this, and in this case, the first oxide semiconductor layer 420 may also include the same oxide semiconductor material as the semiconductor pattern 200.

[0156] Figure 11 It is along Figure 1 The cross-sectional view taken by line A-A' corresponds to Figure 2 .

[0157] Figure 11 The implementation methods shown are the same as Figures 1 to 5 The embodiments shown are essentially the same, therefore explanations of these parts will be omitted, and the differences will be explained primarily. Additionally, the same reference numerals are used for the same components as in the foregoing embodiments.

[0158] exist Figure 2 In the context of a process where a first oxide semiconductor layer 420 and a semiconductor pattern 200 are formed simultaneously in a single process, the bit line BL is interpreted as including the first oxide semiconductor layer 420.

[0159] However, since the first oxide semiconductor layer 420 and the semiconductor pattern 200 are formed simultaneously in one process, as described above, the first oxide semiconductor layer 420 and the semiconductor pattern 200 are combined to form an integral unit, which may include oxide semiconductor materials with the same composition, and their boundaries may not be distinguishable.

[0160] Therefore, the first oxide semiconductor layer 420 can be described not only as a component of the bit line BL, but also as a component of the semiconductor structure 205, which has a first portion 206 corresponding to the semiconductor pattern 200 and a second portion 207 corresponding to the first oxide semiconductor layer 420.

[0161] refer to Figure 11 It shows that the semiconductor structure 205 has a corresponding Figure 2 The first portion 206 of the semiconductor pattern 200 and corresponding to Figure 2 The case of the second part 207 of the first oxide semiconductor layer 420.

[0162] The first portions 206 of the semiconductor structure 205 may be spaced apart from each other in the first direction D1. Each first portion 206 may overlap with a word line WL in the first direction D1. One side of the first portion 206 in the second direction D2 may be connected to the second portion 207. The other side of the first portion 206 in the second direction D2 may be connected to the data storage pattern DS.

[0163] The second portion 207 of the semiconductor structure 205 may extend in the first direction D1. The second portion 207 may extend along the bit line BL in the first direction D1. The second portion 207 may extend in the first direction D1 while being connected to the first portion 206 spaced apart in the first direction D1. The second portion 207 may be located between the bit line BL and the first portion 206.

[0164] The description of the first part 206 is the same as the description of the semiconductor pattern 200, and the description of the second part 207 is the same as the description of the first oxide semiconductor layer 420, so repeated descriptions are omitted.

[0165] The following will refer to Figures 12 to 67 Describes a method for manufacturing semiconductor devices.

[0166] Figures 12 to 67 It is a cross-sectional view showing the process of manufacturing a semiconductor device in sequence. Figures 12 to 67 The manufacturing process is shown. Figures 1 to 5 Methods for developing semiconductor devices.

[0167] Figure 12 It is along Figure 1 The cross-sectional view taken by line A-A' corresponds to Figure 2 . Figure 13 It is along Figure 1 The cross-sectional view taken by line B-B' corresponds to Figure 3 .

[0168] refer to Figure 12 and Figure 13 The sacrificial layer SAL and the active layer ACL can be alternately stacked on the substrate 100. Each of the sacrificial layer SAL and the active layer ACL can include a semiconductor material. The sacrificial layer SAL can include a material that has etch selectivity with the active layer ACL. Therefore, during the removal process of the sacrificial layer SAL, which will be described later, the active layer ACL may not be removed or may be removed to a minimum. For example, the active layer ACL can include silicon (Si), germanium (Ge), or silicon-germanium (SiGe), and the sacrificial layer SAL can include one of silicon (Si), germanium (Ge), or silicon-germanium (SiGe) that is different from the active layer ACL. For example, the active layer ACL can include silicon (Si), and the sacrificial layer SAL can include silicon-germanium (SiGe). The thickness of the sacrificial layer SAL can be greater than the thickness of the active layer ACL.

[0169] In some embodiments, the gate insulating pattern material layer 220L may be located between the sacrificial layer SAL and the active layer ACL. For example, on the substrate 100, the sacrificial layer SAL, the gate insulating pattern material layer 220L, the active layer ACL, and the gate insulating pattern material layer 220L may be stacked in sequence.

[0170] Figure 14 It is along Figure 1 The cross-sectional view taken by line A-A' corresponds to Figure 2 . Figure 15 It is along Figure 1 The cross-sectional view taken by line B-B' corresponds to Figure 3 .

[0171] refer to Figure 14 and Figure 15 A first sacrificial pattern SAP1 and a first primary semiconductor pattern ACP are formed on a third-party D3 spaced apart.

[0172] First, the sacrificial layer SAL, the active layer ACL, and the gate insulating patterning material layer 220L can be patterned to form a first trench. The first trench can extend in a second direction D2 and can be formed to be spaced apart from each other along a third direction D3. The first trench can be formed downward in a first direction D1 from the topmost sacrificial layer SAL or active layer ACL to the substrate 100, such that a portion of the upper surface of the substrate 100 can be exposed to the outside.

[0173] By forming the first trench, the patterned and remaining sacrificial layer SAL can form a first sacrificial pattern SAP1, and the patterned and remaining active layer ACL can form a first primary semiconductor pattern ACP. The first sacrificial pattern SAP1 and the first primary semiconductor pattern ACP can extend in a second direction D2 between the first trenches spaced apart along a third direction D3.

[0174] In some embodiments, the first trench may extend in the second direction D2 and may be formed to be spaced apart from each other along the second direction D2 and the third direction D3. Therefore, the first sacrificial pattern SAP1 and the first primary semiconductor pattern ACP may be located between the first trenches spaced apart in the third direction D3, and may include a region extending in the second direction D2 and a region intersecting the region extending in the second direction D2 and extending in the third direction D3.

[0175] After the first trench is formed, a first primary fill pattern PF1 may fill the first trench. The first primary fill pattern PF1 may cover the upper surface of the exposed substrate 100. The first primary fill pattern PF1 may be spaced apart from each other on a third-direction D3 by a first primary semiconductor pattern ACP and a first sacrificial pattern SAP1. For example, the first primary fill pattern PF1 may include an insulating material, and may include, for example, silicon nitride.

[0176] Figure 16 It is along Figure 1 The cross-sectional view taken by line A-A' corresponds to Figure 2 . Figure 17 It is along Figure 1 The cross-sectional view taken by line B-B' corresponds to Figure 3 .

[0177] refer to Figure 16 and Figure 17 The first sacrificial pattern SAP1 and the second primary semiconductor pattern 170 can be stacked alternately, and the gate insulating pattern layer 220 can be interposed between the first sacrificial pattern SAP1 and the second primary semiconductor pattern 170 to form a primary stack.

[0178] First, after forming the first primary fill pattern PF1, a second trench TR2 can be formed. The second trench TR2 can be formed on both sides of the first sacrificial pattern SAP1, the first primary semiconductor pattern ACP, and the gate insulating pattern material layer 220L in the second direction D2.

[0179] For example, the second trench TR2 can be formed by patterning a portion of the region extending in the third direction D3 of the first sacrificial pattern SAP1, the first primary semiconductor pattern ACP, and the gate insulating pattern material layer 220L on a plane. In some embodiments, forming the second trench TR2 may include removing a portion of the top of the substrate 100.

[0180] By forming the second trench TR2, the patterned and remaining first primary semiconductor pattern ACP can constitute the second primary semiconductor pattern 170. The patterned and remaining gate insulating pattern material layer 220L can constitute the gate insulating pattern layer 220.

[0181] The second trench TR2 can expose one side of the first sacrificial pattern SAP1, the second primary semiconductor pattern 170, and the gate insulating pattern layer 220 in the second direction D2 to the outside. The second trench TR2 can also expose a portion of the upper surface of the substrate 100 to the outside.

[0182] Figure 18 It is along Figure 1 The cross-sectional view taken by line A-A' corresponds to Figure 2. Figure 19 It is along Figure 1 The cross-sectional view taken by line B-B' corresponds to Figure 3 .

[0183] refer to Figure 18 and Figure 19 After the second trench TR2 is formed, a second primary fill pattern PF2 can fill the second trench TR2. The second primary fill pattern PF2 can cover the exposed upper surface of the substrate 100. The second primary fill pattern PF2 can be spaced apart in the second direction D2 by the first sacrificial pattern SAP1, the second primary semiconductor pattern 170, and the gate insulating pattern layer 220. For example, the second primary fill pattern PF2 can include an insulating material, and for example, can include silicon oxide.

[0184] Figure 20 It is along Figure 1 The cross-sectional view taken by line A-A' corresponds to Figure 2 . Figure 21 It is along Figure 1 The cross-sectional views taken by lines B-B' and C-C' correspond to Figure 3 .

[0185] refer to Figure 20 and Figure 21 A portion of the second primary fill pattern PF2 can be removed. For example, the second primary fill pattern PF2 located in the area where the data storage pattern DS will be formed can be removed.

[0186] For example, the second primary fill pattern PF2 can be removed alternately in the second direction D2. In other words, one (first) of the second primary fill patterns PF2 is left, and the next (second) second primary fill pattern PF2 in the second direction D2 is removed, the next (third) second primary fill pattern PF2 in the second direction D2 is left, and the next (fourth) second primary fill pattern PF2 in the second direction D2 can be removed.

[0187] The removal of the second primary fill pattern PF2 can be accomplished by using a photoresist process to expose only the second primary fill pattern PF2 to be removed, and then removing it using a wet or dry etching process.

[0188] As some of the second primary fill pattern PF2 is removed, some of the second trench TR2 can be re-exposed. Additionally, through the second trench TR2, the other side of the first sacrificial pattern SAP1, the second primary semiconductor pattern 170, and the gate insulating pattern layer 220 in the second direction D2 can be exposed to the outside. Through the second trench TR2, a portion of the upper surface of the substrate 100 can be exposed to the outside.

[0189] Figure 22 It is along Figure 1 The cross-sectional view cut by line A-A' corresponds to Figure 2 . Figure 23 It is along Figure 1 The cross-sectional view cut by lines B-B' and C-C' corresponds to Figure 3 .

[0190] refer to Figure 22 and Figure 23 The other side of the first sacrificial pattern SAP1 exposed by the second trench TR2 can be selectively removed by a selective etching process in the second direction D2. After removal by the selective etching process, the remaining first sacrificial pattern SAP1 can form the second sacrificial pattern SAP2.

[0191] During the selective etching process, portions of each of the first primary fill patterns PF1 can be removed together, thereby exposing a portion of the upper surface of the substrate 100. The sidewalls of the first primary fill pattern PF1 in the second direction D2 can be aligned with the sidewalls of the sacrificial pattern SAP2 in the second direction D2.

[0192] The first sacrificial pattern SAP1 is selectively removed from one side in the second direction, and the first internal region INR1 can be formed between adjacent second primary semiconductor patterns 170 in the first direction D1.

[0193] For example, selectively removing the other side of the first sacrificial pattern SAP1 exposed by the second trench TR2 in the second direction D2 may include removing a portion of the other side of the first sacrificial pattern SAP1 in the second direction D2 by a selective etching process such as wet etching or dry etching.

[0194] Figure 24 It is along Figure 1 The cross-sectional view taken by line A-A' corresponds to Figure 2 . Figure 25 It is along Figure 1 The cross-sectional views taken by lines B-B' and C-C' correspond to Figure 3 .

[0195] refer to Figure 24 and Figure 25The first sacrificial insulating pattern 176 can be formed on the other side of the second primary semiconductor pattern 170 in the second direction D2, on the other side of the second sacrificial pattern SAP2 in the second direction D2, and on the other side of the gate insulating pattern layer 220 exposed by removing the first sacrificial pattern SAP1 in the second direction D2 and on one side in the first direction D1. Alternatively, the first sacrificial insulating pattern 176 can also be formed on the upper surface of the substrate 100 exposed by the second trench TR2 and the first internal region INR1.

[0196] For example, the first sacrificial insulating pattern 176 may extend on the third direction D3. The first sacrificial insulating pattern 176 may extend on the third direction D3 while surrounding the second primary semiconductor pattern 170 and the gate insulating pattern layer 220.

[0197] The first sacrificial insulation pattern 176 can be formed conformally. In other words, the first sacrificial insulation pattern 176 can be formed to have a substantially uniform thickness.

[0198] For example, the first sacrificial insulation pattern 176 can be formed by a deposition process such as PVD (physical vapor deposition), CVD (chemical vapor deposition), or ALD (atomic layer deposition).

[0199] The first sacrificial insulating pattern 176 may include an insulating material, for example, it may include silicon nitride.

[0200] Figure 26 It is along Figure 1 The cross-sectional view taken by line A-A' corresponds to Figure 2 . Figure 27 It is along Figure 1 The cross-sectional views taken by lines B-B' and C-C' correspond to Figure 3 .

[0201] refer to Figure 26 and Figure 27 After the first sacrificial insulation pattern 176 is formed, a second sacrificial insulation pattern 177 can be formed on the first sacrificial insulation pattern 176. The second sacrificial insulation pattern 177 can fill the first internal region INR1 on which the first sacrificial insulation pattern 176 is formed.

[0202] The second sacrificial insulation pattern 177 may extend in the third direction D3. In some areas, the first sacrificial insulation pattern 176 and the second sacrificial insulation pattern 177 may be arranged alternately in the first direction D1.

[0203] For example, forming the second sacrificial insulating pattern 177 may include depositing a second sacrificial insulating layer that fills the first internal region INR1 on the first sacrificial insulating pattern 176, and removing the second sacrificial insulating layer formed on the other side of the second primary semiconductor pattern 170 and the gate insulating pattern layer 220 in the second direction D2. The remaining second sacrificial insulating layer after removal can constitute the second sacrificial insulating pattern 177.

[0204] For example, the second sacrificial insulating layer can be formed by deposition processes such as PVD (physical vapor deposition), CVD (chemical vapor deposition), or ALD (atomic layer deposition). Alternatively, the second sacrificial insulating layer can be removed by selective etching or cleaning processes.

[0205] The second sacrificial insulating pattern 177 may include an insulating material, for example, silicon oxide.

[0206] Figure 28 It is along Figure 1 The cross-sectional view taken by line A-A' corresponds to Figure 2 . Figure 29 It is along Figure 1 The cross-sectional views taken by lines B-B' and C-C' correspond to Figure 3 .

[0207] refer to Figure 28 and Figure 29 A third sacrificial insulation pattern 178 can be formed on the first sacrificial insulation pattern 176 and the second sacrificial insulation pattern 177 to form a sacrificial insulation structure 175.

[0208] For example, the third sacrificial insulating pattern 178 can be formed on the first sacrificial insulating pattern 176 located on the other side of the second primary semiconductor pattern 170 in the second direction D2 and on the other side of the gate insulating pattern layer 220 in the second direction D2. The third sacrificial insulating pattern 178 can be formed on the second sacrificial insulating pattern 177. Alternatively, the third sacrificial insulating pattern 178 can be formed on the first sacrificial insulating pattern 176 located on the upper surface of the substrate 100.

[0209] The third sacrificial insulation pattern 178 can be formed conformally. In other words, the third sacrificial insulation pattern 178 can be formed to have a substantially uniform thickness.

[0210] For example, the third sacrificial insulation pattern 178 can be formed by a deposition process such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0211] The third sacrificial insulating pattern 178 may include an insulating material, for example, it may include silicon nitride.

[0212] Figure 30 It is along Figure 1 The cross-sectional view taken by line A-A' corresponds to Figure 2 . Figure 31 It is along Figure 1 The cross-sectional views taken by lines B-B' and C-C' correspond to Figure 3 .

[0213] refer to Figure 30 and Figure 31 The other side of the gate insulating pattern layer 220 in the second direction D2 can be selectively removed by a selective etching process.

[0214] For example, removing the gate insulating pattern layer 220 may include: removing the first sacrificial insulating pattern 176 and the third sacrificial insulating pattern 178 located on the other side of the gate insulating pattern layer 220 in the second direction D2, exposing the other side of the gate insulating pattern layer 220 in the second direction D2, and selectively etching the exposed other side of the gate insulating pattern layer 220 in the second direction D2.

[0215] For example, selective etching processes such as wet etching or dry etching can be used to selectively remove the other side of the gate insulating pattern layer 220 in the second direction D2, and the selective etching process of the gate insulating pattern layer 220 can be time etching performed for an appropriate period of time.

[0216] By selectively removing the other side of the gate insulating pattern layer 220 in the second direction D2, a portion of the other side of the second primary semiconductor pattern 170 in the second direction D2 and both sides in the first direction D1 can be exposed.

[0217] Figure 32 It is along Figure 1 The cross-sectional view taken by line A-A' corresponds to Figure 2 . Figure 33 It is along Figure 1 The cross-sectional views taken by lines B-B' and C-C' correspond to Figure 3 .

[0218] refer to Figure 32 and Figure 33 As the gate insulating pattern layer 220 is removed, the other side of the exposed second primary semiconductor pattern 170 in the second direction D2 can be removed by a selective etching process.

[0219] The other side of the second primary semiconductor pattern 170 in the second direction D2 can be aligned with the other side of the gate insulating pattern layer 220 in the second direction D2. Thus, the other side of the second primary semiconductor pattern 170 in the second direction D2 and the other side of the gate insulating pattern layer 220 in the second direction D2 can form a coplanar surface.

[0220] One side of the second primary semiconductor pattern 170 in the second direction D2 can be selectively removed, and a second internal region INR2 can be formed between adjacent second sacrificial insulating patterns 177 in the first direction D1. Furthermore, the second internal region INR2 can be positioned to be spaced apart in the third direction D3 by the first sacrificial insulating pattern 176. In other words, the second internal region INR2 can be an empty space surrounded by the first sacrificial insulating pattern 176 and the second sacrificial insulating pattern 177.

[0221] For example, selective etching processes such as wet etching or dry etching can be used to selectively remove one side of the second primary semiconductor pattern 170 in the second direction D2, and the selective etching process of the second primary semiconductor pattern 170 can be time etching performed for an appropriate period of time.

[0222] Figure 34 It is along Figure 1 The cross-sectional view taken by line A-A' corresponds to Figure 2 . Figure 35 It is along Figure 1 The cross-sectional views taken by lines B-B' and C-C' correspond to Figure 3 .

[0223] refer to Figure 34 and Figure 35 The first electrode 310 of the data storage pattern DS can be formed within the second internal region INR2. The first electrode 310 can be formed within the second internal region INR2, which is surrounded by a first sacrificial insulating pattern 176 and a second sacrificial insulating pattern 177 on one side of the second primary semiconductor pattern 170 in the second direction D2. For example, the first electrode 310 can be formed to fill the empty space within the second internal region INR2.

[0224] In some embodiments, the first electrode 310 may be formed as a thin film having a uniform thickness along the surface shape within the second internal region INR2. Therefore, the first electrode 310 may have a cylindrical shape with an empty internal space.

[0225] For example, the first electrode 310 can be deposited using an atomic layer deposition process, but is not limited to this.

[0226] Figure 36 It is along Figure 1 The cross-sectional view taken by line A-A', and corresponding to Figure 2 . Figure 37 It is along Figure 1 The cross-sectional view taken by lines B-B' and C-C', and corresponding to Figure 3 .

[0227] refer to Figure 36 and Figure 37 Remove the first sacrificial insulation pattern 176 and the second sacrificial insulation pattern 177.

[0228] For example, the first sacrificial insulating pattern 176 and the second sacrificial insulating pattern 177 can be removed by a selective etching process. By removing the first sacrificial insulating pattern 176 and the second sacrificial insulating pattern 177, the surfaces of both sides of the first electrode 310 in the first direction D1 can be exposed.

[0229] The other side of the second sacrificial pattern SAP2 in the second direction D2 can be aligned with the other side of the second primary semiconductor pattern 170 in the second direction D2 and the other side of the gate insulating pattern layer 220 in the second direction D2. Thus, the other side of the second sacrificial pattern SAP2 in the second direction D2, the other side of the second primary semiconductor pattern 170 in the second direction D2, and the other side of the gate insulating pattern layer 220 in the second direction D2 can form a coplanar surface.

[0230] The first sacrificial insulation pattern 176 and the second sacrificial insulation pattern 177 are removed, and a third internal region INR3 can be formed between adjacent first electrodes 310 in the first direction D1. Furthermore, the third internal region INR3 can overlap with the second trench TR2 and extend in the third direction D3.

[0231] For example, selective removal of the first sacrificial insulating pattern 176 and the second sacrificial insulating pattern 177 can be performed using a selective etching process such as wet etching or dry etching, and the selective etching process for the first sacrificial insulating pattern 176 and the second sacrificial insulating pattern 177 can be time etching performed for an appropriate period of time.

[0232] Figure 38 It is along Figure 1 The cross-sectional view taken by line A-A' corresponds to Figure 2 . Figure 39 It is along Figure 1 The cross-sectional views taken by lines B-B' and C-C' correspond to Figure 3 .

[0233] refer to Figure 38 and Figure 39A data storage pattern DS can be formed by sequentially stacking a dielectric layer 320 and a second electrode 330 on the surface of the first electrode 310.

[0234] First, a dielectric layer 320 is formed on the surface of the first electrode 310.

[0235] The dielectric layer 320 may be formed on the outer surface of the first electrode 310. For example, the dielectric layer 320 may be formed on the outer surface of the first electrode 310 exposed by the third internal region INR3 and the second trench TR2.

[0236] The dielectric layer 320 may be conformally formed on the first electrode 310. In other words, the dielectric layer 320 may be formed as a thin film with a uniform thickness along the surface shape of the first electrode 310.

[0237] For example, the dielectric layer 320 can be deposited using an atomic layer deposition (ALD) process, but is not limited to this.

[0238] In some embodiments, when the first electrode 310 has a cylindrical shape, the dielectric layer 320 may be formed on the inner and outer surfaces of the first electrode 310. Alternatively, the dielectric layer 320 may be formed on one surface of the second sacrificial pattern SAP2 located between the first electrodes 310 spaced apart in the first direction D1, in the second direction D2.

[0239] Next, a second electrode 330 is formed on the dielectric layer 320.

[0240] The second electrode 330 may be formed on the dielectric layer 320. For example, the second electrode 330 may be formed to be spaced apart from the first electrode 310, with the dielectric layer 320 inserted therebetween.

[0241] Furthermore, the second electrode 330 may also be formed on another surface of the second sacrificial pattern SAP2 located between the first electrodes 310 spaced apart in the first direction D1 in the second direction D2.

[0242] The second electrode 330 can be conformally formed on the dielectric layer 320. In other words, the second electrode 330 can be formed as a thin film with a uniform thickness along the surface shape of the first electrode 310.

[0243] For example, the second electrode 330 can be deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD) processes, but is not limited to these.

[0244] In some embodiments, when the first electrode 310 has a cylindrical shape, the second electrode 330 may be formed on both the inner and outer surfaces of the first electrode 310. Furthermore, the second electrode 330 may be formed to fill the third internal region INR3 and the second trench TR2, rather than being formed conformally. In other words, the second electrode 330 may be formed in place of the second spacer 340, which will be described later.

[0245] Next, a second spacer 340 is formed on the second electrode 330.

[0246] The second spacer 340 can be formed to fill the third internal region INR3 and the second trench TR2.

[0247] For example, the second electrode 330 can be formed by physical vapor deposition (PVD) or chemical vapor deposition (CVD) processes, but is not limited to these.

[0248] Figure 40 It is along Figure 1 The cross-sectional view taken by line A-A' corresponds to Figure 2 . Figure 41 It is along Figure 1 The cross-sectional view taken by line B-B' corresponds to Figure 3 .

[0249] refer to Figure 40 and Figure 41 This allows the removal of any remaining portion of the second primary fill pattern PF2. For example, the second primary fill pattern PF2 located in the area where the bit line BL is to be formed can be removed.

[0250] The removal of the second primary fill pattern PF2 can be achieved by exposing the second primary fill pattern PF2 to be removed using a photoresist process, and then removing them by a wet or dry etching process.

[0251] As the second primary fill pattern PF2 is removed, a third trench TR3 can be formed. The third trench TR3 can be formed on one side of the second sacrificial pattern SAP2, the second primary semiconductor pattern 170, and the gate insulating pattern layer 220 in the second direction D2.

[0252] Through the third trench TR3, one side of the second sacrificial pattern SAP2, the second primary semiconductor pattern 170, and the gate insulating pattern layer 220 in the second direction D2 can be exposed to the outside. Through the third trench TR3, a portion of the upper surface of the substrate 100 can be exposed to the outside.

[0253] Figure 42 It is along Figure 1 The cross-sectional view taken by line A-A' corresponds to Figure 2 . Figure 43 It is along Figure 1 The cross-sectional view taken by line B-B' corresponds to Figure 3 .

[0254] refer to Figure 42 and Figure 43 The second sacrificial pattern SAP2 exposed by the third trench TR3 can be selectively removed using a selective etching process. In this case, the second sacrificial pattern SAP2 can be completely removed.

[0255] The second sacrificial pattern SAP2 is selectively removed, and a fourth internal region INR4 can be formed between adjacent second primary semiconductor patterns 170 in the first direction D1. One side of the second electrode 330 of the data storage pattern DS in the second direction D2 can be exposed by the fourth internal region INR4.

[0256] For example, the second sacrificial pattern SAP2 exposed by the third trench TR3 can be removed by a selective etching process such as wet etching or dry etching.

[0257] Figure 44 It is along Figure 1 The cross-sectional view taken by line A-A' corresponds to Figure 2 . Figure 45 It is along Figure 1 The cross-sectional view taken by line B-B' corresponds to Figure 3 .

[0258] refer to Figure 44 and Figure 45 The gate insulating pad material layer 280L can be formed on one side of the second primary semiconductor pattern 170 exposed by removing the second sacrificial pattern SAP2 in the second direction D2, and on one side of the gate insulating pattern layer 220 in the second direction D2 and the first direction D1. Furthermore, the gate insulating pad material layer 280L can be formed on one side of the second electrode 330 of the data storage pattern DS exposed by the fourth internal region INR4 in the second direction D2, and the gate insulating pad material layer 280L can also be formed on the upper surface of the substrate 100 exposed by the third trench TR3 and the fourth internal region INR4.

[0259] For example, the gate insulating pad material layer 280L may extend onto the third direction D3. The gate insulating pad material layer 280L may extend onto the third direction D3 while surrounding the second primary semiconductor pattern 170 and the gate insulating pattern layer 220.

[0260] The gate insulating pad material layer 280L can be formed conformally. In other words, the gate insulating pad material layer 280L can be formed to have a substantially uniform thickness.

[0261] For example, the gate insulating pad material layer 280L can be formed by deposition processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0262] Figure 46 It is along Figure 1 The cross-sectional view taken by line A-A' corresponds to Figure 2 . Figure 47 It is along Figure 1 The cross-sectional view taken by line B-B' corresponds to Figure 3 .

[0263] refer to Figure 46 and Figure 47 A cover material layer 145L can be formed on the gate insulating pad material layer 280L. For example, the cover material layer 145L can be formed on one side of the second primary semiconductor pattern 170 in the second direction D2, on one side of the gate insulating pattern layer 220 in the second direction D2 and on one side in the first direction D1, on one side of the second electrode 330 of the data storage pattern DS in the second direction D2, and on the upper surface of the substrate 100 where the gate insulating pad material layer 280L is located.

[0264] The cover material layer 145L can be formed conformally. In other words, the cover material layer 145L can be formed to have a substantially uniform thickness. For example, the cover material layer 145L can extend in the third direction D3.

[0265] The covering material layer 145L may include an insulating material, for example, it may include a silicon nitride.

[0266] For example, the overlay material layer 145L can be formed by deposition processes such as PVD (physical vapor deposition), CVD (chemical vapor deposition), or ALD (atomic layer deposition).

[0267] Figure 48 It is along Figure 1 The cross-sectional view taken by line A-A' corresponds to Figure 2 . Figure 49 It is along Figure 1 The cross-sectional view taken by line B-B' corresponds to Figure 3 .

[0268] refer to Figure 48 and Figure 49 After forming the cover material layer 145L, a word line separation material layer 150L can be formed on the cover material layer 145L. The word line separation material layer 150L can fill the fourth internal region INR4, on which the gate insulating pad material layer 280L and the cover material layer 145L are formed.

[0269] For example, the word line separation material layer 150L may extend in the third direction D3. In some regions, the gate insulating pad material layer 280L and the word line separation material layer 150L may be arranged alternately in the first direction D1, with the cover material layer 145L interposed therebetween.

[0270] For example, the word line separation material layer 150L can be formed by deposition processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0271] The word line separation layer 150L may include an insulating material, for example, it may include silicon oxide.

[0272] Figure 50 It is along Figure 1 The cross-sectional view cut by line A-A' corresponds to Figure 2 . Figure 51 It is along Figure 1 The cross-sectional view of the line B-B' cut, corresponding to Figure 3 .

[0273] refer to Figure 50 and Figure 51 The word line separation material layer 150L formed on one side of the second primary semiconductor pattern 170 in the second direction D2 and on one side of the gate insulating pattern layer 220 in the second direction D2 can be removed. The remaining word line separation material layer 150L after removal can constitute the word line separation layer 150.

[0274] For example, the word line separating material layer 150L can be removed by selective etching or cleaning processes.

[0275] Figure 52 It is along Figure 1 The cross-sectional view taken by line A-A' corresponds to Figure 2 . Figure 53 It is along Figure 1 The cross-sectional view taken by line B-B' corresponds to Figure 3 .

[0276] refer to Figure 52 and Figure 53 A portion of the cover material layer 145L can be removed by a selective etching process to form the cover pattern 145.

[0277] For example, portions of the cover material layer 145L located on one side of the gate insulating pattern layer 220 and on one side of the second primary semiconductor pattern 170 in the second direction D2 can be removed. Furthermore, portions of the cover material layer 145L located in the first direction D1 between the gate insulating pad material layer 280L and the word line separation layer 150 can be removed.

[0278] However, the portion of the cover material layer 145L located on one side of the second electrode 330 of the data storage pattern DS in the second direction D2 can be retained and not removed, forming the cover pattern 145. The cover pattern 145 can be surrounded by the gate insulating pad material layer 280L, and can include the portion located between the word line separation layer 150 and the gate insulating pattern layer 220 in the first direction D1 and the portion facing the data storage pattern DS in the second direction D2.

[0279] Figure 54 It is along Figure 1 The cross-sectional view taken by line A-A', and corresponding to Figure 2 . Figure 55 It is along Figure 1 The cross-sectional view taken by line B-B', and corresponding to Figure 3 .

[0280] refer to Figure 54 and Figure 55 The gate insulating pad material layer 280L on one side of the gate insulating pattern layer 220 and on one side of the second primary semiconductor pattern 170 in the second direction D2 can be removed. The remaining gate insulating pad material layer 280L after removal can form the gate insulating pad 280.

[0281] At this time, a portion of the gate insulating pad material layer 280L on one side of the gate insulating pattern layer 220 in the first direction D1 and a portion of the word line separating layer 150 facing the gate insulating pad material layer 280L can be partially removed, thereby reducing the length of the gate insulating pad material layer 280L and the word line separating layer 150 in the first direction D1. Therefore, the length of the empty space between the gate insulating pad 280 and the word line separating layer 150 in the first direction D1 can be increased, and space can be ensured for forming the word line WL between the gate insulating pad 280 and the word line separating layer 150. Figure 52 and Figure 54 It is shown that a portion of each of the gate insulating pad material layer 280L and the word line separation layer 150 is removed, but this is not the only possibility. For example, the space can be ensured by partially removing one of the gate insulating pad material layer 280L and the word line separation layer 150.

[0282] The gate insulating pad material layer 280L can be removed by selective etching or cleaning processes.

[0283] Figure 56 It is along Figure 1 The cross-sectional view taken by line A-A', and corresponding to Figure 2 . Figure 57 It is along Figure 1The cross-sectional view taken by line B-B', and corresponding to Figure 3 .

[0284] refer to Figure 56 and Figure 57 The primary gate conductive layer (PGL) can be formed in the empty space between the gate insulating pad 280 and the word line separation layer 150. The primary gate conductive layer (PGL) can extend onto the third direction D3.

[0285] Furthermore, the primary gate conductive layer PGL can be formed on one side of the second primary semiconductor pattern 170 in the second direction D2, on one side of the gate insulating pattern layer 220 in the second direction D2, on one side of the gate insulating pad 280 in the second direction D2, and on one side of the word line separation layer 150 in the second direction D2.

[0286] The primary gate conductive layer (PGL) can be formed conformally. In other words, the primary gate conductive layer (PGL) can be formed to have a substantially uniform thickness.

[0287] In some embodiments, when the gate insulating pattern layer 220 is not formed, the primary gate conductive layer PGL may surround and extend over the third-direction D3 a second primary semiconductor pattern 170 spaced apart thereon.

[0288] For example, the primary gate conductive layer PGL can be deposited using an atomic layer deposition (ALD) process, but is not limited to this.

[0289] Figure 58 It is along Figure 1 The cross-sectional view taken by line A-A' corresponds to Figure 2 . Figure 59 It is along Figure 1 The cross-sectional view taken by line B-B' corresponds to Figure 3 .

[0290] refer to Figure 58 and Figure 59 A portion of the primary gate conductive layer PGL can be removed to form the word line WL.

[0291] For example, the primary gate conductive layer PGL formed on one side of the second primary semiconductor pattern 170 in the second direction D2 and on one side of the gate insulating pattern layer 220 in the second direction D2 can be removed. The remaining primary gate conductive layer PGL after removal can form a word line WL.

[0292] At this time, one side of the word line WL in the second direction D2 can be recessed more than the side of the word line separation layer 150 in the second direction D2, and as described later, a first spacer 140 can be formed in the recessed space of the word line WL.

[0293] The primary gate conductive layer (PGL) can be removed by selective etching or cleaning processes. For example, the etching process can be a wet etching process.

[0294] Figure 60 It is along Figure 1 The cross-sectional view taken by line A-A' corresponds to Figure 2 . Figure 61 It is along Figure 1 The cross-sectional view taken by line B-B' corresponds to Figure 3 .

[0295] refer to Figure 60 and Figure 61 The buried insulation pattern 140L can be formed on the letter line WL.

[0296] The buried insulation pattern 140L can be formed in a recessed space on one side of the letter line WL in the second direction D2. Alternatively, the buried insulation pattern 140L can be formed to fill the third trench TR3.

[0297] For example, the buried insulation pattern 140L can be formed by physical vapor deposition (PVD) or chemical vapor deposition (CVD) processes, but is not limited to these.

[0298] Figure 62 It is along Figure 1 The cross-sectional view taken by line A-A' corresponds to Figure 2 . Figure 63 It is along Figure 1 The cross-sectional view taken by lines B-B' and D-D' corresponds to Figure 3 and Figure 4 .

[0299] refer to Figure 62 and Figure 63 A portion of the buried insulation pattern 140L can be removed. For example, a portion of the buried insulation pattern 140L located in the area where the bit line BL will be formed can be removed.

[0300] However, the buried insulation pattern 140L formed on one side of the recessed area in the second direction D2 of the word line WL may not be removed. The remaining buried insulation pattern 140L that is not removed may form the first spacer 140.

[0301] Alternatively, the buried insulation pattern 140L located between the bit lines BL to be formed on the third-party D3 can remain unremoved. The remaining buried insulation pattern 140L can constitute bit line spacers.

[0302] As a portion of the buried insulating pattern 140L is removed, a fourth trench TR4 can be formed. The fourth trench TR4 can be formed on one side of the second primary semiconductor pattern 170, the gate insulating pattern layer 220, the gate insulating pad 280, the word line WL, and the word line separation layer 150 in the second direction D2.

[0303] Through the fourth trench TR4, one side of the second primary semiconductor pattern 170, gate insulating pattern layer 220, gate insulating pad 280, first spacer 140, and word line separation layer 150 in the second direction D2 can be exposed to the outside. Additionally, through the fourth trench TR4, one side of the second primary semiconductor pattern 170, gate insulating pattern layer 220, gate insulating pad 280, first spacer 140, and word line separation layer 150 in the second direction D2 can be aligned in the first direction D1. Through the fourth trench TR4, a portion of the upper surface of the substrate 100 can be exposed to the outside.

[0304] During the formation process of the fourth trench TR4, a portion of the buried insulation pattern 140L can be removed using a photoresist process. For example, in Figure 60 and Figure 61 After a mask pattern is formed on the structure shown, exposing a portion of the buried insulation pattern 140L, the exposed portion of the buried insulation pattern 140L can be removed using wet and / or dry etching processes.

[0305] Figure 64 It is along Figure 1 The cross-sectional view taken by line A-A' corresponds to Figure 2 . Figure 65 It is along Figure 1 The cross-sectional view taken by lines B-B' and D-D' corresponds to Figure 3 and Figure 4 .

[0306] refer to Figure 64 and Figure 65 The second primary semiconductor pattern 170 exposed by the fourth trench TR4 can be removed by a selective etching process. At this point, the second primary semiconductor pattern 170 can be completely removed.

[0307] The second primary semiconductor pattern 170 can be selectively removed to form a fifth internal region INR5 between adjacent gate insulating pattern layers 220 in the first direction D1. Additionally, the fifth internal regions INR5 can be spaced apart from each other in the third direction D3 by gate insulating pads 280. In other words, the fifth internal region INR5 can be an empty space surrounded by the gate insulating pattern layer 220 and the gate insulating pad 280.

[0308] For example, selectively removing one side of the second primary semiconductor pattern 170 in the second direction D2 can be achieved using a selective etching process such as wet etching or dry etching. For instance, the etching process may include chemical etching that selectively etches between components. In another example, the etching process for selective etching of the second primary semiconductor pattern 170 may include time etching performed for an appropriate period of time.

[0309] Figure 66 It is along Figure 1 The cross-sectional view taken by line A-A' corresponds to Figure 2 . Figure 67 It is along Figure 1 The cross-sectional view taken by lines B-B' and D-D' corresponds to Figure 3 and Figure 4 .

[0310] refer to Figure 66 and Figure 67 It can form a semiconductor pattern 200 and a first oxide semiconductor layer 420.

[0311] For example, semiconductor pattern 200 can be formed within the fifth internal region INR5. Semiconductor pattern 200 can be formed on one side of the first electrode 310 of the data storage pattern DS in the second direction D2 within the fifth internal region INR5, surrounded by gate insulating pattern layer 220 and gate insulating pad 280. For example, semiconductor pattern 200 can be formed to fill empty spaces within the fifth internal region INR5. For example, semiconductor pattern 200 can be deposited via a fourth trench TR4 using an atomic layer deposition (ALD) process.

[0312] For example, the first oxide semiconductor layer 420 can be formed together with the semiconductor pattern 200. For instance, the semiconductor pattern 200 and the first oxide semiconductor layer 420 can be formed by depositing oxide semiconductor material on the surfaces of the gate insulating pattern layer 220 and the gate insulating pad 280 exposed through the fifth internal region INR5, and simultaneously depositing oxide semiconductor material on the surfaces of the gate insulating pattern layer 220, the gate insulating pad 280, the first spacer 140, and the word line separation layer 150 exposed through the fourth trench TR4. The semiconductor pattern 200 and the first oxide semiconductor layer 420 can be formed simultaneously using the same process and can be made of the same material; their boundaries may not be distinguishable.

[0313] In other words, the first oxide semiconductor layer 420 and the semiconductor pattern 200 can be formed simultaneously by conformally covering the surface of the space exposed by the fifth internal region INR5 and the fourth trench TR4 with oxide semiconductor material. The surface of the oxide semiconductor material exposed to the fourth trench TR4 at the corner where one side of the gate insulating pattern layer 220 in the second direction D2 meets one side in the first direction D1 (which is the portion where the first oxide semiconductor layer 420 and the semiconductor pattern 200 are connected) can have a rounded shape in cross-section. Therefore, since the portion where the first oxide semiconductor layer 420 and the semiconductor pattern 200 are connected has a rounded shape in cross-section, the first oxide semiconductor layer 420 can have a recessed portion 421 corresponding to each location in the semiconductor pattern 200. The recessed portion 421 can have a size and shape corresponding to the size and shape on the second direction D2 and the third direction D3 of the semiconductor pattern 200.

[0314] Furthermore, when the semiconductor pattern 200 is formed by filling the fifth internal region INR5 with an oxide semiconductor material, the oxide semiconductor material can be grown simultaneously from the lower surface of one gate insulating pattern layer 220 in the first direction D1 and from the upper surface of another gate insulating pattern layer 220 in the first direction D1. When it fills the fifth internal region INR5 and meets at approximately the midpoint of the fifth internal region INR5 in the first direction D1, the semiconductor pattern 200 can have an interface internally. The interface of the semiconductor pattern 200 extends in the second direction D2, and its ends can meet the recessed portion 421. However, this is not a limitation, as the semiconductor pattern 200 comprises the same material, the interface can be indistinguishable.

[0315] In some embodiments, after the first oxide semiconductor layer 420 is formed, a portion of the surface of the first oxide semiconductor layer 420 exposed to the fourth trench TR4 can be removed by a cleaning process. For example, the cleaning process can be performed to the extent of removing the recessed portion 421 of the first oxide semiconductor layer 420. When the recessed portion 421 is removed by the cleaning process, the length of the first oxide semiconductor layer 420 in the second direction D2 can be reduced, and as... Figure 2 As shown, the first oxide semiconductor layer 420 may not have the recessed portion 421. However, if no cleaning process is performed, the first oxide semiconductor layer 420 may have the recessed portion 421, such as... Figure 6 As shown.

[0316] Refer again Figures 1 to 5Within the fourth trench TR4, a first oxide semiconductor layer 420 is formed, and a core conductive layer 410 can be formed in the remaining space, thereby forming a bit line BL including the core conductive layer 410 and the first oxide semiconductor layer 420. For example, the core conductive layer 410 can be formed to fill all the internal regions of the remaining fourth trench TR4 after the formation of the first oxide semiconductor layer 420.

[0317] For example, the semiconductor pattern 200 and the first oxide semiconductor layer 420 can be formed by PVD (physical vapor deposition), CVD (chemical vapor deposition), or ALD (atomic layer deposition) processes. The core conductive layer 410 can be deposited by an ALD process, but is not limited to this.

[0318] The above detailed description of the embodiments of this disclosure is not intended to limit the scope of this disclosure. On the contrary, various modifications and improvements made by those skilled in the art using the basic concepts of this disclosure as defined in the appended claims also fall within the scope of this disclosure.

[0319] This application claims priority and benefit to Korean Patent Application No. 10-2025-0050620, filed on April 18, 2025, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor device, comprising: Bit lines extend in the first direction. The semiconductor pattern is spaced apart in the first direction and has one end connected to the bit line in a second direction different from the first direction. Word lines, extending upwards in a third direction different from the first and second directions and located on one side of each of the semiconductor patterns in the first direction, and Data storage patterns are connected to the other end of each of the semiconductor patterns in the second direction. The bit line includes a core conductive layer and a first oxide semiconductor layer, wherein the first oxide semiconductor layer is located between the core conductive layer and the semiconductor pattern and is connected to the semiconductor pattern.

2. The semiconductor device according to claim 1, wherein: The semiconductor pattern includes an oxide semiconductor material. The first oxide semiconductor layer comprises an oxide semiconductor material that is the same as the material of the semiconductor pattern, and The first oxide semiconductor layer and the semiconductor pattern constitute a single entity.

3. The semiconductor device of claim 1, wherein the first oxide semiconductor layer has a recessed portion on the side facing the core conductive layer, and the recessed portion is indented relative to the semiconductor pattern.

4. The semiconductor device of claim 3, wherein the first oxide semiconductor layer has a plurality of said recessed portions, each of the plurality of recessed portions corresponding to each position in the semiconductor pattern, and the recessed portions having a size and shape corresponding to the size and shape of the semiconductor pattern.

5. The semiconductor device of claim 3, wherein the core conductive layer has a first protrusion that protrudes toward the recessed portion of the first oxide semiconductor layer.

6. The semiconductor device of claim 1, wherein the bit line further comprises a second oxide semiconductor layer between the core conductive layer and the first oxide semiconductor layer.

7. The semiconductor device of claim 6, wherein the second oxide semiconductor layer comprises an oxide semiconductor material different from the material of the first oxide semiconductor layer and the semiconductor pattern.

8. The semiconductor device of claim 6, wherein the first oxide semiconductor layer has a recessed portion on the side facing the second oxide semiconductor layer that is indented relative to the semiconductor pattern. The second oxide semiconductor layer has a second protrusion that protrudes toward the recessed portion of the first oxide semiconductor layer.

9. A semiconductor device, comprising: Bit lines extend in the first direction. The semiconductor pattern is spaced apart in the first direction and has one end connected to the bit line in a second direction different from the first direction. The word line extends upward in a third direction different from the first and second directions and is located on one side of each of the semiconductor patterns in the first direction. A gate insulating layer, located between the semiconductor pattern and the word line, includes a gate insulating pattern layer positioned toward the semiconductor pattern and a gate insulating pad positioned toward the word line, and A data storage pattern is connected to the other end of the semiconductor pattern in the second direction. The gate insulating pad has a first insulating pad portion located between the word line and the gate insulating pattern layer, and a second insulating pad portion located between the word line and the data storage pattern.

10. The semiconductor device of claim 9, wherein the gate insulating pattern layer is located on one or both sides of the semiconductor pattern in the first direction. The gate insulating pad is located on one or both sides of the semiconductor pattern in the first direction, or on one side of the gate insulating pattern layer in the first direction. The gate insulating pad is located on both sides of the semiconductor pattern in the third direction, and on both sides of the gate insulating pattern layer in the third direction.

11. The semiconductor device of claim 9, wherein the gate insulating layer comprises a plurality of the gate insulating patterned layers. One of the plurality of gate insulating pattern layers is located on one side of the semiconductor pattern in the first direction. Another of the plurality of gate insulating pattern layers is located on the other side of the semiconductor pattern in the first direction, and The length of the gate insulating pattern layer in the third direction is approximately the same as the length of the semiconductor pattern in the third direction.

12. The semiconductor device of claim 9, wherein the gate insulating pad further comprises a third insulating pad portion located between the third-orderly spaced semiconductor patterns, and The first insulating pad portion and the second insulating pad portion extend upward through the semiconductor pattern on the third side.

13. The semiconductor device of claim 12, wherein the gate insulating pad surrounds the semiconductor pattern or surrounds a stack comprising the semiconductor pattern and the gate insulating pattern layer.

14. The semiconductor device of claim 9, wherein the semiconductor device includes a first word line and a second word line, the first word line being located below the semiconductor pattern in the first direction, and the second word line being located above the semiconductor pattern in the first direction. The first word line located below a semiconductor pattern in the first direction is spaced apart from the second word line located above another semiconductor pattern in the first direction, which is also located below the first semiconductor pattern in the first direction, in the first direction.

15. The semiconductor device of claim 14, wherein the semiconductor device further comprises a word line separation layer located between the first word line and the second word line spaced apart in the first direction, and The second insulating pad portion is located between the data storage pattern and the word line separation layer.

16. The semiconductor device of claim 14, wherein the semiconductor device further comprises an overlay pattern located on one side of the semiconductor pattern in the first direction and located between the word line and the data storage pattern in the second direction.

17. The semiconductor device of claim 16, wherein the overlay pattern includes a first overlay portion and a second overlay portion, the first overlay portion being located in the first direction between the word line separation layer and a first insulating pad portion of the gate insulating pad, and the second overlay portion being located in the second direction between the word line separation layer and a second insulating pad portion of the gate insulating pad.

18. The semiconductor device according to claim 17, wherein: The first covering portion is located at one end of the first word line of the one semiconductor pattern in the second direction and at one end of the second word line of the other semiconductor pattern in the second direction. The second covering portion connects the first covering portion located at one end of the first word line in the second direction and the first covering portion located at one end of the second word line in the second direction.

19. The semiconductor device of claim 9, wherein the semiconductor device further includes a first spacer located between the word line and the bit line in the second direction.

20. A semiconductor device, comprising: Bit lines extend in the first direction. A semiconductor structure having one end connected to the bit line in a second direction different from the first direction. The word line extends upward in a third direction different from the first and second directions, and is located on one side of the semiconductor structure in the first direction. A data storage pattern is connected to the other end of the semiconductor structure in the second direction. The semiconductor structure includes a first portion and a second portion, the first portion overlapping the word line in the first direction, having the other end in the second direction connected to the data storage pattern, and being spaced apart in the first direction, and the second portion extending in the first direction, connecting to the first portion, and located between the bit line and the first portion.

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