Memory chip with composite bond pad and semiconductor device including the same

Abstract

A memory chip includes a substrate and a plurality of memory array tiles (MATs). The plurality of MATs are disposed over the substrate. At least one MAT includes a sense circuit, a memory array, and a plurality of first pads. The sense circuit is located in a first region from a top view of the memory chip. The memory array is located in a second region adjacent to the first region and electrically connected to the sense circuit from a top view of the memory chip. The plurality of first pads are located in the first region from a top view of the memory chip. The plurality of first pads are located over the sense circuit. The plurality of first pads are electrically connected to the sense circuit and are used to provide an output of the sense circuit.

Description

Technical Field

[0001] This disclosure relates to memory devices and semiconductor devices, and more particularly to memory devices having composite bonding pads and semiconductor devices including such memory devices. Background Technology

[0002] High-speed computing and artificial intelligence (AI) require memory architectures capable of supporting massive data throughput, low latency, and high energy efficiency. As a result, the memory subsystem has become a key bottleneck in fully realizing the potential of high-speed computing and AI systems. Traditionally, static random-access memory (SRAM) has been the preferred choice for on-chip caches and embedded memory due to its fast access speed and ease of integration with logic circuits. However, the continued shrinking of SRAM faces significant challenges, making it increasingly difficult to meet the growing demand for larger and faster memory arrays. SRAM is also quite expensive due to the complexity of its memory cells. In contrast, dynamic random-access memory (DRAM) offers higher density, smaller per-bit area, and lower cost compared to SRAM, making it a viable alternative for embedded memory. Summary of the Invention

[0003] This disclosure provides a memory chip with several specific embodiments. The memory chip includes a substrate and a plurality of memory array dies (MATs). The plurality of MATs are disposed above the substrate. At least one of the plurality of MATs includes a sensing circuit, a memory array, and a plurality of first bonding pads. From a top view of the memory chip, the sensing circuit is located in a first region. From a top view of the memory chip, the memory array is located in a second region adjacent to the first region and is electrically connected to the sensing circuit. From a top view of the memory chip, the plurality of first bonding pads are located in the first region. The plurality of first bonding pads are located above the sensing circuit. The plurality of first bonding pads are electrically connected to the sensing circuit and are used to provide the output of the sensing circuit.

[0004] This disclosure provides a semiconductor device with several specific embodiments. The semiconductor device includes a memory chip and a logic chip. The memory chip includes a substrate and a plurality of mating arrays (MAs) located on the substrate. At least one of the plurality of MATs includes a sensing circuit, a memory array electrically connected to the sensing circuit, and a plurality of first bonding pads electrically connected to the sensing circuit and used to provide an output of the sensing circuit. The logic chip includes a substrate and a plurality of fourth bonding pads. From a cross-sectional view of the logic chip, the plurality of fourth bonding pads are located on the substrate of the logic chip. The plurality of first bonding pads of the at least one MAT are directly connected to the plurality of fourth bonding pads of the logic chip.

[0005] The memory chip and semiconductor device disclosed in this disclosure are suitable for high-speed computing. The memory chip (which may include DRAM cells) has access time, power consumption, and bandwidth comparable to SRAM. Attached Figure Description

[0006] The best understanding of this disclosure can be obtained from the following detailed description when read in conjunction with the accompanying drawings. Please note that, as is customary in the industry, the various parts are not drawn to scale. In fact, for clarity, the dimensions of many parts may be arbitrarily enlarged or reduced.

[0007] Figure 1 This is a side view of a semiconductor device according to some specific embodiments of this disclosure; Figure 2 According to some comparative embodiments of this disclosure, Figure 1 Functional block diagram of the memory blocks of the memory chip; Figure 3 This is a functional block diagram of a semiconductor device according to some comparative embodiments of this disclosure; Figure 4 According to some comparative embodiments of this disclosure, Figure 3 Functional block diagram of the memory blocks of the memory chip; Figure 5 This is a functional block diagram of a semiconductor device according to some specific embodiments of this disclosure; Figure 6A According to some specific embodiments of this disclosure, Figure 5 A top view of the memory blocks of the memory chip; Figure 6B The present disclosure provides circuit diagrams of memory arrays according to some specific embodiments thereof. Figure 7 According to some specific embodiments of this disclosure, along Figure 6A A cross-sectional view of a midline memory array chip (MAT); Figure 8 According to some specific embodiments of this disclosure, along Figure 6A A cross-sectional view of MAT on another line in the middle; Figure 9 For the purposes of this disclosure, some specific embodiments are as follows: Figure 6A A cross-sectional view of MAT on another line in the middle; Figure 10 This is a cross-sectional view of a semiconductor device according to some specific embodiments of this disclosure; Figure 11 This is a cross-sectional view of a semiconductor device according to some specific embodiments of this disclosure; Figure 12To illustrate some specific embodiments of this disclosure, a functional block diagram of a column formed by MAT is shown; Figure 13 The present disclosure provides a circuit diagram of the MAT according to some specific embodiments thereof; Figure 14 This is a circuit diagram of a column selection unit according to some specific embodiments of this disclosure; Figure 15 The circuit diagram illustrating the connection configuration of the column selection unit between two MATs is shown according to some specific embodiments of this disclosure document. Figure 16 This is a top view of the MAT according to some specific embodiments of this disclosure. Detailed Implementation

[0008] This application claims priority to U.S. Provisional Patent Application Serial No. 63 / 789,467, filed April 16, 2025, the entire contents of which are incorporated herein by reference.

[0009] The following description provides many different specific embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and not limiting. For example, reference numerals and / or letters may be repeated in various examples in this disclosure. This repetition is for simplicity and clarity and does not in itself represent a relationship between the various specific embodiments and / or configurations discussed.

[0010] In addition, this document may use spatial terms such as "up," "down," "front," "back," "left," "right," "horizontal," and "vertical" to describe the relationship between one element or feature and another, as shown in the figures. Besides the orientations depicted in the figures, such spatial terms also cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial terms used herein may be interpreted accordingly. We will understand that when an element is referred to as "coupled to" or "connected to" other elements, it may mean directly coupled to or connected to other elements or that there are intermediate elements present.

[0011] Figure 1This is a side view of a semiconductor device 100 according to some comparative embodiments of this disclosure. The semiconductor device 100 includes a memory chip 110, a logic chip 120, and a package substrate 130 (e.g., a printed circuit board). The memory chip 110 and the logic chip 120 are electrically connected to the package substrate 130, thereby enabling communication via the substrate 130. The memory chip 110 may include logic circuitry (not shown) that controls the operation of the memory chip 110. In some specific embodiments, the memory chip 110 includes one or more memory blocks, such as dynamic random access memory (DRAM) blocks.

[0012] Figure 2 According to some comparative embodiments of this disclosure, Figure 1 A functional block diagram of memory block 200 of memory chip 110. Memory block 200 includes multiple memory array tiles (MATs) 210. MATs 210 include memory arrays 212 (e.g., DRAM memory arrays), sensing circuitry 214, and driving circuitry 216. Memory array 212 may include multiple word lines, multiple bit lines, and multiple memory cells located at the intersections of the word lines and bit lines. During a read operation, sensing circuitry 214 may amplify small voltage differences on the bit lines of memory array 212. Driving circuitry 216 provides the necessary current and voltage levels to activate the word lines of memory array 212 to select a specific tile. Memory block 200 also includes peripheral circuitry located near MATs 210, including an input buffer 220, a command decoder 230, a pre-decoder 240, a decoder 250, a driver 260, secondary sensing circuitry 270, a serial peripheral interface (SPI) 280, and input / output (I / O) circuitry 290.

[0013] Input buffer 220 receives address and control signals from logic chip 120 and ensures that the address and control signals are stable and at the correct voltage level before being provided to command decoder 230. Command decoder 230 resolves control signals (such as column address strobe (RAS), column address strobe (CAS), write enable (WE), and output enable (OE)) and generates internal control signals to manage read, write, refresh, and other operations. Pre-decoder 240 breaks down address bits into smaller groups and partially decodes them; the output of pre-decoder 240 is provided to decoder 250. This increases the speed of decoder 250 and reduces its power consumption. Decoder 250 converts binary address inputs into one-hot global enable signals. Driver 260 buffers and distributes the one-hot global enable signals to specific MAT 210s to activate the driver circuitry 216 of that specific MAT 210. The secondary sensing circuit 270 receives the output of the sensing circuit 214 via a global data line (not shown) and can further amplify the output of the sensing circuit 214.

[0014] However, due to the two-dimensional (2D) configuration of memory chip 110, all I / O pins of memory chip 110 are arranged around its edges. The number of I / O pins is limited by the edge length of memory chip 110. Therefore, the limited number of I / O output pins restricts the bandwidth of memory chip 110. Furthermore, the numerous peripheral circuits of memory chip 110 and the long resistive-capacitive (RC) traces within these peripheral circuits consume considerable power and cause significant signal delay. Due to the strong demand for high-throughput, low-latency data processing in applications such as high-speed computing and artificial intelligence systems, vertically stacked (3D stacked) memory architecture has become a mainstream industry trend. Vertical stacking allows the use of through-silicon vias (TSVs) or other vertical interconnect structures, thereby enabling more interconnect structures within a unit area and increasing bandwidth. Moreover, vertical stacking can shorten the vertical transmission distance of signals, thereby reducing latency and power consumption.

[0015] Figure 3 This is a functional block diagram of a semiconductor device 300 according to some comparative embodiments of this disclosure. The semiconductor device 300 may be implemented using a 3D stacked memory architecture. Wafers 301D and 301L of the semiconductor device 300 may be stacked vertically using a composite bonding process or other suitable processes. Each memory chip 302 formed on wafer 301D (in...) Figure 3 The logic chip 303 (referred to as "MC") formed on substrate 301L can be implemented as a DRAM chip. Figure 3 The components (referred to as "CLC") are used to control the operation of the memory chip 302. In this specific embodiment, each logic chip 303 may include, but is not limited to, an input buffer 304, a command decoder 305, and a controller 306. Figure 3 The input buffer 304 and command decoder 305 are respectively similar to Figure 2 The input buffer 220 and command decoder 230 are included; therefore, their detailed descriptions are omitted. The controller 306 controls the operation of the memory chip 302, the input buffer 304, and the command decoder 305.

[0016] Figure 4 According to some comparative embodiments of this disclosure, Figure 3 A functional block diagram of the memory block 400 of the memory chip 302. Each memory chip 302 includes one or more memory blocks 400. Memory block 400 includes multiple MATs 410, multiple bonding pads 420, multiple bonding pads 430, a pre-decoder 440, a decoder 450, a driver 460, and a secondary sense amplifier 470. MAT 410 includes a memory array 412 (e.g., a DRAM memory array), sensing circuitry 414, and driving circuitry 416. Figure 4 The MAT 410, pre-decoder 440, decoder 450, driver 460, and secondary sense amplifier 470 are respectively connected to... Figure 2 The MAT 210, pre-decoder 240, decoder 250, driver 260 and secondary sensor 270 are similar; therefore, their detailed descriptions are omitted.

[0017] Keypads 420 and 430 are electrically connected to logic chip 303. Keypad 420 receives address and control signals from command decoder 305 of logic chip 303. Keypad 430 supplies the output of secondary sense amplifier 470 to controller 306 of logic chip 303. The number of keypads 420 can range from tens to hundreds, as can the number of keypads 430. Therefore, the bandwidth of memory block 400 is increased compared to memory block 200. Furthermore, since input buffer 304 and command decoder 305 have been moved to logic chip 303, the power consumption and signal delay of memory block 400 are reduced to some extent.

[0018] However, memory chip 302 still contains a significant amount of peripheral circuitry, resulting in considerable power consumption. Furthermore, due to the distance between solder pads 420 and 430 and MAT 410, there is still room for improvement in signal delay. Therefore, to achieve the goal of replacing SRAM with DRAM, a more compact 3D stacked DRAM architecture is needed.

[0019] Figure 5This is a functional block diagram of a semiconductor device 500 according to some specific embodiments of this disclosure. The semiconductor device 500 may be implemented using a 3D stacked memory architecture. Wafers 501D and 501L of the semiconductor device 500 may be stacked vertically using a composite bonding process or other suitable processes. Each memory chip 502 formed on wafer 501D (in...) Figure 5 The logic chip 503 (referred to as "MC") formed on substrate 501L can be implemented as a DRAM chip. Figure 5 The components (referred to as "CLC") are used to control the operation of memory chip 502. In this specific embodiment, each logic chip 503 may include, but is not limited to, an input buffer 504, a command decoder 505, a pre-decoder 506, a decoder 507, a driver 508, and a secondary sensing circuit 509, which are respectively similar to... Figure 2 The input buffer 220, command decoder 230, pre-decoder 240, decoder 250, driver 260, and secondary sensing circuit decoder 270 are included; therefore, their detailed descriptions are omitted. The logic chip 503 may further include a controller 510. The controller 510 can control the operation of the memory chip 502, input buffer 504, command decoder 505, pre-decoder 506, decoder 507, driver 508, and secondary sensing circuit 509.

[0020] Figure 6A According to some specific embodiments of this disclosure, Figure 5 A top view of the memory block 600 of the memory chip 502. Each memory chip 502 includes one or more memory blocks 600. The memory block 600 includes multiple MATs 610. Each MAT 610 includes a memory array 612 (e.g., a DRAM memory array), a sensing circuit 614, and a driving circuit 616, wherein the memory array 612 is connected to the sensing circuit 614 and the driving circuit 616. Figure 6B This is a circuit diagram of a memory array 612 according to some specific embodiments of this disclosure. The memory array 612 includes multiple word lines WL, multiple bit lines BL, and multiple memory cells CE located at the intersections of the word lines WL and the bit lines BL. The memory cells CE may be DRAM memory cells. For example, each memory cell CE of the memory array 612 may be a single-transistor single-capacitor (1T1C) memory cell. The first terminal of each capacitor in the memory cell CE may be connected to a transistor in the same memory cell CE. The second terminal of the capacitors in a group of memory cells CE (e.g., but not limited to capacitors arranged in rows or columns) may be connected to a common electrode 60.

[0021] Please refer to it again. Figure 6AFrom a top view of the memory block 600 of the memory chip 502, it can be seen that a sensing circuit 614 is disposed in a first region R1; a memory array 612 is disposed in a second region R2; and a driving circuit 616 is disposed in a third region R3. The second region R2 is adjacent to the first region R1 and the third region R3. During a read operation, the sensing circuit 614 can amplify a small voltage difference on the bit line BL of the memory array 612. The driving circuit 616 can provide the necessary current and voltage levels to selectively activate one of the word lines WL of the memory array 612 to select a specific column of the memory cell CE.

[0022] MAT 610 further includes multiple first solder pads 620, multiple second solder pads 630, and multiple third solder pads 640. The first solder pads 620 are disposed in a first region R1 and above the sensing circuit 614. The first solder pads 620 are connected to the sensing circuit 614 via generally vertically extending traces. The second solder pads 630 are disposed in a second region R2 and above the memory array 612. The second solder pads 630 are connected to the memory array 612 via generally vertically extending traces. The third solder pads 640 are disposed in a third region R3 and above the driving circuit 616. The third solder pads 640 are connected to the driving circuit 616 via generally vertically extending traces. The first solder pads 620, second solder pads 630, and third solder pads 640 are electrically connected to the logic chip 503. Therefore, the logic chip 503 can access MAT 610 via the first solder pads 620, second solder pads 630, and third solder pads 640.

[0023] In this specific embodiment, the first solder pad 620, the second solder pad 630, and the third solder pad 640 may be arranged in an alternating manner. For example, the first solder pad 620 forms multiple columns extending along direction X and multiple rows extending along direction Y, wherein directions X and Y are perpendicular to each other. Each column of the first solder pad 620 is staggered with adjacent columns in direction Y. Each row of the first solder pad 620 is staggered with adjacent columns in direction X. In some specific embodiments, the spacing between two adjacent first solder pads 620 is less than 2 µm. The spacing may be the distance from the center of one first solder pad 620 to the center of another first solder pad 620. The above description of the first solder pad 620 also applies to the second solder pad 630 and the third solder pad 640. Figure 6A The configuration of the first pad 620, the second pad 630, and the third pad 640 is merely exemplary and is not intended to limit the scope of this disclosure. In some specific embodiments, the first pad 620 may be arranged in a rectangular array, and the same method may be applied to the second pad 630 and the third pad 640.

[0024] Figure 7 According to some specific embodiments of this disclosure, along Figure 6A A cross-sectional view of MAT 610 from the AA' line. Please refer to the following: Figure 5 and Figure 7 Note that wafer 501D is flipped over and connected to wafer 501L. In this flipped configuration, the top surface S1 of the substrate 710 of wafer 501D faces wafer 501L. However, regardless of whether wafer 501D is flipped, substrate 710 is considered the bottom layer of wafer 501D, and other layers of wafer 501D may be formed above the top surface S1 of substrate 710. For example, device layer 720 and dielectric layer 730 are sequentially formed above the top surface S1 of substrate 710. Therefore, the term "above" as used herein refers to the relative position of layers formed on or above the top surface S1 of substrate 710, regardless of the orientation of wafer 501D during bonding.

[0025] Device layer 720 may comprise a single layer or multiple layers of different materials. These materials may include semiconductors, insulators, conductors, or combinations thereof. For example, device layer 720 may include active electronic devices (e.g., transistors), passive electronic devices (e.g., resistors, capacitors, and inductors), and wires connecting these devices. Sensing circuitry 614 may be formed in device layer 720. Dielectric layer 730 may comprise a single layer or multiple layers of different materials. A plurality of data segments 732 of sensing circuitry 614 are formed in dielectric layer 730. Data segments 732 may transmit the output of sensing circuitry 614.

[0026] A first pad 620 is formed in the dielectric layer 730 above the data line segment 732 of the sensing circuit 614, and the first pad 620 is exposed from the dielectric layer 730. Each data line segment 732 can be electrically connected to the corresponding first pad 620 through one or more vias, contacts, wires, or vertical stacking combinations thereof. The number of component layers between the data line segment 732 and the first pad 620 is merely an example and is not intended to limit the scope of this disclosure. The first pad 620 can be used to provide the output of the sensing circuit 614 to the secondary sensing circuit 509 of the logic chip 503. Each first pad 620 has a vertical projection 740 on the top surface of the device layer 720, which overlaps with the sensing circuit 614. In other words, when viewed from the top of MAT 610 (i.e., along direction Z), the first pad 620 overlaps with the sensing circuit 614, where directions X, Y, and Z are perpendicular to each other.

[0027] Figure 8 According to some specific embodiments of this disclosure, along Figure 6A A cross-sectional view of MAT 610 of the BB' in the middle layer. A memory array 612 is formed within the device layer 720. Multiple power lines 734 are formed in the dielectric layer 730. The power lines 734 are electrically connected to the memory array 612 to provide the voltage required for the operation of the memory array 612. In some specific embodiments, the power lines 734 include one or more common electrodes 60 (e.g., ...). Figure 6BAs shown), it is connected to capacitors of multiple memory cells CE. Power line 734 can be used to provide supply voltage (e.g., the highest voltage in memory array 612), ground voltage, or any suitable capacitor plate potential for the multiple capacitors.

[0028] A second pad 630 is formed in the dielectric layer 730 above the power line 734 and is exposed from the dielectric layer 730. Each power line 734 can be electrically connected to the corresponding second pad 630 through one or more via layers, contacts, wires, or a vertical stacking combination thereof. The number of component layers between the power line 734 and the second pad 630 is merely an example and is not intended to limit the scope of this disclosure. The second pad 630 can be used to receive the voltage required for the operation of the memory array 612 from the driver 508 of the logic chip 503. Each second pad 630 has a vertical projection 750 on the top surface of the device layer 720, which overlaps with the memory array 612. In other words, when viewed from the top of the MAT 610 (i.e., along direction Z), the second pad 630 overlaps with the memory array 612.

[0029] Figure 9 According to some specific embodiments of this disclosure, along Figure 6A A cross-sectional view of the MAT 610 with a middle line CC'. A drive circuit 616 is formed within the device layer 720. Multiple drive lines 736 are formed in the dielectric layer 730. The drive lines 736 are electrically connected to the drive circuit 616 to provide the voltage required to start the word line WL of the MAT 610.

[0030] A third pad 640 is formed in dielectric layer 730 above drive line 736 and is exposed from dielectric layer 730. Each drive line 736 can be electrically connected to the corresponding third pad 640 through one or more via layers, contacts, wires, or combinations thereof in a vertical stack. The number of component layers between drive line 736 and third pad 640 is merely an example and is not intended to limit the scope of this disclosure. The third pad 640 can be used to receive a global enable signal GE (e.g., ...) from driver 508 of logic chip 503. Figure 5 (as shown), and transmits the global enable signal GE to the drive circuit 616 to activate the drive circuit 616. The third pad 640 can also be used to receive the local column enable signal RE (as shown). Figure 5As shown), the local bar enable signal is transmitted to the drive circuit 616. The drive circuit 616 can activate a specific word line WL of the memory array 612 according to the local bar enable signal. In some specific embodiments, the global enable signal GE and the local bar enable signal can be thermally independent signals. Each third pad 640 has a vertical projection 760 on the top surface of the device layer 720, which overlaps with the drive circuit 616. In other words, when viewed from the top of the MAT 610 (i.e., along direction Z), the third pad 640 overlaps with the drive circuit 616.

[0031] Figure 10 This is a cross-sectional view of a semiconductor device 500 according to some specific embodiments of this disclosure. Wafer 501D is flipped to be face-to-face with wafer 501L. That is, the substrate 710 of wafer 501D is away from wafer 501L, while the top surface S1 of the substrate 710 of wafer 501D faces wafer 501L. Wafer 501L includes a substrate 101, a device layer 103, and a dielectric layer 105. Device layer 103 may comprise a single layer or multiple layers of different materials. These materials may include semiconductors, insulators, conductors, or combinations thereof. For example, device layer 103 may include active electronic devices (e.g., transistors), passive electronic devices (e.g., resistors, capacitors, and inductors), and wires connecting these devices. Logic chip 503 may be formed in device layer 103. Dielectric layer 105 is formed above device layer 103. Dielectric layer 730 may comprise a single layer or multiple layers of different materials.

[0032] Wafer 501L further includes multiple fourth bonding pads 650, multiple fifth bonding pads 660, and multiple sixth bonding pads 670, which are formed in and exposed from dielectric layer 105. The fourth bonding pads 650, fifth bonding pads 660, and sixth bonding pads 670 of wafer 501L can be directly connected to the first bonding pad 620, second bonding pad 630, and third bonding pad 640 of wafer 501D, respectively. The fourth bonding pads 650, fifth bonding pads 660, and sixth bonding pads 670 can be part of logic chip 503 and are electrically connected to device layer 103. Wafers 501L and 501D can be constructed using face-to-face stacked wafer-to-wafer bonding. The bonding of wafers 501L and 501D can be achieved through hybrid bonding. For example, the fourth pad 650, fifth pad 660, and sixth pad 670 of wafer 501L are aligned with the first pad 620, second pad 630, and third pad 640 of wafer 501D, respectively. The pads then form direct metallic bonds, and the dielectric layer forms covalent bonds. Annealing can then be performed, which helps reduce voids and improve the mechanical and electrical integrity of the composite bonding structure.

[0033] Wafer 501L further includes multiple through-silicon vias (TSVs) 113. The TSVs 113 penetrate the substrate 101 of wafer 501L, electrically connecting device layer 103 to multiple bumps 115. Therefore, logic chip 503 may include TSVs 113. Before forming the TSVs 113, the substrate 101 of wafer 501L may undergo chemical mechanical planarization (CMP) to reduce the thickness of substrate 101 in the Z-direction. Therefore, the thickness of substrate 101 in the Z-direction can be less than the thickness of substrate 710. Note that... Figure 10 In a specific embodiment, the memory chip 502 and the wafer 501D may not have a TSV.

[0034] Figure 11 This is a cross-sectional view of a semiconductor device 500 according to some specific embodiments of this disclosure. Figure 11 Specific embodiments and Figure 10 The specific embodiments are similar; therefore, only the differences are described below. Wafer 501D further includes a plurality of TSVs 117. The TSVs 117 penetrate the substrate 710 of wafer 501D, electrically connecting the device layer 720 to a plurality of bumps 119. Therefore, memory chip 502 may include TSVs 117. Before forming the TSVs 117, the substrate 710 of wafer 501D may be subjected to CMP processing to reduce the thickness of substrate 710 in the Z direction. Therefore, the thickness of substrate 710 in the Z direction may be less than the thickness of substrate 101. Note that... Figure 11 In a specific embodiment, the logic chip 503 and the wafer 501L may not have a TSV.

[0035] Figure 12 To illustrate some specific embodiments of this disclosure, a functional block diagram of the columns formed by MAT m[0] to m[7] is shown. Each MAT m[0] to m[6] is similar to Figure 6A MAT 610. Except that MAT m[7] may not include sensing circuitry 614 and first pad 620, MAT m[7] also... Figure 6A Similar to MAT 610. Therefore, the column formed by MAT m[0] to m[7] can be one of the columns of memory block 600 in FIG. 6. The number of MATs in this column is merely an example and is not intended to limit the scope of this disclosure. Each sensing circuit 614 is disposed between two adjacent memory arrays 612 and is shared by these two adjacent memory arrays 612. In other words, each first region R1 is located between two adjacent second regions R2. In some specific embodiments, when one of MAT m[0] to m[7] is activated, the adjacent MATs that share the sensing circuit 614 with the activated MAT are in an inactive state. For example, when MAT m[1] is activated, MAT m[0] and m[2] are in an inactive state.

[0036] For a column of the memory array 612 disposed between two sensing circuits 614, a portion of the memory cells in the column are connected to one of the sensing circuits 614, while another portion of the memory cells in the column are connected to the other sensing circuit 614. For example, a portion of the memory cells in the column MAT m[1] are connected to the sensing circuit 614 between MAT m[1] and MAT m[0], while another portion of the memory cells in the column MAT m[1] are connected to the sensing circuit 614 between MAT m[1] and MAT m[2]. In other words, the sensing circuit 614 can access data associated with two adjacent MATs. Therefore, by sharing the sensing circuit 614, the overall circuit area can be reduced.

[0037] Figure 13 The circuit diagram of MAT m[0] according to some specific embodiments of this disclosure document. Figure 12 MAT m[1] to m[6] in the MAT can have the same as Figure 13 A similar circuit configuration is shown. MAT m[0] contains multiple word lines WL and multiple bit lines BL perpendicular to the word lines WL. MAT m[0] also contains multiple memory cells CE ( Figure 13 (Not shown in the image), these memory cells are located at the intersection of word line WL and bit line BL. Word line WL is connected to drive circuit 616, while bit line BL is connected to detection circuit 614.

[0038] The sensing circuit 614 includes multiple data lines 732, multiple sensing amplifiers SA, and column selection circuit 810. Therefore, from a top view of the memory chip 502, the data lines 732, sensing amplifiers SA, and column selection circuit 810 are located in the first region R1. The column selection circuit 810 is used to selectively connect the sensing amplifiers SA to the multiple data lines 732 according to multiple column selection signals CSL0_0 / CSL0_1, CSL1_0 / CSL1_1, ..., CSLn_0 / CSLn_1. Therefore, the output of the sensing amplifiers SA is selectively transmitted to the first pad 620. The column selection circuit 810 includes multiple column selection units SU[0] to SU[n], where n is a positive integer. Column selection unit SU[0] is controlled by column selection signals CSL0_0 and CSL0_1; column selection unit SU[1] is controlled by column selection signals CSL1_0 and CSL1_1, and so on. The column selection signal pairs CSL0_0 / CSL0_1, CSL1_0 / CSL1_1, ..., CSLn_0 / CSLn_1 can be the same or different. For example, when the column selection signal pairs CSL0_0 / CSL0_1, CSL1_0 / CSL1_1, ..., CSLn_0 / CSLn_1 are the same, the column selection signals CSL0_0, CSL1_0, ..., CSLn_0 can be activated simultaneously, and the column selection signals CSL0_1, CSL1_1, ..., CSLn_1 can be activated simultaneously. In some specific embodiments, the column selection signals in each pair can be different. For example, the column selection signals CSL0_0 and CSL0_1 can be opposite to each other.

[0039] Data segment 732 is connected to the first solder pad 620 through multiple through-holes VA. Through-holes VA indicate mating. Figure 7 The discussion concerns one or more vias located between a pair of data lines 732 and the first pad 620. In some specific embodiments, the number of bits (i.e., memory cells CE) on each word line WL is less than 688; that is, the number of bit lines BL is less than 688. When each word line WL has k bits (i.e., k bit lines BL), MAT m[0] may contain k / 2+1 data lines 732, where k is a positive integer or k / 2 is a positive integer.

[0040] Figure 14 This is a circuit diagram of a column selection unit SU[0] according to some specific embodiments of this disclosure. Figure 13 Other column selection units SU[1] to SU[n] in the table can have the same characteristics as... Figure 14 A similar circuit configuration is shown. The column selection unit SU[0] is connected to multiple sense amplifiers SA (hereinafter referred to as "sense amplifiers SA0 to SA15"). The column selection unit SU[0] includes multiple first transistors T1[0] to T1[7] and multiple second transistors T2[0] to T2[7]. Figure 14 The number of components shown is merely illustrative and is not intended to limit the scope of this disclosure.

[0041] The first transistors T1[0] to T1[7] are controlled by the column select signal CSL0_0. The second transistors T2[0] to T2[7] are controlled by the column select signal CSL0_1. In some specific embodiments, the first transistors T1[0] to T1[7] and the second transistors T2[0] to T2[7] are N-type transistors. The first terminal of each first transistor T1[0] to T1[7] is connected to the corresponding sense amplifier SA through the corresponding bit line BLB, and the second terminal of each first transistor T1[0] to T1[7] is connected to the corresponding data line 732; the same configuration also applies to the second transistors T2[0] to T2[7]. In other words, the first transistors T1[0] to T1[7] are connected to a set of sense amplifiers SA0, SA1, SA4, SA5, SA8, SA9, SA12 and SA13, while the second transistors T2[0] to T2[7] are connected to another set of sense amplifiers SA2, SA3, SA6, SA7, SA10, SA11, SA14 and SA15. In this specific embodiment, each data segment 732 can be connected to a maximum of two sense amplifiers SA; however, this disclosure is not limited thereto.

[0042] like Figure 14 As shown, data segments 732 (hereinafter referred to as "data segments 732[0] to 732[8]") are arranged horizontally in a first order. This horizontal direction can be compared with... Figure 6A The planes formed by the X and Y directions are parallel; however, this disclosure is not limited thereto. That is, data segments 732[0] to 732[8] are arranged sequentially from left to right. The first transistors T1[0] to T1[7] are arranged horizontally in a second order. That is, the first transistors T1[0] to T1[7] are arranged sequentially from left to right. The second transistors T2[0] to T2[7] are arranged horizontally in a third order. That is, the second transistors T2[0] to T2[7] are arranged sequentially from left to right. The first data segment 732[0] in the first order is connected to the first transistor T1[0] in the second order and is not connected to any second transistor. The last data segment 732[8] in the first order is connected to the last second transistor T2[7] in the third order and is not connected to any first transistor. Each of the remaining data segments 732[1] to 732[7] is connected to the corresponding first transistor and the corresponding second transistor. For example, data segment 732[1] is connected to the first transistor T1[1] and the second transistor T2[0].

[0043] The first transistors T1[0] to T1[7] and the second transistors T2[0] to T2[7] are arranged alternately. A group of transistors containing two first transistors is arranged alternately with a group of transistors containing two second transistors. For example, a group of transistors containing second transistors T2[0] and T2[1] is positioned between a group of transistors containing first transistors T1[0] and T1[1] and a group of transistors containing first transistors T1[2] and T1[3]. In addition, data segments 732[0] to 732[8] are arranged alternately. For example, data segments 732[0] to 732[8] are arranged horizontally, but when viewed from the horizontal direction, they are staggered. The vertical distances of two adjacent data segments to the column select circuit 810 are different. That is, data segments 732[0] to 732[8] are arranged with an alternate distribution pattern in the horizontal direction. However, this disclosure is not limited to this. In some specific embodiments, data segments 732[0] to 732[8] may be aligned with each other in the horizontal direction. That is, data segments 732[0] to 732[8] are configured to have a straight line pattern in the horizontal direction.

[0044] Figure 15 The circuit diagram illustrating the connection configuration of the column selection unit SU[0] between MAT m[0] and MAT m[1] is shown below according to some specific embodiments of this disclosure. Figure 14 and Figure 15 In some specific embodiments, the sense amplifiers SA0 to SA15 may be latched, each including a first input and a second input. The first inputs of the sense amplifiers SA0 to SA15 are respectively connected to the bit lines BL of MAT m[0] (referred to as "bit lines BL0 to BL15"). The second inputs of the sense amplifiers SA0 to SA15 are respectively connected to the bit lines BL of MAT m[1] (referred to as "bit lines BLB0 to BLB15"). In some embodiments, since adjacent MATs do not start simultaneously, the sense amplifiers SA0 to SA15 may each be coupled to the adjacent MAT through only one bit line. For example, please refer to Figure 15 Bit lines BL0 and BLB0 can be connected to each other to form a single conductor, and bit lines BL1 and BLB1 can be connected to each other to form a single conductor, and so on.

[0045] Figure 16 This is a top view of MAT m[0] according to some specific embodiments of this disclosure. Figure 6A Similarly, MAT m[0] includes a first pad 620 in a first region R1, a second pad 630 in a second region R2, and a third pad 640 in a third region R3. The difference is that the first pad 620 of MAT m[0] includes a plurality of first specific pads 622 (i.e. Figure 16 The white square shown) and multiple second specific solder pads 624 (i.e. Figure 16 (The black square shown). The second specific pad 624 is connected to the column select circuit 810 and is used to receive column select signals CSL0_0 / CSL0_1, CSL1_0 / CSL1_1, ..., CSLn_0 / CSLn_1 from the logic chip 503. The second specific pad 624 is disposed in the first region R1 and above the sensing circuit 614. Figure 7 Similarly, the vertical projection of the second specific solder pad 624 is projected onto the top surface of the device layer 720, overlapping with the sensing circuit 614. The second specific solder pad 624 is interposed between the first specific solder pads 622. Viewed from direction X, the first specific solder pads 622 and the second specific solder pads 624 are arranged side by side. For example, each second specific solder pad 624 is disposed between two first specific solder pads 622. However, this disclosure is not limited thereto. In some embodiments, the second specific solder pads 624 are disposed near the edge of the array formed by the first solder pads 620, such that only one side of each second specific solder pad 624 is adjacent to a first specific solder pad 622.

[0046] Table 1 shows Figure 1 Memory chip 110 and Figure 5 Comparison of signal delays between memory chips 502.

[0047] Table 1

[0048] Compared to memory chip 110, memory chip 502 reduces signal latency by removing secondary sensing circuitry, a decoder, a driver, and the global word line connecting the driver and MAT. Furthermore, since the signal activating the local word line WL in MAT 610 can be received from the third pad 640 above the local drive circuit 616, the local drive circuit 616 can be configured compactly. Therefore, the length of the local word line WL can be shortened, thereby reducing RC delay on the local word line WL.

[0049] exist Figure 1 In the illustrated memory chip 110, multiple sense amplifiers share a single long global data line. In contrast, memory chip 502 replaces the global data line with data segments 732, each shared by no more than two sense amplifiers SA, thereby eliminating signal delay caused by the global data line and improving output bandwidth. Furthermore, the shorter wiring length from the sensing circuit 614 to the first pad 620 reduces the output load of the sensing circuit 614, thereby reducing signal delay caused by the sensing circuit 614 and the output wiring.

[0050] According to Table 1, the signal delay (i.e., access time) of memory chip 502 is less than 5 ns. Furthermore, according to circuit simulations, the power consumption of memory chip 502 is approximately 0.03 pJ / bit, and its bandwidth is comparable to SRAM. Therefore, semiconductor device 500 and memory chip 502 (which may include DRAM cells) are suitable for high-speed operations. For example, memory chip 502 is suitable as a replacement for SRAM to implement high-density level 1 to level 3 cache.

[0051] The features of several specific embodiments outlined above enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other operations and structures to achieve the same purpose and / or realize the same advantages of the specific embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0052] Symbol Explanation 100: Semiconductor devices 110, 302, 502: Memory chips 101: Substrate 103: Device Layer 105: Dielectric layer 113, 117: Through-silicon vias 115, 119: Bumps 120, 303, 503: Logic chips 130, 710: Substrate 200, 400: Memory blocks 210, 410, 610: Memory Array Chip (MAT) 212, 412, 612: Memory arrays 214, 414, 614: Sensing circuits 216, 416, 616: Drive circuit 220, 304, 504: Input buffers 230, 305, 505: Command decoder 240, 440, 506: Pre-decoder 250, 450, 507: Decoders 260, 460, 508: Drivers 270, 470, 509: Secondary sensing circuit 280: Sequence Peripheral Interface 290: Input / Output Circuit 300, 500: Semiconductor devices 301D, 301L, 501D, 501L: Wafers 306: Controller 420, 430: Keypad 510: Controller 600: Memory Block 620: First solder pad 622: First Specific Pad 624: Second Specific Pad 630: Second solder pad 640: Third solder pad 650: Fourth solder pad 660: Fifth solder pad 670: Sixth solder pad 720: Device Layer 730: Dielectric layer 732: Data segment 734: Power cord 736: Drive line 740, 750, 760: Projection 810: Circuit S1: Top surface WL: Wordline BL: Bitline CE: Memory Unit GE: Signal enabled across the entire region RE: Local column enable signal SA: Sensing Amplifier SU: Column Selection Cell R1: First Region R2: Second Region R3: Third Region VA: Through Hole X, Y, Z: Direction

Claims

1. A memory chip, characterized in that, include: One substrate; as well as A plurality of memory array chips are disposed above the substrate, wherein at least one of the plurality of memory array chips comprises: A sensing circuit, wherein, viewed from a top view of the memory chip, the sensing circuit is disposed in a first region; A memory array, wherein, viewed from a top view of the memory chip, the memory array is located in a second region adjacent to the first region and is electrically connected to the sensing circuit; and A plurality of first solder pads are disposed in the first region as viewed from a top view of the memory chip, wherein the plurality of first solder pads are disposed above the sensing circuit, wherein the plurality of first solder pads are electrically connected to the sensing circuit and are used to provide the output of the sensing circuit.

2. The memory chip as claimed in claim 1, characterized in that, The memory array includes multiple power lines, wherein the at least one memory array chip further includes: Multiple second solder pads, wherein, viewed from a top view of the memory chip, the multiple second solder pads are disposed in the second region, wherein the multiple second solder pads are disposed above the memory array, wherein the multiple second solder pads are electrically connected to the multiple power lines.

3. The memory chip as claimed in claim 2, characterized in that, The memory array includes multiple capacitors. The plurality of power lines are electrically connected to the plurality of capacitors. Each of the plurality of power lines is used to provide a power supply voltage, a ground voltage, or a capacitor plate potential to the plurality of capacitors.

4. The memory chip as claimed in claim 1, characterized in that, The at least one memory array chip further includes: A driving circuit, wherein, viewed from a top view of the memory chip, the driving circuit is located in a third region adjacent to the second region, wherein the driving circuit is used to selectively activate one of a plurality of word lines in the memory array; and Multiple third pads, wherein, from a top view of the memory chip, the multiple third pads are located in the third region, wherein the multiple third pads are disposed above the drive circuit, and wherein the multiple third pads are electrically connected to the drive circuit.

5. The memory chip as claimed in claim 1, characterized in that, The sensing circuit includes: Multiple data segments, wherein, from a top view of the memory chip, the multiple data segments are disposed in the first region, and the multiple data segments are connected to the multiple first pads; Multiple sense amplifiers; and A column selection circuit is used to selectively connect the plurality of sense amplifiers to the plurality of data segments according to a plurality of column selection signals, wherein each of the plurality of column selection signals is the same as or different from each other.

6. The memory chip as claimed in claim 5, characterized in that, The plurality of first pads include a plurality of first specific pads electrically connected to the plurality of data line segments, and a plurality of second specific pads electrically connected to the column select circuit.

7. The memory chip as claimed in claim 6, characterized in that, From a top view of the memory chip, the plurality of second specific pads are inserted between the plurality of first specific pads.

8. The memory chip as claimed in claim 6, characterized in that, From a top view of the memory chip, the plurality of first specific pads and the plurality of second specific pads are arranged side by side.

9. The memory chip as claimed in claim 5, characterized in that, From a top view of the memory chip, the plurality of data segments are arranged in an alternating pattern along a specific direction.

10. The memory chip as claimed in claim 5, characterized in that, From a top view of the memory chip, the plurality of data segments are arranged to have a straight line pattern along a specific direction.

11. The memory chip as claimed in claim 1, characterized in that, One of the plurality of memory array chips does not have the sensing circuit and the plurality of first bonding pads. Each first region is located between two adjacent second regions, and each sensing circuit is shared by two adjacent memory arrays.

12. The memory chip as claimed in claim 1, characterized in that, The plurality of first pads of the at least one memory array chip are configured to be electrically connected to a plurality of fourth pads of the logic chip via a composite bonding structure.

13. A semiconductor device, characterized in that, include: A memory chip includes a substrate and a plurality of memory array chips disposed above the substrate of the memory chip, wherein at least one of the plurality of memory array chips includes a sensing circuit, a memory array electrically connected to the sensing circuit, and a plurality of first pads electrically connected to the sensing circuit and used to provide the output of the sensing circuit. And a logic chip, including: One substrate; as well as Multiple fourth bonding pads, as seen in the cross-sectional view of the logic chip, are located on the substrate of the logic chip. The plurality of first pads of the at least one memory array chip are directly connected to the plurality of fourth pads of the logic chip.

14. The semiconductor device of claim 13, characterized in that, The memory array includes multiple power lines, wherein the at least one memory array chip further includes: Multiple second solder pads are electrically connected to the multiple power lines; The logic chip further includes a plurality of fifth bonding pads disposed above the substrate of the logic chip, and the plurality of fifth bonding pads of the logic chip are directly connected to the plurality of second bonding pads of the at least one memory array chip.

15. The semiconductor device of claim 14, characterized in that, The memory array includes multiple capacitors, and the multiple power lines are used to provide supply voltage, ground voltage, or capacitor plate potential to the multiple capacitors through the multiple second pads and the multiple fifth pads.

16. The semiconductor device of claim 13, characterized in that, The at least one memory array chip further includes: A driver circuit for selectively activating one of multiple word lines in the memory array; and Multiple third bonding pads are electrically connected to the drive circuit; The logic chip further includes a plurality of sixth bonding pads disposed above the substrate of the logic chip, and the plurality of sixth bonding pads of the logic chip are directly connected to the plurality of third bonding pads of the at least one memory array chip.

17. The semiconductor device of claim 16, characterized in that, This logic chip is used for: A global enable signal is provided to the drive circuit via the plurality of third and sixth solder pads to activate the drive circuit. A partial bar enable signal is provided to the driving circuit via the plurality of third pads and the plurality of sixth pads, wherein the driving circuit is configured to activate one of the plurality of word lines of the memory array according to the partial bar enable signal.

18. The semiconductor device of claim 13, characterized in that, The plurality of first pads on the memory chip and the plurality of fourth pads on the logic chip are interconnected by a composite bonding structure.

19. The semiconductor device of claim 13, characterized in that, The logic chip further includes a device layer electrically connected to the plurality of fourth bonding pads, wherein, as seen in a cross-sectional view of the logic chip, the device layer is disposed above the substrate of the logic chip, and the semiconductor device further includes: Multiple through-silicon vias penetrate the substrate of the logic chip to electrically connect to the device layer of the logic chip. This memory chip does not have through-silicon vias.

20. The semiconductor device of claim 13, characterized in that, The memory chip further includes a device layer electrically connected to the plurality of first bonding pads, wherein, as seen in a cross-sectional view of the memory chip, the device layer is disposed above the substrate of the memory chip, wherein the plurality of memory array wafers are disposed within the device layer, and the semiconductor device further includes: Multiple through-silicon vias penetrate the substrate of the memory chip to electrically connect to the device layer of the memory chip. This logic chip does not have through-silicon vias.

Images