Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate including a cell region and a peripheral region; a first contact disposed in the peripheral region; a first interlayer dielectric layer disposed on the first contact; a via electrode disposed in the peripheral region, penetrating the first interlayer dielectric layer and the substrate; and a second interlayer dielectric layer disposed on the first interlayer dielectric layer and covering a side surface and an upper surface of the via electrode.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2025-0053108, filed on April 23, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0002] Embodiments of this disclosure relate to controllers and storage devices. Background Technology

[0003] As the integration density of semiconductor devices continues to increase, the spacing between wirings within these devices is gradually decreasing. When the spacing between wirings decreases, interference phenomena (e.g., short circuits or parasitic capacitances) may occur between adjacent wirings. Such interference phenomena can adversely affect process stability and device reliability. Therefore, technical solutions for controlling these phenomena are becoming increasingly important. Summary of the Invention

[0004] Embodiments of this disclosure may provide a semiconductor device and a method for manufacturing the same, which can minimize interference between adjacent wirings.

[0005] Embodiments of this disclosure may provide a semiconductor device including a substrate having a cell region and a peripheral region. The semiconductor device may include: a first contact disposed in the peripheral region; a first interlayer dielectric layer disposed on the first contact; a via electrode disposed in the peripheral region, penetrating at least a portion of the first interlayer dielectric layer and the substrate; and a second interlayer dielectric layer disposed on the first interlayer dielectric layer and covering the side and top surfaces of the via electrode.

[0006] Embodiments of this disclosure may provide a semiconductor device comprising: a substrate including a cell region and a peripheral region; a first contact disposed on the substrate; a first interlayer dielectric layer disposed on the first contact; a via electrode penetrating at least a portion of the substrate and having its upper surface positioned above the upper surface of the first contact; and a second interlayer dielectric layer surrounding at least a portion of the side surface of the via electrode and spaced apart from the first contact.

[0007] Embodiments of this disclosure may also provide a method for manufacturing a semiconductor device. The method may include: forming a first contact on a substrate; forming a first interlayer dielectric layer covering the first contact; forming a nitride layer on the first interlayer dielectric layer; forming a via electrode penetrating at least a portion of the first interlayer dielectric layer and the nitride layer; removing residual portions of the first nitride layer; and forming a second interlayer dielectric layer on the first interlayer dielectric layer, such that the second interlayer dielectric layer contacts the upper and side surfaces of the via electrode.

[0008] According to embodiments of this disclosure, interference between adjacent wirings can be minimized.

[0009] The effects of the embodiments disclosed herein are not limited to those described above, and those skilled in the art will clearly understand other effects not mentioned based on the appended claims. Attached Figure Description

[0010] This disclosure will be more fully understood from the following detailed description and accompanying drawings. The following detailed description and accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0011] Figure 1 This is a cross-sectional view illustrating an example of a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 2 yes Figure 1 A magnified view of region 140 in the image.

[0013] Figures 3 to 11 This is a cross-sectional view used to describe a method of manufacturing a semiconductor device according to embodiments of the present disclosure.

[0014] Figure 12 This is a cross-sectional view of a semiconductor device according to another embodiment of the present disclosure. Detailed Implementation

[0015] In the following description of examples or embodiments of this disclosure, reference will be made to the accompanying drawings. The drawings illustrate specific examples or embodiments that may be implemented, and in the drawings, even when the same reference numerals and symbols are shown in different drawings, they may be used to indicate the same or similar components. Furthermore, in the following description of examples or embodiments of this disclosure, detailed descriptions of well-known functions and components included therein will be omitted where it is determined that such detailed descriptions would obscure the subject matter in some embodiments of this disclosure. Terms such as “comprising,” “having,” “including,” “constituting,” “made of,” and “formed from” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Unless the context clearly indicates otherwise, the singular forms used herein are intended to include the plural forms.

[0016] The elements of this disclosure may be described in this document using terms such as “first,” “second,” “A,” “B,” “(A),” or “(B).” These terms are not intended to define the nature, order, sequence, or number of the elements, but are only used to distinguish the corresponding element from other elements.

[0017] When referring to a first element as being "connected or coupled to," "in contact with," or "overlapping" with a second element, it should be interpreted as follows: the first element can not only be "directly connected or coupled to" or "directly contact with or overlap with" the second element, but a third element can also be "inserted" between the first and second elements; or the first and second elements can be "connected or coupled," "in contact with," or "overlapping" with each other through a fourth element, and so on. Here, the second element can be included in at least one of two or more elements that are "connected or coupled," "in contact with," or "overlapping" with each other.

[0018] When time-related terms such as “after,” “following,” “next,” or “before” are used to describe the processing, operation, or flow or step in a method of running, handling, or manufacturing of an element or configuration, these terms may be used to describe non-continuous or non-sequential processing or operation unless used with the terms “directly” or “immediately following.”

[0019] Furthermore, when referring to any size, relative dimensions, etc., even if no specific description is given, it should be assumed that the numerical values ​​or corresponding information (e.g., grades, ranges, etc.) for a component or feature include tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external shocks, noise). Moreover, the term "may" fully encompasses all the meanings of the term "able to".

[0020] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0021] Figure 1 A cross-sectional view of a semiconductor device according to an embodiment of the present disclosure is shown. Figure 2 for Figure 1 A magnified view of the central region 140.

[0022] Reference Figure 1 and Figure 2 The semiconductor device may include: a substrate 100, a gate insulating layer 101, a gate 102, a lower contact plug 103, a lower wiring 104, a first contact 105, a via electrode 106, a via electrode blocking layer 107, a first wiring 108, a second wiring 109, a gate structure 110, a bit line contact 114, a bit line 115, a contact plug 116, a landing pad 117, a dielectric layer 118, a first electrode 119, a second electrode 120, a second contact 121, a third wiring 122, an isolation insulating layer 130, a first cover layer 131, a second cover layer 132, a third cover layer 133, a first interlayer dielectric layer 134, a second interlayer dielectric layer 135B, and a third interlayer dielectric layer 136.

[0023] Substrate 100 (or gate structure 110) may include a semiconductor substrate, such as a silicon wafer or a silicon-on-insulator (SOI) wafer. Substrate 100 may also include a III-V compound semiconductor substrate, such as a gallium arsenide (GaAs) substrate. Substrate 100 may include monocrystalline silicon, polycrystalline silicon, amorphous silicon, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, or combinations thereof.

[0024] Although not illustrated, substrate 100 may include at least one device isolation layer in the cell region CR and the peripheral region PR. The device isolation layer may be formed using trench isolation techniques (e.g., shallow trench isolation (STI)). The device isolation layer may include silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, or a combination thereof.

[0025] In the cell region CR, the gate structure 110 may include a word line 111, a gate insulating layer 112, and a gate capping layer 113. The upper surface of the word line 111 may be positioned below the upper surface of the substrate 100. The word line 111 may be a buried gate or a buried word line. The gate capping layer 113 may be disposed on the word line 111. The gate insulating layer 112 may surround the sidewalls of the word line 111 and the gate capping layer 113.

[0026] Word line 111 may include a conductive material, such as a metal, metal oxide, metal nitride, metal silicide, polysilicon, conductive carbon, or a combination thereof. Gate capping layer 113 may include silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, or a combination thereof. In some embodiments, gate capping layer 113 may include a high-k material.

[0027] The isolation insulating layer 130, the lower contact plug 103, the gate insulating layer 101, the gate 102, the bit line contact 114, and the contact plug 116 can be disposed on the substrate 100.

[0028] In the cell region CR, bit line 115 can be disposed on bit line contact 114. Bit line 115 can be arranged in a direction perpendicular to word line 111. Bit line 115 may not contact contact plug 116. In other words, although not shown, an insulating layer may be disposed between bit line 115 and contact plug 116. Landing pad 117 and first cover layer 131 may be disposed on contact plug 116. Landing pad 117 may overlap contact plug 116 in the vertical direction.

[0029] In the peripheral region PR, the lower contact plug 103 and the gate 102 may be disposed on the substrate 100. The lower wiring 104 and the first cover layer 131 may be disposed on the lower contact plug 103. The lower wiring 104 may overlap with the lower contact plug 103 in the vertical direction. In one embodiment, the lower contact plug 103 and the gate 102 may respectively serve as the source / drain electrode and gate electrode of a transistor included in each circuit of the peripheral region PR.

[0030] In the peripheral region PR, the via electrode 106 can penetrate the insulating layer 130, the first capping layer 131, the second capping layer 132, the third capping layer 133, and the first interlayer dielectric layer 134. The via electrode 106 can extend into the interior of the substrate 100.

[0031] A via electrode blocking layer 107 may be disposed on the side surface 106SS of the via electrode 106. The via electrode blocking layer 107 may include metal, metal nitride, or a combination thereof, such as tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boron alloy (NiB), and tungsten nitride (WN).

[0032] The through-hole electrode 106 may include copper (Cu), manganese (Mn), aluminum (Al), gold (Au), indium (In), nickel (Ni), or a combination thereof.

[0033] The distance from the upper surface 106US of the via electrode 106 to the upper surface of the substrate 100 can be greater than the distance from the upper surface 105US of the first contact 105 to the upper surface of the substrate 100. The upper surface 106US of the via electrode 106 can be located within the second interlayer dielectric layer 135B.

[0034] The second interlayer dielectric layer 135B may surround the upper surface 106US and at least a portion of the side surfaces 106SS of the via electrode 106. The second interlayer dielectric layer 135B may be in contact with the upper surface 106US of the via electrode 106.

[0035] The first contact 105 in the peripheral region PR can penetrate the second cover layer 132 and the third cover layer 133. The first contact 105 can be electrically connected to the lower wiring 104. The first contact 105 can be made of a conductive material.

[0036] The second contact 121 in the cell region CR can pass through the second cover layer 132 and the third cover layer 133. The second contact 121 can be electrically connected to the second electrode 120. The second contact 121 can be made of a conductive material. The upper surface of the second contact 121 can be coplanar with the lower surface of the third wiring 122. The upper surface of the second contact 121 can contact the lower surface of the first interlayer dielectric layer 134.

[0037] In one example, the second contact 121 may include a barrier layer. The second contact 121 may include a conductive material, such as copper (Cu) or copper-manganese (CuMn). The upper surface of the second contact 121 may be coplanar with the upper surface 105US of the first contact 105.

[0038] The first wiring 108, located in the peripheral region PR, can penetrate the second interlayer dielectric layer 135B and the third interlayer dielectric layer 136. The first wiring 108 can be electrically connected to the via electrode 106.

[0039] In the peripheral region PR, the second wiring 109 can penetrate the first interlayer dielectric layer 134, the second interlayer dielectric layer 135B, and the third interlayer dielectric layer 136. The second wiring 109 can be electrically connected to the first contact 105.

[0040] In the cell region CR, the third wiring 122 may penetrate the first interlayer dielectric layer 134, the second interlayer dielectric layer 135B, and the third interlayer dielectric layer 136. The third wiring 122 may be electrically connected to the second contact 121. The second wiring 109 and the third wiring 122 may include the same material as the first wiring 108.

[0041] The first wiring 108 can contact the through-hole electrode 106. The second wiring 109 can cover the upper surface of the first contact 105. The third wiring 122 can cover the upper surface of the second contact 121. The thickness of the first wiring 108 can be less than the thickness of the second wiring 109 and the third wiring 122.

[0042] The distance from the lower surface 108LS of the first wiring 108 to the upper surface of the substrate 100 can be greater than the distance from the lower surface of the second wiring 109 to the upper surface of the substrate 100. The distance from the lower surface of the second wiring 109 to the substrate 100 can be equal to the distance from the lower surface of the third wiring 122 to the substrate 100. The upper surfaces of the first wiring 108, the second wiring 109, and the third wiring 122 can be coplanar.

[0043] The first interlayer dielectric layer 134 and the third interlayer dielectric layer 136 may comprise oxides, such as borosilicate glass (BPSG), phosphosilicate glass (PSG), spin-coated glass (SOG), tetraethyl orthosilicate (TEOS), or high-density plasma (HDP). The first capping layer 131, the second capping layer 132, and the third capping layer 133 may also comprise the same materials as the first interlayer dielectric layer 134 and the third interlayer dielectric layer 136.

[0044] The second interlayer dielectric layer 135B may include a material different from the materials of the first interlayer dielectric layer 134 and the third interlayer dielectric layer 136. For example, the second interlayer dielectric layer 135B may include a nitride.

[0045] The second interlayer dielectric layer 135B may surround the side surface 106SS of the via electrode 106. The second interlayer dielectric layer 135B may be spaced apart from the first contact 105. In one embodiment, an insulating layer may be present between the second interlayer dielectric layer 135B and the first contact 105. In one embodiment, the insulating layer may include an oxide.

[0046] Bit line contact 114, bit line 115, contact plug 116, landing pad 117, lower contact plug 103, gate 102 and lower wiring 104 may include conductive materials, such as metal, metal oxide, metal nitride, metal silicide, polysilicon, conductive carbon or combinations thereof.

[0047] In the cell region CR, a first electrode 119, a dielectric layer 118, and a second electrode 120 can be disposed on a first cover layer 131 and a landing pad 117. The first electrode 119, the dielectric layer 118, and the second electrode 120 can constitute the capacitor of the memory cell. Although not shown, an etch stop layer can be further disposed between the first cover layer 131 and the dielectric layer 118.

[0048] The first electrode 119 may overlap with the landing pad 117 in the vertical direction. Although not shown, a support pattern layer may be provided on the side surface of the first electrode 119. The support pattern layer may surround the side surface of the first electrode 119. The support pattern layer provided on one first electrode 119 may be isolated from the support pattern layer provided on the side surface of the other first electrode 119.

[0049] The dielectric layer 118 can be configured to cover the surface of the support pattern layer and the first electrode 119. The second electrode 120 can be disposed on the dielectric layer 118. The upper surface of the second electrode 120 can be higher than the upper surface of the first electrode 119.

[0050] The first electrode 119 and the second electrode 120 may include conductive materials, such as metals, metal oxides, metal nitrides, metal silicides, polycrystalline silicon, conductive carbon, or combinations thereof. The dielectric layer 118 may include a high-k material, such as silicon oxide, silicon nitride, or combinations thereof.

[0051] Reference Figure 2 The first wiring 108 may include a first wiring conductive layer 108A and a first wiring blocking portion 108B. The first wiring blocking portion 108B may surround the lower surface and side surface of the first wiring conductive layer 108A.

[0052] The first wiring blocking portion 108B may include a conductive material, such as copper (Cu), tungsten (W), tantalum nitride (TaN), or a combination thereof. In one embodiment, the first wiring conductive layer 108A may include a conductive material, such as copper (Cu), manganese (Mn), etc.

[0053] The lower surface 108LS of the first wiring 108 may be located in the second interlayer dielectric layer 135B. The lower surface 108LS of the first wiring 108 may be lower than the upper surface 135BUS of the second interlayer dielectric layer 135B. The lower surface 108LS of the first wiring 108 may be higher than the lower surface 135BLS of the second interlayer dielectric layer 135B.

[0054] The lower surface 108LS of the first wiring 108 can contact the upper surface 106US of the via electrode 106. The upper surface of the first wiring 108 can be coplanar with the upper surface of the third interlayer dielectric layer 136.

[0055] The second wiring 109 may include a second wiring conductive layer 109A and a second wiring blocking portion 109B. The second wiring blocking portion 109B may surround the lower surface and side surface of the second wiring 109.

[0056] The second wiring blocking portion 109B may include a conductive material, such as copper (Cu), tungsten (W), tantalum nitride (TaN), or a combination thereof. In one embodiment, the second wiring conductive layer 109A may include a conductive material, such as copper (Cu), manganese (Mn), etc.

[0057] The lower surface of the second wiring 109 can contact the upper surface 105US of the first contact 105. The upper surface of the second wiring 109 can be coplanar with the upper surface of the third interlayer dielectric layer 136.

[0058] The upper surface 105US of the first contact 105 may be coplanar with the lower surface of the second wiring 109. The first contact 105 may include a first contact barrier layer 105A. For example, the first contact barrier layer 105A may include a conductive material, such as copper (Cu), tungsten (W), tantalum nitride (TaN), or a combination thereof.

[0059] The upper surface 106US of the via electrode 106 can be located between the upper surface 135BUS and the lower surface 135BLS of the second interlayer dielectric layer 135B. The second interlayer dielectric layer 135B can be disposed on the side surface 106SS of the via electrode 106.

[0060] Figures 3 to 11 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to embodiments of the present disclosure.

[0061] Reference Figure 3 A gate structure 110 can be formed in the cell region CR. An isolation insulating layer 130 can be formed on the substrate 100. Bit line contacts 114, bit lines 115, and contact plugs 116 can be formed in the isolation insulating layer 130. A first cover layer 131 and landing pads 117 can be formed on the isolation insulating layer 130. A second cover layer 132 can be disposed on the first cover layer 131. A first electrode 119, a dielectric layer 118, and a second electrode 120 can be formed on the second cover layer 132.

[0062] A gate 102, a gate insulating layer 101, and a lower contact plug 103 can be formed in the peripheral region PR and in the isolation insulating layer 130 on the substrate 100. A lower wiring 104 can be formed on a first cover layer 131 on the isolation insulating layer 130. A second cover layer 132 can be disposed on the first cover layer 131.

[0063] After depositing the second capping layer 132, the upper portion of the second capping layer 132 can be removed by a planarization process. The planarization process may include a chemical mechanical polishing (CMP) process. A third capping layer 133 may be formed on the planarized second capping layer 132. In one embodiment, the third capping layer 133 may include an oxide.

[0064] Reference Figure 4 A contact hole can be formed penetrating the second cover layer 132 and the third cover layer 133. The contact hole may include a first contact hole 401 formed in the peripheral region PR and a second contact hole 402 formed in the cell region CR. The first contact hole 401 can contact the upper surface of the lower wiring 104. The second contact hole 402 can be connected to the second electrode 120. When forming the first contact hole 401, at least a portion of the second cover layer 132 and the third cover layer 133 may be removed.

[0065] The first contact hole 401 may be configured to expose at least a portion of the lower wiring 104. The second contact hole 402 may be configured to expose at least a portion of the second electrode 120. The height of the first contact hole 401 formed in the peripheral region PR may be greater than the height of the second contact hole 402 formed in the cell region CR.

[0066] Reference Figure 5 In the peripheral region PR, the first contact 105 can be formed to fill the first contact hole 401. The lower surface of the first contact 105 can contact the lower wiring 104. The upper surface of the first contact 105 can contact... Figure 6 The first interlayer dielectric layer 134 is in contact with the semiconductor device. Multiple first contacts 105 can be disposed on the substrate 100 of the semiconductor device.

[0067] In the cell region CR, a second contact 121 can be formed to fill the second contact hole 402. The lower surface of the second contact 121 can be connected to the second electrode 120. The upper surface of the second contact 121 can be in contact with the first interlayer dielectric layer 134. The upper surface of the first contact 105 and the upper surface of the second contact 121 can be coplanar.

[0068] Reference Figure 6 A first interlayer dielectric layer 134 is formed on the third cover layer 133. The first interlayer dielectric layer 134 is formed to cover the upper part of the first contact 105 and the second contact 121. The first interlayer dielectric layer 134 can prevent oxidation of the first contact 105 and the second contact 121.

[0069] A nitride layer 135A is formed on the first interlayer dielectric layer 134. In one embodiment, the nitride layer 135A can be used as a barrier layer in a subsequent via electrode 106 formation process. The nitride layer 135A may comprise the same material as the second interlayer dielectric layer 135B.

[0070] Reference Figure 7 The via electrode 701 can penetrate the first capping layer 131, the second capping layer 132, the third capping layer 133, the first interlayer dielectric layer 134, and the second interlayer dielectric layer 135B. The via electrode 701 can extend into the substrate 100. It can be formed in the via electrode 701 through subsequent processes. Figure 8 The through-hole electrode 106 is shown.

[0071] When forming the via electrode 701, at least a portion of the nitride layer 135A in the corresponding region can be removed, and at least a portion of the substrate 100 can also be removed. The via electrode 701 can be formed by exposure and etching processes.

[0072] Reference Figure 8 A through-hole electrode barrier layer 107 can be formed within the through-hole electrode hole 701. The through-hole electrode barrier layer 107 may include tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boron alloy (NiB), or tungsten nitride (WN), or combinations thereof.

[0073] After forming the via electrode barrier layer 107, conductive material can be deposited therein to form the via electrode 106. The via electrode 106 may include copper (Cu), copper-manganese (CuMn), or a combination thereof.

[0074] Reference Figure 9The nitride layer 135A can be etched to expose the first interlayer dielectric layer 134. Etching the nitride layer 135A exposes at least a portion of the upper and side surfaces of the via electrode 106. The etching process may include a chemical mechanical polishing (CMP) process. In subsequent steps, a via electrode 106 can be formed in the area where the nitride layer 135A has been removed. Figure 10 The second interlayer dielectric layer 135B is shown.

[0075] In one embodiment, during the etching process for forming the first wiring via 1101 and the second wiring via 1102, the second interlayer dielectric layer 135B can be used as an etching stop layer.

[0076] Reference Figure 10 A second interlayer dielectric layer 135B can be formed on the first interlayer dielectric layer 134. The thickness of the second interlayer dielectric layer 135B can be greater than the thickness of the previously formed nitride layer 135A. The second interlayer dielectric layer 135B surrounds the upper surface of the via electrode 106 and at least a portion of the side surfaces of the via electrode 106. The second interlayer dielectric layer 135B is formed such that the upper surface of the via electrode 106 is located between the upper and lower surfaces of the second interlayer dielectric layer 135B.

[0077] A third interlayer dielectric layer 136 is formed on the second interlayer dielectric layer 135B. The third interlayer dielectric layer 136 may include oxides, such as BPSG, PSG, SOG, TEOS, or HDP.

[0078] Reference Figure 11 The first wiring hole 1101 can be formed by etching the third interlayer dielectric layer 136. Alternatively, the first wiring hole 1101 can be formed by etching a portion of the second interlayer dielectric layer 135B to expose a portion of the upper surface of the via electrode 106.

[0079] Because the width of the via electrode 106 is greater than the width of the first wiring 108, a portion of the center of the upper surface of the via electrode 106 can be exposed. During the formation of the first wiring via 1101, the side portion of the second interlayer dielectric layer 135B can also be exposed.

[0080] The second wiring via 1102 can be formed by etching the first interlayer dielectric layer 134, the second interlayer dielectric layer 135B, and the third interlayer dielectric layer 136. When forming the second wiring via 1102, the upper surface of the first contact 105 can be exposed. A portion of the side surfaces of the first interlayer dielectric layer 134, the second interlayer dielectric layer 135B, and the third interlayer dielectric layer 136 can also be exposed when forming the second wiring via 1102.

[0081] The third wiring via 1103 can be formed by etching the first interlayer dielectric layer 134, the second interlayer dielectric layer 135B, and the third interlayer dielectric layer 136. When the third wiring via 1103 is formed, the upper surface of the second contact 121 can be exposed. When the third wiring via 1103 is formed, a portion of the side surfaces of the first interlayer dielectric layer 134, the second interlayer dielectric layer 135B, and the third interlayer dielectric layer 136 can also be exposed.

[0082] In one embodiment, the first wiring hole 1101, the second wiring hole 1102, and the third wiring hole 1103 may be formed simultaneously on the through-hole electrode 106, the first contact 105, and the second contact 121, respectively.

[0083] Refer again Figure 11 and Figure 1 A blocking portion can be formed along the inner and bottom surfaces of the first wiring hole 1101, the second wiring hole 1102, and the third wiring hole 1103. Then, conductive material can be deposited in the first wiring hole 1101, the second wiring hole 1102, and the third wiring hole 1103 to form the first wiring 108, the second wiring 109, and the third wiring 122, respectively.

[0084] The surfaces of the first wiring 108, the second wiring 109, and the third wiring 122 can be planarized. The planarization process may include a chemical mechanical polishing (CMP) process.

[0085] The blocking portions of the first wiring 108, the second wiring 109, and the third wiring 122 may include copper (Cu), tungsten (W), tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), or combinations thereof. A conductive material such as copper or tungsten may be deposited within the first wiring 108, the second wiring 109, and the third wiring 122.

[0086] Figure 12 A cross-sectional view illustrating another embodiment of this disclosure. The embodiments described below are different from those described above in this disclosure.

[0087] Reference Figure 12 In relation to the previous statements in this disclosure Figures 1 to 11 In different embodiments described, a first nitride layer 1205 is formed after the via electrode 1201 is formed, followed by the formation of a first contact 1202, and then a second nitride layer 1206. Thus, multiple nitride layers are formed between the wirings 1208. If multiple nitride layers are formed between adjacent wirings 1208, compressive stress may occur between the nitride layers, and copper migration may occur at interfaces where the bonding between the nitride layers is weaker during the etching process of the wirings 1208.

[0088] According to embodiments of this disclosure, since the nitride layer 135A formed on the upper part of the via electrode 106 is removed and a second interlayer dielectric layer 135B is subsequently formed, only a single nitride layer is formed between the first wiring 108, the second wiring 109, and the third wiring 122. Accordingly, since there is no nitride layer interface between the first wiring 108, the second wiring 109, and the third wiring 122, process defects caused by copper migration can be prevented.

[0089] Although different embodiments of the disclosed technology have been described in detail for illustrative purposes, those skilled in the art will understand that various modifications, additions and substitutions can be made based on the content disclosed or illustrated herein without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A semiconductor device, comprising: The substrate includes a unit region and a peripheral region; A first contact element is disposed in the peripheral region; A first interlayer dielectric layer is disposed on the first contact; A via electrode is disposed in the peripheral region and penetrates at least a portion of the first interlayer dielectric layer and the substrate; as well as The second interlayer dielectric layer is disposed on the first interlayer dielectric layer and covers the side and top surfaces of the via electrode.

2. The semiconductor device according to claim 1, in, The upper surface of the through-hole electrode is higher than the upper surface of the first contact.

3. The semiconductor device according to claim 1, further comprising: A first wiring is connected to the through-hole electrode; as well as The second wiring is disposed on the first contact. The lower surface of the first wiring is disposed inside the second interlayer dielectric layer.

4. The semiconductor device according to claim 3, in, The thickness of the first wiring is less than the thickness of the second wiring.

5. The semiconductor device according to claim 3, in, The second wiring penetrates the second interlayer dielectric layer and the first interlayer dielectric layer.

6. The semiconductor device according to claim 3, in, The first wiring and the second wiring include copper, tungsten, tantalum, tantalum nitride, titanium nitride, or a combination thereof.

7. The semiconductor device according to claim 3, in, The second wiring covers the upper surface of the first contact.

8. The semiconductor device according to claim 3, in, The second interlayer dielectric layer is disposed on the side surface of the first wiring.

9. The semiconductor device according to claim 1, in, The second interlayer dielectric layer is configured to contact the upper surface of the via electrode.

10. The semiconductor device according to claim 1, in, The first interlayer dielectric layer comprises an oxide, and the second interlayer dielectric layer comprises a nitride.

11. The semiconductor device according to claim 1, further comprising: A first electrode is disposed in the unit region; The second electrode is disposed on the first electrode; A dielectric layer is disposed between the first electrode and the second electrode; as well as The second contact is connected to the second electrode. The upper surface of the second contact is coplanar with the upper surface of the first contact.

12. A semiconductor device, comprising: Substrate; A first contact element is disposed on the substrate; A first interlayer dielectric layer is disposed on the first contact; A through-hole electrode that penetrates at least a portion of the substrate and whose upper surface is higher than the upper surface of the first contact. as well as A second interlayer dielectric layer surrounds at least a portion of the side surface of the via electrode and is spaced apart from the first contact.

13. The semiconductor device according to claim 12, in, The upper surface of the through-hole electrode is disposed between the top and bottom surfaces of the second interlayer dielectric layer.

14. The semiconductor device according to claim 12, in, The second interlayer dielectric layer is configured to contact the upper surface of the via electrode.

15. The semiconductor device according to claim 12, It also includes a first wiring connected to the through-hole electrode. in, The second interlayer dielectric layer is disposed on the side surface of the first wiring.

16. The semiconductor device according to claim 15, It also includes a second wiring connected to the first contact. in, The thickness of the second wiring is greater than the thickness of the first wiring.

17. A method for manufacturing a semiconductor device, the method comprising: A first contact is formed on the substrate; A first interlayer dielectric layer is formed covering the first contact element; A nitride layer is formed on the first interlayer dielectric layer; Forming a via electrode that penetrates at least a portion of the first interlayer dielectric layer and the nitride layer; Remove any remaining portion of the nitride layer; as well as A second interlayer dielectric layer is formed on the first interlayer dielectric layer, such that the second interlayer dielectric layer is in contact with the upper surface and side surface of the via electrode.

18. The method according to claim 17, in, Removing the residual portion of the nitride layer includes removing the residual portion of the nitride layer to expose at least a portion of the upper surface and side surface of the via electrode.

19. The method of claim 17, further comprising: A first wiring is formed on the first contact, and a second wiring is formed on the through-hole electrode.

20. The method according to claim 19, wherein, Forming the first wiring also includes: At least a portion of the second interlayer dielectric layer is removed to expose the upper surface of the via electrode.

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