Semiconductor structure

Abstract

A semiconductor structure includes a substrate having an array region and a peripheral region surrounding the array region. The substrate includes a plurality of active regions in the array region, the active regions extending along a first direction and arranged in a second direction. The semiconductor structure includes a plurality of word line structures disposed over the substrate and located in the array region, the word line structures extending along the second direction and arranged in the first direction. The semiconductor structure further includes a plurality of contact structures disposed on the active regions and located between the word line structures. The contact structures include a first contact closest to the peripheral region and a second contact adjacent to the first contact. A first width of the first contact in the second direction is greater than a second width of the second contact in the second direction.

Description

Technical Field

[0001] The embodiments of the present invention relate to semiconductor technology, and in particular to the contact structure of a flash memory device. Background Technology

[0002] To increase component density and improve overall performance within flash memory devices, current manufacturing technologies continue to focus on miniaturizing component sizes. However, as component sizes shrink, numerous challenges arise. For example, contact structures at the edges of array regions may exhibit incomplete structures due to etching load effects (e.g., smaller contact areas), leading to unfavorable increases in current density at the contact structures and impacting the electrical performance of the flash memory device. Therefore, the industry still needs to improve flash memory device manufacturing methods to overcome the problems arising from component size reduction. Summary of the Invention

[0003] This invention provides a semiconductor structure comprising a substrate having an array region and a peripheral region surrounding the array region, the substrate including a plurality of active regions in the array region, wherein the active regions extend along a first direction and are arranged in a second direction; a plurality of word line structures disposed above the substrate and located in the array region, wherein the word line structures extend along the second direction and are arranged in the first direction; and a plurality of contact structures disposed on the active regions and located between the word line structures, wherein the contact structure includes a first contact closest to the peripheral region and a second contact adjacent to the first contact, wherein the first width of the first contact in the second direction is greater than the second width of the second contact in the second direction. Attached Figure Description

[0004] Figure 1 This is a top view schematic diagram of a semiconductor structure according to an embodiment of the present invention.

[0005] Figure 2 This is a partial top view schematic diagram of a semiconductor structure according to an embodiment of the present invention.

[0006] Figure 3 , Figure 4 as well as Figure 5 This is a partial top view schematic diagram of a semiconductor structure according to an embodiment of the present invention.

[0007] Figure 6 This is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention.

[0008]

Symbol Explanation

[0009] The embodiments of the present invention modify the pattern design of specific contact structures so that the specific contact structures affected by the etching load effect can have a larger and more stable structure, avoiding the impact on current density, thereby maintaining the yield of flash memory devices.

[0010] See Figure 1 The semiconductor structure 10 may be a flash memory device. In some embodiments, the semiconductor structure 10 includes a substrate 100. The substrate 100 has an array region 105 and a peripheral region 110 surrounding the array region 105. In some embodiments, the substrate 100 may be an elemental semiconductor substrate, a compound semiconductor substrate, or an alloy semiconductor substrate. In other embodiments, the substrate 100 may be a semiconductor-on-insulator (SOI) substrate.

[0011] See next Figure 2 , Figure 2 draw Figure 1 A partial top view of box 115 is shown. In some embodiments, substrate 100 includes a plurality of active regions 120 in array region 105. In some embodiments, the active regions 120 may be separated and defined by isolation structures 125. The active regions 120 extend along a first direction (e.g., direction Y) and are arranged in a second direction (e.g., direction X). The positions of the active regions 120 may overlap with bit line structures, but bit line structures are not shown separately for simplicity. In some embodiments, the first direction intersects the second direction, for example, the first direction is perpendicular to the second direction. In some embodiments, the material of isolation structure 125 may include an insulating material, such as silicon oxide. In some embodiments, isolation structure 125 may include a shallow trench isolation (STI) structure.

[0012] See also Figure 2In some embodiments, the substrate 100 includes a plurality of word line structures 130 disposed above the substrate 100 and located in the array region 105. In some embodiments, the word line structures 130 extend along a second direction (e.g., direction X) and are arranged in a first direction (e.g., direction Y). In some embodiments, the word line structures 130 may have film layers stacked along a third direction (e.g., direction Z). In some embodiments, the third direction intersects both the first and second directions, for example, the third direction is perpendicular to the first direction and the third direction is perpendicular to the second direction.

[0013] See also Figure 2 In some embodiments, the substrate 100 includes a plurality of contact structures 135 disposed on the active region 120 and located between word line structures 130. In some embodiments, the contact structures 135 are arranged along a second direction (e.g., direction X). In some embodiments, the contact structure 135 includes a first contact 137 closest to the peripheral region 110 and a second contact 139 adjacent to the first contact 137. In some embodiments, the contact structure 135 may be a self-aligned contact (SAC). For example, a self-aligned contact is formed by patterning an interlayer dielectric layer using photolithography and etching processes, and using a contact etch stop layer. In some embodiments, the first width W1 of the first contact 137 in the second direction (e.g., direction X) is greater than the second width W2 of the second contact 139 in the second direction. Furthermore, in some embodiments, the contact structure 135 further includes an elongated contact 136 extending along the second direction (e.g., direction X).

[0014] Due to the boundary definition of the peripheral region 110 and the effect of etching load, the first contact 137 located at the edge of the array region 105 may have an incomplete structure. For example, because the etching of the contact opening is incomplete, the first contact 137 located at the edge of the array region 105 may have a smaller contact area with the active region 120 compared to the fully etched contact structure 135 (the part located in the center of the array region 105). A smaller contact area between the first contact 137 and the active region 120 may adversely affect the current density, further reducing the electrical performance of the flash memory device. In this invention, by designing the first width W1 of the first contact 137 to be larger than the second width W2 of the second contact 139 (and other contact structures 135), sufficient contact area between the first contact 137 and the active region 120 can be ensured, avoiding the generation of a large current density. In addition, the design of the first contact 137 can be easily integrated into existing process technologies.

[0015] In some embodiments, the first width W1 is greater than twice the second width W2. In some embodiments, the first width W1 is not greater than three times the second width W2. In other words, the size of the first width W1 is between twice and three times the second width W2. In some embodiments, the ratio of the first width W1 to the second width W2 is 2.5:1, thereby ensuring sufficient contact area between the first contact 137 and the active area 120. In some embodiments, the second width W2 is equal to the spacing S1 of the contact structure 135 in the second direction (e.g., direction X). In some embodiments, the second width W2 is equal to the width W3 of the active area 120 in the second direction (e.g., direction X). In some embodiments, the spacing S1 of the contact structure 135 in the second direction (e.g., direction X) is equal to the spacing S2 of the active area 120 in the second direction (e.g., direction X). In some embodiments, the distance 142 between the first contact 137 and the peripheral area 110 ranges from about 0.26 micrometers to about 0.3 micrometers. In some embodiments, the distance 144 between the first contact 137 and the word line structure 130 in a first direction (e.g., direction Y) ranges from about 0.1 micrometers to about 0.12 micrometers.

[0016] Then see Figure 3 , Figure 4 as well as Figure 5 . Figure 3 , Figure 4 as well as Figure 5 This is a partial top view schematic diagram of a semiconductor structure 10 according to an embodiment of the present invention. More specifically, Figure 3 , Figure 4 as well as Figure 5 draw Figure 2 A partial top view of box 140 in the diagram. In some embodiments, Figure 3 An embodiment is illustrated where the ratio of the first width W1 to the second width W2 is 2.5:1. In some embodiments, Figure 4 An embodiment is illustrated where the ratio of the first width W1 to the second width W2 is 3:1. In some embodiments, Figure 5 An example is illustrated where the ratio of the first width W1 to the second width W2 is 2:1.

[0017] In some embodiments, such as Figures 3 to 5As illustrated, the boundary B1 of the first contact 137 extends beyond the boundary B2 of the active region 120 corresponding to the first contact 137 by a first distance D1 in the second direction (e.g., direction X). In some embodiments, the first distance D1 is greater than the spacing S2 of the active regions 120 in the second direction (e.g., direction X). In some embodiments, the first distance D1 is greater than the spacing S1 of the contact structure 135 in the second direction (e.g., direction X). In some embodiments, as Figure 3 As illustrated, the ratio of the first distance D1 to the spacing S1 of the contact structure 135 in the second direction (e.g., direction X) is 1.5:1. In some embodiments, such as Figure 4 As illustrated, the ratio of the first distance D1 to the spacing S1 of the contact structure 135 in the second direction (e.g., direction X) is 2:1. In some embodiments, such as Figure 5 As shown, the ratio of the first distance D1 to the spacing S1 of the contact structure 135 in the second direction (e.g., direction X) is 1:1.

[0018] See next Figure 6 . Figure 6 This is a schematic cross-sectional view of a semiconductor structure 10 according to an embodiment of the present invention. More specifically, Figure 6 A cross-sectional schematic diagram is shown between the first contact 137, the second contact 139, and the active region 120. In some embodiments, in Figure 6 In this embodiment, the projected area 150 of the first contact 137 on the substrate 100 is greater than the projected area 155 of the second contact 139 on the substrate 100. In some embodiments, in... Figure 6 In this embodiment, the projected area 150 of the first contact 137 on the substrate 100 is greater than the projected area 160 of one of the active regions 120 corresponding to the first contact 137 on the substrate 100. In some embodiments, in Figure 6 In this configuration, the bottom width W4 of the first contact 137 is greater than the bottom width W5 of the second contact 139. In some embodiments, in Figure 6 In this embodiment, the bottom width W4 of the first contact 137 is greater than the top width W6 of the active area 120 corresponding to the first contact 137. In some embodiments, the ratio of the bottom width W4 of the first contact 137 to the top width W6 of the active area 120 corresponding to the first contact 137 is 1.4:1. In some embodiments, the ratio of the bottom width W4 of the first contact 137 to the bottom width W5 of the second contact 139 is 1.4:1.

[0019] In summary, the embodiments of the present invention, by modifying the pattern design of specific contact structures, enable specific contact structures affected by etching load effects to have larger and more stable structures, avoiding impact on current density and thus maintaining the yield of flash memory devices. More specifically, the embodiments of the present invention, by designing the first width of the first contact closest to the peripheral region to be greater than the second width of the second contact adjacent to the first contact (and other contact structures), can ensure sufficient contact area between the first contact and the active region, avoiding the generation of large current densities. Furthermore, the related design of the first contact can be easily integrated into existing process technologies. It should be understood that not all advantages are necessarily discussed herein, nor are all embodiments required to possess specific advantages, and other embodiments may offer different advantages.

[0020] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the viewpoints of the embodiments of the present invention. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of the present invention, and various changes, substitutions, and replacements can be made without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate having an array region and a peripheral region surrounding the array region, the substrate including a plurality of active regions in the array region, wherein the plurality of active regions extend along a first direction and are arranged in a second direction; Multiple word line structures are disposed above the substrate and located in the array region, wherein the multiple word line structures extend along the second direction and are arranged in the first direction; as well as Multiple contact structures are disposed on the multiple active areas and located between the multiple word line structures. The plurality of contact structures include a first contact closest to the peripheral area and a second contact adjacent to the first contact. The first contact member has a first width in the second direction that is greater than the second contact member has a second width in the second direction.

2. The semiconductor structure as described in claim 1, characterized in that, The first width is greater than twice the second width.

3. The semiconductor structure as described in claim 1, characterized in that, The first width is no more than three times the second width.

4. The semiconductor structure as described in claim 1, characterized in that, The second width is equal to the spacing between the plurality of contact structures in the second direction.

5. The semiconductor structure as described in claim 1, characterized in that, The second width is equal to the width of the plurality of active regions in the second direction.

6. The semiconductor structure as described in claim 1, characterized in that, The plurality of contact structures are arranged along the second direction.

7. The semiconductor structure as described in claim 1, characterized in that, The spacing between the plurality of contact structures in the second direction is equal to the spacing between the plurality of active areas in the second direction.

8. The semiconductor structure as described in claim 1, characterized in that, The ratio of the first width to the second width is 2.5:

1.

9. The semiconductor structure as described in claim 1, characterized in that, The boundary of the first contact extends beyond the boundary of one of the plurality of active areas corresponding to the first contact in the second direction by a first distance.

10. The semiconductor structure as described in claim 9, characterized in that, The first distance is greater than the spacing between the plurality of active regions in the second direction.

11. The semiconductor structure as described in claim 9, characterized in that, The first distance is greater than the spacing between the plurality of contact structures in the second direction.

12. The semiconductor structure as claimed in claim 9, characterized in that, The ratio of the first distance to the spacing of the plurality of contact structures in the second direction is 1.5:

1.

13. The semiconductor structure as claimed in claim 1, characterized in that, In a cross-sectional view, the projected area of ​​the first contact on the substrate is greater than the projected area of ​​the second contact on the substrate.

14. The semiconductor structure as claimed in claim 1, characterized in that, In a cross-sectional view, the projected area of ​​the first contact on the substrate is greater than the projected area of ​​one of the plurality of active regions corresponding to the first contact on the substrate.

15. The semiconductor structure as claimed in claim 1, characterized in that, The distance between the first contact and the surrounding area ranges from 0.26 micrometers to 0.3 micrometers.

16. The semiconductor structure as claimed in claim 1, characterized in that, The distance between the first contact and the plurality of word line structures in the first direction ranges from 0.1 micrometers to 0.12 micrometers.

17. The semiconductor structure as claimed in claim 1, characterized in that, In a cross-sectional view, the bottom width of the first contact is greater than the bottom width of the second contact.

18. The semiconductor structure as claimed in claim 1, characterized in that, In a cross-sectional view, the bottom width of the first contact is greater than the top width of one of the plurality of active areas corresponding to the first contact.

19. The semiconductor structure as claimed in claim 1, characterized in that, The ratio of the bottom width of the first contact to the top width of one of the plurality of active areas corresponding to the first contact is 1.4:

1.

20. The semiconductor structure as claimed in claim 1, characterized in that, The ratio of the bottom width of the first contact to the bottom width of the second contact is 1.4:1.

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