Semiconductor device and method of manufacturing the same

Abstract

The application discloses a semiconductor device and a preparation method thereof, and relates to the technical field of memory devices. The semiconductor device comprises a substrate, a selection gate, a floating gate, a control gate, a source region, an erase gate and a drain region, and the substrate is provided with a buried gate groove. The selection gate is located in the buried gate groove. The floating gate is located on the surface of the substrate. The control gate is located on the surface of the substrate and covers the top surface of the floating gate and the sidewall surface close to the selection gate. Compared with the prior art, the embodiment of the application adopts a split gate structure, and the selection gate is a buried gate, so that the arrangement space of the control gate is larger, the control gate can cover the top surface and the sidewall surface of the floating gate, the cross-sectional area of the control gate and the floating gate is greatly increased, the coupling efficiency is higher, the control gate can meet the programming of the device under a relatively low voltage, the reading voltage of the device is reduced, the overall power consumption of the device is lower, the speed is faster, and the boosting structure is simpler.

Description

Technical Field

[0001] This invention relates to the field of storage device technology, and more specifically, to a semiconductor device and its fabrication method. Background Technology

[0002] With the rapid development of semiconductor technology, electronic products face increasingly stringent requirements in terms of reliability, power consumption, speed, and integration. Flash memory, which retains data even after power is lost, includes NAND flash memory and NOR flash memory. NOR flash memory, with its excellent random access performance and high reliability, is widely used in portable electronic components, industrial control, automotive electronics, and aerospace.

[0003] NOR-type split-gate flash memory, as a high-reliability flash memory structure, mainly consists of a control gate, a floating gate, a select gate, and an erase gate. During flash memory programming, a positive voltage is applied to the select gate while a lateral bias exists between the source and drain. Simultaneously, a high voltage is applied to the control gate. Through the coupling effect of the control gate to the floating gate, a positive electric field is formed between the floating gate and the substrate, thereby injecting electrons from the substrate channel into the floating gate via SSI (Source-Side-Injection). Improving the coupling efficiency of the device can effectively reduce the voltage required to be applied to the control gate, which is of great significance for improving data transmission speed, reducing power consumption, and achieving higher integration density. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device and its fabrication method, which can improve the coupling efficiency of the device, effectively reduce the voltage required to control the gate, and improve the data transmission speed, reduce power consumption, and achieve higher integration.

[0005] The embodiments of the present invention are implemented as follows: In one aspect, embodiments of the present invention provide a semiconductor device, comprising: Substrate, wherein the substrate has buried gate trenches; Select the grid, located in the buried grid trench; A floating gate is located on the surface of the substrate, and the projection of the floating gate onto the substrate does not overlap with the selection gate; A control gate is located on the substrate surface and the top surface of the floating gate, the control gate covering the top surface of the floating gate and the sidewall surface near the selection gate; A source region is located in the substrate, the source region is spaced apart from the selection gate, and the projection of the floating gate onto the substrate is located between the source region and the selection gate; An erase gate is located on the substrate surface corresponding to the source region, and the erase gate covers the sidewall of the floating gate away from the select gate and the sidewall of the control gate on the top surface of the floating gate; The drain region is located in the substrate on the side of the selected gate away from the source region.

[0006] In an optional embodiment, a first passivation layer is further provided on the side of the control gate away from the erase gate, and the projection of the first passivation layer onto the substrate does not overlap with the drain region.

[0007] In an optional embodiment, the projection of the control gate of the first passivation layer and the floating gate sidewall onto the substrate overlaps with the selection gate.

[0008] In an optional implementation, it further includes: A first gate oxide layer is located within the buried gate trench and between the select gate and the substrate; the first gate oxide layer also covers the top surface of the select gate.

[0009] In an optional embodiment, a second gate oxide layer is disposed between the substrate and the floating gate, and between the substrate and the control gate.

[0010] In an optional embodiment, a third gate oxide layer is further disposed between the erase gate and the source region.

[0011] In an optional embodiment, a dielectric layer is provided between the floating gate and the control gate.

[0012] In an optional embodiment, the dielectric layer includes a first oxide layer, a second passivation layer, and a second oxide layer stacked sequentially, wherein the first oxide layer covers the top surface and sidewalls of the floating gate, the second passivation layer covers the first oxide layer, and the second oxide layer covers the second passivation layer.

[0013] Secondly, embodiments of the present invention provide a method for fabricating a semiconductor device, the method comprising: Provide substrate; The surface of the substrate is etched to form buried gate trenches; A selection grid is formed in the buried grid trench; A floating gate and a control gate are formed on the substrate surface, wherein the projection of the floating gate onto the substrate does not overlap with the selection gate, and the control gate is located on the substrate surface and the top surface of the floating gate, covering the top surface of the floating gate and the sidewall surface near the selection gate; Implantation is performed on the substrate to form a source region, wherein the source region is spaced apart from the select gate, and the projection of the floating gate onto the substrate is located between the source region and the select gate; An erase gate is formed on the substrate surface corresponding to the source region, the erase gate covering the sidewall of the floating gate away from the select gate and the sidewall of the control gate on the top surface of the floating gate; Implantation is performed on the substrate on the side of the selected gate away from the source region to form the drain region.

[0014] In an optional embodiment, the step of forming the floating gate and the control gate on the substrate surface includes: A first polycrystalline silicon layer is formed on the surface of the substrate; The first polysilicon layer is etched to form a floating gate; A second polysilicon layer is formed covering the substrate surface, the sidewalls of the floating gate, and the top surface; A control gate is formed by etching away a portion of the second polysilicon layer on the substrate surface corresponding to the selection gate, the second polysilicon layer on the substrate surface on the side of the selection gate away from the floating gate, and the second polysilicon layer on the substrate surface on the side of the floating gate away from the selection gate.

[0015] The beneficial effects of the embodiments of the present invention include: The semiconductor device and its fabrication method provided in this invention have a buried gate trench in the substrate, with a select gate located in the buried gate trench to form a buried gate structure. A floating gate is located on the substrate surface, and the projection of the floating gate onto the substrate does not overlap with the select gate. A control gate is located on the substrate surface and the top surface of the floating gate, covering the top surface and sidewalls of the floating gate. A source region is located in the substrate. The source region and the select gate are spaced apart, and the projection of the floating gate onto the substrate is located between the source region and the select gate. An erase gate is located on the substrate surface, corresponding to the source region, and the erase gate can cover the sidewalls of the floating gate and the control gate. A drain region is located in the substrate on the side of the select gate away from the source region.

[0016] Compared to existing technologies, the semiconductor device provided in this invention adopts a split gate structure and selects a buried gate, which makes the arrangement space of the control gate larger. This allows the control gate to cover the top surface and sidewalls of the floating gate, and the side of the floating gate near the drain can also be covered by the control gate. This greatly increases the intersection area of ​​the control gate and the floating gate, resulting in a larger coupling effect and higher coupling efficiency. It can meet the programming requirements of the device even at relatively low voltages, while also reducing the device read voltage. Overall, the device has lower power consumption, faster speed, and a simpler boost structure. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention; Figure 2 for Figure 1 A magnified view of a portion of section II; Figure 3 This is a schematic diagram of the structure corresponding to step S1 in the method for fabricating a semiconductor device provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure corresponding to step S2 in the method for fabricating a semiconductor device provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure corresponding to step S3 in the method for fabricating a semiconductor device provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of the structure corresponding to step S4 in the method for fabricating a semiconductor device provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of the structure corresponding to step S5 in the method for fabricating a semiconductor device provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of the structure corresponding to step S6 in the method for fabricating a semiconductor device provided in an embodiment of the present invention.

[0019] icon: 100 - Semiconductor device; 110 - Substrate; 111 - Buried gate trench; 120 - Select gate; 121 - First gate oxide layer; 130 - Floating gate; 131 - Second gate oxide layer; 140 - Control gate; 150 - Source region; 160 - Erase gate; 161 - Third gate oxide layer; 170 - Drain region; 180 - First passivation layer; 190 - Dielectric layer; 191 - First oxide layer; 192 - Second passivation layer; 193 - Second oxide layer. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0021] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0022] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0023] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this invention is in use. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention. In addition, the terms "first," "second," "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0024] Furthermore, terms such as "horizontal" and "vertical" do not imply that components must be absolutely horizontal or suspended, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0025] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0026] As disclosed in the background section, the coupling effect of the control gate to the floating gate creates a positive electric field on the substrate, thereby injecting electrons from the substrate channel into the floating gate via SSI (Source-Side-Injection). Improving the coupling efficiency of the device can effectively reduce the voltage required to be applied to the control gate, which is of great significance for improving data transmission speed, reducing power consumption, and achieving higher integration density.

[0027] The inventors' research revealed that the coupling efficiency between the control gate and the floating gate primarily depends on the area of ​​the crossover region between them and the dielectric constant of the dielectric layer. However, in conventional technologies, the crossover area between the control gate and the floating gate is relatively small, and the dielectric constant of the dielectric layer between them is relatively high.

[0028] To improve coupling efficiency, this invention provides a novel semiconductor device and its fabrication method. It should be noted that, unless otherwise specified, the features in this invention can be combined with each other.

[0029] See Figure 1 The present invention provides a semiconductor device 100 that can improve the coupling efficiency of the device, effectively reduce the voltage required to be applied to the control gate 140, and improve the data transmission speed, reduce power consumption and achieve higher integration.

[0030] The semiconductor device 100 provided in this embodiment of the invention may include a substrate 110, a select gate 120, a floating gate 130, a control gate 140, a source region 150, an erase gate 160, and a drain region 170. The substrate 110 has a buried gate trench 111. The select gate 120 is located in the buried gate trench 111. The floating gate 130 is located on the surface of the substrate 110 and is offset from the select gate 120 by a first misalignment, meaning that the projection of the floating gate 130 onto the substrate does not overlap with the select gate 120 (it may partially overlap, but not completely). The control gate 140 is located on one side surface of the substrate 110 and covers the top surface of the floating gate 130 and the sidewall near the select gate 120. The source region 150 is located in the substrate 110, and its top surface is bonded to the surface of the substrate 110. The source region 150 is spaced apart from the select gate 120, and the projection of the floating gate 130 onto the substrate 110 is located between the source region 150 and the select gate 120. Erasure gate 160 is located on the surface of substrate 110 corresponding to source region 150, and erase gate 160 covers the sidewall of floating gate 130 away from select gate 120 and the sidewall of control gate 140 located on the top surface of floating gate 130. Drain region 170 is located in substrate 110 on the side of select gate 120 away from source region 150.

[0031] It should be noted that the semiconductor device 100 here may include multiple device units, each of which includes a substrate 110, a select gate 120 (SG), a floating gate 130 (FG), a control gate 140 (CG), a source region 150 (CS), an erase gate 160 (EG), and a drain region 170 (bit line BL). It adopts a split gate structure, and two floating gates 130 can share one erase gate 160. The two control gates 140 respectively cover the top surface and sidewall surface of the two floating gates 130. Because gate 120 is chosen as an embedded gate, the arrangement space of control gate 140 is larger, allowing control gate 140 to cover the top surface and sidewalls of floating gate 130. This also allows the side of floating gate 130 near the drain to be covered by control gate 140, greatly increasing the intersection area between control gate 140 and floating gate 130, resulting in a larger coupling effect and higher coupling efficiency. This allows control gate 140 to be programmed at relatively low voltages, while also reducing device read voltage. Overall, the device has lower power consumption, faster speed, and a simpler boost structure.

[0032] It is worth noting that in this embodiment, the floating gate 130 (FG), control gate 140 (CG), select gate 120 (SG), and erase gate 160 (EG) are all doped polysilicon, and the substrate 110 can be a silicon-based substrate 110. Furthermore, the source region 150 and drain region 170 are both ion-implanted doped regions.

[0033] In this embodiment, the control gate 140 may not completely cover the top surface of the floating gate 130. That is, the control gate 140 located on top of the floating gate 130 has its sidewall facing away from the selection gate 120 recessed by a preset size, so that the floating gate 130 away from the selection gate 120 and the control gate 140 form a stepped structure.

[0034] As mentioned above, the erase grid 160 is located on the side wall of the control grid 140 that covers the side wall of the floating grid 130 away from the selection grid 120 and the top surface of the floating grid 130, that is, the side wall of the erase grid 160 formed is also a reverse stepped structure.

[0035] In some embodiments, a first passivation layer 180 is further disposed on the side of the control gate 140 away from the erase gate 160, and the projection of the first passivation layer 180 onto the substrate does not overlap with the drain region 170. The first passivation layer 180 is a silicon nitride (SiN) layer, which provides passivation protection. The projections of the first passivation layer 180 and the control gate 140 on the sidewall of the floating gate 130 onto the substrate 110 overlap with the select gate 120.

[0036] In some embodiments, the semiconductor device 100 may further include a buried gate trench 111 ( Figure 3The first gate oxide layer 121 is located within the selected gate 120 and between the substrate 110 (as shown). Specifically, the depth of the buried gate trench 111 is greater than the thickness of the selected gate 120, and the first gate oxide layer 121 covers the top surface of the selected gate 120. The first gate oxide layer 121 can be silicon oxide. The depth of the buried gate trench 111 is between 300 Å and 1500 Å, preferably 600 Å; the thickness of the selected gate 120 is between 100 Å and 800 Å, preferably 200 Å. After forming the buried gate trench 111, a layer of silicon oxide (30 Å-200 Å, preferably 100 Å) can be grown first, followed by the growth of polysilicon as the material for the selected gate 120. The thickness of the selected gate 120 is adjusted by etching, and then the remaining buried gate trench 111 is filled with a silicon oxide layer to maintain the flatness of the substrate 110 surface, thereby forming the first gate oxide layer 121 covering the selected gate 120 and ensuring the electrical isolation effect of the selected gate 120.

[0037] In some embodiments, a second gate oxide layer 131 is disposed between the substrate 110 and the floating gate 130, and between the substrate 110 and the control gate 140. The second gate oxide layer 131 is disposed on the surface of the substrate 110, covering the buried gate trench 111. Both the floating gate 130 and the control gate 140 are located on the second gate oxide layer 131. Specifically, the second gate oxide layer 131 can also be silicon oxide, and its thickness is between 30 Å and 200 Å, preferably 120 Å. After forming the first gate oxide layer 121, a layer of silicon oxide can be formed on the surface of the substrate 110 first, and then the floating gate 130 and the control gate 140 can be formed, such that silicon oxide layers are formed between the floating gate 130 and the substrate 110, and between the control gate 140 and the substrate 110.

[0038] See also Figure 1 and Figure 2 Furthermore, a dielectric layer 190 is disposed between the floating gate 130 and the control gate 140. Specifically, the dielectric layer 190 may include a first oxide layer 191, a second passivation layer 192, and a second oxide layer 193 stacked sequentially. The first oxide layer 191 covers the top surface and sidewalls of the floating gate 130, the second passivation layer 192 covers the first oxide layer 191, and the second oxide layer 193 covers the second passivation layer 192. The first oxide layer 191 and the second oxide layer 193 are both silicon oxide, and the second passivation layer 192 is silicon nitride (SiN), forming an ONO (SiO2-Si3N4-SiO2) structure in the dielectric layer 190. This further reduces its dielectric constant, thereby further improving the coupling efficiency between the control gate 140 and the floating gate 130. The thickness of the first oxide layer 191 can be 40-80 Å, preferably 60 Å; the thickness of the second passivation layer 192 can be 40-80 Å, preferably 60 Å; the thickness of the second oxide layer 193 can be 40-80 Å, preferably 60 Å.

[0039] After the second gate oxide layer 131 is prepared, polysilicon can be grown on the second gate oxide layer 131, and then the morphology of the floating gate 130 is dry etched. The thickness of the floating gate 130 is between 100 Å and 1000 Å, preferably 400 Å. Then, a silicon oxide (40 Å-80 Å, preferably 60 Å) / silicon nitride (40 Å-80 Å, preferably 60 Å) / silicon oxide (40 Å-80 Å, preferably 60 Å) film is grown on the surface of the complete floating gate 130. Then, polysilicon is grown again, and a control gate 140 is etched, such that the control gate 140 covers the top surface of the floating gate 130 and the sidewall near the select gate 120. The upper part of the control gate 140 has a thickness of 200 Å-1000 Å, preferably 400 Å, and the width near the select gate 120 is 300 Å-1000 Å, preferably 400 Å.

[0040] Please continue reading Figure 1 In some embodiments, a third gate oxide layer 161 is provided between the erase gate 160 and the substrate 110, between the erase gate 160 and the sidewall of the select gate 120, and between the erase gate 160 and the sidewall of the control gate 140. Specifically, the source region 150 can be defined first, P / AS elements can be implanted (implantation dose 1E15 ions / cm²-9E15 ions / cm², energy 20keV-60keV), followed by annealing and wet cleaning to remove the surface silicon oxide, and then silicon oxide can be regrown using a high-temperature thermal oxidation process, thereby forming the third gate oxide layer 161 on the surface of the substrate 110 of the source region 150, the sidewall of the select gate 120 and the control gate 140. Polysilicon is then grown again, and the morphology of the erase gate 160 is etched. The top surface of the erase gate 160 can be flush with the top surface of the control gate 140.

[0041] The semiconductor device 100 provided in this embodiment of the invention is a discrete-gate non-volatile memory, and its operation is as follows: Device writing: Select gate 120 uses a voltage of about 1.4V, control gate 140 uses a voltage of about 8V, erase gate 160 uses a voltage of about 5V, source (Source / CS) uses a voltage of about 5V, drain is connected to BL (bit line) with a voltage of about 0.3V, and substrate 110 is connected to 0V; control gate 140 has a coupling effect with floating gate 130. When a positive high voltage is applied to control gate 140, the floating gate 130, affected by the coupling effect, generates a longitudinal electric field that acts on the channel, separating the normal opening of the gate. At the same time, a lateral voltage difference is generated between the source and drain, and electrons from the substrate are injected into the floating gate 130.

[0042] Device erasure: The erase gate 160 uses a high voltage of about 11V and uses the FN (Fowler-Nordheim) method to pull the electrons of the floating gate 130 to the erase gate 160.

[0043] Device readout: Select gate 120 is applied at approximately 2.5V, control gate 140 at approximately 1.6V, drain at 0.8V, and all others at 0V. Select gate 120 normally opens its substrate 110 channel. The coupling effect of control gate 140 to floating gate 130 generates an electric field that can open the substrate 110 channel under the unwritten floating gate 130. It cannot open the substrate 110 channel under the written state. The state of floating gate 130 is determined by reading the drain current value.

[0044] This invention also provides a method for fabricating a semiconductor device 100, which includes the following steps: S1: Etch the surface of substrate 110 to form buried gate trench 111.

[0045] See also Figure 3 Specifically, a substrate can be provided first, and then the area of ​​the selection gate 120 can be defined using a photolithography process. Then, a groove can be made on the substrate 110 using a dry etching process, so that the surface of the substrate 110 is recessed and a buried gate trench 111 is formed. The depth of the buried gate trench 111 is between 300 Å and 1500 Å, preferably 600 Å, and then cleaning is performed.

[0046] S2: A selection grid 120 is formed in the buried grid trench 111.

[0047] See also Figure 4 Specifically, a first gate oxide layer can be grown after cleaning, and the first gate oxide layer 121 can be silicon oxide.

[0048] In this embodiment, after forming the buried gate trench 111, a layer of silicon oxide (30A-200A, preferably 100A) can be grown first as the first gate oxide layer. The silicon oxide uniformly covers the bottom surface and sidewalls of the buried gate trench 111, and also covers the surface of the substrate. Then, polycrystalline silicon is grown as the select gate 120 material.

[0049] In this embodiment, the top height of the polysilicon may exceed the depth of the buried gate trench 111. During the production process, the polysilicon and silicon oxide outside the buried gate trench 111 can be removed first by a grinding process.

[0050] Furthermore, the thickness of the select gate 120 within the buried gate trench 111 is adjusted by etching, so that the surface of the select gate 120 is lower than the surface of the substrate.

[0051] Then, a silicon oxide layer is filled into the remaining buried gate trench 111, so that the silicon oxide layer covers the surface of the select gate 120. The silicon oxide layer completely fills the buried gate trench 111, keeping the surface of the substrate 110 flush with the surface of the silicon oxide layer, thereby forming the first gate oxide layer 121 covering the select gate 120, ensuring the electrical isolation effect of the select gate 120.

[0052] S3: A floating gate 130 is formed on the surface of substrate 110, wherein the projection of the floating gate 130 onto substrate 110 does not overlap with the selection gate 120.

[0053] See also Figure 5 Specifically, firstly, the gate oxide of the floating gate 130 is grown, that is, a second gate oxide layer 131 is formed on the surface of the substrate 110, with a thickness of 30-200 Å, preferably 120 Å. Then, a first polysilicon layer is grown, the region of the floating gate 130 is defined by photolithography, and the morphology of the floating gate 130 is etched by dry etching, wherein the thickness of the floating gate 130 is between 100-1000 Å, preferably 400 Å.

[0054] S4: A control gate 140 is formed on the surface of the substrate 110, wherein the control gate 140 is located on the surface of the substrate 110 and the top surface of the floating gate 130, and the control gate 140 covers the top surface of the floating gate 130 and the sidewall surface near the select gate 120.

[0055] See also Figure 6 Specifically, after forming the floating gate 130, a dielectric layer 190 can be formed on the surface of the floating gate 130 first. That is, a first oxide layer 191 is first formed on the top surface and sidewalls of the floating gate 130, then a second passivation layer 192 is formed on the surface of the first oxide layer 191, and finally a second oxide layer 193 is formed on the surface of the second passivation layer 192. In actual fabrication, a silicon oxide (40A-80A, preferably 60A) / silicon nitride (40A-80A, preferably 60A) / silicon oxide (40A-80A, preferably 60A) film can be grown on the surface of the entire floating gate 130. Specifically, a silicon oxide layer that completely covers the substrate 110 and the floating gate 130 can be formed first, and then patterned etching can be performed to remove excess silicon oxide from the surface of the substrate 110 to form the first oxide layer 191. Then, a silicon nitride layer is formed that completely covers the substrate 110 and the first oxide layer 191. After patterning etching to remove excess silicon nitride from the surface of the substrate 110, a second passivation layer 192 is formed. Finally, a silicon oxide layer is formed that completely covers the substrate 110 and the second passivation layer 192. After patterning etching to remove excess silicon oxide from the surface of the substrate 110, a second oxide layer 193 is formed.

[0056] Then, a second polysilicon layer is grown. A photolithography process is used to define the region of the control gate 140. Part of the second polysilicon layer on the substrate 110 surface corresponding to the selection gate 120, the second polysilicon layer on the substrate 110 surface on the side of the selection gate 120 away from the floating gate 130, and the second polysilicon layer on the substrate 110 surface on the side of the floating gate 130 away from the selection gate 120 are etched away, thus etching out the morphology of the control gate 140 and forming the control gate 140. This ensures that the control gate 140 covers the top surface of the floating gate 130 and the sidewall surface near the selection gate 120. The upper thickness of the control gate 140 is 200 Å-1000 Å, preferably 400 Å, and the width near the selection gate 120 is 300 Å-1000 Å, preferably 400 Å.

[0057] It should be noted that the dielectric layer 190 here forms an ONO (SiO2-Si3N4-SiO2) structure, which can further reduce its dielectric constant, thereby further improving the coupling efficiency between the control gate 140 and the floating gate 130.

[0058] S5: Ion implantation is performed on substrate 110 to form source region 150, wherein source region 150 is spaced apart from select gate 120, and the projection of floating gate 130 onto substrate 110 is located between source region 150 and select gate 120.

[0059] See Figure 7 Specifically, a photolithography process is used to define the source region 150, and P / AS elements are implanted using an ion implantation process (implantation dose 1E15 ions / cm²-9E15 ions / cm², energy 20KeV-60KeV). After annealing, wet cleaning is used to remove the silicon oxide on the surface.

[0060] In this embodiment, the formed source region 150 is located in the substrate between the two floating gates 130.

[0061] S6: An erase gate 160 is formed on the surface of the substrate 110 corresponding to the source region 150. The erase gate 160 covers the sidewall of the floating gate 130 away from the select gate 120 and the sidewall of the control gate 140 on the top surface of the floating gate 130.

[0062] See Figure 8 Specifically, after annealing, silicon oxide can be regrowed using a high-temperature thermal oxidation process to form a third gate oxide layer 161 on the surface of the substrate 110 of the source region 150, the sidewalls of the floating gate 130 and the control gate 140. Then, polysilicon can be grown on the surface of the third gate oxide layer 161, and the region of the erase gate 160 can be defined using a photolithography process. The morphology of the erase gate 160 is etched so that the erase gate 160 simultaneously covers the sidewalls of the floating gate 130 away from the select gate 120 and the sidewalls of the control gate 140, and the top surface of the erase gate 160 is flush with the top surface of the control gate 140.

[0063] After the erase gate 160 is formed, a first passivation layer 180 can also be formed on the side of the control gate 140 away from the erase gate 160, wherein the first passivation layer 180 is offset from the drain region 170.

[0064] S7: Drain region 170 is formed in substrate 110, wherein drain region 170 is located on the side of select gate 120 away from source region 150.

[0065] Please continue reading Figure 1 Specifically, the photomask of the drain electrode can be defined, and AS / P elements can be injected into the drain region 170 domain (injection dose 1E15 ions / cm²-9E15 ions / cm², energy 20KeV-60KeV), followed by annealing, and finally subsequent CT and BEOL processes.

[0066] In summary, the semiconductor device 100 and its fabrication method provided in this embodiment of the invention form a buried gate trench 111 by slotting a groove on one side surface of a substrate 110. A select gate 120 fills the buried gate trench 111 to form a buried gate structure. A floating gate 130 is located on one side surface of the substrate 110 and is offset from the select gate 120. A control gate 140 is located on one side surface of the substrate 110 and covers the top surface and sidewalls of the floating gate 130. A source region 150 is located in the substrate 110 and its top surface is bonded to one side surface of the substrate 110. The source region 150 is spaced apart from the select gate 120, and the floating gate 130 is located between the source region 150 and the select gate 120. An erase gate 160 is located on one side surface of the substrate 110 and corresponds to the source region 150, and the erase gate 160 can cover the sidewalls of the floating gate 130 and the control gate 140. Drain region 170 is located in substrate 110 and its top surface is bonded to one side surface of substrate 110. Drain region 170 is located on the side of select gate 120 away from source region 150.

[0067] Compared to existing technologies, the semiconductor device 100 and its fabrication method provided in this embodiment of the invention adopt a split gate structure and selects the gate 120 as a buried gate, which makes the arrangement space of the control gate 140 larger. This allows the control gate 140 to cover the top surface and sidewall of the floating gate 130, and the side of the floating gate 130 near the drain can also be covered by the control gate 140. This greatly increases the intersection area of ​​the control gate 140 and the floating gate 130, resulting in a larger coupling effect and higher coupling efficiency. It can meet the requirements of device programming even at relatively low voltages, while also reducing the device read voltage. The overall device has lower power consumption, faster speed, and a simpler boost structure.

[0068] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized in that, include: Substrate, wherein the substrate has buried gate trenches; Select the grid, located in the buried grid trench; A floating gate is located on the surface of the substrate, and the projection of the floating gate onto the substrate does not overlap with the selection gate; A control gate is located on the substrate surface and the top surface of the floating gate, the control gate covering the top surface of the floating gate and the sidewall surface near the selection gate; A source region is located in the substrate, the source region is spaced apart from the selection gate, and the projection of the floating gate onto the substrate is located between the source region and the selection gate; An erase gate is located on the substrate surface corresponding to the source region, and the erase gate covers the sidewall of the floating gate away from the select gate and the sidewall of the control gate on the top surface of the floating gate; The drain region is located in the substrate on the side of the selected gate away from the source region.

2. The semiconductor device according to claim 1, characterized in that, A first passivation layer is also provided on the side of the control gate away from the erase gate, and the projection of the first passivation layer onto the substrate does not overlap with the drain region.

3. The semiconductor device according to claim 2, characterized in that, The projection of the first passivation layer and the control gate of the floating gate sidewall onto the substrate overlaps with the selection gate.

4. The semiconductor device according to claim 1, characterized in that, Also includes: A first gate oxide layer located within the buried gate trench and between the select gate and the substrate; The first gate oxide layer also covers the top surface of the selection gate.

5. The semiconductor device according to claim 1, characterized in that, A second gate oxide layer is disposed between the substrate and the floating gate, and between the substrate and the control gate.

6. The semiconductor device according to claim 1, characterized in that, A third gate oxide layer is disposed between the erase gate and the source region.

7. The semiconductor device according to claim 1, characterized in that, A dielectric layer is disposed between the floating gate and the control gate.

8. The semiconductor device according to claim 7, characterized in that, The dielectric layer includes a first oxide layer, a second passivation layer, and a second oxide layer stacked sequentially. The first oxide layer covers the top surface and sidewalls of the floating gate, the second passivation layer covers the first oxide layer, and the second oxide layer covers the second passivation layer.

9. A method for fabricating a semiconductor device, characterized in that, The preparation method includes: Provide substrate; The surface of the substrate is etched to form buried gate trenches; A selection grid is formed in the buried grid trench; A floating gate and a control gate are formed on the substrate surface, wherein the projection of the floating gate onto the substrate does not overlap with the selection gate, and the control gate is located on the substrate surface and the top surface of the floating gate, covering the top surface of the floating gate and the sidewall surface near the selection gate; Implantation is performed on the substrate to form a source region, wherein the source region is spaced apart from the select gate, and the projection of the floating gate onto the substrate is located between the source region and the select gate; An erase gate is formed on the substrate surface corresponding to the source region, the erase gate covering the sidewall of the floating gate away from the select gate and the sidewall of the control gate on the top surface of the floating gate; Implantation is performed on the substrate on the side of the selected gate away from the source region to form the drain region.

10. The method for fabricating a semiconductor device according to claim 9, characterized in that, The step of forming a floating gate and a control gate on the substrate surface includes: A first polycrystalline silicon layer is formed on the surface of the substrate; The first polysilicon layer is etched to form a floating gate; A second polysilicon layer is formed covering the substrate surface, the sidewalls of the floating gate, and the top surface; A control gate is formed by etching away a portion of the second polysilicon layer on the substrate surface corresponding to the selection gate, the second polysilicon layer on the substrate surface on the side of the selection gate away from the floating gate, and the second polysilicon layer on the substrate surface on the side of the floating gate away from the selection gate.

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