Semiconductor structure and method of manufacturing the same, memory system

Abstract

The embodiments of the present disclosure provide a semiconductor structure, a manufacturing method thereof and a memory system. The semiconductor structure comprises: a plurality of first storage units, each of the first storage units comprising a first storage layer; and a plurality of second storage units, each of the second storage units comprising a second storage layer; wherein each of the second storage units comprises a ferroelectric transistor, and the material of the first storage layer is different from that of the second storage layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, including but not limited to a semiconductor structure and its manufacturing method, and a memory system. Background Technology

[0002] With the rapid development of semiconductor technology, the demands on the performance and size reduction of memory devices are increasing. NAND flash memory can meet the market application requirements for high-capacity, low-cost applications. Taking NAND flash memory as an example, as semiconductor technology advances rapidly, the number of stacked layers of memory cell arrays in NAND flash memory is increasing, and correspondingly, the size of the driving circuitry in the peripheral circuitry is becoming larger. Therefore, miniaturizing NAND flash memory is becoming increasingly difficult. Summary of the Invention

[0003] In view of the above, embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, as well as a memory system.

[0004] In a first aspect, embodiments of this disclosure provide a semiconductor structure, the semiconductor structure comprising: a plurality of first memory cells, each first memory cell including a first memory layer; a plurality of second memory cells, each second memory cell including a second memory layer; wherein the second memory cells include ferroelectric transistors, and the first memory layer and the second memory layer are made of different materials.

[0005] In some embodiments, the first memory cell includes a NAND transistor.

[0006] In some embodiments, the first storage layer includes a floating gate layer or a charge trapping layer; the second storage layer includes a ferroelectric layer.

[0007] In some embodiments, the semiconductor structure further includes: a sub-semiconductor structure, the sub-semiconductor structure including: a stacked structure including a first insulating layer and a first conductive layer alternately stacked along a first direction; and a channel structure extending through the stacked structure along the first direction, the channel structure including at least a first sub-channel structure and a second sub-channel structure stacked together.

[0008] In some embodiments, the first sub-channel structure includes a first dielectric layer, a first storage layer, a second dielectric layer, and a channel layer in a radially inward direction, and the second sub-channel structure includes the second storage layer and the channel layer in a radially inward direction.

[0009] In some embodiments, the semiconductor structure further includes a peripheral circuit coupled to the sub-semiconductor structure.

[0010] In some embodiments, the peripheral circuit further includes: a first driving circuit configured to apply a voltage to the first conductive layer coupled to the first memory cell; and a second driving circuit configured to apply a voltage to the first conductive layer coupled to the second memory cell; wherein the size of the first driving circuit is larger than the size of the second driving circuit.

[0011] In some embodiments, the semiconductor structure further includes: a first sub-semiconductor structure and a second sub-semiconductor structure stacked along a first direction, the first sub-semiconductor structure and the second sub-semiconductor structure being bonded together; the first sub-semiconductor structure includes: a first stacked structure, the first stacked structure including a first insulating layer and a first conductive layer alternately stacked along the first direction; a first channel structure, the first channel structure extending through the first stacked structure along the first direction; the second sub-semiconductor structure includes: a second stacked structure, the second stacked structure including a second insulating layer and a second conductive layer alternately stacked along the first direction; a second channel structure, the second channel structure extending through the second stacked structure along the first direction.

[0012] In some embodiments, the first channel structure includes a first dielectric layer, a first storage layer, a second dielectric layer, and a first channel layer in a radially inward direction, and the second channel structure includes a second storage layer and a second channel layer in a radially inward direction.

[0013] In some embodiments, the semiconductor structure further includes a peripheral circuit coupled to the first sub-semiconductor structure and the second sub-semiconductor structure.

[0014] In some embodiments, the peripheral circuit further includes: a first driving circuit configured to apply a voltage to the first conductive layer coupled to the first memory cell; and a second driving circuit configured to apply a voltage to the second conductive layer coupled to the second memory cell; wherein the size of the first driving circuit is larger than the size of the second driving circuit.

[0015] Secondly, embodiments of this disclosure provide a memory system, the memory system comprising: a semiconductor structure as described in the above technical solutions; and a controller coupled to the semiconductor structure and configured to control the semiconductor structure.

[0016] Thirdly, embodiments of this disclosure provide a method for manufacturing a semiconductor structure, the method comprising: forming a plurality of first memory cells, each first memory cell including a first memory layer; forming a plurality of second memory cells, each second memory cell including a second memory layer; wherein the second memory cells include ferroelectric transistors, and the first memory layer and the second memory layer are made of different materials.

[0017] In some embodiments, the first memory cell includes a NAND transistor.

[0018] In some embodiments, the first storage layer includes a floating gate layer or a charge trapping layer; the second storage layer includes a ferroelectric layer.

[0019] In some embodiments, forming a plurality of first memory cells includes: providing a first sub-initial stack structure, the first sub-initial stack structure including a first insulating layer and a third insulating layer alternately stacked along a first direction; etching the first sub-initial stack structure to form a first sub-channel via; and forming a first dielectric layer, a first memory layer, a second dielectric layer and a first sacrificial layer in the first sub-channel via to form a first sub-initial channel structure.

[0020] In some embodiments, after forming the first sub-initial channel structure, the method further includes: forming a second sub-initial stack structure on the first sub-initial stack structure, the second sub-initial stack structure including a first insulating layer and a third insulating layer alternately stacked along the first direction; the first sub-initial stack structure and the second sub-initial stack structure together forming an initial stack structure; etching the second sub-initial stack structure to form a second sub-channel via exposing the first sacrificial layer; the first sub-channel via and the second sub-channel via together forming a channel via; forming a second storage layer and a second sacrificial layer in the second sub-channel via to form the second sub-initial channel structure.

[0021] In some embodiments, after forming the second sub-initial channel structure, the method further includes: removing the first sacrificial layer and the second sacrificial layer; forming a channel layer in the channel hole to form a channel structure; the channel structure includes a first sub-channel structure disposed in the first sub-channel hole and a second sub-channel structure disposed in the second sub-channel hole.

[0022] In some embodiments, after forming the channel structure, the method further includes: replacing the third insulating layer in the initial stacked structure with a first conductive layer, and the first insulating layer and the first conductive layer, which are alternately stacked, together forming a stacked structure; the stacked structure and the channel structure together form a sub-semiconductor structure.

[0023] In some embodiments, the method further includes: forming a peripheral circuit coupled to the sub-semiconductor structure.

[0024] In some embodiments, forming a plurality of first memory cells includes: providing a first initial stacked structure, the first initial stacked structure including a first insulating layer and a third insulating layer alternately stacked along a first direction; etching the first initial stacked structure to form a first channel via; forming a first dielectric layer, a first memory layer, a second dielectric layer, and a first channel layer in the first channel via to form a first channel structure; replacing the third insulating layer in the first initial stacked structure with a first conductive layer, the alternately stacked first insulating layer and the first conductive layer together forming a first stacked structure; the first stacked structure and the first channel structure together forming a first sub-semiconductor structure.

[0025] In some embodiments, after forming a plurality of first memory cells, the method further includes: bonding the first sub-semiconductor structure and peripheral circuitry together.

[0026] In some embodiments, forming a plurality of second memory cells includes: providing a second initial stacked structure, the second initial stacked structure including a second insulating layer and a fourth insulating layer alternately stacked along the first direction; etching the second initial stacked structure to form a second channel via; forming a second memory layer and a second channel layer in the second channel via to form a second channel structure; replacing the fourth insulating layer in the second initial stacked structure with a second conductive layer, the alternately stacked second insulating layer and the second conductive layer together forming a second stacked structure; the second stacked structure and the second channel structure together forming a second sub-semiconductor structure.

[0027] In some embodiments, the method further includes: bonding the first sub-semiconductor structure and the second sub-semiconductor structure together, wherein the first sub-semiconductor structure is disposed between the peripheral circuit and the second sub-semiconductor structure.

[0028] This disclosure provides a semiconductor structure, a method for manufacturing the same, and a memory system. In this embodiment, the semiconductor structure includes multiple first memory cells and multiple second memory cells. Each second memory cell includes a ferroelectric transistor. The materials of the first storage layer in the first memory cell and the second storage layer in the second memory cell are different. Low-voltage transistors can be used in the driving circuit that operates the ferroelectric transistors to reduce the size of the driving circuit, thereby reducing the area occupied by the peripheral circuitry and increasing the storage density of the semiconductor structure. Attached Figure Description

[0029] Figure 1 Cross-sectional schematic diagrams of semiconductor structures provided for some examples;

[0030] Figure 2 This is a cross-sectional structural diagram of a semiconductor structure provided in some embodiments of the present disclosure;

[0031] Figure 3 Block diagrams of semiconductor structures provided in some embodiments of this disclosure;

[0032] Figure 4 This is a cross-sectional structural schematic diagram of a semiconductor structure provided in some other embodiments of the present disclosure;

[0033] Figure 5 Block diagrams of semiconductor structures provided in other embodiments of this disclosure;

[0034] Figure 6 A schematic flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of this disclosure;

[0035] Figures 7 to 14 A cross-sectional structural diagram illustrating the semiconductor structure during the manufacturing process provided in some embodiments of this disclosure;

[0036] Figures 15 to 24 A cross-sectional structural diagram of a semiconductor structure during the manufacturing process, provided for other embodiments of this disclosure;

[0037] Figure 25 A block diagram of a memory system provided in an embodiment of this disclosure;

[0038] Figure 26 A block diagram of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0039] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0040] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0041] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0042] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0043] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0044] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0045] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0046] Here, we first define the various directions that may be involved in the following description. The stacking direction in the stacked structure is defined as the first direction (i.e., the Z direction). In the plane perpendicular to the Z direction, the intersecting second direction (i.e., the X direction) and the third direction (i.e., the Y direction) are defined. In some embodiments, the X direction and the Y direction can be perpendicular to each other, so that the X direction, Y direction and Z direction are mutually perpendicular.

[0047] refer to Figure 1 , Figure 1 Cross-sectional schematic diagrams of semiconductor structures are provided for some examples. For instance... Figure 1 As shown, the semiconductor structure 100 includes: a stacked structure 102, which includes a gate dielectric layer 104 and a gate conductive layer 106 alternately stacked along the Z direction; and a channel structure 108 (e.g., Figure 1 (As shown in the dashed box), the channel structure 108 extends along the Z-direction through the stacked structure 102. Figure 1 The enlarged schematic diagram of the channel structure 108 shown in the dashed circle shows that the channel structure 108 includes a barrier layer 110, a storage layer 112, a tunneling layer 114, a channel layer 116, and a filling layer 118 in the radially inward direction. Figure 1 The solid circle in the middle indicates the memory cell 120. The channel structure 108 and the gate conductive layer 106 in contact with it together form the memory cell 120. The gate conductive layer 106 forms the gate of the transistor, the channel layer 116 forms the channel of the transistor, and the channel structure 108 includes a top end and a bottom end opposite to each other along the Z direction. The top end of the channel structure 108 is coupled to the bit line, and the bottom end of the channel structure 108 is coupled to the source line.

[0048] In the aforementioned technical solutions, the semiconductor structure can meet the market application demands for high capacity and low cost. However, with the rapid development of semiconductor technology, the number of stacked layers of memory cell arrays in semiconductor structures is increasing, correspondingly leading to greater pressure on the area occupied by the peripheral circuits corresponding to the memory cell arrays. Therefore, how to reduce the area occupied by the peripheral circuits and improve the storage density of semiconductor structures has become an urgent problem to be solved.

[0049] Still referencing Figure 1As shown, the semiconductor structure 100 may further include: a source layer 122 disposed on one side of the stacked structure 102 along the Z direction; a channel structure 108 extending through the stacked structure 102 along the Z direction and into the source layer 122; the bottom end of the channel structure 108 exposes a channel layer 116, and a portion of the exposed channel layer 116 contacts the source layer 122. Exemplarily, forming... Figure 1 The schematic diagram of the contact morphology between the channel layer 116 and the source layer 122 may include the following steps: providing a substrate; forming an initial stacked structure on one side of the substrate along the Z direction, the initial stacked structure including a gate dielectric layer 104 and a gate sacrificial layer alternately stacked along the Z direction; etching the initial stacked structure along the Z direction to form a channel via that penetrates the initial stacked structure and extends into the substrate; sequentially forming a barrier layer 110, a storage layer 112, a tunneling layer 114, a channel layer 116, and a fill layer 118 in the channel via to form a channel structure 108; and using gate line slots to separate the gate... The sacrificial layer is replaced with a gate conductive layer 106, and the gate dielectric layer 104 and the gate conductive layer 106 are alternately stacked along the Z direction to form a stacked structure 102; the substrate is removed to expose the bottom end of the channel structure 108; the barrier layer 110, the storage layer 112 and the tunneling layer 114 in the bottom end of the channel structure 108 are removed to expose a portion of the channel layer 116 in the bottom end of the channel structure 108; a source layer 122 is formed covering the bottom end of the channel structure 108, and a portion of the channel layer 116 in the bottom end of the channel structure 108 is in contact with the source layer 122.

[0050] Figure 1 The illustrated morphology of the contact between the channel layer 116 and the source layer 122 is for illustrative purposes only, and there may be other contact methods between the channel layer 116 and the source layer 122. In other examples, a substrate is provided; an initial stacked structure is formed on one side of the substrate along the Z-direction, the initial stacked structure including a gate dielectric layer and a gate sacrificial layer alternately stacked along the Z-direction; the initial stacked structure is etched along the Z-direction to form a channel via extending through the initial stacked structure into the substrate; an epitaxial layer is formed at the bottom of the channel via, and a barrier layer, a storage layer, a tunneling layer, and a protective layer are sequentially formed in the channel via, the protective layer, tunneling layer, storage layer, and barrier layer may be, for example, a silicon layer / silicon oxide / silicon nitride / silicon oxide (SONO) structure; the SONO structure is etched to form a via, and the epitaxial layer is etched through the via to form a trench in the epitaxial layer; the protective layer is removed; a channel layer and a fill layer are sequentially formed in the via and the trench; wherein the channel layer and the epitaxial layer are in contact; the gate sacrificial layer is replaced with a gate conductive layer using gate line slots, and the gate dielectric layer and the gate conductive layer alternately stacked along the Z-direction together form the stacked structure. Here, the epitaxial layer can serve as a source layer.

[0051] In some other examples, a substrate is provided; a source sacrificial layer, a semiconductor layer, an insulating layer, and an initial stacked structure are sequentially formed on one side of the substrate along the Z direction, the initial stacked structure including a gate dielectric layer and a gate sacrificial layer alternately stacked along the Z direction; the initial stacked structure, the insulating layer, the semiconductor layer, and the source sacrificial layer are etched along the Z direction to form a channel via extending through the initial stacked structure, the insulating layer, the semiconductor layer, and the source sacrificial layer into the substrate; a barrier layer, a storage layer, a tunneling layer, a channel layer, and a fill layer are sequentially formed in the channel via to form a channel structure; the gate sacrificial layer is replaced with a gate conductive layer using gate wire slots, and the gate dielectric layer and the gate conductive layer alternately stacked along the Z direction together form the stacked structure; the source sacrificial layer can also be removed using gate wire slots to form a lateral recess between the substrate and the semiconductor layer, and a portion of the barrier layer, the storage layer, and the tunneling layer exposed by the lateral recess are removed to expose a portion of the channel layer; a conductive material is deposited in the lateral recess to form a source layer, the source layer being in contact with the sidewalls of the channel structure and the channel layer. When the channel structure extends into the N-type doped region of the substrate and the conductive layer is N-type polysilicon, a sidewall N-poly / N-sub (SWNN) structure is formed.

[0052] In view of the above, embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, as well as a memory system.

[0053] This disclosure provides a semiconductor structure comprising: a plurality of first memory cells, each first memory cell including a first memory layer; a plurality of second memory cells, each second memory cell including a second memory layer; wherein the second memory cells include ferroelectric transistors, and the first and second memory layers are made of different materials.

[0054] In this embodiment, the semiconductor structure includes a plurality of first memory cells and a plurality of second memory cells. Each second memory cell includes a ferroelectric transistor. The materials of the first storage layer in the first memory cell and the second storage layer in the second memory cell are different. Low-voltage transistors can be used in the driving circuit that operates the ferroelectric transistor to reduce the size of the driving circuit, thereby reducing the area occupied by the peripheral circuitry and increasing the storage density of the semiconductor structure.

[0055] In some embodiments, the first storage cell includes a NAND transistor.

[0056] In this embodiment, the first memory cell includes a NAND transistor, and the second memory cell includes a ferroelectric transistor. That is, the semiconductor structure can simultaneously include both NAND transistors and ferroelectric transistors, allowing for a comparison of the characteristics of the first and second memory cells in terms of both storage capacity and the area occupied by the peripheral circuitry.

[0057] Firstly, the storage capacity of the first storage cell and the second storage cell are compared. In some embodiments, each first storage cell may be a single-level cell (SLC) having two possible storage states and thus capable of storing one bit of data. For example, an SLC may have a first storage state "1" and a second storage state "0". Here, the threshold voltage distribution of the first storage state "1" may correspond to a first voltage range, and the threshold voltage distribution of the second storage state "0" may correspond to a second voltage range. The first storage state is an erase state, and the second storage state is a programmable state. In some embodiments, each first storage cell is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four storage states. For example, an MLC may store two bits of data per cell, three bits of data per cell (also known as a triple-level cell (TLC)), or four bits of data per cell (also known as a quad-level cell (QLC)). Each MLC may be programmed to take a voltage range of possible threshold voltage distributions. In one example, if each MLC stores two bits of data, the MLC can have a first storage state "11", a second storage state "10", a third storage state "01", and a fourth storage state "00". Here, the threshold voltage distributions for the first, second, third, and fourth storage states correspond to the first, second, third, and fourth voltage ranges, respectively. The first storage state is the erase state, and the second, third, and fourth storage states are all programming states. Similarly, a TLC can have 8 storage states, including an erase state and 7 programming states; a QLC can have 16 storage states, including an erase state and 15 programming states.

[0058] In the second memory cell, "0" or "1" can be stored depending on the direction of spontaneous polarization in the ferroelectric layer, and the second memory cell can store one bit of data. Therefore, compared with the first memory cell and the second memory cell, the first memory cell has a higher storage capacity. Including the first memory cell in the semiconductor structure is beneficial to improving the storage capacity and integration of the semiconductor structure, meeting the needs of high-capacity application scenarios.

[0059] Secondly, let's compare the area occupied by the peripheral circuits corresponding to the first and second memory cells. The driver circuit (String Driver, SD) that performs operations on the first memory cell requires high-voltage transistors, resulting in a larger driver circuit size. Conversely, the driver circuit that performs operations on the second memory cell can use low-voltage transistors, resulting in a smaller driver circuit size. Therefore, compared to the first memory cell, the peripheral circuit of the second memory cell occupies a smaller area. Including the second memory cell in the semiconductor structure helps reduce the number of high-voltage transistors in the peripheral circuit, thereby reducing the area occupied by the peripheral circuit in the semiconductor structure and meeting the requirements of small-size applications.

[0060] Therefore, integrating NAND transistors and ferroelectric transistors allows for the use of NAND transistors to increase the storage capacity of semiconductor structures and the use of ferroelectric transistors to reduce the area occupied by peripheral circuits in semiconductor structures, thus meeting the needs of different application scenarios and improving design flexibility.

[0061] In some embodiments, the first storage layer includes a floating gate (FG) layer or a charge trap flash (CTF) layer; the second storage layer includes a ferroelectric layer.

[0062] Here, the first storage layer includes a floating gate layer, and the first storage cell is a floating gate transistor; the first storage layer also includes a charge trapping layer, and the first storage cell is a charge trapping transistor. The floating gate transistor includes a substrate and a tunneling layer, a floating gate layer, an oxide layer, and a control gate layer sequentially disposed on the substrate, with the source and drain formed in the substrate on opposite sides of the control gate layer, respectively. The charge trapping transistor includes a substrate and a tunneling layer, a charge trapping layer, an oxide layer, and a control gate layer sequentially disposed on the substrate, with the source and drain formed in the substrate on opposite sides of the control gate layer, respectively. The difference between the floating gate transistor and the charge trapping transistor lies in the materials of the floating gate layer and the charge trapping layer. The floating gate layer uses a conductive material to store charge, while the charge trapping layer uses an insulating material with high charge trapping density (e.g., silicon nitride) to store charge. During programming, a high voltage is applied to the control gate layer to generate a strong electric field, allowing electrons in the channel to gain sufficient energy to enter the floating gate layer (or the charge trapping layer) and be stored. At this point, the floating gate layer (or charge trapping layer) carries a negative charge, indicating that "0" is stored. During the erase operation, a high voltage is applied to the substrate, causing electrons in the floating gate layer (or charge trapping layer) to return to the substrate, and the floating gate layer (or charge trapping layer) loses its charge, indicating that "1" is stored.

[0063] Here, we briefly explain the changes in the ferroelectric layer in the second memory cell during the application and removal of an external electric field. When an external electric field is applied to the ferroelectric layer, the polarization P follows a hysteresis loop as the applied external electric field strength E changes. More specifically, when a positive external electric field is applied to the ferroelectric layer and the external electric field strength E is gradually increased, the polarization P of the ferroelectric layer also gradually increases until it reaches a saturation state Ps. Afterward, if the external electric field strength E is decreased, when the external electric field strength E is 0, the ferroelectric layer still has residual polarization Pr. In other words, after removing the positive external electric field, the polarization in the ferroelectric layer does not disappear; the ferroelectric layer still has residual polarization Pr. If it is necessary to completely depolarize the ferroelectric layer, a negative external electric field needs to be applied to the ferroelectric layer until the external electric field strength E reaches a negative coercive field -Ec. Continuing to increase the external electric field strength E, the polarization P of the ferroelectric layer also gradually increases until it reaches a saturation state -Ps. Subsequently, if the external electric field strength E is reduced, the ferroelectric layer still exhibits negative remanent polarization -Pr when the external electric field strength E is 0. In other words, removing the negative external electric field does not eliminate the polarization in the ferroelectric layer; the ferroelectric layer still possesses remanent polarization -Pr. If it is necessary to completely depolarize the ferroelectric layer, a positive external electric field needs to be applied until the external electric field strength E reaches the positive coercive field Ec. In this way, the hysteresis loop can be repeated multiple times to change the polarization direction in the ferroelectric layer. Depending on the direction of spontaneous polarization in the ferroelectric layer, either "0" or "1" can be stored.

[0064] A ferroelectric transistor includes a substrate and a ferroelectric layer and a control gate layer sequentially disposed on the substrate. The source and drain are formed in the substrate on opposite sides of the control gate layer, respectively. During programming, a positive voltage is applied to the control gate layer. When the polarization is downward, the ferroelectric layer induces a negative charge in the channel, resulting in a lower threshold voltage. That is, after programming, the threshold voltage of the ferroelectric transistor decreases. During erasing, a positive voltage is applied to the channel of the ferroelectric transistor. When the polarization is upward, the ferroelectric layer induces a positive charge in the channel, resulting in a higher threshold voltage. That is, after erasing, the threshold voltage of the ferroelectric transistor increases.

[0065] In some embodiments, the semiconductor structure may include multiple sub-decks, such as a first sub-deck and a second sub-deck, wherein the first sub-deck has multiple first sub-channel structures and the second sub-deck has multiple second sub-channel structures; wherein the first sub-channel structure includes a first memory layer and the second sub-channel structure includes a second memory layer. The following will combine... Figure 2 and Figure 3 The semiconductor structure is described in detail.

[0066] refer to Figure 2 and Figure 3 , Figure 2This is a cross-sectional schematic diagram of a semiconductor structure provided in some embodiments of this disclosure. Figure 3 Block diagrams illustrating semiconductor structures provided in some embodiments of this disclosure. For example... Figure 2 and Figure 3 As shown, in some embodiments, the semiconductor structure 200 further includes: a sub-semiconductor structure 206, the sub-semiconductor structure 206 including: a stacked structure 208, the stacked structure 208 including a first insulating layer 210 and a first conductive layer 212 alternately stacked along the Z direction; a channel structure 214, the channel structure 214 extending through the stacked structure 208 along the Z direction, the channel structure 214 including at least a first sub-channel structure 216 and a second sub-channel structure 218 stacked.

[0067] Here, the stacked structure 208 may include a plurality of first insulating layers 210 and a plurality of first conductive layers 212. The first insulating layer 210 may also be referred to as a gate dielectric layer, and the first conductive layer 212 may also be referred to as a gate conductive layer. The first insulating layer 210 includes an insulating material, such as silicon oxide. The first conductive layer 212 includes a conductive material, such as tungsten metal. This disclosure does not impose any particular limitation on the number of first insulating layers 210 and first conductive layers 212 included in the stacked structure 208, nor on the thickness of the first insulating layers 210 and first conductive layers 212; these can be selected according to actual conditions. In some embodiments, the first conductive layer 212 may include a single-layer structure, such as a tungsten metal layer. In other embodiments, the first conductive layer 212 may include a multilayer structure, such as a titanium nitride layer and a tungsten metal layer.

[0068] Here, the stacking structure 208 includes at least a first sub-stack structure 266 and a second sub-stack structure 268 disposed on the first sub-stack structure 266. The first sub-stack structure 266 may include a plurality of first insulating layers 210 and a plurality of first conductive layers 212 alternately stacked along the Z direction. The second sub-stack structure 268 may include a plurality of first insulating layers 210 and a plurality of first conductive layers 212 alternately stacked along the Z direction. In some embodiments, the number of first insulating layers 210 and first conductive layers 212 included in the first sub-stack structure 266 and the number of first insulating layers 210 and first conductive layers 212 included in the second sub-stack structure 268 may be the same or different, that is, the height of the first sub-stack structure 266 along the Z direction and the height of the second sub-stack structure 268 along the Z direction may be the same or different.

[0069] In some embodiments of this disclosure, the stacked structure 208 is exemplified by including a first sub-stacked structure 266 and a second sub-stacked structure 268. In practice, the stacked structure 208 may include more sub-stacked structures. This disclosure does not impose a special limitation on the number of sub-stacked structures included in the stacked structure 208, and the number can be selected according to the actual situation. The number of first insulating layers 210 and first conductive layers 212 included in different sub-stacked structures may be the same or different, that is, the height of different sub-stacked structures along the Z direction may be the same or different.

[0070] Here, each of the plurality of channel structures 214 extends along the Z-direction and passes through the stacked structure 208. Each channel structure 214 includes at least a first sub-channel structure 216 and a second sub-channel structure 218 disposed on the first sub-channel structure 216. The first sub-channel structure 216 includes a first storage layer 222, and the second sub-channel structure 218 includes a second storage layer 232. The first storage layer 222 and the second storage layer 232 are made of different materials. In some embodiments, the height of the first sub-channel structure 216 along the Z-direction and the height of the second sub-channel structure 218 along the Z-direction may be the same or different.

[0071] In some embodiments of this disclosure, each channel structure 214 is exemplarily described as including a first sub-channel structure 216 and a second sub-channel structure 218. In practice, each channel structure 214 may include more sub-channel structures. This disclosure does not impose a special limitation on the number of sub-channel structures included in each channel structure 214, and the number can be selected according to the actual situation. The heights of different sub-channel structures in each channel structure 214 along the Z direction may be the same or different.

[0072] It should be noted that the number of sub-stack structures included in the stacked structure is the same as the number of sub-channel structures included in each channel structure. In each channel structure, multiple sub-channel structures are connected in series sequentially.

[0073] In some embodiments, the first sub-channel structure 216 and the first conductive layer 212 in contact with it together form a first memory cell 202, and the second sub-channel structure 218 and the first conductive layer 212 in contact with it together form a second memory cell 204. The first memory cell 202 and the second memory cell 204 can together form a memory cell array. Figure 2 The solid circle in the middle indicates the first storage unit 202 and the second storage unit 204.

[0074] In some embodiments, Figure 2The first sub-channel structure 216 and the second sub-channel structure 218 shown in the dashed circle are enlarged schematic diagrams. The first sub-channel structure 216 includes at least a first dielectric layer 220, a first storage layer 222, a second dielectric layer 224 and a channel layer 226 in the radially inward direction. The second sub-channel structure 218 includes at least a second storage layer 232 and a channel layer 226 in the radially inward direction.

[0075] Here, for the first memory cell 202, the first conductive layer 212 serves as a control gate layer, the first dielectric layer 220 serves as an oxide layer, the first memory layer 222 serves as a floating gate layer or a charge trapping layer, the second dielectric layer 224 serves as a tunneling oxide layer, and the channel layer 226 serves as a channel in a floating gate transistor or a charge trapping transistor. Exemplarily, the first sub-channel structure 216 may include a composite layer of silicon oxide / silicon nitride / silicon oxide (ONO). For the second memory cell 204, the first conductive layer 212 serves as a control gate layer, the second memory layer 232 serves as a ferroelectric layer, and the channel layer 226 serves as a channel in a ferroelectric transistor. It should be noted that the channel layer 226 in the first sub-channel structure 216 and the second sub-channel structure 218 can be formed in the same process, and the channel layer 226 may include, for example, polysilicon.

[0076] In some embodiments, the first sub-channel structure 216 further includes a filler layer 228, the channel layer 226 being disposed between the second dielectric layer 224 and the filler layer 228; the second sub-channel structure 218 further includes a filler layer 228, the channel layer 226 being disposed between the second storage layer 232 and the filler layer 228. The material of the filler layer 228 can be, for example, silicon oxide. It should be noted that the filler layer 228 in the first sub-channel structure 216 and the second sub-channel structure 218 can be formed in the same process.

[0077] In some embodiments, the second sub-channel structure 218 further includes a third dielectric layer 230 disposed between the second storage layer 232 and the first conductive layer 212. The third dielectric layer 230 can be used to reduce the interaction between the second storage layer 232 and the first conductive layer 212. The material of the third dielectric layer 230 can be, for example, silicon oxide, silicon nitride, silicon oxynitride, or other dielectric materials.

[0078] In some embodiments, the second sub-channel structure 218 further includes a fourth dielectric layer 234 disposed between the second storage layer 232 and the channel layer 226. The fourth dielectric layer 234 can be used to reduce the possibility of material mixing between the second storage layer 232 and the channel layer 226. The material of the fourth dielectric layer 234 can be, for example, silicon oxide, silicon nitride, silicon oxynitride, or other dielectric materials.

[0079] In the above embodiments, the first sub-channel structure 216 includes a plurality of first memory cells 202 connected in series, that is, the first sub-channel structure 216 includes a plurality of NAND transistors connected in series; the second sub-channel structure 218 includes a plurality of second memory cells 204 connected in series, that is, the second sub-channel structure 218 includes a plurality of ferroelectric transistors connected in series. In the same channel structure 214, the NAND transistors and the ferroelectric transistors are connected in series.

[0080] It should be noted that, Figure 2 The final product structure was not shown. Figure 2 The channel structure 214 illustrated herein can be in contact with the source layer using the methods described above. For example, a source layer in contact with the exposed channel layer 226 can be formed by exposing the channel layer 226 at the bottom end of the channel structure 214; alternatively, the epitaxial layer and the channel layer 226 can be in contact using a SONO structure; still alternatively, the source layer can be in contact with a portion of the exposed channel layer 226 on the sidewall of the channel structure 214 using an SWNN structure. This disclosure does not impose any particular limitations on the contact method between the channel layer 226 and the source layer, nor on the method for forming the source layer, and the appropriate method can be flexibly selected according to the actual situation.

[0081] like Figure 3 As shown, in some embodiments, the semiconductor structure 200 further includes a peripheral circuit 236 coupled to the sub-semiconductor structure 206.

[0082] In some embodiments, the sub-semiconductor structure 206 and peripheral circuitry 236 can be fabricated on the same wafer, with the peripheral circuitry 236 disposed adjacent to the sub-semiconductor structure 206 (Peripheral Near Core, PNC). In other embodiments, the sub-semiconductor structure 206 and peripheral circuitry 236 can be fabricated on different wafers, for example, the sub-semiconductor structure 206 can be fabricated on a first wafer, and the peripheral circuitry 236 can be fabricated on a second wafer. The first and second wafers are then bonded together, and the sub-semiconductor structure 206 and peripheral circuitry 236 are bonded together. The sub-semiconductor structure 206 and peripheral circuitry 236 are stacked along the Z-direction, for example, the peripheral circuitry 236 is disposed above the sub-semiconductor structure 206 (Peripheral Above Core, PAC) or below the sub-semiconductor structure 206 (Peripheral Under Core, PUC). Stacking the sub-semiconductor structure 206 and peripheral circuitry 236 helps to reduce the area occupied by the semiconductor structure 200. Figure 3 The PUC architecture is used as an example for illustration.

[0083] In this document, the term "bonding" can include any suitable bonding technique, such as hybrid bonding, anodic bonding, fusion bonding, transfer bonding, adhesive bonding, and eutectic bonding. Hybrid bonding is a direct bonding technique that forms a bond between surfaces without the use of an intermediate layer such as solder or adhesive, and can simultaneously achieve metal-to-metal and dielectric-to-dielectric bonding.

[0084] In some embodiments, the peripheral circuit 236 further includes: a first driving circuit 238 configured to apply a voltage to a first conductive layer 212 coupled to a first memory cell 202; and a second driving circuit 240 configured to apply a voltage to a first conductive layer 212 coupled to a second memory cell 204; wherein the size of the first driving circuit 238 is larger than the size of the second driving circuit 240.

[0085] Here, the voltage applied by the first driving circuit 238 to the first conductive layer 212 coupled to the first memory cell 202 is greater than the voltage applied by the second driving circuit 240 to the first conductive layer 212 coupled to the second memory cell 204. The first driving circuit 238 requires the use of high-voltage transistors, while the second driving circuit 240 can use low-voltage transistors. In other words, the operating voltage of the transistors in the first driving circuit 238 is greater than the operating voltage of the transistors in the second driving circuit 240, meaning the size of the first driving circuit 238 is greater than the size of the second driving circuit 240.

[0086] In other embodiments, the semiconductor structure may include multiple stacked structures, such as a first stacked structure and a second stacked structure. The first stacked structure has a plurality of first channel structures, and the second stacked structure has a plurality of second channel structures. The first channel structure includes a first memory layer, and the second channel structure includes a second memory layer. The following will combine... Figure 4 and Figure 5 The semiconductor structure is described in detail.

[0087] refer to Figure 4 and Figure 5 , Figure 4 This is a cross-sectional schematic diagram of a semiconductor structure provided in other embodiments of this disclosure. Figure 5 Block diagrams illustrating semiconductor structures provided for other embodiments of this disclosure. For example... Figure 4 and Figure 5As shown, in some embodiments, the semiconductor structure 300 further includes: a first sub-semiconductor structure 306 and a second sub-semiconductor structure 308 stacked along the Z direction, the first sub-semiconductor structure 306 and the second sub-semiconductor structure 308 being bonded together; the first sub-semiconductor structure 306 includes: a first stacked structure 310, the first stacked structure 310 including a plurality of first insulating layers 312 and a plurality of first conductive layers 314 alternately stacked along the Z direction; a plurality of first channel structures 316, each first channel structure 316 extending through the first stacked structure 310 along the Z direction; the second sub-semiconductor structure 308 includes: a second stacked structure 318, the second stacked structure 318 including a plurality of second insulating layers 320 and a plurality of second conductive layers 322 alternately stacked along the Z direction; a plurality of second channel structures 324, each second channel structure 324 extending through the second stacked structure 318 along the Z direction.

[0088] Here, the first stacked structure 310 may include a plurality of first insulating layers 312 and a plurality of first conductive layers 314, and the second stacked structure 318 may include a plurality of second insulating layers 320 and a plurality of second conductive layers 322. Both the first insulating layer 312 and the second insulating layer 320 comprise an insulating material, such as silicon oxide. Both the first conductive layer 314 and the second conductive layer 322 comprise a conductive material, such as tungsten metal. This disclosure does not impose any particular limitation on the number of first insulating layers 312 and first conductive layers 314 included in the first stacked structure 310, the number of second insulating layers 320 and second conductive layers 322 included in the second stacked structure 318, the thickness of the first insulating layer 312 and the first conductive layer 314, and the thickness of the second insulating layer 320 and the second conductive layer 322, and these can be selected according to actual conditions. In some embodiments, the first conductive layer 314 and the second conductive layer 322 may comprise a single-layer structure, such as a tungsten metal layer. In other embodiments, the first conductive layer 314 and the second conductive layer 322 may comprise a multilayer structure, such as a titanium nitride layer and a tungsten metal layer.

[0089] Here, the first stacked structure 310 can be disposed on the first wafer, and the second stacked structure 318 can be disposed on the second wafer. The number of the first insulating layer 312 and the first conductive layer 314 included in the first stacked structure 310 and the number of the second insulating layer 320 and the second conductive layer 322 included in the second stacked structure 318 can be the same or different. That is, the height of the first stacked structure 310 along the Z direction and the height of the second stacked structure 318 along the Z direction can be the same or different.

[0090] In other embodiments of this disclosure, the semiconductor structure 300 is illustrated by including a first stacked structure 310 and a second stacked structure 318. In practice, the semiconductor structure 300 may include more stacked structures. This disclosure does not impose a special limitation on the number of stacked structures included in the semiconductor structure 300, and the number can be selected according to the actual situation. The number of insulating layers and conductive layers included in different stacked structures may be the same or different, that is, the height of different stacked structures along the Z direction may be the same or different.

[0091] Here, each of the plurality of first channel structures 316 extends along the Z-direction and passes through the first stack structure 310, and each first channel structure 316 includes a first storage layer 328; each of the plurality of second channel structures 324 extends along the Z-direction and passes through the second stack structure 318, and each second channel structure 324 includes a second storage layer 338; wherein the first storage layer 328 and the second storage layer 338 are made of different materials. In some embodiments, the height of the first channel structure 316 along the Z-direction and the height of the second channel structure 324 along the Z-direction may be the same or different.

[0092] In some embodiments, the first channel structure 316 and the first conductive layer 314 in contact with it together form a first memory cell 302, and multiple first memory cells 302 can form a first memory cell array; the second channel structure 324 and the second conductive layer 322 in contact with it together form a second memory cell 304, and multiple second memory cells 304 can form a second memory cell array. The first memory cell array and the second memory cell array can be stacked. Figure 4 The solid circle in the middle indicates the first storage unit 302 and the second storage unit 304.

[0093] In some embodiments, Figure 4 The first channel structure 316 and the second channel structure 324 shown in the dashed circle are enlarged schematic diagrams. The first channel structure 316 includes at least a first dielectric layer 326, a first storage layer 328, a second dielectric layer 330 and a first channel layer 332 in the radially inward direction. The second channel structure 324 includes at least a second storage layer 338 and a second channel layer 342 in the radially inward direction.

[0094] Here, for the first memory cell 302, the first conductive layer 314 serves as a control gate layer, the first dielectric layer 326 serves as an oxide layer, the first memory layer 328 serves as a floating gate layer or a charge trapping layer, the second dielectric layer 330 serves as a tunneling oxide layer, and the first channel layer 332 serves as a channel in a floating gate transistor or a charge trapping transistor. Exemplarily, the first channel structure 316 may include a composite layer of silicon oxide / silicon nitride / silicon oxide (ONO). For the second memory cell 304, the second conductive layer 322 serves as a control gate layer, the second memory layer 338 serves as a ferroelectric layer, and the second channel layer 342 serves as a channel in a ferroelectric transistor. It should be noted that the first channel layer 332 and the second channel layer 342 are formed in different processes, and the first channel layer 332 and the second channel layer 342 may include, for example, polysilicon.

[0095] In some embodiments, the first channel structure 316 further includes a first filler layer 334, and the first channel layer 332 is disposed between the second dielectric layer 330 and the first filler layer 334; the second channel structure 324 further includes a second filler layer 344, and the second channel layer 342 is disposed between the second storage layer 338 and the second filler layer 344. The material of the first filler layer 334 and the second filler layer 344 can be, for example, silicon oxide. It should be noted that the first filler layer 334 and the second filler layer 344 are formed in different processes.

[0096] In some embodiments, the second channel structure 324 further includes a third dielectric layer 336 disposed between the second storage layer 338 and the second conductive layer 322. The third dielectric layer 336 can be used to reduce the interaction between the second storage layer 338 and the second conductive layer 322. The material of the third dielectric layer 336 can be, for example, silicon oxide, silicon nitride, silicon oxynitride, or other dielectric materials.

[0097] In some embodiments, the second channel structure 324 further includes a fourth dielectric layer 340 disposed between the second storage layer 338 and the second channel layer 342. The fourth dielectric layer 340 can be used to reduce the possibility of mixing between the second storage layer 338 and the second channel layer 342. The material of the fourth dielectric layer 340 can be, for example, silicon oxide, silicon nitride, silicon oxynitride, or other dielectric materials.

[0098] In the above embodiments, the first channel structure 316 includes a plurality of first memory cells 302 connected in series, that is, the first channel structure 316 includes a plurality of NAND transistors connected in series; the second channel structure 324 includes a plurality of second memory cells 304 connected in series, that is, the second channel structure 324 includes a plurality of ferroelectric transistors connected in series.

[0099] like Figure 5As shown, in some embodiments, the semiconductor structure 300 further includes a peripheral circuit 346, which is coupled to the first sub-semiconductor structure 306 and the second sub-semiconductor structure 308.

[0100] In some embodiments, a first sub-semiconductor structure 306 may be fabricated on a first wafer, a second sub-semiconductor structure 308 on a second wafer, and a peripheral circuit 346 on a third wafer. The first, second, and third wafers are then bonded together, and the first sub-semiconductor structure 306, the second sub-semiconductor structure 308, and the peripheral circuit 346 are bonded together. This disclosure does not impose any particular limitations on the relative positional relationship or bonding order between the first sub-semiconductor structure 306, the second sub-semiconductor structure 308, and the peripheral circuit 346. Figure 5 The example shown is that the first sub-semiconductor structure 306 is disposed between the second sub-semiconductor structure 308 and the peripheral circuit 346.

[0101] In some embodiments, the peripheral circuit 346 further includes: a first driving circuit 348 configured to apply a voltage to a first conductive layer 314 coupled to a first memory cell 302; and a second driving circuit 350 configured to apply a voltage to a second conductive layer 322 coupled to a second memory cell 304; wherein the size of the first driving circuit 348 is larger than the size of the second driving circuit 350.

[0102] Here, the voltage applied by the first driving circuit 348 to the first conductive layer 314 coupled to the first memory cell 302 is greater than the voltage applied by the second driving circuit 350 to the second conductive layer 322 coupled to the second memory cell 304. The first driving circuit 348 requires the use of high-voltage transistors, while the second driving circuit 350 can use low-voltage transistors. In other words, the operating voltage of the transistors in the first driving circuit 348 is greater than the operating voltage of the transistors in the second driving circuit 350, meaning the size of the first driving circuit 348 is larger than the size of the second driving circuit 350.

[0103] refer to Figure 6 , Figure 6 This is a schematic flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of this disclosure. Figure 6 As shown in the embodiments of this disclosure, a method for manufacturing a semiconductor structure is provided, the method comprising:

[0104] Step S410: Form a plurality of first storage cells, each first storage cell including a first storage layer;

[0105] Step S420: Form a plurality of second memory cells, each second memory cell including a second memory layer; wherein the second memory cell includes a ferroelectric transistor, and the materials of the first memory layer and the second memory layer are different.

[0106] refer to Figures 7 to 14 , Figures 7 to 14 This is a cross-sectional structural diagram illustrating the semiconductor structure during the manufacturing process, as provided in some embodiments of this disclosure. The following will be combined with... Figure 6 and Figures 7 to 14 The present disclosure provides a detailed description of the manufacturing process of semiconductor structures provided in some embodiments.

[0107] like Figure 7 As shown, a first substrate 242 is provided; in some embodiments, step S410 includes: forming a first sub-initial stack structure 244 on one side of the first substrate 242 along the Z direction, the first sub-initial stack structure 244 including a plurality of first insulating layers 210 and a plurality of third insulating layers 250 alternately stacked along the Z direction; etching the first sub-initial stack structure 244 along the Z direction to form a first sub-channel hole 252 that penetrates the first sub-initial stack structure 244 and extends into the first substrate 242; and sequentially forming a first dielectric layer 220, a first storage layer 222, a second dielectric layer 224 and a first sacrificial layer 262 in the first sub-channel hole 252 to form a first sub-initial channel structure 258. Figure 7 The dashed circle in the middle provides an enlarged view of the first sub-initial channel structure 258.

[0108] Here, the first substrate 242 may be a semiconductor substrate, specifically including at least one elemental semiconductor material (e.g., silicon (Si) substrate, germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (e.g., gallium nitride (GaN) substrate, gallium arsenide (GaAs) substrate, indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. It may also include other substrates containing semiconductor materials, such as silicon-on-insulator (SOI) substrates, germanium-on-insulator (GeOI) substrates, polycrystalline semiconductor layers on insulating layers, silicon-germanium substrates, etc.

[0109] Here, the first insulating layer 210 can also be referred to as the gate dielectric layer, and the third insulating layer 250 can also be referred to as the gate sacrificial layer. Both the first insulating layer 210 and the third insulating layer 250 include insulating materials; the first insulating layer 210 includes, for example, silicon oxide, and the third insulating layer 250 includes, for example, silicon nitride. Both the first dielectric layer 220 and the second dielectric layer 224 include dielectric materials; both the first dielectric layer 220 and the second dielectric layer 224 include, for example, silicon oxide.

[0110] Here, the first sub-initial stacked structure 244 is etched along the Z direction. As the number of stacked layers increases, the etching process becomes more difficult. The top cross-sectional dimension of the first sub-channel hole 252 formed by etching is greater than or equal to the bottom cross-sectional dimension. In some embodiments, the cross-sectional shape of the first sub-channel hole 252 perpendicular to the Z direction includes a circle, an ellipse, or a polygon, etc., and multiple first sub-channel holes 252 are arranged in an array or a honeycomb pattern in a plane perpendicular to the Z direction.

[0111] Here, a first sacrificial material is filled into the first sub-channel hole 252 to form a first sacrificial material layer, which fills the first sub-channel hole 252 and covers the surface of the first sub-initial stack structure 244. The first sacrificial material layer is planarized to form a first sacrificial layer 262 that exposes the surface of the first sub-initial stack structure 244, and the surface of the first sacrificial layer 262 is substantially flush with the surface of the first sub-initial stack structure 244. In some embodiments, the planarization process may include, but is not limited to, chemical mechanical polishing (CMP) processing.

[0112] Here, the deposition process for forming the first insulating layer 210, the third insulating layer 250, the first dielectric layer 220, the first storage layer 222, the second dielectric layer 224 and the first sacrificial layer 262 may include, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0113] like Figure 8 As shown, in some embodiments, after forming the first sub-initial channel structure 258, the method further includes: forming a second sub-initial stack structure 246 on the first sub-initial stack structure 244, the second sub-initial stack structure 246 including a plurality of first insulating layers 210 and a plurality of third insulating layers 250 alternately stacked along the Z direction, the first sub-initial stack structure 244 and the second sub-initial stack structure 246 together forming an initial stack structure 248.

[0114] like Figure 9 As shown, in some embodiments, the second sub-initial stack structure 246 is etched along the Z direction to form a second sub-channel hole 254 that exposes the first sacrificial layer 262; the first sub-channel hole 252 and the second sub-channel hole 254 together form the channel hole 256.

[0115] Here, the second sub-initial stacked structure 246 is etched along the Z-direction. As the number of stacked layers increases, the etching process becomes more difficult. The top cross-sectional dimension of the etched second sub-channel hole 254 is greater than or equal to the bottom cross-sectional dimension. In some embodiments, the cross-sectional shape of the second sub-channel hole 254 perpendicular to the Z-direction includes a circle, an ellipse, or a polygon, etc., and multiple second sub-channel holes 254 are arranged in an array or a honeycomb pattern in a plane perpendicular to the Z-direction.

[0116] Here, the first sub-initial stack structure 244 is etched to form the first sub-channel hole 252; the second sub-initial stack structure 246 is etched to form the second sub-channel hole 254. In some embodiments, the axes of the first sub-channel hole 252 and the second sub-channel hole 254 coincide.

[0117] like Figure 10 As shown, in some embodiments, a third dielectric layer 230, a second storage layer 232, a fourth dielectric layer 234, and a second sacrificial layer 264 are sequentially formed in the second sub-channel via 254 to form a second sub-initial channel structure 260. Figure 10 The dashed circle in the middle provides an enlarged view of the second sub-initial channel structure 260.

[0118] Here, a second sacrificial material is filled into the second sub-channel hole 254 to form a second sacrificial material layer, which fills the second sub-channel hole 254 and covers the surface of the second sub-initial stack structure 246. The second sacrificial material layer is then planarized to form a second sacrificial layer 264 that exposes the surface of the second sub-initial stack structure 246, with the surface of the second sacrificial layer 264 substantially flush with the surface of the second sub-initial stack structure 246. In some embodiments, the planarization process may include, but is not limited to, CMP processing.

[0119] Here, the deposition process for forming the third dielectric layer 230, the second storage layer 232, the fourth dielectric layer 234, and the second sacrificial layer 264 may include, but is not limited to, CVD, PVD, ALD, or any combination thereof.

[0120] Combination Figure 10 and Figure 11 As shown, in some embodiments, after forming the second sub-initial channel structure 260, the method further includes removing the first sacrificial layer 262 and the second sacrificial layer 264. Here, after removing the first sacrificial layer 262, the second dielectric layer 224 is exposed in the first sub-channel aperture 252; after removing the second sacrificial layer 264, the surface of the fourth dielectric layer 234 is exposed in the second sub-channel aperture 254.

[0121] In some embodiments, the materials of the first sacrificial layer 262 and the second sacrificial layer 264 may be the same or different. When the materials of the first sacrificial layer 262 and the second sacrificial layer 264 are the same, the same etching liquid can be used to remove the first sacrificial layer 262 and the second sacrificial layer 264 simultaneously, saving manufacturing steps.

[0122] like Figure 12 As shown, in some embodiments, a channel layer 226 is formed in the channel hole 256, a second dielectric layer 224 in the first sub-channel hole 252 is in contact with the channel layer 226, and a fourth dielectric layer 234 in the second sub-channel hole 254 is in contact with the channel layer 226.

[0123] like Figure 13 As shown, a filling layer 228 is formed in the channel hole 256. The channel layer 226 and the filling layer 228 are in contact in the first sub-channel hole 252, and the channel layer 226 and the filling layer 228 are in contact in the second sub-channel hole 254. Here, in the first sub-channel hole 252, the first dielectric layer 220, the first storage layer 222, the second dielectric layer 224, the channel layer 226, and the filling layer 228 arranged sequentially in the radially inward direction together form the first sub-channel structure 216; in the second sub-channel hole 254, the third dielectric layer 230, the second storage layer 232, the fourth dielectric layer 234, the channel layer 226, and the filling layer 228 arranged sequentially in the radially inward direction together form the second sub-channel structure 218; wherein, the first sub-channel structure 216 and the second sub-channel structure 218 stacked along the Z direction together form the channel structure 214.

[0124] Combination Figure 13 and Figure 14 As shown, in some embodiments, after forming the channel structure 214, the method further includes: etching the initial stacked structure 248 along the Z direction to form a gate line slot through the initial stacked structure 248; removing the third insulating layer 250 through the gate line slot to form a gap; and forming a first conductive layer 212 in the gap. The first conductive layer 212 may also be referred to as the gate conductive layer.

[0125] Here, the space occupied by the third insulating layer 250 in the first sub-initial stacked structure 244 is replaced by the first conductive layer 212, and a plurality of first insulating layers 210 and a plurality of first conductive layers 212 alternately stacked along the Z direction together form the first sub-stacked structure 266; the space occupied by the third insulating layer 250 in the second sub-initial stacked structure 246 is replaced by the first conductive layer 212, and a plurality of first insulating layers 210 and a plurality of first conductive layers 212 alternately stacked along the Z direction together form the second sub-stacked structure 268; wherein, the first sub-stacked structure 266 and the second sub-stacked structure 268 stacked along the Z direction together form the stacked structure 208. The stacked structure 208 and a plurality of channel structures 214 extending through the stacked structure 208 along the Z direction together form the sub-semiconductor structure 206.

[0126] In some embodiments, the first storage layer 222 includes a floating gate layer or a charge trapping layer; the second storage layer 232 includes a ferroelectric layer.

[0127] In some embodiments, a first sub-channel structure 216 and a first conductive layer 212 in contact with it together form a first memory cell 202, the first memory cell 202 including a NAND transistor; a second sub-channel structure 218 and a first conductive layer 212 in contact with it together form a second memory cell 204, the second memory cell 204 including a ferroelectric transistor.

[0128] Return to reference Figure 3 In some embodiments, the method further includes forming a peripheral circuit 236 coupled to the sub-semiconductor structure 206.

[0129] In some embodiments, the sub-semiconductor structure 206 further includes a first bonding layer, and the peripheral circuit 236 further includes a second bonding layer, with a bonding interface formed between the first and second bonding layers. Electrical signal transmission between the sub-semiconductor structure 206 and the peripheral circuit 236 can be achieved through interconnections (e.g., bonding contacts) across the bonding interface. The first bonding layer includes a first bonding contact and a first dielectric material layer isolating the first bonding contact; the second bonding layer includes a second bonding contact and a second dielectric material layer isolating the second bonding contact; the first and second bonding contacts are bonded, and the first and second dielectric material layers are bonded.

[0130] In some embodiments, the first and second bonding contacts may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. The first and second dielectric material layers may include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric materials, or any combination thereof. The first and second bonding layers can be used to form hybrid bonds, simultaneously achieving metal-to-metal and dielectric-to-dielectric bonds.

[0131] In some embodiments, the sub-semiconductor structure 206 further includes a first interconnect layer, and the peripheral circuit 236 further includes a second interconnect layer. The first and second interconnect layers may include multiple interconnect structures, such as laterally extending wiring layers and vertically extending via structures, which may be formed in one or more inter-layer dielectric (ILD) layers. The interconnect structures may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. The inter-layer dielectric layer may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric materials, or any combination thereof.

[0132] refer to Figures 15 to 24 , Figures 15 to 24 This is a cross-sectional structural diagram illustrating the semiconductor structure during the manufacturing process, as provided in some embodiments of this disclosure. The following will be combined with... Figure 6 and Figures 15 to 24 The manufacturing process of the semiconductor structure provided in other embodiments of this disclosure is described in detail.

[0133] like Figure 15 As shown, a first substrate 352 is provided; in some embodiments, step S410 includes: forming a first initial stack structure 354 on one side of the first substrate 352 along the Z direction, the first initial stack structure 354 including a plurality of first insulating layers 312 and a plurality of third insulating layers 356 alternately stacked along the Z direction; etching the first initial stack structure 354 along the Z direction to form a first channel hole 358 that penetrates the first initial stack structure 354 and extends into the first substrate 352.

[0134] Here, the first insulating layer 312 can also be referred to as the gate dielectric layer, and the third insulating layer 356 can also be referred to as the gate sacrificial layer. For a description of the first substrate 352, the first insulating layer 312, and the third insulating layer 356, please refer to [reference needed]. Figures 7 to 14 The relevant descriptions will not be repeated here.

[0135] Combination Figure 15 and Figure 16As shown, in some embodiments, step S410 includes: sequentially forming a first dielectric layer 326, a first storage layer 328, a second dielectric layer 330, a first channel layer 332, and a first fill layer 334 in the first channel via 358 to form a first channel structure 316; etching a first initial stacked structure 354 along the Z direction to form a gate line slot penetrating the first initial stacked structure 354; removing a third insulating layer 356 through the gate line slot to form a gap; and forming a first conductive layer 314 in the gap. The first conductive layer 314 may also be referred to as a gate conductive layer. Figure 16 The dashed circle in the middle provides an enlarged view of the first channel structure 316.

[0136] Here, the space occupied by the third insulating layer 356 in the first initial stacked structure 354 is replaced by the first conductive layer 314. Multiple first insulating layers 312 and multiple first conductive layers 314, alternately stacked along the Z direction, together form the first stacked structure 310. The multiple first insulating layers 312 and multiple first conductive layers 314, alternately stacked along the Z direction, together form the first stacked structure 310. The first stacked structure 310 and multiple first channel structures 316 extending along the Z direction and passing through the first stacked structure 310 together form the first sub-semiconductor structure 306.

[0137] In some embodiments, the first storage layer 328 includes a floating gate layer or a charge trapping layer.

[0138] In some embodiments, the first channel structure 316 and the first conductive layer 314 in contact with it together form the first memory cell 302 (e.g., ...). Figure 16 (As shown in the solid circle in the middle), the first storage cell 302 includes NAND transistors.

[0139] like Figure 16 As shown, a first channel plug 360 is formed and coupled to the first channel layer 332. The first channel plug 360 can be used to bring out electrical signals from the top of the first channel layer 332 so as to be coupled to the bit line.

[0140] like Figure 17 As shown, in some embodiments, after step S410, the method further includes: bonding the first sub-semiconductor structure 306 and the peripheral circuit 346 together.

[0141] In some embodiments, the first sub-semiconductor structure 306 further includes a first bonding layer, and the peripheral circuit further includes a second bonding layer, with a bonding interface formed between the first bonding layer and the second bonding layer. Electrical signal transmission between the first sub-semiconductor structure 306 and the peripheral circuit 346 can be achieved through interconnections (e.g., bonding contacts) across the bonding interface. The first bonding layer includes a first bonding contact and a first dielectric material layer isolating the first bonding contact, and the second bonding layer includes a second bonding contact and a second dielectric material layer isolating the second bonding contact. A description of the first bonding contact, the second bonding contact, the first dielectric material layer, and the second dielectric material layer can be found here. Figures 7 to 14 The relevant descriptions will not be repeated here.

[0142] Combination Figure 17 and Figure 18 As shown, the first sub-semiconductor structure 306 and peripheral circuit 346, which are bonded together, are flipped over, and the first substrate 352 is removed to expose the bottom end of the first channel structure 316; the first channel structure 316 (as shown) is removed. Figure 18 The first dielectric layer 326, the first storage layer 328, and the second dielectric layer 330 in the bottom of the first channel structure 316 (shown in the dashed box) are exposed to expose the first channel layer 332 in the bottom of the first channel structure 316; a first source layer 378 is formed covering the bottom of the first channel structure 316; and a first source contact 362 is formed in contact with the first source layer 378. The process of forming the first source contact 362 described above can also be called the Back Side Source Connect (BSSC) process.

[0143] like Figure 19 As shown, the first sub-semiconductor structure 306 and the peripheral circuit 346 that are bonded together are flipped over, and the peripheral circuit 346 is disposed on the first sub-semiconductor structure 306.

[0144] like Figure 20 As shown, a second substrate 364 is provided; in some embodiments, step S420 includes: forming a second initial stack structure 366 on one side of the second substrate 364 along the Z direction, the second initial stack structure 366 including a plurality of second insulating layers 320 and a plurality of fourth insulating layers 368 alternately stacked along the Z direction; etching the second initial stack structure 366 along the Z direction to form a second channel hole 370 that penetrates the second initial stack structure 366 and extends into the second substrate 364.

[0145] Here, the second insulating layer 320 can also be referred to as the gate dielectric layer, and the fourth insulating layer 368 can also be referred to as the gate sacrificial layer. The relevant descriptions of the second substrate 364, the second insulating layer 320, and the fourth insulating layer 368 can be found above and will not be repeated here.

[0146] Combination Figure 20 and Figure 21 As shown, in some embodiments, step S420 includes: sequentially forming a third dielectric layer 336, a second storage layer 338, a fourth dielectric layer 340, a second channel layer 342, and a second fill layer 344 in the second channel via 370 to form a second channel structure 324; etching a second initial stacked structure 366 along the Z direction to form a gate line slot penetrating the second initial stacked structure 366; removing the fourth insulating layer 368 through the gate line slot to form a gap; and forming a second conductive layer 322 in the gap. The second conductive layer 322 may also be referred to as a gate conductive layer. Figure 21 The dashed circle in the middle provides an enlarged view of the second channel structure 324.

[0147] Here, the space occupied by the fourth insulating layer 368 in the second initial stacked structure 366 is replaced by the second conductive layer 322. Multiple second insulating layers 320 and multiple second conductive layers 322, alternately stacked along the Z direction, together form the second stacked structure 318. The multiple second insulating layers 320 and multiple second conductive layers 322, alternately stacked along the Z direction, together form the second stacked structure 318. The second stacked structure 318 and multiple second channel structures 324 extending along the Z direction and passing through the second stacked structure 318 together form the second sub-semiconductor structure 308.

[0148] In some embodiments, the second storage layer 338 includes a ferroelectric layer.

[0149] In some embodiments, the second channel structure 324 and the second conductive layer 322 in contact with it together form the second memory cell 304 (e.g., ...). Figure 21 (As shown in the solid circle in the middle), the second storage unit 304 includes a ferroelectric transistor.

[0150] like Figure 21 As shown, a second channel plug 372 is formed and coupled to the second channel layer 342. The second channel plug 372 can be used to bring out electrical signals from the top of the second channel layer 342 so as to be coupled to the bit line.

[0151] like Figure 22 As shown, an interconnection structure 374 can also be formed, which is used to extract electrical signals from the second channel plug 372.

[0152] like Figure 23 As shown, in some embodiments, the method further includes bonding the first sub-semiconductor structure 306 and the second sub-semiconductor structure 308 together, wherein the first sub-semiconductor structure 306 is disposed between the peripheral circuit 346 and the second sub-semiconductor structure 308.

[0153] like Figure 24 As shown, the second substrate 364 is removed to expose the bottom end of the second channel structure 324; the second channel structure 324 is removed (as shown in the image). Figure 24 The third dielectric layer 336, the second storage layer 338, and the fourth dielectric layer 340 at the bottom of the second channel structure 324 (shown in the dashed box) expose the second channel layer 342 at the bottom of the second channel structure 324; a second source layer 380 is formed covering the bottom of the second channel structure 324; and a second source contact 376 is formed that contacts the second source layer 380. The above-described formation of the second source contact 376 can also be referred to as the BSSC process.

[0154] It should be noted that, Figure 24 The diagram illustrates the formation of a first source layer 378 in contact with the exposed first channel layer 332 at the bottom end of the first channel structure 316 (see reference). Figure 18 As shown, a second source layer 380 is formed and contacts the exposed second channel layer 342 by exposing the second channel layer 342 in the bottom end of the second channel structure 324. This disclosure does not impose any particular limitations on the contact method between the first channel layer 332 and the first source layer 378, the contact method between the second channel layer 342 and the second source layer 380, or the method of forming the first source layer 378 and the second source layer 380; these can be flexibly selected according to actual circumstances.

[0155] In some embodiments, different memory layer materials can be used in different sub-stack structures, and the memory layer formation process in different sub-stack structures can be differentiated by segmentation. In other embodiments, different memory layer materials can be used in different memory arrays, and the different memory arrays are stacked to form a semiconductor structure. Ferroelectric transistors have lower voltage requirements in the drive circuit, which helps to reduce the number of high-voltage transistors, promotes the improvement of memory density, and increases design freedom. Hybrid designs of NAND transistors and ferroelectric transistors can realize multi-scenario applications.

[0156] refer to Figure 25 , Figure 25 A block diagram of a memory system provided for an embodiment of this disclosure. (See diagram below.) Figure 25 As shown, this disclosure provides a memory system 500, which includes: a semiconductor structure 502; and a controller 504 coupled to the semiconductor structure 502 and configured to control the semiconductor structure 502. Here, the semiconductor structure 502 can be the one described above. Figure 2 and Figure 3 The semiconductor structure 200 shown in the diagram, or, could be the one described above. Figure 4 and Figure 5 The semiconductor structure 300 is shown in the diagram.

[0157] In some embodiments, the controller 504 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0158] In some embodiments, the controller 504 is designed to operate in a high duty cycle environment solid-state drive (SSD) or embedded multi-media card (eMMC), which serves as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0159] Controller 504 can be configured to control the operation of semiconductor structure 502, such as read, erase, and program operations. Controller 504 can also be configured to manage various functions related to data stored or to be stored in semiconductor structure 502, including but not limited to bad block management, garbage collection, logical address to physical address translation, and wear leveling. In some embodiments, controller 504 is also configured to process error correcting codes (ECCs) related to data read from or written to semiconductor structure 502.

[0160] Controller 504 can also perform any other suitable functions, such as formatting semiconductor structure 502. Controller 504 can communicate with external devices (e.g., a host) according to a specific communication protocol. For example, controller 504 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Drive Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0161] The controller 504 and one or more semiconductor structures 502 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 500 can be implemented and packaged into different types of end electronic products.

[0162] In some embodiments, the controller 504 and the single semiconductor structure 502 may be integrated into the memory card. The memory card may include Personal Computer Memory Card International Association (PCMCIA) cards, CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (e.g., MMC, Reduced-Size MMC (RS-MMC), microMMC), SD cards (e.g., SD, miniSD, microSD, Secure Digital High Capacity (SDHC)), UFS, etc. The memory card may also include a memory card connector that couples the memory card to a host computer.

[0163] In some embodiments, the controller 504 and multiple semiconductor structures 502 may be integrated into the solid-state drive. The solid-state drive may also include a solid-state drive connector that couples the solid-state drive to a host. In some embodiments, the storage capacity and / or operating speed of the solid-state drive is greater than the storage capacity and / or operating speed of the memory card.

[0164] refer to Figure 26 , Figure 26 A block diagram of an electronic device provided in an embodiment of this disclosure. (As shown) Figure 26 As shown, this disclosure provides an electronic device 600, which may include: the memory system 500 in the above technical solution; and a host 602 coupled to the memory system 500.

[0165] Here, electronic device 600 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory therein.

[0166] Electronic device 600 may include a host 602 and a memory system 500, the memory system 500 having one or more semiconductor structures 502 and a controller 504. The host 602 may be a processor of the electronic device (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)). The host 602 may be configured to send data to or receive data from the semiconductor structure 502.

[0167] In some embodiments, controller 504 is coupled to semiconductor structure 502 and host 602 and is configured to control semiconductor structure 502. Controller 504 can manage data stored in semiconductor structure 502 and communicate with host 602.

[0168] This disclosure provides a semiconductor structure, a method for manufacturing the same, and a memory system. In this embodiment, the semiconductor structure includes multiple first memory cells and multiple second memory cells. Each second memory cell includes a ferroelectric transistor. The materials of the first storage layer in the first memory cell and the second storage layer in the second memory cell are different. Low-voltage transistors can be used in the driving circuit that operates the ferroelectric transistors to reduce the size of the driving circuit, thereby reducing the area occupied by the peripheral circuitry and increasing the storage density of the semiconductor structure.

[0169] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0170] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A semiconductor structure, characterized in that, The semiconductor structure includes: Multiple first storage units, each first storage unit including a first storage layer; A plurality of second memory cells, each second memory cell including a second memory layer; wherein the second memory cell includes a ferroelectric transistor, and the first memory layer and the second memory layer are made of different materials.

2. The semiconductor structure according to claim 1, characterized in that, The first memory cell includes NAND transistors.

3. The semiconductor structure according to claim 2, characterized in that, The first storage layer includes a floating gate layer or a charge trapping layer; the second storage layer includes a ferroelectric layer.

4. The semiconductor structure according to claim 3, characterized in that, The semiconductor structure further includes: a sub-semiconductor structure, the sub-semiconductor structure comprising: A stacked structure, the stacked structure comprising a first insulating layer and a first conductive layer alternately stacked along a first direction; A channel structure extending through the stacked structure along the first direction, the channel structure comprising at least a first sub-channel structure and a second sub-channel structure stacked together.

5. The semiconductor structure according to claim 4, characterized in that, The first sub-channel structure includes a first dielectric layer, a first storage layer, a second dielectric layer, and a channel layer in the radially inward direction, and the second sub-channel structure includes a second storage layer and the channel layer in the radially inward direction.

6. The semiconductor structure according to claim 4, characterized in that, The semiconductor structure also includes: Peripheral circuitry, which is coupled to the sub-semiconductor structure.

7. The semiconductor structure according to claim 6, characterized in that, The peripheral circuit also includes: A first driving circuit is configured to apply a voltage to the first conductive layer coupled to the first memory cell. A second driving circuit is configured to apply a voltage to the first conductive layer coupled to the second memory cell; wherein the size of the first driving circuit is larger than the size of the second driving circuit.

8. The semiconductor structure according to claim 3, characterized in that, The semiconductor structure further includes: a first sub-semiconductor structure and a second sub-semiconductor structure stacked along a first direction, wherein the first sub-semiconductor structure and the second sub-semiconductor structure are bonded together; The first sub-semiconductor structure includes: a first stacked structure, the first stacked structure including a first insulating layer and a first conductive layer alternately stacked along the first direction; and a first channel structure, the first channel structure extending through the first stacked structure along the first direction. The second sub-semiconductor structure includes: a second stacked structure, the second stacked structure including a second insulating layer and a second conductive layer alternately stacked along the first direction; and a second channel structure, the second channel structure extending through the second stacked structure along the first direction.

9. The semiconductor structure according to claim 8, characterized in that, The first channel structure includes a first dielectric layer, a first storage layer, a second dielectric layer, and a first channel layer in the radially inward direction, and the second channel structure includes a second storage layer and a second channel layer in the radially inward direction.

10. The semiconductor structure according to claim 8, characterized in that, The semiconductor structure also includes: The peripheral circuit is coupled to the first sub-semiconductor structure and the second sub-semiconductor structure.

11. The semiconductor structure according to claim 10, characterized in that, The peripheral circuit also includes: A first driving circuit is configured to apply a voltage to the first conductive layer coupled to the first memory cell. A second driving circuit is configured to apply a voltage to a second conductive layer coupled to a second memory cell; wherein the size of the first driving circuit is larger than the size of the second driving circuit.

12. A memory system, characterized in that, The memory system includes: The semiconductor structure as described in any one of claims 1 to 11; and A controller coupled to the semiconductor structure and configured to control the semiconductor structure.

13. A method for manufacturing a semiconductor structure, characterized in that, The method includes: Multiple first storage units are formed, and each first storage unit includes a first storage layer; Multiple second memory cells are formed, each second memory cell including a second memory layer; wherein the second memory cell includes a ferroelectric transistor, and the first memory layer and the second memory layer are made of different materials.

14. The manufacturing method according to claim 13, characterized in that, The first memory cell includes NAND transistors.

15. The manufacturing method according to claim 14, characterized in that, The first storage layer includes a floating gate layer or a charge trapping layer; the second storage layer includes a ferroelectric layer.

16. The manufacturing method according to claim 15, characterized in that, The formation of multiple first storage units includes: A first sub-initial stack structure is provided, the first sub-initial stack structure comprising a first insulating layer and a third insulating layer alternately stacked along a first direction; The first sub-initial stack structure is etched to form the first sub-channel hole; A first dielectric layer, a first storage layer, a second dielectric layer, and a first sacrificial layer are formed in the first sub-channel via to form a first sub-initial channel structure.

17. The manufacturing method according to claim 16, characterized in that, After forming the first sub-initial channel structure, the method further includes: A second sub-initial stack structure is formed on top of the first sub-initial stack structure. The second sub-initial stack structure includes a first insulating layer and a third insulating layer that are alternately stacked along the first direction. The first sub-initial stack structure and the second sub-initial stack structure together form an initial stack structure. The second sub-initial stack structure is etched to form a second sub-channel via that exposes the first sacrificial layer; the first sub-channel via and the second sub-channel via together form a channel via; The second storage layer and the second sacrificial layer are formed in the second sub-channel via to form the second sub-initial channel structure.

18. The manufacturing method according to claim 17, characterized in that, After forming the second sub-initial channel structure, the method further includes: Remove the first sacrificial layer and the second sacrificial layer; A channel layer is formed in the channel hole to form a channel structure; the channel structure includes a first sub-channel structure disposed in the first sub-channel hole and a second sub-channel structure disposed in the second sub-channel hole.

19. The manufacturing method according to claim 18, characterized in that, After forming the channel structure, the method further includes: The third insulating layer in the initial stacked structure is replaced with the first conductive layer, and the first insulating layer and the first conductive layer are alternately stacked to form a stacked structure; the stacked structure and the channel structure together form a sub-semiconductor structure.

20. The manufacturing method according to claim 19, characterized in that, The method further includes: A peripheral circuit is formed that is coupled to the sub-semiconductor structure.

21. The manufacturing method according to claim 15, characterized in that, The formation of multiple first storage units includes: A first initial stacking structure is provided, the first initial stacking structure comprising a first insulating layer and a third insulating layer alternately stacked along a first direction; The first initial stacked structure is etched to form the first channel via; A first dielectric layer, a first storage layer, a second dielectric layer, and a first channel layer are formed in the first channel hole to form a first channel structure; The third insulating layer in the first initial stacked structure is replaced with the first conductive layer, and the first insulating layer and the first conductive layer are alternately stacked to form a first stacked structure; the first stacked structure and the first channel structure together form a first sub-semiconductor structure.

22. The manufacturing method according to claim 21, characterized in that, After forming a plurality of first storage units, the method further includes: The first sub-semiconductor structure and the peripheral circuit are bonded together.

23. The manufacturing method according to claim 22, characterized in that, The formation of multiple second storage units includes: A second initial stacking structure is provided, the second initial stacking structure comprising a second insulating layer and a fourth insulating layer alternately stacked along the first direction; The second initial stack structure is etched to form the second channel via; The second storage layer and the second channel layer are formed in the second channel hole to form a second channel structure; The fourth insulating layer in the second initial stacked structure is replaced with the second conductive layer, and the second insulating layer and the second conductive layer are alternately stacked to form a second stacked structure; the second stacked structure and the second channel structure together form a second sub-semiconductor structure.

24. The manufacturing method according to claim 23, characterized in that, The method further includes: The first sub-semiconductor structure and the second sub-semiconductor structure are bonded together, with the first sub-semiconductor structure disposed between the peripheral circuit and the second sub-semiconductor structure.

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