A memory device and a method of fabricating the same

Abstract

The application relates to the technical field of semiconductors, in particular to a memory device and a preparation method thereof. The memory device comprises a substrate, the substrate being provided with an active region, the active region comprising two adjacent convex parts, and a groove being formed between the two convex parts; a wide-bandgap semiconductor material layer being formed on the surface of the convex part and covering at least the top region and the bottom corner region of the convex part; two half-floating gate transistors being formed on the two convex parts respectively, the two half-floating gate transistors sharing a same floating gate, the floating gate being a continuous structure, and the floating gate part located at the bottom of the groove connecting the two half-floating gate transistors; wherein one of the two half-floating gate transistors is configured as a write transistor, and the other is configured as an erase transistor. The application can effectively alleviate the electric field concentration effect at the corner of the three-dimensional structure, reduce the leakage current of the gate dielectric layer, and thus significantly improve the data retention and reliability of the memory device, and meanwhile optimize the array layout of the memory cell and the erase and write efficiency.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a memory device and its fabrication method. Background Technology

[0002] Multi-Time Programmable Memory (MTP), as an important type of non-volatile memory, is widely used in embedded systems such as microcontrollers, power management chips, and sensor calibration chips. Traditional MTP devices typically use floating-gate transistors or semi-floating-gate transistors (SFGTs) as basic memory cells, and data writing and erasing are achieved by injecting or extracting charge into the floating gate.

[0003] As semiconductor process nodes continue to shrink, memory devices with three-dimensional structures (such as FinFET structures or trench structures) are gradually becoming mainstream in order to increase storage density and enhance gate control over the channel within a limited chip area. However, in existing three-dimensional memory devices, severe electric field concentration effects are easily generated at the top corners of the active region protrusions (such as fins) and the bottom corners of the trenches between adjacent protrusions.

[0004] This concentration of electric field at corners can lead to the following serious problems:

[0005] 1) Degradation of tunneling oxide layer: The high electric field stress at the corner will accelerate the loss of the gate dielectric layer (tunneling oxide layer), resulting in a significant increase in leakage current, which seriously affects the data retention and durability of the device.

[0006] 2) Increased risk of breakdown: During repeated erase and write operations (especially high-voltage erase operations), the oxide layer at the corners is prone to soft or hard breakdown, reducing the overall reliability of the device.

[0007] 3) Erasing and writing interference: In dense arrays, electric field coupling between adjacent memory cells and corner leakage can easily lead to erasing and writing interference, limiting further miniaturization of memory arrays.

[0008] Furthermore, traditional memory cells often require complex transistor combinations and large layout areas when performing write and erase operations, and the electric field distribution in the erase window area is difficult to control precisely, which further restricts the improvement of device performance. Summary of the Invention

[0009] The purpose of this invention is to provide a memory device and its fabrication method, which can effectively alleviate the electric field concentration effect at the corner of a three-dimensional structure, reduce the leakage current of the gate dielectric layer, thereby significantly improving the data retention and reliability of the memory device, while optimizing the array layout and erase / write efficiency of the memory cells.

[0010] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0011] In a first aspect, the present invention provides a memory device comprising: a substrate having an active region thereon, the active region including two adjacent protrusions, a groove formed between the two protrusions; a wide bandgap semiconductor material layer formed on the surface of the protrusions, and at least covering the top region and bottom corner region of the protrusions; two semi-floating gate transistors formed on the two protrusions respectively, the two semi-floating gate transistors sharing a common floating gate, the floating gate being a continuous structure, wherein the floating gate portion located at the bottom of the groove connects the two semi-floating gate transistors; wherein one of the two semi-floating gate transistors is configured as a write transistor and the other is configured as an erase transistor.

[0012] In one embodiment of the present invention, each of the semi-floating gate transistors further includes a control gate formed above the floating gate; the floating gate is a single, continuously extending structure that extends continuously along the bottom of the groove and the surface of the protrusion.

[0013] In one embodiment of the present invention, the invention further includes: a first gate dielectric layer located between the floating gate and the active region; a second gate dielectric layer located between the floating gate and the control gate; and the source and drain of each of the semi-floating gate transistors being formed on both sides of the active region, respectively.

[0014] In one embodiment of the present invention, a contact window is formed on the wide bandgap semiconductor material layer and the first gate dielectric layer, and the substrate is exposed through the contact window.

[0015] In one embodiment of the present invention, in a cross section perpendicular to the extension direction of the groove, the width of the control gate is greater than the width of the floating gate, and the sidewall of the control gate extends laterally beyond the sidewall of the floating gate.

[0016] In one embodiment of the present invention, the material of the wide bandgap semiconductor material layer includes at least one of gallium nitride, silicon carbide, and aluminum nitride.

[0017] In one embodiment of the present invention, the wide bandgap semiconductor material layer has a discontinuous structure, the sidewall surface of the protrusion is exposed, and the wide bandgap semiconductor material layer is only distributed on the top surface of the protrusion and the corner area at the bottom of the protrusion.

[0018] In a second aspect, the present invention provides a method for fabricating a memory device, comprising: providing a substrate; etching an active region on the substrate, the active region including two adjacent protrusions, and etching a trench between the two protrusions; depositing a wide bandgap semiconductor material on the surface of the protrusions and etching thereon such that the remaining wide bandgap semiconductor material layer at least covers the top region and bottom corner region of the protrusions; depositing a floating gate material on the bottom of the trench and the surface of the protrusions to form semi-floating gate transistors on the two protrusions respectively, and connecting the two semi-floating gate transistors through a floating gate located at the bottom of the trench; wherein one of the two semi-floating gate transistors is configured as a write transistor and the other is configured as an erase transistor.

[0019] In one embodiment of the present invention, the deposition of a wide bandgap semiconductor material on the surface of the protrusion and etching thereon, such that the retained wide bandgap semiconductor material layer at least covers the top region and the bottom corner region of the protrusion, includes:

[0020] A wide bandgap semiconductor material layer and a protective layer are conformally deposited on the surfaces of the protrusion and the groove;

[0021] The protective layer and the wide bandgap semiconductor material layer are removed by anisotropic plasma etching, leaving only a portion of the wide bandgap semiconductor material layer in the corner region at the bottom of the protrusion;

[0022] After forming a wide bandgap semiconductor material layer in the bottom corner region of the protrusion, a wide bandgap semiconductor material layer and a protective layer are conformally deposited again on the surfaces of the protrusion and the trench. The protective layer is patterned using photolithography and etching processes so that it at least covers the top region of the protrusion. Using the patterned protective layer as a mask, the underlying wide bandgap semiconductor material layer is etched to form the wide bandgap semiconductor material layer in the top region of the protrusion, thereby forming a discontinuous structure of the wide bandgap semiconductor material layer.

[0023] In one embodiment of the present invention, the semi-floating gate transistor further includes a control gate formed above the floating gate; the fabrication method further includes: after depositing the floating gate material, etching with a first photomask to define a continuous floating gate pattern on the protrusion and the surface of the groove; after depositing the inter-gate dielectric layer and the control gate material, etching with a second photomask to pattern the control gate material, and simultaneously removing the floating gate material below it that is not covered by the control gate; wherein the linewidth of the second photomask is greater than the linewidth of the first photomask, so that the width of the formed control gate is greater than the width of the floating gate, and the sidewall of the control gate extends beyond the sidewall of the floating gate in the lateral direction.

[0024] The present invention has the following beneficial effects:

[0025] 1. The present invention introduces a wide bandgap semiconductor material layer in the top region of the protrusion and the corner region at the bottom of the groove. The wide bandgap semiconductor material has an extremely high critical breakdown electric field and wide bandgap characteristics, which can effectively suppress the electric field concentration effect at the corner, significantly reduce the leakage current of the tunnel oxide layer at the corner, thereby significantly improving the data retention and breakdown resistance of the device and extending the service life of the device.

[0026] 2. By setting the wide bandgap semiconductor material layer as a discontinuous structure, retaining it only at the top and bottom corners and exposing the sidewalls, this invention solves the technical problem of corner electric field concentration and avoids the adverse effects of the wide bandgap material on the sidewall channel turn-on voltage, thus ensuring the normal read / write speed and drive current of the semi-floating gate transistor.

[0027] 3. The present invention adopts a U-shaped groove and a double protrusion structure, so that two semi-floating gate transistors share the bottom floating gate as a common charge storage node. One of the two semi-floating gate transistors is configured as a write transistor and the other is configured as an erase transistor. This "one write and one erase" topology not only simplifies the array layout of the memory cells and improves the chip integration, but also enables the write and erase operations to be performed independently and efficiently, thus optimizing the overall write and erase efficiency.

[0028] 4. This invention uses two photomask etching processes with different linewidths to form a specific cladding morphology where the control gate width is greater than the floating gate width. This enhances the electrostatic control capability of the control gate over the channel, effectively reduces parasitic capacitance and erase / write interference between adjacent cells, and further improves the stability of the memory array. Attached Figure Description

[0029] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is one of the structural schematic diagrams of the storage device according to an embodiment of this application;

[0031] Figure 2 This is a second schematic diagram of the structure of the storage device according to an embodiment of this application;

[0032] Figure 3 This is a schematic flowchart of a method for fabricating a storage device according to an embodiment of this application;

[0033] Figures 4a to 4h This is a schematic cross-sectional view of some stages in the formation process of the protrusion;

[0034] Figures 5a to 5b This is a schematic cross-sectional view of some stages in the formation process of the U-shaped trench;

[0035] Figures 6a to 6d This is a schematic cross-sectional view of some stages in the formation of the wide bandgap semiconductor material layer at the bottom region of the protrusion;

[0036] Figures 7a to 7f This is a schematic cross-sectional view of some stages in the formation of the wide bandgap semiconductor material layer in the top region of the protrusion;

[0037] Figure 8 This is a schematic cross-sectional view after the formation of the first gate dielectric layer;

[0038] Figures 9a to 9b This is a schematic cross-sectional view of some stages in the formation of the contact window;

[0039] Figures 10a to 10f This is a schematic cross-sectional view of some stages in the formation process of the floating gate and control gate.

[0040] Label Explanation:

[0041] 10-Substrate, 101-Active region, 102-Protrusion, 103-Groove, 104-U-shaped trench, 105-Contact window

[0042] 20-Wide bandgap semiconductor material layer,

[0043] 30 - Semi-floating gate transistor, 301 - Floating gate, 302 - Control gate, 303 - First gate dielectric layer, 304 - Second gate dielectric layer.

[0044] 50-field oxygen, 60-isolation layer,

[0045] 70 - Hard mask layer,

[0046] 81-First photomask, 82-Second photomask, 83-Third photoresist, 84-Fourth photoresist, 85-Fifth photomask, 86-Sixth photoresist

[0047] 90 - Protective layer. Detailed Implementation

[0048] The embodiments of the present invention will be described below with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are only for illustrating the present invention and not for limiting the scope of protection of the present invention.

[0049] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the shape, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0050] In one embodiment, this application provides a storage device, such as Figure 1 and Figure 2 As shown, the memory device includes: a substrate 10, a wide bandgap semiconductor material layer 20, and two semi-floating gate transistors 30.

[0051] The substrate 10 has an active region 101, which includes two adjacent protrusions 102, and a groove 103 is formed between the two protrusions 102.

[0052] A wide bandgap semiconductor material layer 20 is formed on the surface of the protrusion 102 and at least covers the top region and bottom corner region of the protrusion 102.

[0053] Two semi-floating gate transistors 30 are formed on two protrusions 102 respectively. The two semi-floating gate transistors 30 share a common floating gate 301, which is a continuous structure. The portion of the floating gate 301 located at the bottom of the groove 103 connects the two semi-floating gate transistors 30. One of the two semi-floating gate transistors 30 is configured as a write transistor, and the other is configured as an erase transistor.

[0054] In this embodiment, a three-dimensional device structure is constructed by forming two adjacent protrusions 102 on the active region 101 of the substrate 10 and a groove 103 between the protrusions 102. A wide bandgap semiconductor material layer 20 is covered on the top and bottom corner regions of the protrusions 102. Utilizing the high critical breakdown electric field characteristics of the wide bandgap material, the electric field concentration effect at the corners of the three-dimensional structure is effectively mitigated. Simultaneously, two semi-floating gate transistors 30 are connected through a floating gate 301 at the bottom of the groove 103, sharing the same charge storage node, and are respectively configured as a write transistor and an erase transistor, realizing a "one-write-one-erase" memory architecture. The wide bandgap semiconductor material layer 20 significantly reduces the gate dielectric leakage current at the corners of the protrusions 102, improving the device's data retention and soft breakdown resistance. The dual-transistor shared architecture of the floating gate 301 simplifies the layout of the memory cells, improves chip integration, and enables independent and efficient write and erase operations.

[0055] As an optional implementation of the embodiments of this application, such as Figure 1 and Figure 2As shown, each of the semi-floating gate transistors 30 further includes a control gate 302 formed above the floating gate 301; the floating gate 301 is a single, continuously extending structure that extends continuously along the bottom of the groove 103 and the surface of the protrusion 102.

[0056] In this embodiment, the control gate 302 is disposed above the floating gate 301 and is used to apply a control voltage during read / write operations to regulate the conduction and cutoff of the channel. The floating gate 301 extends continuously along the bottom of the tank 103 and the surface of the protrusion 102, forming a continuous U-shaped or wave-shaped charge storage structure. Its advantages are: the continuously extending floating gate 301 increases the effective surface area of ​​charge storage and improves the margin of the storage window; the control gate 302, located above the floating gate 301, enhances the electrostatic control capability of the channel below through capacitive coupling, thereby improving the device's read speed and drive current.

[0057] As an optional implementation of the embodiments of this application, such as Figure 1 As shown, the memory device also includes a first gate dielectric layer 303, a second gate dielectric layer 304, and a source and drain for each of the semi-floating gate transistors 30.

[0058] The first gate dielectric layer 303 is located between the floating gate 301 and the active region 101. As a tunneling oxide layer, it isolates the floating gate 301 from the active region 101, allowing carriers to enter and exit the floating gate 301 through the tunneling effect during erase and write operations.

[0059] The second gate dielectric layer 304 is located between the floating gate 301 and the control gate 302. As an inter-gate dielectric layer, it isolates the floating gate 301 from the control gate 302 to prevent charge from leaking upward.

[0060] The source and drain of each of the semi-floating gate transistors 30 are formed on both sides of the active region 101, forming a complete current path.

[0061] The arrangement of the first gate dielectric layer 303 and the second gate dielectric layer 304 ensures stable storage of charge in the floating gate 301. Combined with the suppression of corner electric field by the wide bandgap semiconductor material layer 20, the loss rate of the first gate dielectric layer 303 at the corner is greatly reduced, and the erase and write lifetime of the memory device is significantly extended.

[0062] Furthermore, a contact window 105 is formed on the wide bandgap semiconductor material layer and the first gate dielectric layer 303, such as... Figure 2 and Figure 9bAs shown, the substrate 10 below (specifically, the doped region within the active region 101) is exposed through the contact window 105, thus providing a physical channel for the subsequently deposited floating gate 301 to directly contact the substrate 10. This structure allows the floating gate 301 to directly contact the substrate 10 through the contact window 105, thereby forming a diode junction (PN junction) at the contact window 105. This diode junction provides an efficient charge erasure path for the semi-floating gate transistor 30 configured as an erase transistor; during the erase operation, by applying a forward bias voltage to the diode junction, charge carriers (such as holes) can be rapidly injected into the floating gate 301 through the junction region at the contact window 105, thereby significantly improving the erase speed, reducing the voltage required for the erase operation, and effectively improving the overall erase and write efficiency of the memory device.

[0063] As an optional implementation of the embodiments of this application, such as Figure 1 and Figure 2 As shown, in a cross section perpendicular to the extending direction of the groove 103, the width of the control grid 302 is greater than the width of the floating grid 301, and the sidewall of the control grid 302 extends beyond the sidewall of the floating grid 301 in the lateral direction.

[0064] In this embodiment, the control gate 302 completely covers and extends beyond the sidewall of the floating gate 301 in the lateral direction, forming a specific morphology of "wide control gate and narrow floating gate". The structure of the control gate 302 sidewall extending beyond the sidewall of the floating gate 301 enhances the control force of the control gate 302 on the edge electric field of the floating gate 301 edge and the channel below, effectively reduces the parasitic capacitance coupling between adjacent memory cells, reduces the erase and write interference phenomenon in the dense array, and improves the overall stability of the memory array.

[0065] As an optional embodiment of this application, the wide bandgap semiconductor material layer 20 is made of at least one of gallium nitride, silicon carbide, and aluminum nitride.

[0066] Gallium nitride (GaN), silicon carbide (SiC), or aluminum nitride (AlN) have band gaps much larger than silicon. For example, GaN has a band gap of approximately 3.4 eV, while Si's is only 1.12 eV. They also possess extremely high critical breakdown electric fields (more than 10 times that of silicon) and excellent thermal stability. Applying them to the corner region of the protrusion 102 can fundamentally suppress carrier injection and oxide layer degradation under high electric field stress, thereby improving device reliability.

[0067] As an optional embodiment of this application, the wide bandgap semiconductor material layer 20 has a discontinuous structure, the sidewall surface of the protrusion 102 is exposed, and the wide bandgap semiconductor material layer 20 is only distributed on the top surface of the protrusion 102 and the corner area at the bottom of the protrusion 102.

[0068] In this embodiment, the wide bandgap semiconductor material layer 20 does not completely cover the protrusion 102, but is only retained on the top surface where the electric field is most easily concentrated and at the corner area at the bottom of the protrusion 102. The sidewall surface of the protrusion 102 remains exposed, that is, in direct contact with the first gate dielectric layer 303. Its beneficial effect is that this discontinuous structure accurately solves the problem of electric field concentration at the corner, while avoiding the adverse effects of the wide bandgap material on the turn-on voltage (Vth) of the main channel region on the sidewall of the protrusion 102, ensuring the normal turn-on of the sidewall channel of the semi-floating gate transistor 30, and taking into account both the reliability and read / write performance of the device.

[0069] In one embodiment, this application provides a method for fabricating a storage device, such as... Figure 3 As shown, the method includes the following steps:

[0070] S1, a substrate 10 is provided, an active region 101 is etched on the substrate 10, the active region 101 includes two adjacent protrusions 102, and a groove 103 is etched between the two protrusions 102.

[0071] By etching the substrate 10 to form a three-dimensional active region 101 structure with the protrusions 102 and the trench 103, the effective surface area of ​​the channel is significantly increased, thereby improving the drive current and read / write performance of the device.

[0072] S2, a wide bandgap semiconductor material is deposited on the surface of the protrusion 102 and etched so that the remaining wide bandgap semiconductor material layer 20 at least covers the top region and the bottom corner region of the protrusion 102.

[0073] The wide bandgap semiconductor material layer 20 is precisely formed in the top and bottom corner regions where the electric field is most concentrated on the surface of the protrusion 102. By utilizing the high critical breakdown electric field characteristics of the wide bandgap material, the electric field concentration effect at the corner of the three-dimensional structure is effectively alleviated, the degradation of the gate dielectric layer and the generation of leakage current are suppressed, and the reliability and data retention of the device are greatly improved.

[0074] S3, depositing floating gate material at the bottom of the groove 103 and on the surface of the protrusion 102 to form semi-floating gate transistors 30 on the two protrusions 102 respectively, and connecting the two semi-floating gate transistors 30 through a floating gate 301 located at the bottom of the groove 103; wherein, one of the two semi-floating gate transistors 30 is configured as a write transistor and the other is configured as an erase transistor.

[0075] This step involves depositing floating gate material to form two semi-floating gate transistors 30 sharing the floating gate 301. These transistors are configured as a write transistor and an erase transistor, respectively, achieving an independent "one write, one erase" operation architecture. This fabrication process is clear, streamlined, and highly compatible with existing CMOS semiconductor manufacturing processes. It can efficiently fabricate three-dimensional semi-floating gate memory devices with high integration, high reliability, and excellent write / erase performance.

[0076] As an optional embodiment of this application, the step of depositing a wide bandgap semiconductor material on the surface of the protrusion 102 and etching it so that the remaining wide bandgap semiconductor material layer 20 at least covers the top region and the bottom corner region of the protrusion 102 includes:

[0077] A wide bandgap semiconductor material layer 20 and a protective layer 90 are conformally deposited on the surfaces of the protrusion 102 and the groove 103;

[0078] The protective layer 90 and the wide bandgap semiconductor material layer 20 are removed by anisotropic plasma etching, leaving only a portion of the wide bandgap semiconductor material layer 20 in the corner region at the bottom of the protrusion 102;

[0079] The wide bandgap semiconductor material layer 20 on the sidewall surface of the protrusion 102 is removed by a wet etching process, and the wide bandgap semiconductor material layer 20 is retained on the top surface of the protrusion 102 to form a discontinuous structure of the wide bandgap semiconductor material layer 20.

[0080] In this embodiment, the wide bandgap semiconductor material layer 20 and the protective layer 90 are first conformally deposited. The protective layer 90 serves to protect the underlying material during subsequent etching. Next, utilizing the anisotropic characteristics of anisotropic plasma etching (such as RIE), the etching rate in the vertical direction is much greater than in the horizontal direction, thereby removing most of the material from the horizontal surface and sidewall surfaces. Only a portion of the wide bandgap semiconductor material layer 20 is retained in the corner region at the bottom of the protrusion 102 (a dead corner region with a slow etching rate due to its geometry). Finally, utilizing the isotropic characteristics of wet etching, the remaining wide bandgap semiconductor material layer 20 on the sidewall surface of the protrusion 102 is removed. Simultaneously, due to the thicker material on the top surface or a different etching selectivity, the wide bandgap semiconductor material layer 20 is retained on the top surface of the protrusion 102.

[0081] This embodiment, through a clever combination of dry and wet etching, enables the formation of a discontinuous wide bandgap semiconductor material layer 20 on the top surface and bottom corner region of the protrusion 102 where the electric field is most concentrated. This not only simplifies the fabrication process and reduces manufacturing costs, but also ensures the exposure of the main channel region on the sidewall of the protrusion 102, avoiding the adverse effects of the wide bandgap material on the turn-on voltage of the sidewall channel, and balancing the reliability of the device corner with the normal read / write performance of the main channel.

[0082] As an optional embodiment of this application, the semi-floating gate transistor 30 further includes a control gate 302, which is formed above the floating gate 301. The fabrication method further includes: after depositing the floating gate material, etching using a first photomask 81; after depositing the inter-gate dielectric layer and the control gate material, etching using a second photomask 82 to simultaneously remove excess control gate material and the floating gate material. The linewidth of the second photomask 82 is greater than the linewidth of the first photomask 81, so that the width of the formed control gate 302 is greater than the width of the floating gate 301, and the sidewalls of the control gate 302 extend laterally beyond the sidewalls of the floating gate 301.

[0083] In this embodiment, two independent photolithography and etching processes are employed in the formation of the floating gate 301 and the control gate 302. First, the first photomask 81 is used to define and etch a narrower pattern of the floating gate 301. Then, an inter-gate dielectric layer (i.e., the second gate dielectric layer 304) and control gate material are deposited. Next, the second photomask 82 with a larger linewidth is used for etching to remove excess control gate material and the exposed floating gate material in one go. Finally, the control gate 302 with a width greater than that of the floating gate 301 is formed, and the sidewalls of the control gate 302 completely cover and extend beyond the sidewalls of the floating gate 301 in the lateral direction.

[0084] By controlling the linewidth difference between the first photomask 81 and the second photomask 82, a specific morphology of "wide control gate, narrow floating gate" can be precisely formed without complex sidewall processes or multiple alignments. The structure of the control gate 302 sidewall extending beyond the floating gate 301 sidewall enhances the control force of the control gate 302 on the edge electric field of the floating gate 301 edge and the channel below, effectively reducing parasitic capacitive coupling between adjacent memory cells and reducing erase / write interference in dense arrays. At the same time, this self-aligned etching process ensures the precise forming of the gate structure, improving the overall stability and yield of the memory array.

[0085] The following analysis and explanation will be based on specific examples.

[0086] like Figure 4aAs shown, in the initial stage, a hard mask layer 70, such as a silicon nitride layer, is deposited on the surface of the substrate 10, and a third photoresist 83 is coated on it. Exposure and etching are then performed using the third photoresist 83, such as... Figure 4b As shown, this defines the initial outline of the active region 101. Figure 4c As shown, the active region 101 extends along the y-direction.

[0087] Subsequently, as Figure 4d As shown, the hard mask layer 70 is pulled back along the x-direction. Figure 4e As shown, silicon oxide material is then deposited and the surface is smoothed using a chemical mechanical polishing (CMP) process to obtain a smooth morphological base, that is, in the x direction, field oxygen 50 composed of silicon oxide material is formed on both sides of the active region 101.

[0088] Next, as Figure 4f As shown, the remaining hard mask layer 70 is removed. Figure 4g As shown, using the retained field oxide 50 as a mask, the substrate 10 is etched downwards, and the oxide layer on the surface of the field oxide 50 is thinned, thereby forming a protrusion structure with a certain height on the substrate 10, such as... Figure 4h As shown, the final result includes two adjacent protrusions 102 and a groove 103 located between them.

[0089] like Figure 5a As shown, a fourth photoresist 84 is coated on the surface of the substrate 10, and exposure and etching are performed using the fourth photoresist 84, such as... Figure 5b As shown, a U-shaped trench 104 is formed in the active region 101.

[0090] After the U-shaped groove 104 is formed, as Figure 6a As shown, a thin gallium nitride (GaN) material layer is conformally deposited on the surface of the active region 101 of the substrate 10 where the protrusion 102 has been formed. The specific thickness is reasonably set according to actual performance requirements. The GaN material layer covers the bottom, sidewalls, and surface of the protrusion 102 of the trench 103. Subsequently, a silicon nitride (SiN) layer is conformally deposited on the surface of the GaN material layer as a protective layer 90, and the silicon nitride protective layer 90 completely covers the GaN material layer.

[0091] like Figure 6b As shown, the silicon nitride protective layer 90 is etched using anisotropic plasma etching process. By precisely controlling the etching parameters and time, only a portion of the silicon nitride protective layer 90 is retained in the corner area at the bottom of the protrusion 102, while the silicon nitride protective layer 90 in other areas is completely removed.

[0092] like Figure 6c As shown, the gallium nitride material layer is etched using the retained silicon nitride protective layer 90 as a mask. Through selective etching, only a portion of the gallium nitride material layer is retained in the corner area at the bottom of the protrusion 102, while the gallium nitride material layer in other areas is completely removed.

[0093] like Figure 6d As shown, the remaining silicon nitride protective layer 90 is completely removed using a wet etching process, resulting in a gallium nitride material layer, i.e., a wide bandgap semiconductor material layer 20, that is, retained only in the bottom corner region of the protrusion 102.

[0094] After forming a wide bandgap semiconductor material layer 20 in the bottom corner region of the protrusion 102, as Figure 7a As shown, a silicon nitride material layer is conformally deposited on the surface of the substrate 10, on which a wide bandgap semiconductor material layer 20 has been formed, as a new protective layer 90. The silicon nitride material layer completely fills the trench 103 and covers the surface of the protrusion 102. Subsequently, the silicon nitride material layer is thinned to the middle position of the trench 103 using chemical mechanical polishing and wet etching processes, so that the surface of the silicon nitride material layer is lower than the top of the protrusion 102.

[0095] like Figure 7b As shown, a thin gallium nitride (GaN) material layer is conformally deposited on the surface of the thinned silicon nitride material layer, covering the bottom, sidewalls, and surface of the protrusion 102 of the trench. Then, a silicon nitride protective layer 90 is conformally deposited on the surface of the GaN material layer, completely covering the GaN material layer.

[0096] like Figure 7c and Figure 7d As shown, photolithography and etching are performed using the fifth photomask 85 to form a patterned area on the silicon nitride protective layer 90, while retaining the silicon nitride protective layer 90 at the top region of the protrusion 102.

[0097] like Figure 7e As shown, the gallium nitride (GaN) material layer is etched using a thermal KOH wet etching process. By precisely controlling the etching time and temperature, the etching process is stopped at the top region of the protrusion 102, thereby retaining a thin layer of GaN material at the top of the protrusion 102 as a wide bandgap semiconductor material layer 20 in the top region of the protrusion 102, while the GaN material layer in the remaining regions is completely removed. Exemplarily, a Cl2-based plasma etching process (such as Cl2 or BCl3) can also be used, utilizing the selectivity between GaN and silicon nitride (selectivity up to 30:1) to precisely etch the GaN material layer, forming an ideal thickness and morphology.

[0098] like Figure 7f As shown, the residual silicon nitride protective layer 90 is removed using a hot phosphoric acid solution, resulting in a gallium nitride material layer that remains only in the top region of the protrusion 102.

[0099] For example, fluorine-based plasma etching processes, such as CF4, SF6, and NF3, can also be used. The fluorine radicals generated by the fluorine-based plasma react with Si to produce volatile SiF4, which can be removed by a vacuum pump. Simultaneously, fluorine also reacts with nitrogen, but the N in silicon nitride is released as N2 or a small amount of NF3, thus achieving etching. For gallium nitride: fluorine radicals react with gallium to produce GaF3, which has extremely poor volatility at typical etching temperatures (<150°C) and will deposit on the gallium nitride surface, forming a "protective-like layer" that prevents further etching. Therefore, the etching rate of gallium nitride in pure fluorine chemistry is very low. Under optimized fluorine-based chemistry and low bias conditions, the selectivity between gallium nitride and silicon nitride can easily reach over 50:1, even exceeding 200:1.

[0100] After forming the wide bandgap semiconductor material layer 20 at the top region and bottom corner of the protrusion 102, as Figure 8 As shown, an atomic layer deposition (ALD) process is used to deposit a dielectric layer (e.g., a silicon oxide layer) on the surface of the substrate 10 as a first gate dielectric layer 303. The first gate dielectric layer 303 conformally covers the surfaces of the protrusion 102 and the wide bandgap semiconductor material layer 20.

[0101] like Figure 9a As shown, a sixth photoresist 86 is coated on the surface of the first gate dielectric layer 303, and the sixth photoresist 86 is used for exposure and development to define the contact window 105 region to be etched. The pattern of the sixth photoresist 86 corresponds to the position of the contact window 105 to be formed.

[0102] like Figure 9b As shown, using the patterned sixth photoresist 86 as a mask, a dry etching process is employed to selectively etch the first gate dielectric layer 303 and the wide bandgap semiconductor material layer 20 in the exposed area. By precisely controlling the etching time and parameters, the first gate dielectric layer 303 and the wide bandgap semiconductor material layer 20 in the exposed area are removed, forming a contact window 105 of appropriate depth, thereby exposing the underlying substrate 10.

[0103] like Figure 10aAs shown, taking the area corresponding to contact window 105 as an example, a floating gate polysilicon layer is conformally deposited on the surface of the substrate 10 using a furnace deposition process. This furnace deposition process has excellent uniformity and step coverage capabilities, enabling the formation of polysilicon films with highly consistent thickness on complex three-dimensional surface structures. Subsequently, the floating gate polysilicon layer is surface-planarized using a chemical mechanical polishing process to remove surface protrusions and ensure that its surface achieves nanometer-level flatness. Next, photolithography and etching processes are performed using a first photomask 81, where the linewidth of the first photomask 81 is defined as CD1. Specifically, photoresist is coated on the surface of the floating gate polysilicon layer, and after exposure and development, a patterned area is formed.

[0104] like Figure 10b As shown, a dry etching process is used to pattern the floating gate polysilicon material in the exposed area, defining a continuous floating gate pattern on the protrusion and the surface of the trench, wherein the floating gate portion located at the bottom of the trench for connecting two half-floating gate transistors is retained.

[0105] like Figure 10c As shown, an atomic layer deposition process is used to deposit a high-quality dielectric layer, such as silicon oxide or a high-k dielectric material, on the surface of the floating gate structure as the second gate dielectric layer 304. The excellent conformality of the atomic layer deposition process ensures that the second gate dielectric layer 304 can form a uniform, dense, and defect-free thin film on the sidewalls, top, and bottom of the floating gate 301, effectively isolating the floating gate 301 from the subsequently formed control gate 302, while maintaining excellent interface characteristics.

[0106] like Figure 10d As shown, a control gate polysilicon layer is deposited on the surface of the second gate dielectric layer 304, and the surface is planarized again using CMP process to ensure that the surface of the control gate polysilicon layer is highly flat.

[0107] like Figure 10e and Figure 10f As shown, a second photolithography and etching process is performed using a second photomask 82, where the linewidth of the second photomask 82 is defined as CD2, where CD2 > CD1. This process precisely removes the control gate polysilicon material not protected by the photoresist and part of the floating gate structure, forming a control gate 302 structure with a linewidth of CD2. The larger linewidth of CD2 effectively enhances the control gate's control capability over the channel region, improving the device's switching characteristics and drive current.

[0108] like Figure 2As shown, a chemical vapor deposition (CVD) process is used to deposit silicon oxide as an isolation layer 60 in the gaps between control gates 302 to prevent electrical interference between adjacent devices. Next, the isolation layer 60 is subjected to a chemical mechanical polishing process to remove excess material from the surface, ensuring that the surface of the silicon oxide isolation layer 60 is flush with the top of the control gates 302, thus guaranteeing surface flatness for subsequent processes.

[0109] Subsequently, using photolithography and etching processes, openings are formed in the isolation layer 60 to expose the sidewall surfaces of the gate structure and the two side regions of the active region 101. Specifically, photoresist is coated and patterned on the surface of the isolation layer 60 to define the gate sidewalls and active region regions to be exposed. Then, an anisotropic dry etching process is used to remove the isolation layer 60 in the exposed areas until the underlying gate sidewalls and active region 101 surfaces are exposed.

[0110] Then, the sidewall formation process, source / drain region formation process, and contact hole formation process are performed sequentially:

[0111] Sidewall formation: A layer of silicon nitride or silicon oxide material is deposited on both sides of the gate structure, and a sidewall structure is formed by anisotropic etching to precisely control the doping distribution of the source and drain regions and prevent short-channel effects;

[0112] Source / drain region formation: Source / drain regions are formed on both sides of the active region 101 through ion implantation or selective epitaxial growth process, and rapid thermal annealing is performed to activate the dopant to ensure that the source / drain regions have good conductivity and junction characteristics.

[0113] Contact hole formation: Contact holes are formed above the source / drain region and gate structure using photolithography and dry etching processes to provide electrical connection channels for subsequent metal interconnects.

[0114] Finally, a metal layer (such as copper or aluminum) is deposited inside and on the surface of the contact holes using a metal deposition process (such as PVD or CVD), and a planar metal interconnect structure is formed by a chemical mechanical polishing process. By repeating the above process steps multiple times, a multilayer metal interconnect network can be formed.

[0115] In summary, this application proposes a memory device and its fabrication method. Through systematic innovation in device structure design and fabrication process, it effectively solves key technical bottlenecks in existing three-dimensional memory devices, such as concentrated electric field at corners, large leakage current in the gate dielectric layer, insufficient data retention, and complex layout of memory cell arrays. This achieves a comprehensive improvement in the reliability, electrical performance, and integration of the memory device.

[0116] At the structural level, this application introduces a wide bandgap semiconductor material layer 20 in the top region and bottom corner region of the protrusion 102. By fully utilizing its extremely high critical breakdown electric field and wide bandgap characteristics, it effectively suppresses the electric field concentration effect at the corner of the three-dimensional structure, significantly reduces the leakage current of the tunneling oxide layer in the high electric field region, and significantly improves the data retention and breakdown resistance of the device. Simultaneously, the wide bandgap semiconductor material layer 20 is designed as a discontinuous structure, remaining only in the top and bottom corner regions while exposing the sidewalls. This alleviates the electric field concentration problem at the corners and avoids adverse effects on the sidewall channel turn-on voltage, achieving a good balance between reliability and electrical performance.

[0117] At the array architecture level, this application adopts a U-shaped groove and a double protrusion structure. The floating gate 301 at the bottom serves as a common charge storage node shared by the two semi-floating gate transistors 30, and is configured as a write transistor and an erase transistor, respectively. This "one write and one erase" topology simplifies the array layout of the memory cells, improves the chip integration, and enables the write and erase operations to be performed independently and efficiently.

[0118] At the process level, this application precisely controls the distribution morphology of the wide bandgap semiconductor material layer 20 through a combination of conformal deposition, anisotropic plasma etching, and wet etching, resulting in strong process controllability and good repeatability. By employing two photomask etching processes with different linewidths, a specific cladding structure is formed where the width of the control gate 302 is greater than the width of the floating gate 301, enhancing the electrostatic control capability of the control gate 302 over the channel and effectively reducing parasitic capacitance and erase / write interference between adjacent cells. A high-quality inter-gate dielectric layer is formed through atomic layer deposition, ensuring high uniformity and density of the dielectric layer thickness on complex three-dimensional morphology surfaces, further improving the breakdown voltage and long-term reliability of the gate structure.

[0119] Furthermore, the memory device and its fabrication method described in this application are highly compatible with existing CMOS manufacturing processes, requiring no special equipment or additional complex process steps. They possess excellent scalability and industrialization prospects, and can be further applied to the design of higher-density three-dimensional memory arrays, providing conditions for the development of next-generation high-density non-volatile memories.

[0120] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A storage device, characterized in that, include: A substrate having an active region, the active region including two adjacent protrusions, and a groove formed between the two protrusions; A wide bandgap semiconductor material layer is formed on the surface of the protrusion and at least covers the top region and bottom corner region of the protrusion; Two semi-floating gate transistors are formed on the two protrusions respectively. The two semi-floating gate transistors share the same floating gate. The floating gate is a continuous structure, wherein the floating gate portion located at the bottom of the groove connects the two semi-floating gate transistors. One of the two semi-floating gate transistors is configured as a write transistor, and the other is configured as an erase transistor.

2. The storage device according to claim 1, characterized in that: Each of the semi-floating gate transistors also includes a control gate formed above the floating gate; The floating grid is a single, continuously extending structure that extends continuously along the bottom of the groove and the surface of the protrusion.

3. The storage device according to claim 2, characterized in that, Also includes: A first gate dielectric layer is located between the floating gate and the active region; A second gate dielectric layer is located between the floating gate and the control gate; The source and drain of each of the semi-floating gate transistors are formed on both sides of the active region, respectively.

4. The storage device according to claim 3, characterized in that: Contact windows are formed on the wide bandgap semiconductor material layer and the first gate dielectric layer, and the substrate is exposed through the contact windows.

5. The storage device according to claim 2, characterized in that: In a cross section perpendicular to the extension direction of the groove, the width of the control grid is greater than the width of the floating grid, and the sidewall of the control grid extends laterally beyond the sidewall of the floating grid.

6. The storage device according to claim 1, characterized in that: The wide bandgap semiconductor material layer is made of at least one of gallium nitride, silicon carbide, and aluminum nitride.

7. The storage device according to claim 1, characterized in that: The wide bandgap semiconductor material layer has a discontinuous structure, the sidewall surface of the protrusion is exposed, and the wide bandgap semiconductor material layer is only distributed on the top surface of the protrusion and the corner area at the bottom of the protrusion.

8. A method for manufacturing a storage device as described in any one of claims 1 to 7, characterized in that, include: A substrate is provided, on which an active region is etched to form, the active region including two adjacent protrusions, and a groove is etched between the two protrusions; A wide bandgap semiconductor material is deposited on the surface of the protrusion and etched so that the remaining wide bandgap semiconductor material layer at least covers the top region and the bottom corner region of the protrusion; A floating gate material is deposited on the bottom of the trench and the surface of the protrusion to form a semi-floating gate transistor on each of the two protrusions, and the two semi-floating gate transistors are connected through a floating gate located at the bottom of the trench; wherein, one of the two semi-floating gate transistors is configured as a write transistor and the other is configured as an erase transistor.

9. The method for manufacturing the storage device according to claim 8, characterized in that, The process of depositing a wide bandgap semiconductor material on the surface of the protrusion and etching it to ensure that the remaining wide bandgap semiconductor material layer at least covers the top region and the bottom corner region of the protrusion includes: A wide bandgap semiconductor material layer and a protective layer are conformally deposited on the surfaces of the protrusion and the groove. The protective layer and the wide bandgap semiconductor material layer are removed by anisotropic plasma etching, leaving only a portion of the wide bandgap semiconductor material layer in the corner region at the bottom of the protrusion; After forming a wide bandgap semiconductor material layer in the bottom corner region of the protrusion, a wide bandgap semiconductor material layer and a protective layer are conformally deposited again on the surfaces of the protrusion and the trench. The protective layer is patterned using photolithography and etching processes so that it at least covers the top region of the protrusion. Using the patterned protective layer as a mask, the underlying wide bandgap semiconductor material layer is etched to form the wide bandgap semiconductor material layer in the top region of the protrusion, thereby forming a discontinuous structure of the wide bandgap semiconductor material layer.

10. The method for manufacturing a storage device according to claim 8, characterized in that, The semi-floating gate transistor further includes a control gate formed above the floating gate; The preparation method further includes: After depositing the grating material, etching is performed using a first photomask to define a continuous grating pattern on the protrusion and the surface of the groove. After depositing the inter-gate dielectric layer and control gate material, the control gate material is etched using a second photomask to pattern the control gate material and simultaneously remove the floating gate material underneath that is not covered by the control gate. The linewidth of the second photomask is greater than that of the first photomask, so that the width of the formed control grid is greater than the width of the floating grid, and the sidewall of the control grid extends beyond the sidewall of the floating grid in the lateral direction.

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