Semiconductor device and method of manufacturing the same, electronic device

Abstract

Embodiments of the present application provide a semiconductor device and a manufacturing method thereof, and an electronic device, and relate to the technical field of semiconductor. The manufacturing method of the semiconductor device comprises: manufacturing a first signal line on one side of a substrate; manufacturing a first dielectric layer covering the first signal line, a second signal line and a first stop layer in sequence; forming a first hole penetrating through the first stop layer, the second signal line and the first dielectric layer, the first hole stopping at the first signal line, the first hole being in a stepped shape and comprising a first hole segment and a second hole segment away from the substrate in sequence, the diameter of the second hole segment being greater than the diameter of the first hole segment; forming a first semiconductor layer, a first gate insulating layer and a first gate structure in a conformal covering and filling manner to fill the first hole, to obtain a first transistor; the first gate structure comprises a first gate in the first hole segment and a first connecting electrode in the second hole segment. The embodiments of the present application can improve the electrical performance of the semiconductor device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor device and its manufacturing method, and an electronic device. Background Technology

[0002] Currently, integrated circuit technology is developing towards increasing integration density and reducing component size. To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor device design and process optimizations to meet current product demands. Summary of the Invention

[0003] This application proposes a semiconductor device and its manufacturing method, as well as an electronic device, to solve the technical problem of high manufacturing costs due to the large number of times photomasks are used in the semiconductor device manufacturing process.

[0004] This application provides a method for manufacturing a semiconductor device, including:

[0005] A first signal line is fabricated on one side of the substrate;

[0006] A first dielectric layer, a second signal line, and a first stop layer are sequentially manufactured to cover the first signal line; the orthographic projections of the first signal line and the second signal line on the substrate intersect and are both parallel to the substrate;

[0007] A first hole is formed that penetrates the first stop layer, the second signal line, and the first dielectric layer. The first hole stops at the first signal line. The first hole is stepped and includes a first hole segment and a second hole segment that move away from the substrate in sequence. The diameter of the second hole segment is larger than the diameter of the first hole segment.

[0008] A first semiconductor layer, a first gate insulating layer, and a first gate structure are formed to conformally cover and fill the first hole, thereby obtaining a first transistor; the first gate structure includes a first gate located in the first hole segment and a first connection electrode located in the second hole segment.

[0009] Optionally, forming a first hole penetrating the first stop layer, the second signal line, and the first dielectric layer includes:

[0010] A first initial protective layer and a second initial protective layer are sequentially formed on the side of the first stop layer away from the substrate;

[0011] The second initial protective layer is patterned to obtain a fourth hole and an intermediate protective layer; the orthographic projection of the inner wall of the fourth hole on the substrate overlaps with the orthographic projection of the inner wall of the first hole segment on the substrate.

[0012] The intermediate protective layer and the first initial protective layer are patterned to obtain a fifth hole, a second protective layer, and a first protective layer; the fifth hole is stepped and includes a fifth hole segment located in the first protective layer and a sixth hole segment located in the second protective layer; the orthographic projection of the inner wall of the fifth hole segment on the substrate overlaps with the orthographic projection of the inner wall of the first hole segment on the substrate; the orthographic projection of the inner wall of the sixth hole segment on the substrate overlaps with the orthographic projection of the inner wall of the second hole segment on the substrate.

[0013] Using the second protective layer and the first protective layer as masks, an etching process is performed to obtain the first hole.

[0014] Optionally, a first semiconductor layer, a first gate insulating layer, and a first gate structure are formed to conformally cover and fill the first hole to obtain a first transistor, including:

[0015] An initial first semiconductor layer, an initial first gate insulating layer, and an initial first gate layer are sequentially formed to conformally cover and fill the first hole and cover the first stop layer;

[0016] The initial first gate layer, the initial first gate insulating layer, and the initial first semiconductor layer are subjected to chemical mechanical polishing until the first stop layer is exposed, thereby obtaining the first transistor and its first semiconductor layer, first gate insulating layer, and first gate structure.

[0017] Optionally, after forming a first semiconductor layer, a first gate insulating layer, and a first gate structure that conformally cover and fill the first hole to obtain the first transistor, the method further includes:

[0018] A first planar layer is formed on the side of the first connecting electrode away from the substrate;

[0019] A second hole is formed that penetrates the first planarization layer and exposes the connection portion; the connection portion and the first signal line belong to the same signal line layer;

[0020] A third signal line layer is formed on the side of the first planarization layer away from the substrate; the third signal line layer includes conductive pillars that fill the second hole and are electrically connected to the connection portion.

[0021] Optionally, after forming the third signal line layer on the side of the planarization layer away from the substrate, the method further includes:

[0022] The third signal line layer is patterned to obtain a third signal line; the third signal line includes a third source and drain.

[0023] Manufacture a second stop layer covering the third signal line;

[0024] A third hole is formed that penetrates the second stop layer, the third signal line, and the first planarization layer. The third hole stops at the first connection electrode. The third hole is stepped and includes a third hole segment and a fourth hole segment that move away from the substrate in sequence. The diameter of the fourth hole segment is larger than the diameter of the third hole segment.

[0025] A second semiconductor layer, a second gate insulating layer, and a second gate structure are formed to conformally cover and fill the third hole, thereby obtaining a second transistor; the second gate structure includes a second gate located in the third hole segment and a second connection electrode located in the fourth hole segment.

[0026] Optionally, a first planarization layer is formed on the side of the first connection electrode away from the substrate, including:

[0027] A first mask layer is formed on the side of the first semiconductor layer, the first gate insulating layer, and the first connection electrode away from the substrate;

[0028] Using the first mask layer as a mask, the first stop layer is removed, and the exposed first semiconductor layer is removed by lateral etching to obtain a bottom groove;

[0029] A first planar layer is formed that fills the bottom groove and covers the side of the first mask layer away from the substrate.

[0030] This application also provides a semiconductor device, including:

[0031] The first signal line is located on one side of the substrate and includes the first source and drain electrodes;

[0032] The second signal line is located on the side of the first signal line away from the substrate and is insulated from the first signal line, and includes a second source and drain electrode;

[0033] The first stop layer is located on the side of the second signal line away from the substrate;

[0034] A first transistor includes a first semiconductor layer, a first gate insulating layer, and a first gate structure. The first semiconductor layer, the first gate insulating layer, and the first gate structure sequentially conformally cover and fill a first hole. The first hole penetrates the first stop layer and the second signal line and stops at the first signal line. The first hole is stepped and includes a first hole segment and a second hole segment that are sequentially away from the substrate. The diameter of the second hole segment is larger than the diameter of the first hole segment. The first gate structure includes a first gate located in the first hole segment and a first connection electrode located in the second hole segment. The first semiconductor layer, the first gate insulating layer, the first gate structure, and the first stop layer are all flush with the side away from the substrate.

[0035] Optionally, the semiconductor device also includes:

[0036] A first planarization layer is located on the side of the first connection electrode away from the substrate, and includes a second hole that penetrates the first planarization layer and exposes the connection portion, wherein the connection portion and the first signal line belong to the same signal line layer;

[0037] The third signal line is located on the side of the first planarization layer away from the substrate, and includes a conductive pillar filled in the second hole and electrically connected to the connection portion, and a third source / drain electrode parallel to the substrate.

[0038] Optionally, the semiconductor device also includes:

[0039] The second stop layer is located on the side of the third signal line away from the substrate;

[0040] The second transistor includes a second semiconductor layer, a second gate insulating layer, and a second gate structure. The second semiconductor layer, the second gate insulating layer, and the second gate structure sequentially conformally cover and fill a third hole. The third hole penetrates the second stop layer, the third signal line, and the first planarization layer, and terminates at the first connection electrode. The third hole is stepped and includes a third hole segment and a fourth hole segment that are sequentially away from the substrate. The diameter of the fourth hole segment is larger than the diameter of the third hole segment. The second gate structure includes a second gate located in the third hole segment and a second connection electrode located in the fourth hole segment. The second semiconductor layer, the second gate insulating layer, the second gate structure, and the second stop layer are all flush with the side away from the substrate.

[0041] Optionally, it may also include at least one of the following:

[0042] The material of the first semiconductor layer is a metal oxide semiconductor layer;

[0043] The first stop layer includes an oxide layer or a polysilicon layer.

[0044] This application also provides an electronic device, including any of the semiconductor devices described above.

[0045] The beneficial technical effects of the technical solutions provided in this application include:

[0046] By forming a first hole penetrating the first stop layer, the second signal line, and the first dielectric layer, with the first hole stopping at the first signal line, and the first hole being stepped and comprising a first hole segment and a second hole segment moving away from the substrate in sequence, the diameter of the second hole segment being larger than the diameter of the first hole segment, thus forming a damascus structure for the first hole, then backfilling the first semiconductor layer, the first gate insulating layer, and the first gate with the material, followed by chemical mechanical polishing, a conformal structure of the first semiconductor layer, the first gate insulating layer, and the first gate is obtained, which covers and fills the first hole. The first gate structure includes a first gate located in the first hole segment and a first connection electrode located in the second hole segment. In other words, compared to the prior art method of forming a metal layer separately and then patterning the metal layer to obtain the first connection electrode, the first gate and the first connection electrode in this embodiment are prepared through the same process, which can reduce the number of patterning processes using a photomask, improve process efficiency, and reduce manufacturing costs.

[0047] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description

[0048] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0049] Figure 1a A schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application;

[0050] Figures 1b to 20 Schematic diagrams of the various structures obtained in each step of a semiconductor device manufacturing method provided in this application embodiment;

[0051] Figures 1b to 5 , Figures 21 to 26 Schematic diagrams of the various structures obtained in each step of another semiconductor device manufacturing method provided in this application embodiment.

[0052] 11-Substrate;

[0053] 12-First transistor; 121-First semiconductor layer; 1210-Initial first semiconductor layer; 122-First gate insulating layer; 1220-Initial first gate insulating layer; 123-First gate structure; 123a-First gate; 123b-First connection electrode; 1230-Initial first gate layer;

[0054] 13-Second transistor; 131-Second semiconductor layer; 132-Second gate insulating layer; 133-Second gate structure; 133a-Second gate; 133b-Second connection electrode;

[0055] 141 - First signal line; 142 - Connector; 14 - First signal line layer;

[0056] 151 - Second signal line; 15 - Second signal line layer;

[0057] 161 - Third signal line; 162 - Conductive post; 16 - Third signal line layer;

[0058] 17-First dielectric layer; 18-First stop layer; 19-First initial protective layer; 191-First protective layer; 20-Second initial protective layer; 200-Intermediate protective layer; 201-Second protective layer; 21-First planarization layer; 22-Second planarization layer; 23-Third dielectric layer; 24-Second dielectric layer; 25-Third mask layer; 26-Second mask layer; 27-First mask layer; 28-First photoresist layer; 29-Second photoresist layer;

[0059] 30 - First hole; 31 - Second hole; 32 - Third hole; 33 - Fourth hole; 34 - Bottom groove. Detailed Implementation

[0060] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions of the embodiments of this application.

[0061] Those skilled in the art will understand that, unless specifically stated otherwise, the terms "described" and "the" as used herein may also include plural forms. It should be further understood that the term "comprising" as used in this application's specification means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude implementations of other features, information, data, steps, operations, elements, components, and / or combinations thereof supported by this art. It should be understood that when we say an element is "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or it may mean that the element and the other element are connected through an intermediate element. Furthermore, "connected" or "coupled" as used herein may include wireless connections or wireless coupling. The term "and / or" as used herein refers to at least one of the items defined by the term; for example, "A and / or B" may be implemented as "A," or as "B," or as "A and B."

[0062] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0063] In the prior art, a metal layer needs to be formed separately, and then the metal layer needs to be patterned to obtain a first connection electrode. The first connection electrode is used to realize the electrical connection between the first gate of the first transistor and the second semiconductor layer of the second transistor.

[0064] Because the first connecting electrode needs to be fabricated separately, the semiconductor device manufacturing process involves multiple patterning processes using photomasks, resulting in higher manufacturing costs.

[0065] The technical solution of this application and how it solves the above-mentioned technical problems are described in detail below with specific embodiments. It should be noted that the following embodiments can be referenced, borrowed, or combined with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be described again.

[0066] This application provides a method for manufacturing a semiconductor device, the process flow of which is shown in the figure below. Figure 1a As shown, the method includes steps S1 to S4.

[0067] S1: Fabricate a first signal line 141 on one side of the substrate 11.

[0068] In some embodiments, the first signal line 141 includes a first source and drain.

[0069] S2: Sequentially manufacture a first dielectric layer 17, a second signal line 151, and a first stop layer 18 covering the first signal line 141; the orthogonal projections of the first signal line 141 and the second signal line 151 on the substrate 11 intersect and are both parallel to the substrate 11.

[0070] In some embodiments, the second signal line 151 includes a second source and drain.

[0071] S3: Form a first hole 30 that penetrates the first stop layer 18, the second signal line 151 and the first dielectric layer 17. The first hole 30 stops at the first signal line 141. The first hole 30 is stepped and includes a first hole segment and a second hole segment that are successively away from the substrate 11. The diameter of the second hole segment is larger than the diameter of the first hole segment.

[0072] S4: Form a first semiconductor layer 121, a first gate insulating layer 122, and a first gate structure 123 that conformally cover and fill the first hole 30 to obtain a first transistor; the first gate structure 123 includes a first gate 123a located in the first hole segment and a first connection electrode 123b located in the second hole segment.

[0073] By forming a first hole 30 that penetrates the first stop layer 18, the second signal line 151, and the first dielectric layer 17, with the first hole 30 stopping at the first signal line 141, the first hole 30 is stepped and includes a first hole segment and a second hole segment that are sequentially moved away from the substrate 11. The diameter of the second hole segment is larger than the diameter of the first hole segment, thus forming a damascus structure for the first hole 30. Then, the material of the first semiconductor layer 121, the first gate insulating layer 122, and the first gate 123a is backfilled, and then chemical mechanical polishing is performed to obtain a first semiconductor layer 121 that conformally covers and fills the first hole 30. The first gate insulating layer 122 and the first gate structure 123 are provided. The first gate structure 123 includes a first gate 123a located in a first aperture segment and a first connecting electrode 123b located in a second aperture segment. In other words, compared with the prior art, which forms a metal layer separately and then patterns the metal layer to obtain the first connecting electrode 123b, the first gate 123a and the first connecting electrode 123b are prepared by the same process in this embodiment. This can reduce the number of times the photomask is used for patterning, improve the process efficiency, and reduce the manufacturing cost.

[0074] Figure 1b A top view of the semiconductor device fabricated by this method, perpendicular to the substrate. For greater clarity, Figure 1b Various dielectric layers and substrate 11 are omitted in the text.

[0075] Optionally, the first stop layer 18 may include a polysilicon layer or an oxide layer.

[0076] As an example, in the first embodiment of this application, the first stop layer 18 may include a polysilicon layer, and the semiconductor device manufacturing method provided in this embodiment includes steps S101 to S114.

[0077] The structural diagrams obtained in each step of this embodiment can be found in [reference]. Figures 2 to 20 .

[0078] S101: A first signal line 141 is fabricated on one side of the substrate 11; the first signal line 141 includes a first source and drain.

[0079] In some embodiments, the first signal line 141 may be a first bit line. Multiple first bit lines extend along a third direction parallel to the substrate 11 and are arranged along a second direction; the first semiconductor layer 121 of the first transistor of each column of memory cells is electrically connected to a first bit line.

[0080] The third direction and the second direction are at a 90-degree angle or other angles, which is not specifically limited in this application.

[0081] Optionally, in some embodiments, step S1 may include steps S111 to S112.

[0082] S111: A second dielectric layer 24, a first signal line layer 14, and a third mask layer 25 are sequentially fabricated on one side of the substrate 11.

[0083] After step S111, the structural schematic diagram along the AA direction is as follows: Figure 2 As shown.

[0084] S112: Using photolithography and etching processes, the third mask layer 25 and the first signal line layer 14 are patterned to obtain the patterned third mask layer 25 and the first signal line 141.

[0085] After step S112, the structural schematic diagram along the AA direction is as follows: Figure 3 As shown.

[0086] S102: Sequentially fabricate a first dielectric layer 17, a second signal line 151, and a first stop layer 18 covering the first signal line 141; the orthogonal projections of the first signal line 141 and the second signal line 151 on the substrate 11 intersect and are both parallel to the substrate 11; the second signal line 151 includes a second source and drain.

[0087] Optionally, in some embodiments, the second signal line 151 may be a first word line. Multiple first word lines extend along a second direction parallel to the substrate 11 and are arranged along a third direction; the first semiconductor layer 121 of the first transistor of each memory cell in each row is electrically connected to a first word line.

[0088] In some embodiments, the first stop layer 18 may include a polysilicon layer, and step S102 may include steps S121 to S125.

[0089] S121: Form a first dielectric layer 17 covering the second dielectric layer 24 and the patterned third mask layer 25, and perform chemical mechanical polishing on the first dielectric layer 17.

[0090] After step S121, the structural schematic diagram along the AA direction is as follows: Figure 4 As shown.

[0091] S122: Sequentially manufacture the second signal line layer 15 and the second mask layer 26 covering the first dielectric layer 17.

[0092] After step S122, the structural schematic diagram along the AA direction is as follows: Figure 5 As shown.

[0093] S123: Using photolithography and etching processes, the second mask layer 26 and the second signal line layer 15 are patterned to obtain the patterned second mask layer 26 and the second signal line 151.

[0094] It should be noted that after step S123, the structural schematic diagram obtained along the AA direction is... Figure 5 Similarly, it will not be elaborated here.

[0095] S124: Form a third dielectric layer 23 covering the first dielectric layer 17 and the patterned second mask layer 26, and perform chemical mechanical polishing on the third dielectric layer 23.

[0096] After step S124, the structural schematic diagram along the AA direction is as follows: Figure 6 As shown.

[0097] It should be noted that in some embodiments, the material (e.g., oxide) of the third dielectric layer 23 and the second mask layer 26 can be the same, and the third dielectric layer 23 covers the second mask layer 26. Figure 6 No additional annotations are made for the second mask layer 26.

[0098] S125: Form a first stop layer 18 covering the third dielectric layer 23. The first stop layer 18 may include a polysilicon layer.

[0099] After step S125, the structural schematic diagram along the AA direction is as follows: Figure 7 As shown.

[0100] S103: Form a first hole 30 that penetrates the first stop layer 18, the second signal line 151 and the first dielectric layer 17. The first hole 30 stops at the first signal line 141. The first hole 30 is stepped and includes a first hole segment and a second hole segment that are successively away from the substrate 11. The diameter of the second hole segment is larger than the diameter of the first hole segment.

[0101] Optionally, in some embodiments, step S103 may include steps S131 to S134.

[0102] S131: A first initial protective layer 19 and a second initial protective layer 20 are sequentially formed on the side of the first stop layer 18 away from the substrate 11.

[0103] After step S131, the structural schematic diagram along the AA direction is as follows: Figure 8 As shown.

[0104] S132: The second initial protective layer 20 is patterned using the patterned first photoresist layer 28 to obtain the third hole 32 and the intermediate protective layer 200; the orthographic projection of the inner wall of the third hole 32 on the substrate 11 overlaps with the orthographic projection of the inner wall of the first hole segment on the substrate 11.

[0105] In some embodiments, the orthographic projection of the first photoresist layer 28 onto the substrate 11 overlaps with the orthographic projection of the inner wall of the first aperture segment onto the substrate 11.

[0106] After step S132, the structural schematic diagram along the AA direction is as follows: Figure 9 As shown.

[0107] S133: The intermediate protective layer 200 and the first initial protective layer 19 are patterned using the patterned second photoresist layer 29 to obtain the fourth hole 33, the second protective layer 201 and the first protective layer 191; the fourth hole 33 is stepped and includes a fifth hole segment located in the first protective layer 191 and a sixth hole segment located in the second protective layer 201; the orthographic projection of the inner wall of the fifth hole segment on the substrate 11 overlaps with the orthographic projection of the inner wall of the first hole segment on the substrate 11; the orthographic projection of the inner wall of the sixth hole segment on the substrate 11 overlaps with the orthographic projection of the inner wall of the second hole segment on the substrate 11.

[0108] In some embodiments, the orthographic projection of the second photoresist layer 29 onto the substrate 11 overlaps with the orthographic projection of the inner wall of the second aperture segment onto the substrate 11.

[0109] The second protective layer 201 can be used as a hard mask layer, and the material of the second protective layer 201 may include silicon oxynitride.

[0110] The first protective layer 191 can serve as an auxiliary mask layer, and the material of the first protective layer 191 may include ACL.

[0111] In some embodiments, before step S133 and after step S132, the process further includes removing the patterned first photoresist layer 28 and fabricating a patterned second photoresist layer 29.

[0112] After step S133, the structural schematic diagram along the AA direction is as follows: Figure 10 As shown. S134: Using the second protective layer 201 and the first protective layer 191 as masks, an etching process is performed to obtain the first hole 30.

[0113] In some embodiments, before step S134, the patterned second photoresist layer 29 is removed. After step S134, the second protective layer 201 and the first protective layer 191 are removed.

[0114] After step S134, the structural schematic diagram along the AA direction is as follows: Figure 11 As shown.

[0115] S104: Form a first semiconductor layer 121, a first gate insulating layer 122, and a first gate structure 123 that conformally cover and fill the first hole 30 to obtain a first transistor; the first gate structure 123 includes a first gate 123a located in the first hole segment and a first connection electrode 123b located in the second hole segment.

[0116] Optionally, in some embodiments, step S104 may include steps S141 to S142.

[0117] S141: Sequentially form an initial first semiconductor layer 1210, an initial first gate insulating layer 1220, and an initial first gate layer 1230 that conformally cover and fill the first hole 30 and cover the first stop layer 18.

[0118] After step S141, the structural schematic diagram along the AA direction is as follows: Figure 12 As shown.

[0119] S142: Perform chemical mechanical polishing on the initial first gate layer 1230, the initial first gate insulating layer 1220 and the initial first semiconductor layer 1210 until the first stop layer 18 is exposed, to obtain the first transistor and its first semiconductor layer 121, first gate insulating layer 122 and first gate structure 123.

[0120] In other words, the first gate 123a extends along a first direction perpendicular to the substrate 11; the first gate insulating layer 122 surrounds the outer periphery and bottom of the first gate 123a; and the first semiconductor layer 121 surrounds the outer periphery and bottom of the first gate insulating layer 122. In this embodiment, the first transistor adopts a ring channel structure, which simplifies the fabrication process and reduces the manufacturing difficulty.

[0121] Compared to the method of etching the initial first semiconductor layer 121 to obtain the first semiconductor layer 121, this embodiment uses chemical mechanical polishing (CMP process) to obtain the first semiconductor layer 121. This avoids the risk of metal contamination in the first semiconductor layer 121 during the etching process, as well as the problem of the small tilt angle of the sidewall of the first semiconductor layer 121 (usually only up to 85 degrees), thereby improving the electrical performance of the first transistor.

[0122] After step S142, the structural schematic diagram along the AA direction is as follows: Figure 13 As shown.

[0123] S105: A first planarization layer 21 is formed on the side of the first connecting electrode 123b away from the substrate 11.

[0124] Optionally, in some embodiments, step S105 may include steps S151 to S153.

[0125] S151: A first mask layer 27 is formed on the side of the first semiconductor layer 121, the first gate insulating layer 122 and the first connection electrode 123b away from the substrate 11.

[0126] After step S151, the structural schematic diagram along the AA direction is as follows: Figure 14 As shown.

[0127] S152: Using the first mask layer 27 as a mask, the first stop layer 18 is removed, and the exposed first semiconductor layer 121 is removed by lateral etching to obtain the bottom groove 34.

[0128] After step S152, the structural schematic diagram along the AA direction is as follows: Figure 15 As shown in the figure, the exposed first semiconductor layer 121 includes a first semiconductor layer in contact with the first stop layer 18.

[0129] S153: Form a filling bottom groove 34 and cover the first planarization layer 21 on the side of the first mask layer 27 away from the substrate 11.

[0130] In some embodiments, the first mask layer 27 and the first planarization layer 21 are made of the same material, and in this case, there is no clear boundary between the first mask layer 27 and the first planarization layer 21. Figure 16 The first mask layer 27 is not marked in the text.

[0131] After step S153, the structural schematic diagram along the AA direction is as follows: Figure 16 As shown.

[0132] S106: A second hole 31 is formed that penetrates the first planarization layer 21 and exposes the connection portion 142; the connection portion 142 and the first signal line 141 belong to the same signal line layer (in this embodiment, the first signal line layer 14).

[0133] That is, a first signal line layer 14 is formed; the first signal line layer 14 is patterned to obtain a first signal line 141 and a connecting portion 142.

[0134] By using the same process, the first signal line 141 and the connector 142 can be formed simultaneously, which optimizes the process flow and reduces manufacturing costs.

[0135] Furthermore, since the subsequently formed third signal line layer 16 includes conductive pillars 162 that fill the second hole 31 and are electrically connected to the connection portion 142, interlayer electrical connection can be achieved. After step S106, the resulting structural schematic diagram along the BB direction is as follows... Figure 17 As shown.

[0136] It should be noted that after step S106, the structural schematic diagram obtained along the AA direction is... Figure 16 Similarly, this will not be elaborated upon here.

[0137] S107: A third signal line layer 16 is formed on the side of the first planarization layer 21 away from the substrate 11; the third signal line layer 16 includes conductive pillars 162 that are filled in the second hole 31 and electrically connected to the connection portion 142.

[0138] The conductive pillars 162 and the third signal line 161 are formed using the third signal line layer 16, meaning that the conductive pillars 162 and the third signal line 161 belong to the same signal line layer, which simplifies the process and reduces manufacturing costs.

[0139] After step S107, the structural schematic diagram along the AA direction is as follows: Figure 18 As shown.

[0140] After step S107, the structural schematic diagram along the BB direction is as follows: Figure 19 As shown.

[0141] Optionally, in some embodiments, steps S107 may be followed by steps S108 to S111.

[0142] S108: Pattern the third signal line layer 16 to obtain the third signal line 161; the third signal line 161 includes the third source and drain.

[0143] In some embodiments, the third signal line 161 may be a second bit line. Multiple second bit lines extend along a third direction parallel to the substrate 11 and are arranged along a second direction; the second semiconductor layer 131 of the second transistor of each column of memory cells is electrically connected to a second bit line.

[0144] In some embodiments, the manufacturing process of the third signal line 161 in step S108 is similar to that of the second signal line 151 in step S2, and will not be described again here.

[0145] S109: Manufacturing a second stop layer covering the third signal line 161.

[0146] S110: A third hole is formed that penetrates the second stop layer, the third signal line 161 and the first planarization layer 21. The third hole stops at the first connection electrode 123b. The third hole is stepped and includes a third hole segment and a fourth hole segment that move away from the substrate 11 in sequence. The diameter of the fourth hole segment is larger than the diameter of the third hole segment.

[0147] In some embodiments, the manufacturing process of the third hole is similar to that of the first hole 30, and will not be described again here.

[0148] S111: A second semiconductor layer 131, a second gate insulating layer 132, and a second gate structure 133 are formed to cover and fill the third hole, thereby obtaining a second transistor; the second gate structure 133 includes a second gate 133a located in the third hole segment and a second connection electrode 133b located in the fourth hole segment.

[0149] In other words, the second gate 133a extends along a first direction perpendicular to the substrate 11. The second gate insulating layer 132 surrounds the outer periphery and bottom of the second gate 133a. The second semiconductor layer 131 surrounds the outer periphery and bottom of the second gate insulating layer 132 and is electrically connected to the first gate 123a via the first connection electrode 123b.

[0150] Optionally, in some embodiments, step S111 may include: sequentially forming an initial second semiconductor layer, an initial second gate insulating layer, and an initial second gate layer that conformally cover and fill the third hole and cover the first connection electrode 123b; performing chemical mechanical polishing on the initial second gate layer, the initial second gate insulating layer, and the initial second semiconductor layer until the second stop layer is exposed, thereby obtaining the second transistor and its second semiconductor layer 131, second gate insulating layer 132, and second gate structure 133.

[0151] Compared to the method of etching the initial second semiconductor layer 131 to obtain the second semiconductor layer 131, this embodiment uses chemical mechanical polishing (CMP) to obtain the second semiconductor layer 131. This avoids the risk of metal contamination in the second semiconductor layer 131 during the etching process and the problem of the small tilt angle of the sidewall of the second semiconductor layer 131 (usually only up to 85 degrees), thereby improving the electrical performance of the second transistor.

[0152] Optionally, in some embodiments, the second stop layer includes a polysilicon layer, and steps S112 to S114 may be included after step S111.

[0153] S112: A fourth mask layer is formed on the side of the second semiconductor layer 131, the second gate insulating layer 132, and the second connection electrode 133b away from the substrate 11.

[0154] S113: Using the fourth mask layer as a mask, the second stop layer is removed, and the exposed second semiconductor layer 131 is removed by lateral etching to obtain the second undercut groove. The exposed second semiconductor layer 131 includes a first semiconductor layer in contact with the second stop layer.

[0155] S114: Form a second planar layer 22 that fills the second bottom groove and covers the fourth mask layer on the side away from the substrate 11.

[0156] After step S114, the structural schematic diagram along the AA direction is as follows: Figure 20 As shown.

[0157] In some embodiments, the first semiconductor layer 121 and the second semiconductor layer 131 may be metal-oxide-semiconductor layers. For example, the materials of the first semiconductor layer 121 and the second semiconductor layer 131 may be indium gallium zinc oxide (IGZO). The materials of the first planarization layer 21, the second planarization layer 22, and each dielectric layer may include oxides. The substrate 11 may be a silicon substrate 11. Each signal line layer and each signal line may be a metal layer (e.g., titanium nitride). The materials of the first gate structure 123 and the second gate structure 133 may include indium zinc oxide. The materials of the first gate insulating layer 122 and the second gate insulating layer 132 may be high-k materials.

[0158] As an example, in the second embodiment of this application, the first stop layer 18 may include an oxide layer, and the semiconductor device manufacturing method provided in this embodiment includes steps S201 to S211.

[0159] The structural diagrams obtained in each step of this embodiment can be found in [reference]. Figures 2 to 5 , Figures 21 to 26 .

[0160] S201: A first signal line 141 is fabricated on one side of the substrate 11; the first signal line 141 includes a first source and drain.

[0161] Step S201 in this embodiment is similar to step S101 in the previous embodiment, and can be found in [reference]. Figure 2 and Figure 3 This will not be elaborated upon here.

[0162] S202: Sequentially fabricate a first dielectric layer 17, a second signal line 151, and a first stop layer 18 covering the first signal line 141; the orthogonal projections of the first signal line 141 and the second signal line 151 on the substrate 11 intersect and are both parallel to the substrate 11; the second signal line 151 includes a second source and drain.

[0163] In some embodiments, step S202 may include steps S221 to S224.

[0164] S221: Form a first dielectric layer 17 covering the second dielectric layer 24 and the patterned third mask layer 25, and perform chemical mechanical polishing on the first dielectric layer 17.

[0165] After step S221, a structural schematic diagram along the AA direction is obtained (see attached diagram). Figure 4 .

[0166] S222: Sequentially manufacture the second signal line layer 15 and the second mask layer 26 covering the first dielectric layer 17.

[0167] After step S222, the structural schematic diagram along the AA direction can be found here. Figure 5 .

[0168] S223: Using photolithography and etching processes, the second mask layer 26 and the second signal line layer 15 are patterned to obtain the patterned second mask layer 26 and the second signal line 151.

[0169] It should be noted that the structural schematic diagram along the AA direction obtained after step S223 can be found by referring to [further details needed]. Figure 5 .

[0170] S224: Form a first stop layer 18 covering the first dielectric layer 17 and the patterned second mask layer 26, and perform chemical mechanical polishing on the first stop layer 18. The first stop layer 18 may include an oxide layer.

[0171] After step S224, the structural schematic diagram along the AA direction can be found here. Figure 21 .

[0172] S203: Form a first hole 30 that penetrates the first stop layer 18, the second signal line 151 and the first dielectric layer 17. The first hole 30 stops at the first signal line 141. The first hole 30 is stepped and includes a first hole segment and a second hole segment that are successively away from the substrate 11. The diameter of the second hole segment is larger than the diameter of the first hole segment.

[0173] After step S203, the structural schematic diagram along the AA direction is as follows: Figure 22 As shown.

[0174] S204: A first semiconductor layer 121, a first gate insulating layer 122, and a first gate structure 123 are formed to cover and fill the first hole 30, thereby obtaining a first transistor; the first gate structure 123 includes a first gate 123a located in the first hole segment and a first connection electrode 123b located in the second hole segment.

[0175] After step S204, the structural schematic diagram along the AA direction is as follows: Figure 23 As shown.

[0176] S205: Form a first planarization layer 21 covering the first stop layer 18, the first semiconductor layer 121, the first gate insulating layer 122 and the first connection electrode 123b.

[0177] After step S205, the structural schematic diagram along the AA direction is as follows: Figure 24 As shown.

[0178] It should be noted that in some embodiments, the materials (e.g., oxides) of the first planarization layer 21 and the first stop layer 18 may be the same, and the first planarization layer 21 covers the first stop layer 18. Figure 24 No additional annotation is made for the first stopping layer 18.

[0179] S206: A second hole 31 is formed that penetrates the first planarization layer 21 and exposes the connection portion 142; the connection portion 142 and the first signal line 141 belong to the same signal line layer.

[0180] After step S206, the structural schematic diagram along the BB direction is as follows: Figure 25 As shown.

[0181] It should be noted that in some embodiments, the materials (e.g., oxides) of the first planarization layer 21 and the first stop layer 18 may be the same, and the first planarization layer 21 covers the first stop layer 18. Figure 25 No additional annotation is made for the first stopping layer 18.

[0182] It should be noted that after step S106, the structural schematic diagram obtained along the AA direction is... Figure 24 Similarly, this will not be elaborated upon here.

[0183] S207: A third signal line layer 16 is formed on the side of the first planarization layer 21 away from the substrate 11; the third signal line layer 16 includes conductive pillars 162 that are filled in the second hole 31 and electrically connected to the connection portion 142.

[0184] S208: Pattern the third signal line layer 16 to obtain the third signal line 161; the third signal line 161 includes the third source and drain.

[0185] The processes of steps S207 and S208 in this embodiment are similar to those of steps S107 and S108 in the previous embodiments, and will not be described again here.

[0186] S209: Fabricate a second stop layer covering the third signal line 161, the second stop layer comprising an oxide layer.

[0187] S210: A third hole is formed that penetrates the second stop layer, the third signal line 161 and the first planarization layer 21. The third hole stops at the first connection electrode 123b. The third hole is stepped and includes a third hole segment and a fourth hole segment that move away from the substrate 11 in sequence. The diameter of the fourth hole segment is larger than the diameter of the third hole segment.

[0188] S211: A second semiconductor layer 131, a second gate insulating layer 132, and a second gate structure 133 are formed to conformally cover and fill the third hole, thereby obtaining a second transistor; the second gate structure 133 includes a second gate 133a located in the third hole segment and a second connection electrode 133b located in the fourth hole segment.

[0189] The processes of steps S210 and S211 in this embodiment are similar to those of steps S110 and S111 in the previous embodiments, and will not be described again here.

[0190] After step S211, the structural schematic diagram along the AA direction is as follows: Figure 26 As shown.

[0191] It should be noted that in the embodiments of this application, when the materials (e.g., oxides) of two adjacent film layers are the same, the film layer manufactured first will not be additionally labeled.

[0192] The beneficial technical effects of the technical solutions provided in this application include:

[0193] By forming a first hole 30 that penetrates the first stop layer 18, the second signal line 151, and the first dielectric layer 17, with the first hole 30 stopping at the first signal line 141, the first hole 30 is stepped and includes a first hole segment and a second hole segment that are sequentially moved away from the substrate 11. The diameter of the second hole segment is larger than the diameter of the first hole segment, thus forming a damascus structure for the first hole 30. Then, the material of the first semiconductor layer 121, the first gate insulating layer 122, and the first gate 123a is backfilled, and then chemical mechanical polishing is performed to obtain a first semiconductor layer 121 that conformally covers and fills the first hole 30. The first gate insulating layer 122 and the first gate structure 123 are provided. The first gate structure 123 includes a first gate 123a located in a first aperture segment and a first connecting electrode 123b located in a second aperture segment. In other words, compared with the prior art, which forms a metal layer separately and then patterns the metal layer to obtain the first connecting electrode 123b, the first gate 123a and the first connecting electrode 123b are prepared by the same process in this embodiment. This can reduce the number of times the photomask is used for patterning, improve the process efficiency, and reduce the manufacturing cost.

[0194] Compared to the method of etching the initial first semiconductor layer 121 to obtain the first semiconductor layer 121, this embodiment uses a damascus structure chemical mechanical polishing (CMP process) to chemically and mechanically polish the initial first semiconductor layer 121 to obtain the first semiconductor layer 121. This can avoid the risk of metal contamination of the first semiconductor layer 121 during the etching process, as well as the problem of the small tilt angle of the sidewall of the first semiconductor layer 121 (usually only up to 85 degrees), thereby improving the electrical performance of the first transistor.

[0195] The conductive pillars 162 and the third signal line 161 are formed using the third signal line layer 16, meaning that the conductive pillars 162 and the third signal line 161 belong to the same signal line layer, which simplifies the process and reduces manufacturing costs.

[0196] Based on the same inventive concept, this application also provides a semiconductor device, which includes a first signal line 141, a second signal line 151, a first stop layer 18, and a first transistor.

[0197] The first signal line 141 is located on one side of the substrate 11, and the first signal line 141 includes a first source and drain.

[0198] The second signal line 151 is located on the side of the first signal line 141 away from the substrate 11 and is insulated from the first signal line 141. The second signal line 151 includes a second source and drain.

[0199] The first stop layer 18 is located on the side of the second signal line 151 away from the substrate 11.

[0200] The first transistor includes a first semiconductor layer 121, a first gate insulating layer 122, and a first gate structure 123. The first semiconductor layer 121, the first gate insulating layer 122, and the first gate structure 123 sequentially cover and fill a first hole 30. The first hole 30 penetrates the first stop layer 18 and the second signal line 151 and stops at the first signal line 141. The first hole 30 is stepped and includes a first hole segment and a second hole segment that are sequentially away from the substrate 11. The diameter of the second hole segment is larger than the diameter of the first hole segment. The first gate structure 123 includes a first gate 123a located in the first hole segment and a first connection electrode 123b located in the second hole segment. The first semiconductor layer 121, the first gate insulating layer 122, the first gate structure 123, and the first stop layer 18 are all flush with the side away from the substrate 11.

[0201] In other words, the first gate 123a extends along a first direction perpendicular to the substrate 11; the first gate insulating layer 122 surrounds the outer periphery and bottom of the first gate 123a; and the first semiconductor layer 121 surrounds the outer periphery and bottom of the first gate insulating layer 122. In this embodiment, the first transistor adopts a ring channel structure, which simplifies the fabrication process and reduces the manufacturing difficulty.

[0202] In some embodiments, the first signal line 141 may be a first bit line. Multiple first bit lines extend along a third direction parallel to the substrate 11 and are arranged along a second direction; the first semiconductor layer 121 of the first transistor of each column of memory cells is electrically connected to a first bit line.

[0203] In some embodiments, the second signal line 151 may be a first word line. Multiple first word lines extend along a second direction parallel to the substrate 11 and are arranged along a third direction; the first semiconductor layer 121 of the first transistor of each memory cell in each row is electrically connected to a first word line.

[0204] The third direction and the second direction are at a 90-degree angle or other angles, which is not specifically limited in this application.

[0205] Optionally, the semiconductor device may also include a first planarization layer 21 and a third signal line 161.

[0206] The first planarization layer 21 is located on the side of the first connection electrode 123b away from the substrate 11. The first planarization layer 21 includes a second hole 31 that penetrates the first planarization layer 21 and exposes the connection portion 142. The connection portion 142 and the first signal line 141 belong to the same signal line layer.

[0207] The third signal line 161 is located on the side of the first planarization layer 21 away from the substrate 11. The third signal line 161 includes a conductive post 162 that fills the second hole 31 and is electrically connected to the connection portion 142, and a third source / drain electrode that is parallel to the substrate 11.

[0208] Optionally, the semiconductor device may also include a second stop layer and a second transistor.

[0209] The second stop layer is located on the side of the third signal line 161 away from the substrate 11.

[0210] The second transistor includes a second semiconductor layer 131, a second gate insulating layer 132, and a second gate structure 133. The second semiconductor layer 131, the second gate insulating layer 132, and the second gate structure 133 sequentially cover and fill a third hole. The third hole penetrates the second stop layer, the third signal line 161, and the first planarization layer 21, and stops at the first connection electrode 123b. The third hole is stepped and includes a third hole segment and a fourth hole segment that are sequentially away from the substrate 11. The diameter of the fourth hole segment is larger than the diameter of the third hole segment. The second gate structure 133 includes a second gate 133a located in the third hole segment and a second connection electrode 133b located in the fourth hole segment. The second semiconductor layer 131, the second gate insulating layer 132, the second gate structure 133, and the second stop layer are all flush with the side away from the substrate 11.

[0211] In other words, the second gate 133a extends along a first direction perpendicular to the substrate 11. The second gate insulating layer 132 surrounds the outer periphery and bottom of the second gate 133a. The second semiconductor layer 131 surrounds the outer periphery and bottom of the second gate insulating layer 132 and is electrically connected to the first gate 123a via the first connection electrode 123b.

[0212] Optionally, the first semiconductor layer 121 can be a metal oxide semiconductor layer.

[0213] In some embodiments, the material of the first semiconductor layer 121 may be indium gallium zinc oxide (IGZO). Due to the large bandgap (Eg) of IGZO, leakage current of the first transistor can be reduced, and the hold time can be increased.

[0214] In some embodiments, the material of the first semiconductor layer 121 may further comprise one or more of the following: indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), and indium tungsten oxide (InWO4). Materials include IWO, titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), etc. The specific materials can be adjusted according to the actual situation.

[0215] Furthermore, the materials of the second semiconductor layer 131 and the first semiconductor layer 121 are similar, and will not be described in detail here.

[0216] In some embodiments, the materials of the first planarization layer 21, the second planarization layer 22, and each dielectric layer may include oxides, the substrate 11 may be a silicon substrate 11, each signal line layer and each signal line may be a metal layer (e.g., titanium nitride), the materials of the first gate structure 123 and the second gate structure 133 may include indium zinc oxide, and the materials of the first gate insulating layer 122 and the second gate insulating layer 132 may be high-K materials.

[0217] Optionally, in some embodiments, the first stop layer 18 includes an oxide layer or a polysilicon layer.

[0218] This embodiment is an embodiment of the memory corresponding to the aforementioned semiconductor device embodiment. Specific technical details and effects can be referred to each other, and will not be repeated here.

[0219] Based on the same inventive concept, embodiments of this application provide an electronic device, including: a semiconductor device as provided in the above embodiments.

[0220] In this embodiment, since the electronic device uses any of the semiconductor devices provided in the foregoing embodiments, the principle and technical effects are described in the foregoing embodiments and will not be repeated here.

[0221] Optionally, the electronic device may include a storage device, a smartphone, a computer, a tablet computer, artificial intelligence, a wearable device, or a smart mobile terminal.

[0222] It should be noted that the electronic devices are not limited to the above-mentioned types. Those skilled in the art can set any of the semiconductor devices provided in the above embodiments of this application in different devices according to actual application needs, thereby obtaining the electronic devices provided in the embodiments of this application.

[0223] In the description of this application, the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate directions or positional relationships based on the exemplary directions or positional relationships shown in the accompanying drawings. They are used to facilitate the description or simplification of the embodiments of this application and are not intended to indicate or imply that the device or component referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0224] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0225] The above description is only a partial implementation of this application. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this application, without departing from the technical concept of this application, also fall within the protection scope of the embodiments of this application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: A first signal line is fabricated on one side of the substrate; A first dielectric layer, a second signal line, and a first stop layer are sequentially manufactured to cover the first signal line; the orthographic projections of the first signal line and the second signal line on the substrate intersect and are both parallel to the substrate; A first hole is formed that penetrates the first stop layer, the second signal line, and the first dielectric layer. The first hole stops at the first signal line. The first hole is stepped and includes a first hole segment and a second hole segment that move away from the substrate in sequence. The diameter of the second hole segment is larger than the diameter of the first hole segment. A first semiconductor layer, a first gate insulating layer, and a first gate structure are formed to conformally cover and fill the first hole, thereby obtaining a first transistor; the first gate structure includes a first gate located in the first hole segment and a first connection electrode located in the second hole segment.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Forming a first via penetrating the first stop layer, the second signal line, and the first dielectric layer includes: A first initial protective layer and a second initial protective layer are sequentially formed on the side of the first stop layer away from the substrate; The second initial protective layer is patterned to obtain a fourth hole and an intermediate protective layer; the orthographic projection of the inner wall of the fourth hole on the substrate overlaps with the orthographic projection of the inner wall of the first hole segment on the substrate. The intermediate protective layer and the first initial protective layer are patterned to obtain a fifth hole, a second protective layer, and a first protective layer; the fifth hole is stepped and includes a fifth hole segment located in the first protective layer and a sixth hole segment located in the second protective layer; the orthographic projection of the inner wall of the fifth hole segment on the substrate overlaps with the orthographic projection of the inner wall of the first hole segment on the substrate; the orthographic projection of the inner wall of the sixth hole segment on the substrate overlaps with the orthographic projection of the inner wall of the second hole segment on the substrate. Using the second protective layer and the first protective layer as masks, an etching process is performed to obtain the first hole.

3. The method for manufacturing a semiconductor device according to claim 1, characterized in that, A first semiconductor layer, a first gate insulating layer, and a first gate structure are formed to conformally cover and fill the first hole, thereby obtaining a first transistor, comprising: An initial first semiconductor layer, an initial first gate insulating layer, and an initial first gate layer are sequentially formed to conformally cover and fill the first hole and cover the first stop layer; The initial first gate layer, the initial first gate insulating layer, and the initial first semiconductor layer are subjected to chemical mechanical polishing until the first stop layer is exposed, thereby obtaining the first transistor and its first semiconductor layer, first gate insulating layer, and first gate structure.

4. The method for manufacturing a semiconductor device according to claim 1, characterized in that, After forming a first semiconductor layer, a first gate insulating layer, and a first gate structure that conformally cover and fill the first hole to obtain a first transistor, the process further includes: A first planar layer is formed on the side of the first connecting electrode away from the substrate; A second hole is formed that penetrates the first planarization layer and exposes the connection portion; the connection portion and the first signal line belong to the same signal line layer; A third signal line layer is formed on the side of the first planarization layer away from the substrate; the third signal line layer includes conductive pillars that fill the second hole and are electrically connected to the connection portion.

5. The method for manufacturing a semiconductor device according to claim 4, characterized in that, After forming the third signal line layer on the side of the first planarization layer away from the substrate, the method further includes: The third signal line layer is patterned to obtain a third signal line; the third signal line includes a third source and drain. Manufacture a second stop layer covering the third signal line; A third hole is formed that penetrates the second stop layer, the third signal line, and the first planarization layer. The third hole stops at the first connection electrode. The third hole is stepped and includes a third hole segment and a fourth hole segment that move away from the substrate in sequence. The diameter of the fourth hole segment is larger than the diameter of the third hole segment. A second semiconductor layer, a second gate insulating layer, and a second gate structure are formed to conformally cover and fill the third hole, thereby obtaining a second transistor; the second gate structure includes a second gate located in the third hole segment and a second connection electrode located in the fourth hole segment.

6. The method for manufacturing a semiconductor device according to claim 4, characterized in that, A first planarization layer is formed on the side of the first connection electrode away from the substrate, comprising: A first mask layer is formed on the side of the first semiconductor layer, the first gate insulating layer, and the first connection electrode away from the substrate; Using the first mask layer as a mask, the first stop layer is removed, and the exposed first semiconductor layer is removed by lateral etching to obtain a bottom groove; A first planar layer is formed that fills the bottom groove and covers the side of the first mask layer away from the substrate.

7. A semiconductor device, characterized in that, include: The first signal line is located on one side of the substrate and includes the first source and drain electrodes; The second signal line is located on the side of the first signal line away from the substrate and is insulated from the first signal line, and includes a second source and drain electrode; The first stop layer is located on the side of the second signal line away from the substrate; A first transistor includes a first semiconductor layer, a first gate insulating layer, and a first gate structure. The first semiconductor layer, the first gate insulating layer, and the first gate structure sequentially conformally cover and fill a first hole. The first hole penetrates the first stop layer and the second signal line and stops at the first signal line. The first hole is stepped and includes a first hole segment and a second hole segment that are sequentially away from the substrate. The diameter of the second hole segment is larger than the diameter of the first hole segment. The first gate structure includes a first gate located in the first hole segment and a first connection electrode located in the second hole segment. The first semiconductor layer, the first gate insulating layer, the first gate structure, and the first stop layer are all flush with the side away from the substrate.

8. The semiconductor device according to claim 7, characterized in that, Also includes: A first planarization layer is located on the side of the first connection electrode away from the substrate, and includes a second hole that penetrates the first planarization layer and exposes the connection portion, wherein the connection portion and the first signal line belong to the same signal line layer; The third signal line is located on the side of the first planarization layer away from the substrate, and includes a conductive pillar filled in the second hole and electrically connected to the connection portion, and a third source / drain electrode parallel to the substrate.

9. The semiconductor device according to claim 8, characterized in that, Also includes: The second stop layer is located on the side of the third signal line away from the substrate; The second transistor includes a second semiconductor layer, a second gate insulating layer, and a second gate structure. The second semiconductor layer, the second gate insulating layer, and the second gate structure sequentially conformally cover and fill a third hole. The third hole penetrates the second stop layer, the third signal line, and the first planarization layer, and terminates at the first connection electrode. The third hole is stepped and includes a third hole segment and a fourth hole segment that are sequentially away from the substrate. The diameter of the fourth hole segment is larger than the diameter of the third hole segment. The second gate structure includes a second gate located in the third hole segment and a second connection electrode located in the fourth hole segment. The second semiconductor layer, the second gate insulating layer, the second gate structure, and the second stop layer are all flush with the side away from the substrate.

10. The semiconductor device according to claim 7, characterized in that, It also includes at least one of the following: The first semiconductor layer is a metal oxide semiconductor layer; The first stop layer includes an oxide layer or a polysilicon layer.

11. An electronic device, characterized in that, include: The semiconductor device as described in any one of claims 7 to 10.

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