Semiconductor device and method of manufacturing the same, electronic device

Abstract

The present disclosure provides a semiconductor device and a manufacturing method thereof, and an electronic device, the semiconductor device including: memory cell layers stacked along a first direction, each memory cell layer including a plurality of memory cells arranged in an array; each memory cell including a transistor; the transistor including: a gate electrode extending along a second direction, and a semiconductor layer penetrating the gate electrode along a third direction and surrounded by the gate electrode, the third direction intersecting the second direction and both being perpendicular to the first direction; and the gate electrodes of the plurality of memory cells arranged along the second direction being connected to each other.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to semiconductor devices and their manufacturing methods, and electronic devices. Background Technology

[0002] The development of application markets such as the Internet of Things (IoT), artificial intelligence (AI), and smart cities has significantly increased the application demand for massive computing architectures. Massive computing architectures process massive amounts of data, placing higher demands on memory performance. Among mainstream memory technologies, Dynamic Random Access Memory (DRAM) is characterized by its high speed and ability to be read and written at any time, making it suitable for storing frequently accessed data or data being processed. The development of big data has placed even higher demands on DRAM. 3D DRAM can increase the storage capacity of DRAM and is a major direction for the future development of DRAM. Summary of the Invention

[0003] According to a first aspect of this disclosure, a semiconductor device is provided, the semiconductor device comprising:

[0004] A stacked layer of memory cells along a first direction, each of the memory cell layers comprising a plurality of memory cells arranged in an array; each of the memory cells comprising a transistor;

[0005] The transistor includes a gate and a semiconductor layer, the gate extending along a second direction, the semiconductor layer penetrating the gate and surrounding the gate along a third direction, the third direction intersecting the second direction and being perpendicular to the first direction; and the gates of a plurality of memory cells arranged along the second direction are connected to each other.

[0006] According to a second aspect of this disclosure, a method for manufacturing a semiconductor device is provided, the method comprising:

[0007] A stacked structure is formed on a substrate, the stacked structure comprising a plurality of interlayer dielectric layers and a plurality of sacrificial layers alternately stacked along a first direction perpendicular to the substrate;

[0008] A plurality of gates are formed in the sacrificial layer, extending along a second direction parallel to the substrate and interconnected with each other;

[0009] A plurality of semiconductor layers are formed in the plurality of gates, extending through the gates along a third direction and surrounded by the gates, the plurality of semiconductor layers being spaced apart along the second direction; the third direction intersects the second direction and is parallel to the substrate.

[0010] According to a third aspect of this disclosure, an electronic device is provided, comprising: a semiconductor device as described in any of the first aspects of this disclosure, and / or a semiconductor device manufactured by a manufacturing method as described in any of the second aspects of this disclosure.

[0011] The semiconductor device provided in this disclosure includes multiple memory cell layers stacked along a first direction. Each memory cell layer includes multiple memory cells arranged in an array, forming a three-dimensional memory cell array. This increases the number of memory cells per unit area, thereby improving the storage density of the semiconductor device. In each memory cell layer, each memory cell includes a transistor. The transistor includes a gate and a semiconductor layer. The gate extends along a second direction, and the gates of the multiple memory cells arranged along the second direction are coupled to each other to form a horizontal word line. The semiconductor layer passes through the gate along a third direction and is surrounded by the gate. The gate is located on two opposing surfaces of the semiconductor layer along the first direction and two opposing surfaces of the semiconductor layer along the second direction. The gate is located on four surfaces of the semiconductor layer, which is equivalent to each transistor having four channels, thereby effectively increasing the on-state current of the transistor and improving the strength of the read / write signals. Furthermore, the gate surrounds the channels, improving the gate's control over the channels and increasing the switching speed of the transistor, thereby improving the read / write speed of the memory cell.

[0012] Furthermore, two adjacent semiconductor layers along the second direction are isolated by a gate. This prevents electrons from transferring between adjacent semiconductor layers, reducing parasitic transistor effects between transistors in adjacent memory cells. This reduces coupling between adjacent memory cells, improving data retention time, read / write performance, and storage reliability. Additionally, the gate surrounds the semiconductor layers, creating a gate between the semiconductor layer of the memory cell and adjacent memory cells in the first direction. The gate provides shielding, reducing the coupling of the selected memory cell's gate to the semiconductor layer of the adjacent non-selected memory cells in the first direction (i.e., vertically). Attached Figure Description

[0013] Figure 1 This is a three-dimensional schematic diagram of a semiconductor device provided in an embodiment of this disclosure.

[0014] Figures 2a to 2f for Figure 1 The diagram shows multiple cross-sectional views of the semiconductor device.

[0015] Figure 3 This is a three-dimensional schematic diagram of another semiconductor device provided in an embodiment of this disclosure.

[0016] Figures 4a to 4d for Figure 3 The diagram shows multiple cross-sectional views of the semiconductor device.

[0017] Figures 5a to 5cThese are schematic diagrams of multiple processes for manufacturing a semiconductor device according to embodiments of this disclosure.

[0018] Figures 6a to 18c This is a schematic diagram of the structure of a semiconductor device during the manufacturing process, provided as an embodiment of this disclosure.

[0019] Figures 19a to 22d This is a schematic diagram of the structure of another semiconductor device during the manufacturing process, provided as an embodiment of this disclosure. Detailed Implementation

[0020] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0021] Where possible, the same reference numerals will be used throughout the accompanying drawings to refer to the same or similar parts. It is obvious that the aspects described are only some, and not all, of the aspects of this disclosure. Features in the various aspects may be interchanged and / or combined.

[0022] In the description of this disclosure, it should be understood that the terms “length,” “width,” “depth,” “upper,” “lower,” “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0023] The widespread application and development of artificial intelligence technology has placed higher demands on memory storage density. 3D DRAM, by vertically stacking multiple memory cell layers, can achieve higher capacity per unit chip area, thereby increasing storage density. 3D DRAM can adopt a horizontal word line design, but currently, the horizontal word line design still faces problems such as parasitic transistor effects between transistors in memory cells on the same word line, small on-state current of transistors within memory cells, and pass-gate effect (PGE) between memory cells on adjacent word lines.

[0024] This disclosure provides a semiconductor device comprising: a memory cell layer 130 stacked along a first direction, each memory cell layer 130 including a plurality of memory cells arranged in an array; each memory cell including: a transistor and a capacitor; the transistor including: a gate 210 and a semiconductor layer 220, the gate 210 extending along a second direction D2, the semiconductor layer 220 penetrating through the gate 210 and surrounding the gate 210 along a third direction D3, the third direction D3 intersecting the second direction D2 and both perpendicular to the first direction D1; and the gates 210 of the plurality of memory cells arranged along the second direction D2 being interconnected. A capacitor is located on one of the opposite sides of the semiconductor layer 220 along the third direction D3, and a first electrode 310 of the capacitor is coupled to the semiconductor layer 220. A bit line 410 is located on the other side of the opposite sides of the semiconductor layer 220 along the third direction, the bit line 410 extending along the first direction D1 and coupled to the semiconductor layer 220 of the plurality of memory cells.

[0025] For example, in this disclosure, "connection" refers to a direct connection, including physical contact or the two being integral. "Coupling" means that the two can be directly or indirectly connected.

[0026] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure. Figure 2a , Figure 2b , Figure 2c , Figure 2d , Figure 2e and Figure 2f The following are shown in sequence Figure 1 The diagram shows a cross-sectional view of the semiconductor device along lines aa′, bb′, cc′, dd′, ee′, and ff′. See also... Figures 1 to 2f The semiconductor device includes a substrate 110, and an interlayer dielectric layer 512 and a memory cell layer 130 alternately stacked on the substrate 110 along a first direction D1. The first direction D1 is perpendicular to the substrate 110. For example, the substrate 110 extends in a horizontal direction, and the first direction may be a vertical direction.

[0027] In the memory cell layer 130, a plurality of memory cells are arranged in an array along intersecting second direction D2 and third direction D3. Both the second direction and the third direction are parallel to the substrate. The intersection of the second direction and the third direction includes the second direction and the third direction being perpendicular to each other. This embodiment of the present disclosure is described with the second direction and the third direction being perpendicular as an example. Each memory cell includes a transistor and a capacitor, and the transistor and the capacitor are arranged along the third direction D3. The transistor includes a gate 210, a semiconductor layer 220, and a gate dielectric layer 230 located between the gate and the semiconductor layer. The gate 210 extends along the second direction D2, wherein the gates 210 of the plurality of memory cells arranged along the second direction are connected to each other to form a word line extending along the second direction. It can be understood that the plurality of memory cells in the second direction are coupled to the same word line.

[0028] like Figure 2a and Figure 2f As shown, the semiconductor layer 220 penetrates and surrounds the gate 210 along a third direction. Specifically, the gate 210 is located on two opposing surfaces of the semiconductor layer 220 along the first direction D1 and two opposing surfaces along the second direction D2. The gate 210 is located on four surfaces of the semiconductor layer 220, which is equivalent to each transistor having four channels, effectively increasing the transistor's on-state current and improving the strength of read / write signals. Furthermore, the gate surrounding the channels enhances the gate's control over the channels, increasing the transistor's switching speed and thus improving the read / write speed of the memory cell.

[0029] The capacitor includes a first electrode 310, a second electrode 320, and a dielectric layer 330 located between the first electrode 310 and the second electrode 320. The first electrode 310 is coupled to a first side of the semiconductor layer 220 opposite to each other along a third direction D3. The bit line 410 is coupled to a second side of the semiconductor layer 220 opposite to each other along a third direction D3. When a turn-on voltage higher than the threshold voltage of the transistor is applied to the word line, electrons in the first electrode 310 enter the bit line 410 through the semiconductor layer 220, or electrons in the bit line 410 pass through the semiconductor layer 220 to the first electrode 310.

[0030] See Figure 2cTwo adjacent semiconductor layers 220 along the second direction D2 are isolated by a gate 210. This prevents electron transfer between adjacent semiconductor layers, reducing parasitic transistor effects between transistors in adjacent memory cells, thereby reducing coupling between adjacent memory cells and improving data retention time, read / write performance, and storage reliability. Furthermore, the semiconductor layer 220 in this embodiment has a channel width along the third direction D3. The distance between semiconductor layers of adjacent memory cells arranged along the second direction D2 does not affect the channel width. This allows the semiconductor device of this disclosure to reduce parasitic transistor effects between memory cells coupled to the same word line while ensuring a larger channel width in the semiconductor layer to increase the on-state current of the transistors, thereby increasing read signal strength, accelerating write speed, and improving the read / write performance of the semiconductor device.

[0031] Furthermore, the gate surrounds the semiconductor layer, ensuring that adjacent semiconductor layers in the first direction D1 have a gate. The gate provides shielding, reducing the coupling effect of the selected word line on the semiconductor layers of adjacent unselected memory cells in the first direction (i.e., vertically). For example, if the semiconductor layer is located outside the gate, the structure between the selected word line and the semiconductor layers of the unselected memory cells on the upper and lower sides includes the semiconductor layer of the selected memory cell and the interlayer dielectric layer. The voltage on the selected word line might affect the semiconductor layers of the unselected memory cells, causing changes in the threshold voltage of the unselected memory cells that could lead to data loss. In this application, the gate provides shielding, reducing the impact of the selected word line on adjacent semiconductor layers and improving the reliability of data storage.

[0032] In some embodiments, such as Figure 2c As shown, the gate 210 includes: a first gate portion 211, a second gate portion 212, a third gate portion 213, and a fourth gate portion 214; the first gate portion 211 and the second gate portion 212 are respectively located on opposite sides of the semiconductor layer 220 along the first direction D1, and the third gate portion 213 and the fourth gate portion 214 are respectively located on opposite sides of the semiconductor layer 220 along the second direction D2; wherein, each of the third gate portion 213 and the fourth gate portion 214 is connected to the first gate portion 211 and the second gate portion 212; the first gate portions 211 of the plurality of memory cells arranged along the second direction are connected to each other, and the second gate portions 212 of the plurality of memory cells are connected to each other.

[0033] Along the second direction D2, the first gate portions 211 of multiple memory cells are connected to each other, forming a first sub-word line extending along the second direction D2 above the semiconductor layer 220. The second gate portions 212 of multiple memory cells are connected, forming a second sub-word line extending along the second direction below the semiconductor layer. The first and second sub-word lines form a horizontal word line, which can control the opening of a row of memory cells. A third gate portion 213 is located between and connected to the first gate portion 211 and the second gate portion 212, and a fourth gate portion 214 is located between and connected to the first gate portion 211 and the second gate portion 212. The third gate portion 213 and the fourth gate portion 214 further increase the overlap area between the gate 210 and the semiconductor layer 220, which can improve the control capability of the channel.

[0034] In some embodiments, in two adjacent memory cells along the second direction D2, the third gate portion 213 of one memory cell is in contact with the fourth gate portion 214 of the other memory cell.

[0035] like Figure 2c As shown, in two adjacent memory cells along the second direction, there is no gap or heterogeneous material between the third gate portion 213 of one memory cell and the fourth gate portion 214 of the other memory cell, making them connected without any gap. It should be noted that this embodiment divides the gates into four gate portions for clearer description of their positions; in reality, as shown... Figure 2c As shown, the components of the gates of the memory cells are synchronized, so there is no obvious interface or no interface between the four gate portions. Furthermore, the gate components of adjacent memory cells are the same, so there is no obvious interface or no interface between the third gate portion 213 and the fourth gate portion 214 of adjacent memory cells, and there is no obvious interface or no interface between the first gate portion 211 and the second gate portion 212 of adjacent memory cells.

[0036] In the gate provided in this embodiment, the third gate portion 213 and the fourth gate portion 214 of adjacent memory cells are in direct contact to form a large conductive block, which can reduce the resistance of the word line, shorten the boost time of the word line, meet the circuit's requirements for word line timing, improve programming or reading speed, and also reduce power consumption.

[0037] Figure 3 This is a schematic diagram of the structure of another semiconductor device provided in the disclosed embodiments. Figure 4a , Figure 4b , Figure 4c and Figure 4d The following are shown in sequence Figure 3 The diagram shows a cross-sectional view of the semiconductor device along lines gg′, hh′, cc′, and ff′.

[0038] In some embodiments, such as Figure 3 , Figures 4a to 4d As shown, in two adjacent memory cells along the second direction, a separation structure 250 is provided between the third gate portion 213 of one memory cell and the fourth gate portion 214 of the other memory cell. The material of the separation structure 250 is different from the material of the gate 210.

[0039] For example, the material of the separator 250 can be a conductive material or an insulating material. In this embodiment, the material of the separator 250 is amorphous silicon or polycrystalline silicon.

[0040] and Figures 1 to 2f Similar to the gate 210 shown, in this embodiment, the first gate portions 211 of the plurality of memory cells arranged along the second direction D2 are connected to each other, and the second gate portions 212 of the plurality of memory cells are connected to each other. For example, the gates 210 of the plurality of memory cells arranged along the second direction D2 are integral. That is, the first gate portion 211, second gate portion 212, third gate portion 213, and fourth gate portion 214 of each memory cell are integral, and are integral with the gates of the other plurality of memory cells. In other words, the gates of the plurality of memory cells are deposited in a single deposition step.

[0041] also, Figure 3 The semiconductor device shown is Figure 1 The semiconductor devices described herein have substantially the same semiconductor layers, bit lines, and capacitors. These will be discussed together later in this document. Figure 1 and Figure 3 The semiconductor layer, bit line, and capacitor of the semiconductor device are described.

[0042] In some embodiments, such as Figure 2a , Figure 2f , Figure 4c and Figure 4d As shown, the semiconductor layer 220 includes: a top sidewall 221 and a bottom sidewall 222 opposite to each other along a first direction D1, a first sidewall 223 and a second sidewall 224 opposite to each other along a third direction D3, and a third sidewall 225 and a fourth sidewall 226 opposite to each other along a second direction D2; wherein each of the first sidewall 223, the second sidewall 224, the third sidewall 225 and the fourth sidewall 226 is connected to the top sidewall 221 and the bottom sidewall 222.

[0043] The semiconductor layer 220 is generally a hollow cuboid structure, including six sidewalls. It should be noted that each sidewall can be a planar sidewall or a curved sidewall. In this embodiment, as shown... Figure 2a and 2fAs shown, the top sidewall 221 and bottom sidewall 222 of the semiconductor layer 220 are both planar sidewalls, the first sidewall 223 and second sidewall 224 are generally planar sidewalls, and the third sidewall 225 and fourth sidewall 226 are both arcuate sidewalls. The first gate portion 211 of the gate 210 is located on the surface of the top sidewall 221 of the semiconductor layer, the second gate portion 212 is located on the surface of the bottom sidewall 222, the third gate portion 213 is located on the surface of the third sidewall 225, and the fourth gate portion 214 is located on the surface of the fourth sidewall 226. For example, the first gate portion 211, the second gate portion 212, the third gate portion 213, and the fourth gate portion 214 each cover the corresponding sidewall of the semiconductor layer 220. The first electrode 310 of the capacitor is coupled to the first sidewall 223 of the semiconductor layer, and the bit line 410 is coupled to the second sidewall 224.

[0044] The first sidewall 223, top sidewall 221, second sidewall 224, and bottom sidewall 222 are connected sequentially, forming a first channel in the first sidewall 223, top sidewall 221, and second sidewall 224, and a second channel in the first sidewall 223, bottom sidewall 222, and second sidewall 224. Furthermore, the third sidewall 225 is connected to the top sidewall 221 and bottom sidewall 222, forming a third channel that sequentially passes through the first sidewall 223, top sidewall 221 / bottom sidewall 222, third sidewall 225, top sidewall 221 / bottom sidewall 222, and second sidewall 224. The fourth sidewall 226 is connected to the top sidewall 221 and the bottom sidewall 222, forming a fourth channel that passes sequentially through the first sidewall 223, the top sidewall 221 / bottom sidewall 222, the fourth sidewall 226, the top sidewall 221 / bottom sidewall 222, and the second sidewall 224. When the transistor is turned on, the four channels can increase the transistor's on-state current, improve the read / write signal strength and read / write speed, and thus improve memory performance.

[0045] For example, the first sidewall 223, the second sidewall 224, the third sidewall 225, and the fourth sidewall 226 are spaced apart from each other. In other embodiments, the first sidewall 223, the second sidewall 224, the third sidewall 225, and the fourth sidewall 226 may also be connected to each other.

[0046] For example, the top sidewall 221, bottom sidewall 222, first sidewall 223, second sidewall 224, third sidewall 225 and fourth sidewall 226 of the semiconductor layer are integral and are deposited in one step in the same deposition process.

[0047] In some embodiments, such as Figure 2a , Figure 2f , Figure 4c and Figure 4dAs shown, the semiconductor device also includes multiple support structures 240; each support structure 240 is surrounded by a first sidewall 223, a second sidewall 224, a third sidewall 225, a fourth sidewall 226, a top sidewall 221, and a bottom sidewall 222 of a semiconductor layer. That is, the support structures 240 fill the interior of the semiconductor layer 220 to support the semiconductor layer 220.

[0048] For example, the material of the support structure 240 is an insulating material, which includes, but is not limited to, inorganic insulating materials such as silicon oxide and silicon nitride, as well as organic insulating materials. In this embodiment, the material of the support structure is silicon oxide.

[0049] In some embodiments, the first electrode 310 of the capacitor is in contact with the semiconductor layer 220. Specifically, the first electrode 310 is in contact with the surface of the first sidewall 223 of the semiconductor layer 220. Thus, no first source / drain layer is provided between the first electrode 310 and the semiconductor layer 220, which reduces the area occupied by the memory cell and facilitates the miniaturization of the semiconductor device. In another embodiment, a first source / drain layer may also be provided between the first electrode 310 and the semiconductor layer 220.

[0050] In some embodiments, such as Figure 2a , Figure 2f , Figure 4a and Figure 4d As shown, the first electrode 310 of the capacitor is a hollow structure with one side open. The bottom wall of the hollow structure opposite to the opening is in contact with the semiconductor layer. The sidewall of the hollow structure extends along the third direction D3 and includes a first segment 311 and a second segment 312 connected to each other. The first segment 311 is located between the semiconductor layer 220 and the second segment 312. The spacing of the first segment 311 along the first direction D1 is smaller than the spacing of the second segment 312 along the first direction D1.

[0051] The first electrode 310 is a hollow structure with steps, wherein the spacing of the first segment 311 along the first direction is smaller than that of the second segment 312. This can avoid the gate 210, increase the distance between the first electrode 310 and the gate 210 (the first gate portion 211 and the second gate portion 212), and improve the isolation performance between the two.

[0052] For example, the second segment 312 of the first electrode 310 has an annular cross-section perpendicular to a third direction, and the outer contour of the annulus is rectangular. For example, the first segment 311 and the second segment 312 have the same wall thickness, and the first segment 311 and the second segment 312 of the first electrode can be integral, formed by deposition in the same deposition step. The hollow structure of the first electrode 310 provided in this embodiment has a large area, which can improve the capacitance of the capacitor, and is beneficial for extending the data retention time, read signal strength and anti-interference capability.

[0053] In some embodiments, the second electrode 320 of the capacitor is located on the side of the first electrode 310 away from the semiconductor layer 220, the second electrode 320 extends into the hollow structure from the opening of the first electrode 310, and the capacitor dielectric layer 330 is located between the first electrode 310 and the second electrode 320.

[0054] In some embodiments, such as Figure 2f and Figure 4d As shown, the second electrode 320 also extends into at least a portion of the region between adjacent first electrodes 310 along the first direction D1, and the second electrodes 320 of the plurality of memory cells arranged along the first direction D1 are connected to each other.

[0055] like Figure 2f As shown, the second electrode 320 extends into a portion of the region between adjacent first electrodes 310 in the first direction to increase the distance between the second electrode and the gate 210, thereby improving the isolation performance between them. For example, the second electrode 320 extends into the region between second segments 312 of adjacent first electrodes 310, opposite a portion of the outer surface of the second segment 312. In other embodiments, the second electrode 320 may also be located in the entire region between adjacent first electrodes 310 in the first direction, wherein the capacitor dielectric layer 330 can isolate the second electrode 320 and the gate.

[0056] In this embodiment, the inner surface of the second electrode 320 is opposite to the inner surface of the first electrode 310, and is opposite to the outer surfaces of the two sidewalls of the first electrode 310 along the first direction. This increases the relative area between the second electrode 320 and the first electrode 310, which can improve the capacitance, thereby improving data retention time, enhancing read signal strength, and improving anti-interference capability, thus improving the reliability of the semiconductor device.

[0057] See also Figure 2f and Figure 4d The second electrodes 320 of the plurality of memory cells in the first direction are connected to each other. For example, the second electrodes 320 of the plurality of memory cells in the first direction are an integral structure, which are deposited in one step in the same deposition process.

[0058] In some embodiments, the second electrode 320 further extends into at least a portion of the region between adjacent first electrodes 310 along the second direction D2; wherein the second electrodes 320 of the plurality of memory cells arranged along the second direction D2 are connected to each other.

[0059] like Figure 2a and Figure 4a As shown, the second electrode 320 also extends into the second segment of the adjacent first electrode 310 along the second direction D2, opposite to the outer surfaces of the two sidewalls of the first electrode 310 along the second direction D2. Figure 2a and Figure 2fAs shown, in this embodiment, the second electrode 320 surrounds the outer surfaces of the four sidewalls of the second segment 312 of the first electrode 310, which further increases the relative area between the second electrode 320 and the first electrode 310, thereby improving the capacitance. For example, the second electrodes 320 of multiple memory cells arranged along the first direction are an integrated structure, and the second electrodes 320 of multiple memory cells arranged along the second direction are also an integrated structure.

[0060] In some embodiments, no second source / drain layer is provided between the bit line 410 and the semiconductor layer 220. Specifically, the surfaces of the bit line 410 and the second sidewall 224 of the semiconductor layer 220 are in contact with each other. This reduces the area occupied by the memory cell and facilitates the miniaturization of the semiconductor device. In another embodiment, a second source / drain layer may also be provided between the bit line 410 and the semiconductor layer 220.

[0061] In some embodiments, such as Figure 2f and Figure 4d The bit line 410 includes a bit line body 411 and a plurality of protrusions 412; the bit line body 411 passes through a plurality of interlayer dielectric layers 512 and a plurality of memory cell layers 130 along a first direction D1; each protrusion 412 is located on one side of the bit line body 411 along a third direction and extends into a memory cell layer, and the protrusion 412 is in contact with the semiconductor layer 220.

[0062] When a bit line is selected, and current is transferred between a memory cell in the first direction and the bit line 410, most of the current flows within the bit line body 411. Because the bit line body 411 is far from the word line (gate 210), the coupling between it and unselected word lines is reduced, minimizing the impact on unselected memory cells and improving data storage reliability. In other embodiments, the bit line 410 can also be in other forms; for example, the bit line 410 can be a columnar structure extending along the first direction.

[0063] In some embodiments, the semiconductor layer 220 is made of metal oxide semiconductor. Metal oxide semiconductors include, but are not limited to, IGZO (indium gallium zinc oxide), ITO (indium tin oxide), and ITZO (indium tin zinc oxide). Transistors using metal oxide semiconductors as the semiconductor layer have lower leakage current, longer data retention time, and improved data storage performance.

[0064] In addition, in other embodiments, the material of the semiconductor layer can also be an undoped intrinsic semiconductor such as silicon, germanium, or silicon-germanium, or a doped semiconductor such as silicon-doped, germanium-doped, or silicon-germanium-doped, which is uniformly doped in all areas, or other semiconductor materials such as gallium arsenide.

[0065] This disclosure also provides a method for manufacturing a semiconductor device, such as... Figure 5aAs shown, the method for manufacturing a semiconductor device includes:

[0066] S100: A stacked structure is formed on a substrate, the stacked structure including a plurality of interlayer dielectric layers spaced apart along a first direction perpendicular to the substrate;

[0067] S200: A plurality of gates are formed between adjacent interlayer dielectric layers, extending in a second direction parallel to the substrate and interconnected with each other;

[0068] S300: A plurality of semiconductor layers are formed in a plurality of gates, extending through the gates along a third direction and surrounded by the gates, the plurality of semiconductor layers being spaced apart along a second direction; the third direction intersects the second direction and is parallel to the substrate.

[0069] The semiconductor device manufacturing method provided in this embodiment forms a plurality of gates extending along a second direction. These gates are arranged along the second direction and interconnected to form horizontal word lines. A semiconductor layer passes through the gates along a third direction and is surrounded by the gates. The gates are located on two opposing surfaces of the semiconductor layer along a first direction and two opposing surfaces along the second direction. The gates are located on four surfaces of the semiconductor layer, which is equivalent to each transistor having four channels, thereby effectively increasing the on-state current of the transistor and improving the strength of the read / write signals. Furthermore, the gates surrounding the channels improve the gates' control over the channels, increasing the switching speed of the transistors and thus improving the read / write speed of the memory cells. Moreover, two adjacent semiconductor layers along the second direction are isolated by the gates. This prevents electrons in adjacent semiconductor layers from transferring to each other, reducing parasitic transistor effects between transistors in adjacent memory cells, thereby reducing coupling between adjacent memory cells and improving data retention time, read / write performance, and storage reliability. Additionally, the gates surrounding the semiconductor layers ensure that there are gates between adjacent semiconductor layers in the first direction. The gates can provide shielding, reducing the coupling of the selected word line to the channel layer semiconductor layer of the adjacent unselected memory cell in the first direction (i.e., vertically).

[0070] In some embodiments, such as Figure 5b As shown, the manufacturing method also includes:

[0071] S400: On the first side of multiple gates along a third direction, multiple bit lines are formed that pass through the stacked structure in a first direction and are arranged in a second direction;

[0072] S500: On the second side of the multiple gates along the third direction, a plurality of first electrodes are formed in the sacrificial layer arranged along the second direction; the first electrodes are opposite to the bit lines.

[0073] In some embodiments, such as Figure 5c As shown, step S300 may include:

[0074] S310: A dummy structure is formed that penetrates the gate along a third direction and is surrounded by the gate; the dummy structure is parallel to and in contact with the bit line and the first electrode along a third direction;

[0075] S320: A release hole is formed between each adjacent bit line and / or each adjacent first electrode, the release hole revealing a dummy structure;

[0076] S330: Based on the release hole, the dummy structure is removed to form the first cavity;

[0077] S340: A semiconductor layer is formed on the surface of the first cavity based on the release hole.

[0078] The semiconductor device manufacturing method provided in this embodiment uses a dummy structure to reserve space for the semiconductor layer. The dummy structure is removed only after the bit lines and the first electrode of the capacitor are formed, and the semiconductor layer is formed within the first cavity created by removing the dummy structure. This manufacturing process avoids damage to the semiconductor layer caused by the solutions used in depositing and etching metal materials, as well as by high-temperature environments, thereby maintaining high quality of the semiconductor layer. This helps reduce leakage current in transistors and improves memory reliability.

[0079] Figures 6a to 18c This is a schematic diagram illustrating the structure of a semiconductor device during the manufacturing process, as provided in an embodiment of this disclosure. The following is in conjunction with… Figures 5a to 5c , Figures 6a to 18c The method for manufacturing a semiconductor device provided in the embodiments of this disclosure will be further described in detail.

[0080] Figures 6a to 9c The process of forming a gate connection structure is illustrated. In some embodiments, the step of forming the gate connection structure includes:

[0081] A plurality of first isolation structures are formed, passing through the stacked structure along a first direction and arranged along a second direction; a trench structure extending along the second direction is formed on one side of the plurality of first isolation structures along a third direction, and a conductive layer extending along the second direction is formed in each sacrificial layer between the first isolation trench structure and the trench structure; a plurality of first holes are formed in the trench structure, arranged along the second direction, and the first holes are staggered with the first isolation structures; the conductive layer is etched based on the plurality of first holes to narrow the conductive layer at multiple locations; a plurality of second holes are formed on the side of the conductive layer opposite to the first initial hole; the sacrificial layer and the conductive layer located between adjacent first isolation structures are etched based on the second holes to break the conductive layer at the narrowing point, thereby forming a plurality of gate connection structures.

[0082] Figures 6a to 9c A process for forming an initial stacked structure and multiple gate connection structures is illustrated below. Figures 6a to 9c The process of forming the initial stacked structure and multiple gate connection structures is described in detail.

[0083] See Figures 6a to 6g ,in, Figure 6b , Figure 6c , Figure 6d , Figure 6e , Figure 6f and Figure 6g The following are shown in sequence Figure 6a The diagram shows a cross-sectional view of the semiconductor device along lines aa′, bb′, cc′, dd′, ee′, and ff′.

[0084] like Figures 6a to 6g As shown, a stacked structure 510 is formed on a substrate 110. The stacked structure 510 includes an initial sacrificial layer 511 and an interlayer dielectric layer 512 that are alternately stacked along a first direction.

[0085] For example, substrate 110 may be made of silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), III-V compounds (e.g., GaN, GaAs, InAs, etc.) or any other suitable semiconductor material. The substrate may also be made of other materials. In this embodiment, substrate 110 is a silicon substrate.

[0086] There should be a certain etching selectivity between the initial sacrificial layer 511 and the interlayer dielectric layer 512, such that the interlayer dielectric layer 512 is not etched when the initial sacrificial layer 511 is etched, and the initial sacrificial layer 511 is not etched when the interlayer dielectric layer 512 is etched. Here and thereafter, "not etched" includes both complete non-etching and minimal etching within an acceptable range. Furthermore, in actual manufacturing, absolute non-etching is usually non-existent; as long as the material that is not allowed to be etched is etched very little without affecting reliability, it can be understood as not being etched. The initial sacrificial layer 511 can be selected from materials commonly used in the art. In this embodiment, the material of the initial sacrificial layer 511 is silicon nitride. The material of the interlayer dielectric layer 512 is an insulating material, which can be an inorganic insulating material such as silicon oxide or silicon nitride, or an organic insulating material. In this embodiment, the material of the interlayer dielectric layer 512 is silicon oxide. For example, the initial sacrificial layer 511 and the interlayer dielectric layer 512 can be formed using a plasma-enhanced chemical vapor deposition (PECVD) process.

[0087] In some embodiments, a protective layer 140 may be disposed between the bottommost interlayer dielectric layer 512 and the substrate 110. The protective layer 140 can serve as an etching stop layer during the etching of the stacked structure and can also protect the substrate surface. The protective layer 140 has a certain etching selectivity with both the initial sacrificial layer 511 and the interlayer dielectric layer 512. The protective layer 140 can be made of materials commonly used in the art. In this embodiment, the material of the protective layer is a silicon-germanium alloy (SiGe).

[0088] See also Figure 6a , 6b Formed by 6c and 6e, a plurality of first isolation structures 610 extend along the first direction D1 through the stacked structure, and the plurality of first isolation structures 610 are arranged along the second direction D2. For example, the first isolation structures 610 penetrate the stacked structure 510. The first isolation structures 610 have a large etching selectivity ratio with the initial sacrificial layer 511.

[0089] In some embodiments, the first isolation structure 610 includes an isolation body 612 and an isolation auxiliary layer 611 surrounding the isolation body 612. For example, the isolation body 612, the interlayer dielectric layer 512, and the initial sacrificial layer 511 all have a large etch selectivity, and the isolation auxiliary layer 611 may be made of the same material as the interlayer dielectric layer 512. In this embodiment, the material of the isolation body 612 is amorphous silicon or polycrystalline silicon, and the material of the isolation auxiliary layer 611 is silicon oxide.

[0090] For example, the step of forming the first isolation structure 610 may include: etching the stacked structure 510 to form a plurality of isolation trenches that penetrate the stacked structure 510 and are arranged along a second direction; forming an isolation auxiliary layer on the surface of the isolation trenches; filling the remaining area of ​​the isolation trenches with isolation body material, wherein a portion of the isolation body material is located on the top surface of the stacked structure; treating the isolation body material with a chemical mechanical polishing (CMP) process; and forming the remaining isolation body material located in the isolation trenches to form the isolation body 612.

[0091] See Figures 7a to 7c A trench 621 is formed on one of the first sides of the plurality of first isolation structures 610 opposite each other along the third direction D3. The trench 621 penetrates the stacked structure 510 along the first direction and extends along the second direction D2. Then, a plurality of initial sacrificial layers 511 are etched laterally based on the trench to form a plurality of second grooves 701 arranged along the first direction, wherein each second groove exposes a plurality of first isolation structures 610.

[0092] Lateral etching, as used here and thereafter, refers to etching along multiple directions parallel to the substrate. For example, a wet etching process can be used to etch the initial sacrificial layer 511 laterally.

[0093] Next, a conductive layer 710 is formed in each second groove 701, and the trench 621 is filled to form a trench structure 620.

[0094] For example, the steps of forming the conductive layer 710 and the trench structure 620 specifically include: filling each second groove 701 and trench 621 with conductive material; removing the conductive material in the trench 621, with the remaining conductive material in each second groove 701 forming a corresponding conductive layer 710; filling the trench 621 with trench structure material, wherein a portion of the trench structure material is located on the top surface of the stacked structure; and processing the trench structure material using a chemical mechanical polishing process, with the remaining trench structure material in the trench forming the trench structure 620.

[0095] For example, the material of the conductive layer 710 may include metals and metal nitrides. Metals include, but are not limited to, tungsten, copper, aluminum, gold, titanium, silver, cobalt, and nickel, while metal nitrides include, but are not limited to, titanium nitride and tungsten nitride. There is a large etching selectivity between the material of the trench structure 620 and the material of the conductive layer 710, and the material of the trench structure 620 can be any material commonly used in the art. In this embodiment, the material of the trench structure 620 is amorphous silicon or polycrystalline silicon.

[0096] See Figures 8a to 8c This forms a plurality of first holes 631 that pass through the trench structure 620 along a first direction and are arranged along a second direction. The plurality of first holes 631 are staggered with the plurality of first isolation structures 610. The staggered arrangement here means that the first hole 631 is offset by a certain distance relative to the first isolation structure 610 along the second direction D2, so that the two are not in the same row in the third direction. For example, the orthographic projection of the first hole 631 on the plane perpendicular to the third direction lies between the orthographic projections of the adjacent first isolation structures 610 on that plane.

[0097] For example, the step of forming the first hole 631 may include: forming a patterned first mask layer 522 on the stacked structure 510, etching a trench structure 620 based on the patterned first mask layer 522, and forming the first hole 631 through the trench structure. For example, the first hole 631 may be formed using a wet etching process or a dry etching process.

[0098] Next, based on the multiple first holes 631, multiple regions of the conductive layer 710 are narrowed through an etching process. For example... Figure 8a As shown, based on a plurality of first holes 631, the conductive layer 710 is etched laterally, such that the conductive layer 710 is narrowed at the positions corresponding to the first holes 631. For example, the amount of etching at the narrowed position is approximately half the width of the conductive layer 710.

[0099] Next, the material of the sacrificial layer 513 is filled at the etched locations of the conductive layer 710. For example, the sacrificial layer material can be deposited first at the etched locations of the conductive layer 710 and within the first via 631, and then the sacrificial layer material within the first via 631 can be etched away. For example, the material of the sacrificial layer 513 is the same as the material of the initial sacrificial layer 511, both being silicon nitride.

[0100] See Figures 9a to 9c Multiple first holes 631 are filled to obtain multiple first filled structures 632. For example, the material of the trench structure 620 can be used to fill the first holes 631. In this embodiment, amorphous silicon or polycrystalline silicon is used to fill the multiple first holes 631. For example, a deposition process and a chemical mechanical polishing process can be performed sequentially to form the first filled structures 632.

[0101] Next, a second hole 641 is formed in the first isolation structure 610 at a location away from the trench structure along a third direction. The second hole 641 penetrates the stacked structure 510 along the first direction D1, or its bottom rests in the lowest interlayer dielectric layer 512. For example, the step of forming the second hole 641 includes: forming a patterned second mask layer 524 on the first mask layer, and etching the stacked structure based on the patterned second mask layer 524 to form the second hole 641 penetrating the stacked structure.

[0102] The second hole 641 can be located between adjacent first isolation structures 610, or it can be located on the side of the first isolation structure 610 facing away from the trench structure 620 along a third direction and opposite to the first filling structure 632. For example, multiple second holes 641 can be isolated from each other or connected to each other. For instance, when the second hole 641 is located between adjacent first isolation structures 610, multiple second holes 641 can be isolated by the first isolation structure 610. When all or part of the second hole 641 is located on the side of the first isolation structure 610 facing away from the trench structure 620, multiple second holes 641 can be connected to each other on the side of the first isolation structure 610 facing away from the trench structure 620. In this embodiment, multiple second holes 641 and multiple first isolation structures 610 are alternately arranged along a second direction, with adjacent second holes 641 being isolated by the first isolation structure 610. Furthermore, the second hole 641 is located near the end of the first isolation structure 610 away from the trench structure 620, thus allowing for a larger first groove along a third direction in subsequent steps to increase the area of ​​the first electrode.

[0103] Subsequently, initial sacrificial layers 511 located between adjacent first isolation structures 610 are laterally etched based on multiple second vias 641, wherein multiple initial sacrificial layers 511 along the first direction D1 are etched. After the conductive layer 710 is exposed, lateral etching of each conductive layer 710 begins, so that the conductive layer 710 is broken at the narrowing point, becoming multiple segments, each segment forming a gate connection structure 711. For example, the etching solutions used to etch the initial sacrificial layers 511 and the conductive layers 710 are different.

[0104] After the gate connection structure 711 is formed, material of the sacrificial layer 513 is deposited at the locations where the initial sacrificial layer between adjacent first isolation structures 610 is removed and at the locations where the conductive layer 710 is removed.

[0105] At this point, the sacrificial layer 513 in the stacked structure 510 at least partially replaces the initial sacrificial layer 511. The initial sacrificial layer 511 and the sacrificial layer 513 are made of the same material; in this embodiment, both the initial sacrificial layer 511 and the sacrificial layer 513 are made of silicon nitride. Figure 9a As shown, a plurality of gate connection structures 711 are formed in each sacrificial layer 513 of the stacked structure 510 at intervals along the second direction.

[0106] Figures 10a to 14c The process of forming multiple gates, multiple dummy structures, and bit lines is illustrated.

[0107] In some embodiments, step S200, forming the gate, may specifically include:

[0108] A plurality of gate connection structures are formed in the sacrificial layer at intervals along a second direction; a plurality of first holes are formed on the first side of the plurality of gate connection structures along a third direction at intervals along the second direction, the first holes being parallel to the sacrificial layer located between adjacent gate connection structures; the sacrificial layer between each adjacent gate connection structure is removed based on the plurality of first holes to form a plurality of second cavities at intervals along the second direction; a plurality of gate layers are formed in the plurality of second cavities; the plurality of gates includes a plurality of gate connection structures and a plurality of gate layers.

[0109] See Figure 10a and Figure 10b Multiple second holes 641 are filled to form multiple second filled structures 642. For example, the material of the second filled structure 642 is amorphous silicon or polycrystalline silicon. The second filled structure 642 can be formed by sequentially performing a deposition process and a chemical mechanical polishing process.

[0110] See also Figure 10a and Figure 10bA plurality of first holes 631 are formed on the first side of the multiple gate connection structures 711 opposite each other along the third direction D3. The multiple first holes 631 are arranged along the second direction D2 and are located in the same row parallel to the third direction with the sacrificial layer 513 between the multiple gate connection structures 711.

[0111] For example, the step of forming the first hole 631 includes: forming a patterned third mask layer 525 in the second mask layer 524, etching a plurality of first filling structures 632 based on the patterned third mask layer 525, and releasing a plurality of first holes 631.

[0112] It should be noted that in some other embodiments, the second hole 641 can be formed first to narrow the conductive layer 710, and then the first hole 631 can be formed. The gate connection structure 711 is then formed by breaking the conductive layer 710 based on the first hole 631. In this case, the first hole 631 can be used directly.

[0113] By removing the sacrificial layer 513 between each adjacent gate connection structure 711 using multiple first vias 631, a plurality of second cavities 810 spaced apart along the second direction D2 are formed. The second cavities 810 expose portions of the first isolation structure 610. For example, this step is accomplished by etching the sacrificial layer laterally using a wet etching process.

[0114] Next, a gate layer is formed in each second cavity 810, and a dummy structure is formed simultaneously. Figures 11a to 14c The process of forming multiple gate layers and multiple dummy structures is illustrated. In some embodiments, forming multiple gate layers and multiple dummy structures includes: forming an initial gate layer; sequentially forming an initial gate dielectric layer and an initial dummy layer on the surface of the initial gate layer within multiple second cavities; wherein the initial dummy layer and the initial gate layer are offset from each other on the side exposed by a first via; forming multiple electrode isolation structures along a first direction through the stacked structure and arranged along a second direction on a second side of multiple gate connection structures (or partition structures in another embodiment) along a third direction; the electrode isolation structures are arranged side-by-side with the gate connection structures (or partition structures); forming multiple second vias on the second side of multiple gate connection structures (or partition structures) along a third direction; removing the sacrificial layer located between adjacent electrode isolation structures, the initial gate layer and the initial gate dielectric layer on the side of the initial dummy layer facing away from the first via based on the multiple second vias, and offsetting the initial gate layer and the initial dummy layer from each other on the side exposed by the second vias; the remaining portions of the multiple initial dummy layers form multiple dummy structures.

[0115] The electrode isolation structure can be either a first isolation structure 610 or a subsequent third isolation structure 672. If the initial gate layer and initial gate dielectric layer on the side of the initial dummy layer facing away from the first via are etched before forming the third isolation structure, then the electrode isolation structure is the first isolation structure. An implementation using the third isolation structure as the electrode isolation structure is described later. The initial gate layer between the first isolation structure 610 and the gate connection structure (or separator structure) may or may not be removed. The second insulating layer formed later can isolate the initial gate layer and the first electrode at this location. However, this paper subsequently removes the initial gate layer between the first isolation structure 610 and the gate connection structure, which increases the distance between the gate and the first electrode, improving their isolation performance.

[0116] See Figures 11a to 11d An initial gate layer 720, an initial gate dielectric layer 231, and an initial dummy layer 730 are sequentially formed on the surface of a plurality of second cavities 810, wherein the side of the initial gate layer 720 exposed in the first hole 631 is offset from the side of the initial dummy layer 730.

[0117] In this embodiment, as Figure 11c As shown, the side of the initial gate layer 720 exposed within the first hole 631 is recessed along a third direction D3 relative to the side of the initial dummy layer 730. In other embodiments, the side of the initial gate layer 720 exposed within the first hole 631 may protrude along a third direction D3 relative to the side of the initial dummy layer 730, as described below. Figures 14a to 14c The structure and manufacturing process of the initial gate layer 720 near the first electrode are shown.

[0118] In some embodiments, the steps of forming the initial gate layer 720, the initial gate dielectric layer 231, and the initial dummy layer 730 may include: depositing a gate material on the surfaces of a plurality of second cavities 810 and a plurality of first holes 631; depositing a gate dielectric material on the surface of the gate material; depositing dummy material on the surface of the gate dielectric material until the dummy material fills the remaining areas within the second cavities 810 and the first holes 631; and then sequentially etching the dummy material, the gate dielectric material, and the gate material. The dummy material within the first holes 631 is removed, and the remaining dummy material located within the second cavities 810 forms the initial dummy layer 730. Figure 11c As shown, the gate dielectric material and gate material in the first hole 631 are removed, and the gate material and gate dielectric material in the second cavity 810 are partially etched, causing the remaining gate material and gate dielectric material to retract a certain distance in a third direction relative to the initial dummy layer 730. The remaining gate material forms the initial gate layer 720, and the remaining gate dielectric material forms the initial gate dielectric layer 231.

[0119] See also Figure 11cA first insulating layer 740 is formed on the surface of the initial gate layer 720 exposed in the first via 631. The purpose of the first insulating layer 740 is to isolate the initial gate layer 720 (used to form the gate) from the bit lines formed subsequently.

[0120] In this embodiment, the upper and lower surfaces of the first trench to be filled 661 expose the interlayer dielectric layer 512 and the initial gate dielectric layer 231, respectively. In other embodiments, the side surface of the initial gate dielectric layer 231 may also be retracted relative to the side surface of the initial dummy layer 730 along a third direction D3 to form a larger first trench to be filled 661. Corresponding to the formation of the first trench to be filled 661, the step of forming a first insulating layer 740 on the exposed surface of each initial gate layer 720 specifically includes: forming a first insulating layer 740 within each first trench to be filled 661.

[0121] For example, the first insulating layer 740 can be formed using a deposition process and an etching process. Specifically, a first insulating material is first deposited in each first fill trench 661 and first hole 631, and then the first insulating material in the first hole 631 is etched away, so that the side surface of the remaining first insulating material is substantially flush with the side surface of the initial dummy layer 730, thus forming the first insulating layer 740. In this embodiment, the material of the first insulating layer 740 is the same as the material of the interlayer dielectric layer, for example, silicon oxide.

[0122] See Figures 12a to 12c Step S200 is executed to form multiple bit lines 410 within the plurality of first holes 631. For example, two bit lines 410 may be formed within each first hole 631, the two bit lines 410 being symmetrically arranged, and each bit line 410 being coupled to a memory cell. In some embodiments, the two bit lines 410 may be as follows: Figure 12a The two bit lines are connected to each other. It should be understood that a memory cell can be uniquely selected by selecting a bit line and a word line. Even if the two bit lines are connected, a memory cell can be selected by selecting a word line for programming or reading memory cells one by one. In other embodiments, the two bit lines 410 can be isolated from each other, for example, by having a fifth insulating layer 750 pass through the bit lines in a second direction to isolate the two bit lines.

[0123] In some embodiments, step S400, which involves forming the bit line 410 within the first hole 631, includes:

[0124] Multiple initial dummy layers 730 are etched so that the side of each initial dummy layer 730 exposed in the first hole 631 is retracted relative to the first insulating layer 740 to form multiple second fill grooves 662; multiple protrusions 412 of bit lines 410 are formed in the multiple second fill grooves 662, and bit line bodies 411 of bit lines 410 are formed in the first hole 631.

[0125] like Figures 12a to 12c As shown, the initial dummy layer 730 can be laterally etched using a wet etching process to form the second filler trench 662. The bit line 410 can be formed using a deposition process and a dry etching / punching process. Specifically, bit line material is deposited in multiple second filler trenches 662 and the first hole 631 until the first hole 631 is filled. Then, a dry etching / punching process is used to remove part of the bit line material in the first hole 631. The remaining bit line material extending along the first direction D1 in the first hole 631 forms the bit line body 411, while the bit line material in each second filler trench 662 forms a protrusion 412. The bit line 410 includes the bit line body 411 and multiple protrusions 412.

[0126] like Figure 12a and Figure 12b As shown, the bitline material in the central region of the first aperture 631 is removed. Next, a fifth insulating layer 750 can be formed in the central region of the first aperture 631 using a deposition process and a chemical mechanical polishing process. Furthermore, the third mask layer 525 can also be removed.

[0127] In some embodiments, the manufacturing method further includes: forming a plurality of third holes that are alternately arranged with bit lines along a second direction; removing a plurality of first isolation structures to form a plurality of isolation trenches; etching an initial gate layer and an initial gate dielectric layer to expose a gate connection structure (or a partition structure in another embodiment) and an initial dummy layer based on the plurality of third holes and the plurality of isolation trenches; the remaining initial gate layer forming a gate layer; filling the plurality of third holes with second isolation structures; filling the plurality of isolation trenches with third isolation structures; wherein the third isolation structures serve as electrode isolation structures.

[0128] See Figure 13a and Figure 13b A third via 681 is formed between each adjacent bit line 410, and the first isolation structure 610 is removed to release the isolation trench 671. The isolation trench 671, the gate connection structure 711, and the third via 681 are located in the same row along the third direction D3. The third via 681 penetrates the trench structure 620 along the first direction, and multiple third vias 681 and multiple bit lines 410 are arranged alternately along the second direction.

[0129] In some specific embodiments, the isolation trench 671 and the third via 681 can be formed by the following method: a patterned fourth mask layer can be formed on the stacked structure 510; based on the patterned second mask layer, the trench structure 620 and the first isolation structure 610 are simultaneously etched to remove the remaining trench structure 620 between adjacent bit lines 410, forming the third via 681; the first isolation structure 610 is removed to release the isolation trench 671. The same material in the trench structure 620 and the first isolation structure 610 can be removed simultaneously, for example, the same amorphous silicon material can be removed simultaneously.

[0130] The isolation trench 671 and the third via 681 expose the initial gate layer 720. Next, the initial gate layer 720 is laterally etched based on the multiple isolation trenches 671 and the multiple third vias 681 to remove a portion of the initial gate layer 720 located on the two opposite sides of the multiple gate connection structures 711 along the third direction D3 and on the two opposite sides of the multiple initial dummy layers 730 along the third direction; then the initial gate dielectric layer 231 in these regions is laterally etched away, exposing the two opposite sides of the gate connection structures 711 along the third direction D3.

[0131] See Figures 14a to 14c Multiple third isolation structures 672 are formed within multiple isolation grooves 671. That is, a third isolation structure 672 is formed at the location where the first isolation structure 610 is removed. Multiple third holes 681 are filled to form multiple second isolation structures 682. That is, a second isolation structure 682 is formed between adjacent bit lines 410.

[0132] For example, both the third isolation structure 672 and the second isolation structure 682 include a first sublayer 62a and a second sublayer 62b surrounding the first sublayer 62a. For example, the second sublayer 62b can be deposited first, and then the first sublayer 62a can be formed in the remaining area of ​​the isolation trench 671 and the third hole 681 by a deposition process and a chemical mechanical polishing process. For example, the material of the first sublayer 62a is amorphous silicon or polycrystalline silicon, and the material of the second sublayer 62b is silicon oxide.

[0133] See also Figures 14a to 14c Multiple second vias 641 are formed on the side of the multiple initial dummy layers 730 away from the bit line 410. For example, the step of forming the second vias 641 may include: forming a patterned fifth mask layer 526 on the initial stacked structure, and etching multiple second fill structures 642 based on the patterned fifth mask layer 526 to remove the second fill structures 642 and release the second vias 641.

[0134] By laterally etching sacrificial layers through multiple second vias 641, multiple sacrificial layers between adjacent third isolation structures 672 are removed, exposing the initial gate layer 720. Then, the initial gate layer 720 and the initial gate dielectric layer 231 are sequentially etched laterally through the multiple second vias 641 to remove the remaining regions of the initial gate layer 720 and the initial gate dielectric layer 231 on the sides of the multiple initial dummy layers 730 away from the bit line 410. Next, the initial gate layer 720 or the initial dummy layer 730 may be etched so that the side of the initial gate layer 720 exposed within the second vias 641 is offset relative to the side of the initial dummy layer 730.

[0135] At this point, the remaining portion of each initial dummy layer 730 forms a dummy structure 731, and the remaining portion of each initial gate dielectric layer forms a gate dielectric layer 230. The remaining portion of each initial gate layer 720 forms a gate layer 721. In this embodiment, the material of the gate connection structure 711 is the same as the material of the initial gate layer 720 (gate layer 721). Multiple gate connection structures 711 and multiple gate layers 721 together form... Figures 1 to 2f The diagram shows a continuous word line (or multiple gates) along the second direction. Each gate 210 can be considered to include a gate connection structure 711 and a gate layer 721. Due to the large conductive blocks between adjacent gate layers 721, i.e., the gate connection structure, the resistance of the word line can be reduced, the boost time of the word line can be shortened, the timing requirements of the circuit for the word line can be met, and the programming or reading speed can be improved, while also reducing power consumption.

[0136] In some embodiments, the manufacturing method further includes forming a second insulating layer 760 on the surface of the gate layer 721 exposed in the second via 641. The purpose of the second insulating layer 760 is to isolate the gate layer 721 (for forming the gate) from the subsequently formed first electrode.

[0137] In this embodiment, as Figure 14c As shown, the side of the gate layer 721 exposed within the second hole 641 protrudes in a third direction relative to the corresponding side of the dummy structure 731. The step of forming the second insulating layer may include forming a second insulating layer 760 on the side and inner surface of the gate layer 721 exposed in the second hole 641.

[0138] For example, the second insulating layer can be formed by deposition and etching processes. Specifically, a first groove 830 is formed at the location where the multiple sacrificial layers 513, the initial gate layer 720, the initial gate dielectric layer 231, and the initial dummy layer 730 between adjacent third isolation structures 672 are removed. A second insulating material layer is formed within the second hole 641 and the multiple first grooves 830, and then the second insulating material layer is etched using a wet etching process, leaving only the second insulating material exposed on the side of the gate layer 721 and facing the inner surface of the gate dielectric layer 230, forming a second insulating layer 760.

[0139] In this embodiment, the dummy structure 731 is recessed by a certain distance relative to the gate layer 721, and a second insulating layer is formed to wrap the gate layer 721, which can improve the isolation performance between the subsequently formed first electrode and the gate.

[0140] It should be noted that, in some other embodiments, the side of the initial gate layer 720 exposed in the second hole 641 may be retracted relative to the side of the initial dummy layer 730. The specific formation steps can refer to the step described above of etching the initial gate layer 720 so that the side of the initial gate layer 720 exposed in the first hole 631 is retracted relative to the side of the initial dummy layer 730. Correspondingly, the step of forming the second insulating layer 760 can refer to the step of forming the first insulating layer 740 described above, and will not be repeated here.

[0141] Figures 15a to 17c A method for forming a capacitor and a semiconductor layer is shown.

[0142] See Figures 15a to 15c Step S500 is performed to form the first electrode 310. For example, forming the first electrode includes forming a hollow structure with an opening on one side within a first groove 830.

[0143] The method for manufacturing the semiconductor device further includes forming a fourth isolation structure 692 in the remaining area after the first electrode is formed in the first groove and in the second hole.

[0144] For example, the steps of forming the first electrode 310 and the fourth isolation structure 692 include: depositing a first electrode material layer on the surface of each first groove 830 and the second hole 641 based on the second hole 641; depositing a fourth isolation material layer on the surface of the first electrode material layer; laterally etching the fourth isolation material layer and the first electrode material layer to remove the fourth isolation material layer and the first electrode material layer in the second hole 641, retaining the first electrode material on the surface of the first groove 830 to form the first electrode 310; redepositing the fourth isolation material layer in the second hole 641, and treating the retained fourth isolation material layer in the second hole 641 using a chemical mechanical polishing process, wherein the fourth isolation material layer redeposited in the second hole 641 and the fourth isolation material layer in the first groove 830 together form the fourth isolation structure 692.

[0145] In some embodiments, step S320, forming a release hole between each adjacent bit line and / or each adjacent first electrode, includes: removing the second isolation structure to release a third hole, the release hole including the third hole; and / or removing the third isolation structure to release an isolation groove, the release hole including the isolation groove.

[0146] See Figures 16a to 16cA patterned sixth mask layer can be formed on the stacked structure. Based on the patterned sixth mask layer, the second isolation structure 682 and the third isolation structure 672 are simultaneously etched to remove the second isolation structure 682 to release the third hole 681; and to remove the third isolation structure 672 to release the isolation trench 671. The same material as the third isolation structure 672 and the second isolation structure 682 can be removed simultaneously; for example, the second sublayer 62b can be removed simultaneously, and the first sublayer 62a can be removed simultaneously.

[0147] In this embodiment, the isolation trench 671 and the third hole 681 are used as release holes, which allows the dummy structure 731 to be replaced with the semiconductor layer 220 more quickly in subsequent steps. In other embodiments, the isolation trench 671 can be used as a release hole on one end, or the third hole 681 can be used as a release hole alone.

[0148] The third hole 681 and the isolation trench 671 expose the dummy structure 731. Next, step S330 is performed to remove the dummy structures 731 based on the multiple third holes 681 and the multiple isolation trenches 671, forming multiple first cavities 820. The first cavities 820 are surrounded by the bit line 410, the first electrode 310, and the gate 210. For example, a wet etching process can be used to remove the dummy structures 731.

[0149] See Figures 17a to 17d Step S500 is executed to form a semiconductor layer 220 on the surface of each first cavity 820.

[0150] In some embodiments, the method of manufacturing a semiconductor device further includes forming a support structure 240 within each semiconductor layer 220.

[0151] For example, the semiconductor layer 220 and the support structure 240 can be formed by deposition and wet etching processes. Specific steps include: depositing semiconductor material on the surfaces of the third hole 681, the isolation trench 671, and the first cavity 820; depositing support material on the surface of the semiconductor material; removing the support material within the third hole 681 and the isolation trench 671 using a wet etching process, and then removing the semiconductor material within the third hole 681 and the isolation trench 671 again using a wet etching process; the semiconductor material retained within the first cavity 820 serves as the semiconductor layer 220, and the support material retained within the first cavity 820 serves as the support structure 240.

[0152] like Figure 17a As shown, based on the above-described method for manufacturing semiconductor layer 220, the first sidewall 223, second sidewall 224, third sidewall 225, and fourth sidewall 226 of the prepared semiconductor layer 220 may be spaced apart from each other. In other embodiments, after removing the semiconductor material in the third hole 681 and the isolation trench 671 using a wet etching process, semiconductor material can be deposited and etched again to achieve the desired effect. Figure 17a The surface of the exposed support structure 240 is supplemented with semiconductor material, so that the first sidewall 223, the second sidewall 224, the third sidewall 225 and the fourth sidewall 226 of the semiconductor layer 220 are connected to each other.

[0153] See Figures 18a to 18c After forming the semiconductor layer 220, a plurality of third insulating layers 770 are formed within a plurality of isolation trenches 671, and a plurality of fourth insulating layers 780 are formed within a plurality of third vias 681. For example, the third insulating layers 770 and the fourth insulating layers 780 are made of the same material. The material of the third insulating layer 770 is, for example, silicon oxide. The material of the fourth insulating layer 780 is, for example, silicon oxide.

[0154] For example, the third insulating layer 770 and the fourth insulating layer 780 can be formed simultaneously using a deposition process and a chemical mechanical polishing process.

[0155] The method for manufacturing a semiconductor device further includes: forming a capacitor dielectric layer 330 and a second electrode 320; wherein the second electrode 320 is located on the side of the first electrode 310 away from the semiconductor layer 220, and the second electrode 320 extends into the hollow structure of the first electrode 310, at least a portion of the region between adjacent first electrodes 310 along a first direction D1, and at least a portion of the region between adjacent first electrodes 310 along a second direction D2; wherein the second electrodes 320 of a plurality of memory cells arranged along the first direction are connected to each other, and the second electrodes 320 of a plurality of memory cells arranged along the second direction are connected to each other; the capacitor dielectric layer 330 is located between the first electrode 310 and the second electrode 320.

[0156] In some embodiments, the method of forming the second electrode 320330 and the capacitor dielectric layer 330320 includes:

[0157] The fourth isolation structure 692 is etched to release the second via 641, and the remaining fourth isolation structure 692 is removed based on the plurality of second vias 641; a plurality of third insulating layers 770 are etched based on the plurality of second vias 641 to expose a portion of each of the two opposing sides of each first electrode 310 along the second direction; a plurality of interlayer dielectric layers 512 are etched based on the plurality of second vias 641 to expose a portion of each of the two opposing sides of each first electrode 310 along the first direction; a capacitor dielectric layer 330 is deposited on the exposed surface of the first electrode 310; a second electrode 320 is deposited on the surface of the capacitor dielectric layer 330; wherein the second electrode 320 is located in the region where the fourth isolation structure 692, the third insulating layer 770 and the interlayer dielectric layer 512 are removed.

[0158] See also Figures 18a to 18cA patterned seventh mask layer 527 is formed on the stacked structure. Based on the patterned seventh mask layer 527, the fourth isolation structure 692 is etched to release a plurality of second holes 641. Based on the plurality of second holes 641, the remaining fourth isolation structure 692 is etched laterally until it is removed to expose the inner surface of the hollow first electrode 310.

[0159] For example, the third insulating layer 770 and the interlayer dielectric layer 512 are made of the same material. Then, multiple third insulating layers 770 and multiple interlayer dielectric layers 512 can be etched simultaneously based on the second hole 641 to expose a portion of each of the two opposing sides of the first electrode 310 along the second direction, and a portion of each of the two opposing sides of the first electrode 310 along the first direction, so that the first electrode 310 is suspended.

[0160] Next, return to the previous page. Figures 1 to 2f A capacitor dielectric layer 330 is deposited on the inner surface and the exposed outer surface of the first electrode 310. For example, the capacitor dielectric layer 330 is made of a high dielectric constant material.

[0161] Next, a second electrode 320 is deposited on the surface of the capacitor dielectric layer 330. The second electrode 320 fills the region where the fourth isolation structure 692, the third insulating layer 770, and the interlayer dielectric layer 512 have been removed. For example, the second electrode 320 can be formed using a deposition process and a chemical mechanical polishing process.

[0162] Furthermore, it should be noted that in this embodiment, the first insulating layer 740, the second insulating layer 760, the third insulating layer 770, the fourth insulating layer 780, and the interlayer dielectric layer 512 are all made of the same material: silicon oxide. These layer structures are all designed to isolate adjacent memory cells; using the same material improves the consistency of isolation performance and reduces manufacturing complexity. Figure 2e The insulating spacer structure 430 includes the remaining third insulating layer 770, fourth insulating layer 780, first insulating layer 740 and second insulating layer 760.

[0163] Figures 19a to 22d It shows the formation Figures 3 to 4d The process of the gate 210 and the separator structure 250 is shown below. (Followed by...) Figures 19a to 22d To elaborate further.

[0164] In some embodiments, step S200, forming a plurality of gates extending along a second direction parallel to the substrate and interconnected with each other in the sacrificial layer, includes:

[0165] A plurality of partition structures spaced apart along a second direction are formed in the sacrificial layer, and a partition layer is located on two opposing surfaces of the plurality of partition structures along a first direction. The partition layer extends along the second direction and contacts the plurality of partition structures. A plurality of first holes spaced apart along the second direction are formed on a first side of the plurality of partition structures along a third direction. The first holes are parallel to the sacrificial layer located between adjacent partition structures. The partition layers and the sacrificial layer between each adjacent partition structure are removed based on the plurality of first holes to form a plurality of second cavities arranged along the second direction and a connecting cavity connecting adjacent second cavities. A gate layer is formed on the surface of the plurality of second cavities and the connecting cavity. The gate layer constitutes a plurality of gates in an integrated structure.

[0166] In some embodiments, the step of forming the partition structure 250 and the partition layer 793 includes:

[0167] A plurality of first isolation structures 610 are formed, passing through the stacked structure 510 along a first direction and arranged along a second direction; a trench 621 extending along the second direction is formed on one side of the plurality of first isolation structures 610 along a third direction; a plurality of initial sacrificial layers 511 are etched laterally based on the trench 621 to form a plurality of second grooves 701 arranged along the first direction, wherein the second grooves 701 expose the plurality of first isolation structures 610; an initial separation layer 791 is formed on the surface of the second grooves 701, and the area after the formation of the initial separation layer 791 in the second grooves 701 is filled with a separation body 792, and the trench 621 is filled to form a trench structure 620; a plurality of first isolation structures 620 are formed, passing through the trench structure 620 along the first direction D1 and arranged along the second direction D2. A first hole 631 is provided, and multiple first holes 631 are staggered with multiple first isolation structures 610. Based on the multiple first holes 631, multiple regions of the partition body 792 are narrowed by etching. Multiple second holes 641 are formed on the side of the partition body 792 facing away from the first holes 631 along a third direction. Based on the multiple second holes 641, the initial sacrificial layer 511, the initial partition layer 791 and the partition body 792 located between adjacent first isolation structures 610 are etched to remove the initial partition layer 791 on the side of the partition body 792 facing away from the first holes, and to break the partition body 792 at the narrowing point. The broken partition body 792 forms multiple partition structures 250, and the remaining initial partition layer 791 forms a partition layer 793.

[0168] See Figures 19a to 19c The first isolation structure 610, the groove 621, and the second groove 701 are formed. For example, the steps of forming the first isolation structure 610, the groove 621, and the second groove 701 in this embodiment can refer to the above embodiment, and therefore will not be repeated.

[0169] After forming the second groove 701, a first separating material is deposited on the surface of each second groove 701 and trench 621, and a second separating material is deposited on the surface of the first separating material until the second groove 701 and trench 621 are filled; the second separating material and the first separating material in the trench 621 are etched away, the remaining first separating material in the second groove 701 forms the initial separating layer 791, and the remaining second separating material in the second groove 701 forms the separating body 792.

[0170] For example, the initial separator layer 791 is made of any material commonly used in the art; in this embodiment, the initial separator layer 791 is made of aluminum oxide. The separator body 792 is made of a different material than the initial gate layer 720; in this embodiment, the separator body 792 is made of amorphous silicon.

[0171] Next, the trench 621 is filled to form the trench structure 620. The steps are the same as those for forming the trench structure 620 described above. For example, in this embodiment, the material of the trench structure 620 is silicon oxide.

[0172] like Figure 20a and Figure 20b As shown, a plurality of first holes 631 are formed, passing through the trench structure 620 along a first direction and arranged along a second direction D2. Multiple regions of the separating body 792 are narrowed by an etching process based on the plurality of first holes 631, and a sacrificial layer 513 is deposited in the regions where the separating body 792 is removed. For example, the step of forming the first holes 631 can refer to the above embodiment. For example, the step of narrowing the separating body 792 can be similar to the step of narrowing the conductive layer 710 described above, the difference including the different etching solution used in the wet etching process. For example, the step of depositing the sacrificial layer 513 can refer to the above embodiment.

[0173] See Figure 20b The initial separation layer 791 located on the two opposite surfaces of the separation body 792 along the first direction D1 is not etched and narrowed, but maintains its shape extending along the second direction.

[0174] See Figures 21a to 21d A plurality of first holes 631 are filled to form a plurality of first filling structures 632, and then a second hole 641 is formed between every two adjacent first isolation structures 610. For example, the steps of filling the first holes 631 and forming the second holes 641 can be referred to the above embodiment.

[0175] Next, the initial sacrificial layer 511 located between adjacent first isolation structures 610 is etched laterally based on the second hole 641 to expose the initial separation layer 791; then the initial separation layer 791 is etched laterally to expose the separation body 792; next, the separation body 792 is etched laterally so that the separation body 792 is broken at the narrowing point into multiple segments, each segment forming a separation structure 250. As a result, multiple separation structures 250 are formed at intervals along the second direction D2.

[0176] See Figure 21c and Figure 21d The initial separation layer 791, located on the two opposing surfaces of the separation body 792 along the first direction D1, is not etched but retains its shape extending along the second direction, forming the separation layer 793. Material of the sacrificial layer is deposited in the region where the initial sacrificial layer, the initial separation layer 791, and the separation body 792 are removed.

[0177] See Figure 22a As shown in Figure 22, multiple second holes 641 are first filled to obtain multiple second filling structures 642, and then multiple first filling structures 632 are removed to release the first holes 631. For example, the steps of filling the second holes 641 and releasing the first holes 631 can be referred to the above embodiment.

[0178] Based on the removal of the partition layer 793 and the sacrificial layer 513 between each adjacent partition structure 250 using multiple first holes 631, the locations where the sacrificial layer 513 between adjacent partition structures 250 is removed form second cavities, while the locations where the partition layer 793 is removed form connecting cavities between adjacent second cavities 810. These connecting cavities allow the multiple second cavities 810 to communicate with each other. Furthermore, the partition layer 793 on the side of the first isolation structure 610 is also removed; that is, all remaining partition layers 793 are removed.

[0179] When forming the initial gate layer 720, the initial gate layer 720 is deposited on the surface of a plurality of interconnected second cavities 810 and interconnected cavities 840, such that the initial gate layer 720 extends continuously along the second direction D2, so that after the gate is formed, the gates of the plurality of memory cells arranged along the second direction D2 are an integrated structure.

[0180] This completes the stacked structure 510, which includes the separating structure 250. For example, the subsequent steps are the same as described above. Figures 12a to 18c The same, thus forming Figures 3 to 4d The semiconductor device shown. The method for forming the gate and separator structure provided in this embodiment can deposit the gate in a single deposition step.

[0181] The semiconductor device manufacturing method provided in this disclosure uses a dummy structure to reserve the position of the semiconductor layer, avoiding the method of breaking the semiconductor material to form the semiconductor layer, thus reducing damage to the semiconductor layer. Furthermore, the dummy structure is removed only after the bit lines and the first electrode of the capacitor are formed, and the semiconductor layer is formed in the first cavity formed by removing the dummy structure. This manufacturing process avoids damage to the semiconductor layer caused by the solutions used in the deposition and etching of metal materials and the high-temperature environment, thereby maintaining the high quality of the semiconductor layer, which is beneficial for reducing leakage current in transistors and improving memory reliability. This embodiment also provides two gate technologies: one process uses a separator structure as part of the gate, which can reduce word line resistance and meet the circuit's word line timing requirements; the other process can deposit the gate in one step. The appropriate gate manufacturing process can be selected according to different gate requirements.

[0182] This disclosure also provides an electronic device, including the semiconductor device described above, and / or a semiconductor device formed by the manufacturing method of the semiconductor device described above.

[0183] For example, the semiconductor device provided in this disclosure is a memory. When the memory cell includes a capacitor, the memory can be DRAM. When the capacitor dielectric layer in the capacitor is replaced by a ferroelectric layer, the memory can be a ferroelectric memory. When the capacitor dielectric layer is replaced by a resistive switching layer, the memory can be a resistive switching memory layer.

[0184] It should be noted that since the electronic devices in the embodiments of this application include semiconductor devices manufactured using the semiconductor device manufacturing method provided in the embodiments of this application or semiconductor devices in the embodiments of this application, the electronic devices in the embodiments of this application also have the above-mentioned beneficial effects of the semiconductor device manufacturing method provided in the embodiments of this application or semiconductor devices in the embodiments of this application, which will not be repeated here.

[0185] For example, electronic devices include storage devices, smartphones, computers, tablets, artificial intelligence devices, wearable devices, or power banks, etc. Storage devices may include, for example, memory in a computer; this application does not limit the scope of the application to such devices.

[0186] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0187] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: A stacked layer of storage cells along a first direction, each of the storage cell layers comprising a plurality of storage cells arranged in an array; Each of the memory cells includes a transistor; The transistor includes: a gate and a semiconductor layer, the gate extending along a second direction, the semiconductor layer penetrating the gate and surrounding the gate along a third direction, the third direction intersecting the second direction and both being perpendicular to the first direction; Furthermore, the gates of the plurality of memory cells arranged along the second direction are connected to each other.

2. The semiconductor device according to claim 1, characterized in that, The gate includes: a first gate portion, a second gate portion, a third gate portion, and a fourth gate portion; The first gate portion and the second gate portion are respectively located on opposite sides of the semiconductor layer along the first direction; The third gate portion and the fourth gate portion are respectively located on opposite sides of the semiconductor layer along the second direction; Each of the third gate portion and the fourth gate portion is connected to the first gate portion and the second gate portion; The first gate portions of the plurality of memory cells arranged along the second direction are connected to each other, and the second gate portions of the plurality of memory cells are connected to each other.

3. The semiconductor device according to claim 2, characterized in that, In two adjacent memory cells along the second direction, a separation structure is provided between the third gate portion of one memory cell and the fourth gate portion of the other memory cell, and the material of the separation structure is different from the material of the gate.

4. The semiconductor device according to claim 2, characterized in that, In two adjacent memory cells along the second direction, the third gate portion of one memory cell is in contact with the fourth gate portion of the other memory cell.

5. The semiconductor device according to claim 1, characterized in that, The semiconductor layer includes: The top sidewall and bottom sidewall opposite each other along the first direction; Along the third direction opposite the first and second sidewalls; and, The third and fourth sidewalls opposite each other along the second direction; Each of the first sidewall, the second sidewall, the third sidewall, and the fourth sidewall is connected to the top sidewall and the bottom sidewall.

6. The semiconductor device according to claim 5, characterized in that, The semiconductor device also includes multiple support structures; Each of the support structures is surrounded by a first sidewall, a second sidewall, a third sidewall, a fourth sidewall, a top sidewall, and a bottom sidewall of a semiconductor layer.

7. The semiconductor device according to claim 1, characterized in that, The storage unit also includes a capacitor; The capacitor is located on one of the two opposite sides of the semiconductor layer along the third direction, and the first electrode of the capacitor is in contact with the semiconductor layer.

8. The semiconductor device according to claim 7, characterized in that, The first electrode of the capacitor is a hollow structure with one open side; The bottom wall of the hollow structure is in contact with the semiconductor layer; The sidewalls of the hollow structure extend along the third direction and include a first segment and a second segment connected to each other. The first segment is located between the semiconductor layer and the second segment, and the spacing of the first segment along the first direction is smaller than the spacing of the second segment along the first direction.

9. The semiconductor device according to claim 8, characterized in that, The capacitor further includes: a second electrode and a capacitor dielectric layer; The second electrode is located on the side of the first electrode away from the semiconductor layer, and the second electrode extends into the hollow structure from the opening of the first electrode; The capacitor dielectric layer is located between the first electrode and the second electrode.

10. The semiconductor device according to claim 9, characterized in that, The second electrode also extends into at least a portion of the region between adjacent first electrodes along the first direction, and the second electrodes of the plurality of memory cells arranged along the first direction are connected to each other; and / or, The second electrode extends into at least a portion of the region between adjacent first electrodes along the second direction, and the second electrodes of the plurality of memory cells arranged along the second direction are connected to each other.

11. The semiconductor device according to claim 1, characterized in that, Also includes bit lines: The bit line is located on one side of the semiconductor layer along the third direction, and the bit line extends along the first direction and is coupled to the semiconductor layer of the plurality of memory cells; The bit line includes: a bit line body, and a plurality of protrusions connected to the bit line body; The bit line body passes through the plurality of memory cell layers along the first direction; Each of the protrusions is located on one side of the bit line body along the third direction and extends into one of the memory cell layers, the protrusions being in contact with the semiconductor layer.

12. A method for manufacturing a semiconductor device, characterized in that, The manufacturing method includes: A stacked structure is formed on a substrate, the stacked structure comprising a plurality of interlayer dielectric layers spaced apart along a first direction perpendicular to the substrate; A plurality of gates are formed between adjacent interlayer dielectric layers, extending in a second direction parallel to the substrate and interconnected with each other; A plurality of semiconductor layers are formed in the plurality of gates, extending through the gates along a third direction and surrounded by the gates, the plurality of semiconductor layers being spaced apart along the second direction; the third direction intersects the second direction and is parallel to the substrate.

13. The method for manufacturing a semiconductor device according to claim 12, characterized in that, The manufacturing method further includes: On a first side of the plurality of gates along the third direction, a plurality of bit lines are formed that pass through the stacked structure along the first direction and are arranged along the second direction; On the second side of the plurality of gates along the third direction, a plurality of first electrodes are formed between adjacent interlayer dielectric layers arranged along the second direction, the first electrodes being opposite to the bit lines; The method of forming a plurality of semiconductor layers in the plurality of gates that extend through the gates in a third direction and are surrounded by the gates includes: A dummy structure is formed that extends through the gate along the third direction and is surrounded by the gate; the dummy structure is side-by-side with and in contact with the bit line and the first electrode along the third direction; a release hole is formed between each adjacent bit line and / or each adjacent first electrode, the release hole exposing the dummy structure; The dummy structure is removed based on the release hole to form a first cavity; A semiconductor layer is formed on the surface of the first cavity based on the release hole.

14. The method for manufacturing a semiconductor device according to claim 13, characterized in that, The formation of a plurality of gates extending in a second direction parallel to the substrate and interconnected between adjacent interlayer dielectric layers includes: A plurality of gate connection structures are formed in a sacrificial layer between adjacent interlayer dielectric layers, spaced apart along the second direction; A plurality of first holes are formed on a first side of the plurality of gate connection structures along the third direction and spaced apart along the second direction, the first holes being side by side with the sacrificial layer located between adjacent gate connection structures; The sacrificial layer between each adjacent gate connection structure is removed based on the plurality of first holes to form a plurality of second cavities spaced apart along the second direction; Multiple gate layers are formed within multiple second cavities; the multiple gates include multiple gate connection structures and multiple gate layers.

15. The method for manufacturing a semiconductor device according to claim 13, characterized in that, The formation of a plurality of gates extending in a second direction parallel to the substrate and interconnected between adjacent interlayer dielectric layers includes: A plurality of partition structures are formed in a sacrificial layer between adjacent interlayer dielectric layers, spaced apart along the second direction, and a partition layer is located on two opposing surfaces of the plurality of partition structures along the first direction, the partition layer extending along the second direction and contacting the plurality of partition structures; A plurality of first holes are formed on a first side of the plurality of partition structures along the third direction and spaced apart along the second direction, the first holes being adjacent to the sacrificial layer located between adjacent partition structures; By removing the partition layer and the sacrificial layer between each adjacent partition structure based on multiple first holes, a plurality of second cavities arranged along the second direction and a connecting cavity connecting adjacent second cavities are formed; A gate layer is formed within a plurality of second cavities and the communicating cavity; the gate layer constitutes a plurality of gates in an integrated structure.

16. The method for manufacturing a semiconductor device according to claim 14 or 15, characterized in that, The formation of multiple gate layers and multiple dummy structures includes: Form the initial gate layer; An initial gate dielectric layer and an initial dummy layer are sequentially formed on the surface of the initial gate layer within a plurality of second cavities; wherein the initial dummy layer and the initial gate layer are offset from each other when exposed on the side of the first hole; On the second side of the plurality of gate connection structures or the partition structures along the third direction, a plurality of electrode isolation structures are formed that pass through the stacked structure along the first direction and are arranged along the second direction; the electrode isolation structures are side by side with the gate connection structures or the partition structures; A plurality of second holes are formed on the second side of the plurality of gate connection structures or the partition structures along the third direction; The initial gate layer and the initial gate dielectric layer located between adjacent electrode isolation structures are removed based on multiple second holes, and the initial gate layer and the initial dummy layer on the side opposite to the first hole are made to be staggered from the initial gate layer and the initial dummy layer exposed on the side of the second hole; the remaining portions of the multiple initial dummy layers form multiple dummy structures.

17. The method for manufacturing a semiconductor device according to claim 16, characterized in that, The initial gate layer is exposed on the side of the first hole and retracts along the third direction relative to the corresponding side of the initial dummy layer to form a first groove to be filled; The method further includes: filling the first insulating layer into the first groove to be filled; The formation of bit lines includes: The initial dummy layers are etched so that the sides of the initial dummy layers exposed in the first hole retract relative to the first insulating layer to form a plurality of second grooves to be filled. Multiple protrusions of the bit line are formed in multiple second fill slots, and the bit line body of the bit line is formed in the first hole.

18. The method for manufacturing a semiconductor device according to claim 16, characterized in that, The method further includes: Before forming the gate connection structure or the partition structure, a plurality of first isolation structures are formed that pass through the stack structure along the first direction and are arranged along the second direction; the first isolation structures are located on the second side of the gate connection structure or the partition structure along the third direction; Forming a plurality of third holes that are alternately arranged with the bit lines along the second direction; Multiple isolation structures are removed to form multiple isolation trenches; Based on the plurality of third holes and the plurality of isolation trenches, the initial gate layer and the initial gate dielectric layer are etched to expose the gate connection structure or the partition structure and the initial dummy layer; the remaining initial gate layer forms the gate layer; A second isolation structure is filled within the plurality of said third holes; A third isolation structure is filled within the plurality of isolation grooves; wherein the third isolation structure serves as the electrode isolation structure.

19. The method for manufacturing a semiconductor device according to claim 18, characterized in that, The gate layer is exposed on the side of the second hole and protrudes along the third direction relative to the corresponding side of the dummy structure; The method further includes: forming a second insulating layer on the side and inner surface of the gate layer exposed in the second hole; After the second insulating layer is formed, the remaining areas at the locations where the multiple sacrificial layers, the initial gate layer, the initial gate dielectric layer, and the initial dummy layer are removed between two adjacent electrode isolation structures form multiple first grooves; The formation of the first electrode includes: forming a hollow structure with an opening on one side within the first groove.

20. The method for manufacturing a semiconductor device according to claim 19, characterized in that, The step of forming a release hole between each adjacent bit line and / or each adjacent first electrode includes: Remove the second isolation structure to release the third hole, the release hole including the third hole; And / or, Remove the third isolation structure to release the isolation groove, the release hole including the isolation groove.

21. The method for manufacturing a semiconductor device according to claim 20, characterized in that, The manufacturing method further includes: A fourth isolation structure is formed in the remaining area after the first electrode is formed in the first groove, and in the second hole; A third insulating layer is formed within the isolation groove; A fourth insulating layer is formed within the third hole; The fourth isolation structure is etched to release the second aperture, and the remaining fourth isolation structure is removed based on the plurality of second apertures; Based on the multiple second holes, the multiple third insulating layers are etched to expose a portion of each of the two opposite sides of each of the first electrode along the second direction; Based on the multiple second holes, the multiple interlayer dielectric layers are etched to expose a portion of each of the two opposite sides of each of the first electrodes along the first direction; A capacitor dielectric layer is deposited on the surface exposed by the first electrode; A second electrode is deposited on the surface of the capacitor dielectric layer; wherein the second electrode is located in the region where the fourth isolation structure, the third insulating layer and the interlayer dielectric layer are removed.

22. The method for manufacturing a semiconductor device according to claim 13, characterized in that, The manufacturing method also includes: A support structure is formed within each of the semiconductor layers.

23. An electronic device, characterized in that, include: The semiconductor device as described in any one of claims 1 to 11, and / or the semiconductor device manufactured by the method of manufacturing the semiconductor device as described in any one of claims 12 to 22.

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