Semiconductor device with channel spacer layer having different crystal phases

Abstract

A semiconductor device includes a first semiconductor structure and a second semiconductor structure connected to the first semiconductor structure. The second semiconductor structure includes: a conductive layer; a stack structure; an upper interconnection structure; an upper junction structure; and a channel structure extending into the stack structure in a first direction and protruding to an upper surface of the stack structure. Each channel structure includes a through portion and a head portion, and each channel structure includes: a conductive spacer layer; a first buried insulating layer; a channel layer including a folded portion and a channel portion; a second buried insulating layer spaced apart from the first buried insulating layer; and a data storage structure disposed on an outer side surface of the channel layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2025-0049736, filed on April 16, 2025, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This application relates to semiconductor devices with channel spacer layers having different crystalline phases. Background Technology

[0004] There is a need for semiconductor devices capable of storing large amounts of data in data storage systems. Accordingly, methods for increasing the data storage capacity of semiconductor devices have been investigated. For example, a semiconductor device comprising three-dimensional storage cells instead of two-dimensional storage cells has been developed. Summary of the Invention

[0005] Some exemplary embodiments of this disclosure provide a semiconductor device with improved integration density and reliability.

[0006] According to an exemplary embodiment of this disclosure, a semiconductor device includes: a first semiconductor structure including a first substrate, circuit elements on the first substrate, a lower interconnect structure connected to the circuit elements, and a lower bonding structure connected to the lower interconnect structure; and a second semiconductor structure connected to the first semiconductor structure, wherein the second semiconductor structure includes: a conductive layer; a stacked structure disposed below the conductive layer and including an interlayer insulating layer and a gate electrode stacked in a first direction perpendicular to the lower surface of the conductive layer; an upper interconnect structure below the stacked structure; an upper bonding structure connected to the upper interconnect structure and bonded to the lower bonding structure; and a channel structure penetrating the stacked structure in the first direction and protruding... The channel structure extends to the upper surface of the stacked structure, wherein each of the channel structures includes a through portion penetrating the stacked structure and a head portion protruding to the upper surface of the stacked structure, wherein each of the channel structures includes: a conductive spacer layer forming an outer region of the head portion and contacting the conductive layer; a first buried insulating layer on an inner surface of the conductive spacer layer; a channel layer disposed in the through portion and including a folded portion covering the lower surface of the first buried insulating layer and a channel portion extending from the lower end of the conductive spacer layer in a first direction; a second buried insulating layer disposed on an inner surface of the channel layer and spaced apart from the first buried insulating layer; and a data storage structure on an outer surface of the channel layer.

[0007] According to an exemplary embodiment of this disclosure, a semiconductor device includes: gate electrodes stacked and spaced apart from each other in a first direction, the gate electrodes including an uppermost gate electrode; a channel structure extending through the gate electrodes in the first direction, each channel structure including a channel layer, a channel-filling insulating layer on an inner surface of the channel layer, a data storage structure on an outer surface of the channel layer, and a conductive spacer layer on the channel layer; and a conductive layer contacting the conductive spacer layer of the channel structure on the uppermost gate electrode, wherein the channel layer of each of the channel structures includes: a channel portion extending in the first direction; and a folded portion bending from the channel portion at a level higher than the upper surface of the uppermost gate electrode and covering the upper end of the channel-filling insulating layer, and wherein, in a plan view parallel to the lower surface of the conductive layer, the minimum width of the channel layer is greater than the minimum width of the conductive spacer layer and less than the maximum width of the conductive spacer layer.

[0008] According to an exemplary embodiment of this disclosure, a data storage system includes: a semiconductor memory device including a first semiconductor structure, a second semiconductor structure, and input / output pads, the first semiconductor structure including a substrate and circuit elements on the substrate, the second semiconductor structure on the first semiconductor structure, and the input / output pads electrically connected to the circuit elements; and a controller electrically connected to the semiconductor memory device via the input / output pads and controlling the semiconductor memory device, wherein the second semiconductor structure includes: a conductive layer; a stacked structure below the conductive layer and including an interlayer insulating layer and a gate electrode stacked in a first direction perpendicular to the lower surface of the conductive layer; and a channel structure penetrating the stacked structure in the first direction and protruding The upper surface of the stacked structure, wherein each of the channel structures includes a through portion penetrating the stacked structure and a head portion protruding to the upper surface of the stacked structure, wherein each of the channel structures includes: a conductive spacer layer forming an outer region of the head portion and contacting the conductive layer; a first buried insulating layer on an inner surface of the conductive spacer layer; a channel layer disposed in the through portion and including a folded portion covering a lower surface of the first buried insulating layer and a channel portion extending from the lower end of the conductive spacer layer in a first direction; a second buried insulating layer disposed on an inner surface of the channel layer and spaced apart from the first buried insulating layer; and a data storage structure disposed on an outer surface of the channel layer. Attached Figure Description

[0009] The above and other aspects, features and advantages of this disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

[0010] Figure 1A This is a plan view showing a semiconductor device according to an exemplary embodiment of the present disclosure.

[0011] Figure 1BThis is a cross-sectional view showing a semiconductor device according to an exemplary embodiment of the present disclosure.

[0012] Figure 1C This is an enlarged cross-sectional view showing a portion of a semiconductor device according to an exemplary embodiment of the present disclosure.

[0013] Figure 1D This is an enlarged plan view showing a portion of a semiconductor device according to an exemplary embodiment of the present disclosure.

[0014] Figure 2A This is an enlarged cross-sectional view showing a portion of a semiconductor device according to an exemplary embodiment of the present disclosure.

[0015] Figure 2B This is a plan view showing a portion of a semiconductor device according to an exemplary embodiment of the present disclosure.

[0016] Figure 3 This is an enlarged cross-sectional view showing a portion of a semiconductor device according to an exemplary embodiment of the present disclosure.

[0017] Figure 4 This is an enlarged cross-sectional view showing a portion of a semiconductor device according to an exemplary embodiment of the present disclosure.

[0018] Figure 5A This is a cross-sectional view showing a semiconductor device according to an exemplary embodiment of the present disclosure.

[0019] Figure 5B This is a cross-sectional view showing a portion of a semiconductor device according to an exemplary embodiment of the present disclosure.

[0020] Figure 6 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure.

[0021] Figure 7 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure.

[0022] Figure 8 , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16 , Figure 17A , Figure 18 , Figure 19 , Figure 20 and Figure 21A This is an enlarged cross-sectional view showing the process of manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure.

[0023] Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 17B and Figure 21B This is an enlarged cross-sectional view showing the process of manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure.

[0024] Figure 22 This is a diagram illustrating a data storage system of a semiconductor device including an example embodiment of the present disclosure.

[0025] Figure 23 This is a perspective view illustrating a data storage system of a semiconductor device including an example embodiment of the present disclosure. Detailed Implementation

[0026] The embodiments of this disclosure will be described below with reference to the accompanying drawings.

[0027] In the example implementation, unless otherwise indicated, terms such as "upper," "upper part," "upper surface," "above," "lower," "lower part," "lower surface," "below," and "side surface" may be used based on the accompanying drawings. The term "upper end" of an element indicates the portion positioned at the highest horizontal level based on the accompanying drawings, and the term "lower end" of an element indicates the portion positioned at the lowest horizontal level based on the accompanying drawings. "Horizontal" indicates the position in the vertical direction (Z-direction) based on the accompanying drawings, and the higher the element is positioned in the vertical direction, the higher the horizontal level can be.

[0028] Figure 1A This is a plan view illustrating a semiconductor device according to an example embodiment, showing a portion of the elements of the semiconductor device.

[0029] Figure 1B It shows along Figure 1A The image shows a cross-sectional view of a semiconductor device according to an example embodiment, taken by line I-I'.

[0030] Figure 1C This is an enlarged cross-sectional view showing a portion of a semiconductor device according to an example embodiment, illustrating... Figure 1B Region "A" in the text.

[0031] Figure 1D It is along Figure 1C Enlarged planar views of a portion of the semiconductor device according to the example embodiment, taken from lines Ia-Ia', Ib-Ib', Ic-Ic', and Id-Id'.

[0032] During the integration of semiconductor devices, defects such as breakage of the head portion CH_1 of the channel structure CH or isolation from the through portion CH_2 may occur during the process. In some example embodiments, because the channel structure CH includes a conductive spacer layer 251 and a channel layer 255 with different crystal structures, defects in the head portion CH_1 can be prevented during the process, thereby providing a semiconductor device with higher reliability and integration density, as well as a data storage system including the semiconductor device. A detailed description will follow in the description of each element and the description of the manufacturing method.

[0033] refer to Figure 1A , Figure 1B , Figure 1C and Figure 1D The semiconductor device 10 may include a first semiconductor structure S1 and a second semiconductor structure S2, and the first semiconductor structure S1 may be stacked relative to the second semiconductor structure S2 in the Z direction (which may be vertical). Specifically, the first semiconductor structure S1 may be disposed below the second semiconductor structure S2 in the Z direction. Alternatively, in an example embodiment, the second semiconductor structure S2 may be disposed below the first semiconductor structure S1.

[0034] In an example implementation, semiconductor device 10 may include: a peripheral circuit structure PERI (see...). Figure 1B The first semiconductor structure S1 has a peripheral circuit region formed on a first substrate 101; and the memory cell structure CELL (see [link to CELL]). Figure 1B ), which is a second semiconductor structure S2 including a conductive layer CP.

[0035] In some example embodiments, the first semiconductor structure S1 can form peripheral circuitry by forming transistors and metal patterns for wiring the transistors on the first substrate 101. After forming peripheral circuitry in the first semiconductor structure S1, a second semiconductor structure S2 can be formed, but the example embodiments are not limited thereto.

[0036] The semiconductor device 10 may include a cell region and an extension region disposed in the X direction. Figure 1A A portion of the cell region is shown. The cell region may be a memory cell region in which memory cells are disposed, and a channel structure CH may be disposed in the cell region. The extension region may be a region for electrically connecting the memory cells to the peripheral circuit structure PERI. For this purpose, the gate electrode layer may extend to different lengths in the cell region, but the example implementation is not limited thereto.

[0037] The first semiconductor structure S1, which serves as the peripheral circuit structure, may include a first substrate 101, circuit elements 120 on the first substrate 101, a lower interconnect structure 130, a lower bonding structure 180, and a lower capping layer 190.

[0038] The first substrate 101 may include a semiconductor material (e.g., a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor). The first substrate 101 may be a bulk wafer or an epitaxial layer. In the first substrate 101, an active region may be defined by a device isolation layer 110. Source / drain regions 105, including impurities, may be disposed in a portion of the active region.

[0039] Circuit element 120 may include a transistor. Each circuit element 120 may include a circuit gate dielectric layer 122, a circuit gate electrode 124, a spacer layer 126, and a source / drain region 105. The source / drain regions 105, including impurities, may be disposed on both sides of the circuit gate electrode 124 in a first substrate 101. The spacer layer 126 may be disposed on both sides of the circuit gate electrode 124. The circuit gate dielectric layer 122 may include silicon oxide, silicon nitride, or a high-k material. The circuit gate electrode 124 may include at least one of doped silicon, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tungsten silicon nitride (WSiN), tungsten (W), copper (Cu), aluminum (Al), molybdenum (Mo), or ruthenium (Ru). For example, the circuit gate electrode 124 may include a doped polysilicon layer. According to some example embodiments, the circuit gate electrode 124 may include two or more multilayer structures.

[0040] The lower interconnect structure 130 can be electrically connected to the circuit gate electrode 124 and the source / drain region 105 of the circuit element 120. The lower interconnect structure 130 can include a lower contact plug 135 and a lower interconnect line 137 having at least one linear region. A portion of the lower contact plug 135 can be connected to the source / drain region 105, and another portion of the lower contact plug 135 can be connected to the circuit gate electrode 124. The lower contact plug 135 can be electrically connected to the lower interconnect line 137 disposed at a different level from the upper surface of the first substrate 101. The lower interconnect structure 130 can include a conductive material (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), and each element can also include a diffusion barrier comprising at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or tungsten nitride (WN). According to an example embodiment, the number and arrangement of the lower contact plugs 135 and lower interconnect lines 137 included in the lower interconnect structure 130 can vary.

[0041] The lower bonding structure 180 can be connected to the lower interconnect structure 130. The lower bonding structure 180 may include a lower bonding via 182, a lower bonding pad 184, and a lower bonding insulating layer 186. The lower bonding via 182 can be connected to the lower interconnect structure 130. The lower bonding pad 184 can be connected to the lower bonding via 182. The lower bonding via 182 and the lower bonding pad 184 may include conductive materials (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), and each element may also include a diffusion barrier. The lower bonding insulating layer 186 may also serve as a diffusion barrier for the lower bonding pad 184 and may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide. The thickness of the lower bonding insulating layer 186 may be less than the thickness of the lower bonding pad 184, but exemplary embodiments are not limited thereto. The lower bonding structure 180 can directly contact and bond or connect to the upper bonding structure 280 via a hybrid bonding process. For example, the lower bonding pad 184 can contact and couple to the upper bonding pad 284 via a copper-to-copper bonding, and the lower bonding insulating layer 186 can contact and couple to the upper bonding insulating layer 286 via a dielectric-to-dielectric bonding. Together with the upper bonding structure 280, the lower bonding structure 180 can provide an electrical connection path between the peripheral circuit structures PERI and S1 and the memory cell structures CELL and S2.

[0042] The lower capping layer 190 may be disposed on the first substrate 101 and may cover the circuit element 120 and the lower interconnect structure 130. The lower capping layer 190 may include multiple insulating layers. The lower capping layer 190 may include an insulating material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide).

[0043] The second semiconductor structure S2, as a memory cell structure, may include in the cell region (memory cell region): a conductive layer CP; a stacked structure ST, which includes a gate electrode 230 and an interlayer insulating layer 220 alternately stacked on the lower surface of the conductive layer CP; a channel structure CH, configured to extend into the stacked structure ST; an isolation region MS, extending through the gate electrode 230 and extending in one direction; and an insulating region SS, extending into a portion of the gate electrode 230. The second semiconductor structure S2 may also include a protrusion 272 for electrical connection with the first semiconductor structure S1, an upper interconnect 271 below the stacked structure ST, and an upper bonding structure 280 connected to the upper interconnect 271.

[0044] exist Figure 1A and Figure 1BIn the cell region of the semiconductor device 10 shown, gate electrodes 230 can be stacked and spaced apart from each other in a vertical direction (e.g., the Z direction), and a channel structure CH can be formed. The vertical direction can be defined as a first direction. In the extension region, contact plugs can be disposed on at least one side of the cell region in the X direction, can be connected to the gate electrodes 230 respectively, and can electrically connect the memory cells to the first semiconductor structure S1.

[0045] The gate electrode 230 can be disposed below the lower surface of the conductive layer CP, can be vertically stacked and spaced apart from each other, and can form a stacked structure ST together with the interlayer insulating layer 220. In some example embodiments, the conductive layer CP can be an element formed on a stacked structure ST in which the interlayer insulating layer 220 and the gate electrode 230 are alternately stacked, and its specific description will be described later in the description of the manufacturing method. Figure 1B In this context, the stacked structure ST can be configured as a single stacked structure, but its example implementation is not limited to this. The stacked structure ST can include multiple stacked structures stacked in the vertical direction, as will be discussed in subsequent references. Figure 5A and Figure 5B The description is provided in the description.

[0046] The gate electrode 230 may include at least one first gate electrode 230a forming the gate of a ground selection transistor, a memory gate electrode 235 forming a plurality of memory cells, and a second gate electrode 230b forming the gate of a string selection transistor. Here, reference is made to... Figure 1B The first gate electrode 230a can be referred to as the upper gate electrode 230a, the second gate electrode 230b can be referred to as the lower gate electrode 230b, and the memory gate electrode 235 can be referred to as the intermediate gate electrode 235. Among the gate electrodes 230, the gate electrode most adjacent to the conductive layer CP can be referred to as the uppermost gate electrode 230a, and the gate electrode most adjacent to the lower insulating layer 290 can be referred to as the lowermost gate electrode 230b. The number of memory gate electrodes 235 forming memory cells can be determined according to the capacity of the semiconductor device 10. In example embodiments, the number of upper gate electrodes 230a and lower gate electrodes 230b can be one to two or more, and they can have the same or different structures as the memory gate electrodes 235. In some example embodiments, the erase gate electrode can be further disposed below the lower gate electrode 230b. Furthermore, a portion of the gate electrode 230 (e.g., the memory gate electrode 235 adjacent to the upper gate electrode 230a or the lower gate electrode 230b) can be a dummy gate electrode, but the example embodiments are not limited thereto.

[0047] Gate electrodes 230 can be isolated from each other in the X direction by isolation regions MS that extend continuously in the cell region and the extension region. Gate electrodes 230 between a pair of isolation regions MS can form a memory block BLK, but the scope of the memory block BLK is not limited thereto. A portion of the gate electrodes 230 (e.g., memory gate electrode 235) can form a layer in each memory block BLK.

[0048] The gate electrodes 230 can be vertically stacked and spaced apart from each other in the cell region and the extension region, can extend from the cell region to the extension region at different lengths, and can form part of the extension region (e.g., a stepped structure in the extension region), but exemplary embodiments thereof are not limited thereto. The gate electrodes 230 can be connected to contact plugs respectively.

[0049] The gate electrode 230 may include a metallic material, such as tungsten (W). In an example embodiment, the gate electrode 230 may include polycrystalline silicon or a metal silicide material. According to an example embodiment, the gate electrode 230 may also include a diffusion barrier, for example, the diffusion barrier may include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0050] Interlayer insulating layers 220 may be disposed between gate electrodes 230 and may form a stacked structure ST. Similar to gate electrodes 230, interlayer insulating layers 220 may be spaced apart from each other in a direction perpendicular to the lower surface of conductive layer CP and may extend in the X direction. Interlayer insulating layers 220 may comprise insulating materials such as silicon oxide or silicon nitride.

[0051] In the example implementation, the thickness of the interlayer insulating layer 220 can be different. For example, the thickness of the first interlayer insulating layer 220a, which is most adjacent to the conductive layer CP, and the second interlayer insulating layer 220b, which is most adjacent to the lower insulating layer 290, can be greater than the thickness of the intermediate interlayer insulating layer 225, but the example implementation is not limited to this. The intermediate interlayer insulating layer 225 can be defined as the interlayer insulating layer disposed between the first interlayer insulating layer 220a and the second interlayer insulating layer 220b. The first interlayer insulating layer 220a can be referred to as the uppermost interlayer insulating layer 220a, and the second interlayer insulating layer 220b can be referred to as the lowermost interlayer insulating layer 220b.

[0052] The isolation region MS can be configured to extend into at least a portion of the gate electrode 230 and extend in the Y direction. The isolation regions MS can be spaced apart from each other in the X direction and can be arranged parallel to each other. The isolation region MS can extend through the entire gate electrode 230 of the stack and can be connected to the lower insulating layer 290. The isolation region MS can extend as a whole region in the Y direction, or can extend intermittently in a partial manner, or can be provided only in a portion of the region.

[0053] An isolation insulating layer 264 may be provided in the isolation region MS. The isolation insulating layer 264 may have a shape in which its width decreases towards the conductive layer CP due to a high aspect ratio, but exemplary embodiments are not limited to this. The lower end of the isolation insulating layer 264 may contact the lower insulating layer 290, and the upper end may protrude above the upper surface of the stacked structure ST and may contact the conductive layer CP. The width of the upper end of the isolation region MS in the X direction may be greater than the width of the upper end of each channel structure CH, but exemplary embodiments are not limited to this. The isolation insulating layer 264 may include an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0054] The insulating region SS can extend in the Y direction between adjacent insulating regions MS along the X direction. The insulating region SS can be disposed within the cell region and can also be partially disposed within the extended region. The insulating region SS can extend through the second gate electrode 230b adjacent to the lower insulating layer 290 within the gate electrode 230. For example... Figure 1B As shown, the insulating region SS can separate the second gate electrode 230b in the X direction. Figure 1B The diagram shows that each insulating region SS isolates multiple second gate electrodes 230b, but in the example embodiment, the number of second gate electrodes 230b isolated by the insulating region SS can be varied. For example, each insulating region SS can isolate a single second gate electrode 230b.

[0055] An insulating region SS can be provided by intersecting a portion of a channel structure CH. The insulating region SS can have a predetermined width in the X direction and can extend in the Y direction to intersect multiple channel structures CH arranged in a zigzag pattern. Therefore, when multiple channel structures CH are arranged with the same spacing, the insulating region SS can extend to intersect with channel structures CH in a row simultaneously. The insulating region SS can be recessed into the lower end of the channel structure CH (e.g., the portion of the channel structure CH opposite the second gate electrode 230b), and thus, a portion of the channel structure CH can be removed. In this case, the recessed length of the channel structure CH can be less than the radius of the channel structure CH from the channel central axis to the inner wall of the channel hole. Therefore, the insulating region SS may not pass through the channel central axis of the channel structure CH, and 1 / 2 or more of the channel structure CH may remain on the lower surface, but its exemplary embodiments are not limited thereto. The channel structure CH into which the insulating region SS is recessed can be an effective channel structure actually used as a memory cell, rather than a dummy channel structure. Each insulating region SS may include a lower insulating layer 268. The lower insulating layer 268 may include an insulating material (e.g., silicon oxide, silicon nitride, or silicon oxynitride).

[0056] The channel structures CH can be spaced apart from each other in rows and columns below the conductive layer CP of the cell region. The channel structures CH can be configured in a sawtooth shape in one direction of the XY plane. The channel structures CH can extend vertically into the stacked structure ST including the gate electrode 230 and the interlayer insulating layer 220, and can protrude above the stacked structure ST and extend into the conductive layer CP. The channel structures CH can extend in a first direction (e.g., in the Z direction, which is a vertical direction perpendicular to the lower surface of the conductive layer CP), and can have a sloping side surface whose width decreases toward the conductive layer CP according to the aspect ratio. That is, the channel structures CH can have a sloping side surface whose width decreases upward.

[0057] Each channel structure CH may include a through portion CH_2 extending into the stacked structure ST and a head portion CH_1 protruding from the upper part of the through portion CH_2. The through portion CH_2 may contact the gate electrode 230 and the interlayer insulating layer 220 of the stacked structure ST, and the head portion CH_1 may contact the conductive layer CP. Each channel structure CH may include a bent portion CH_s. The bent portion CH_s may include a first bent portion CH_sa included in the head portion CH_1 and a second bent portion CH_sb between the head portion CH_1 and the through portion CH_2. The bent portion CH_s may be a step difference formed by a width difference or variation of the channel structure CH, and the width of each channel structure CH may vary continuously in the portions other than the bent portion CH_s. For example, the width of each channel structure CH may decrease continuously toward the conductive layer CP in the portions other than the bent portion CH_s.

[0058] The first curved portion CH_sa may be included in the head portion CH_1 and may be positioned at a level overlapping with the conductive layer CP. The configuration of the element positioned at the overlap level may indicate that the element overlaps in a direction perpendicular to a first direction (e.g., the Z direction, which is vertical) (e.g., the X or Y direction). In some example embodiments, the width of the head portion CH_1 may increase downwards, except for the first curved portion CH_sa. The width of the head portion CH_1 may decrease discontinuously downwards with the first curved portion CH_sa as the boundary. The head portion CH_1 may include a step difference formed by the width difference of the first curved portion CH_sa. The head portion CH_1 may have a minimum width at a level that is the same as or lower than the level of the first curved portion CH_sa, and may have a maximum width at a level that is the same as or higher than the level of the first curved portion CH_sa. The channel structure CH may have a minimum width in the first curved portion CH_sa of the head portion CH_1. Since the head portion CH_1 includes the first curved portion CH_sa, the cross-sectional shape of the head portion CH_1 can be a mushroom shape or an umbrella shape.

[0059] The second curved portion CH_sb can be positioned at the lower end of the head portion CH_1 or the upper end of the through portion CH_2. The second curved portion CH_sb can be positioned at a level lower than the first curved portion CH_sa and higher than the uppermost first gate electrode 230a. The head portion CH_1 and the through portion CH_2 can be distinguished from each other by the second curved portion CH_sb as a boundary. The width of the channel structure CH can decrease discontinuously upwards with the second curved portion CH_sb as a boundary. Due to the second curved portion CH_sb, the lower end of the head portion CH_1 and the upper end of the through portion CH_2 can have a width difference. The second curved portion CH_sb can contact the lower surface of the conductive layer CP. In some example embodiments, the second curved portion CH_sb can be positioned at the same level as the interface between the conductive layer CP and the first interlayer insulating layer 220a. In some example embodiments, the second curved portion CH_sb can be coplanar with the lower surface of the conductive layer CP or the upper surface of the first interlayer insulating layer 220a.

[0060] Each channel structure CH may include a data storage structure 245, a buried insulating layer 248, a conductive structure 250, and a channel pad 259. The buried insulating layer 248 may include a first buried insulating layer 247 and a second buried insulating layer 249. The conductive structure 250 may include a conductive spacer layer 251 and a channel layer 255.

[0061] The conductive structure 250 can be completely disposed in the head portion CH_1 and the through portion CH_2 of the channel structure CH, and can be disposed from the upper end of the head portion CH_1 to the lower end of the through portion CH_2. The conductive structure 250 may include a conductive spacer layer 251 included in the outer region of the head portion CH_1 and a channel layer 255 disposed in the through portion CH_2.

[0062] The conductive spacer layer 251 and the channel layer 255 may comprise the same semiconductor material (e.g., silicon) and may have different crystal states. Because the conductive spacer layer 251 and the channel layer 255 are formed in separate processes, they may have different crystal states even when comprising the same semiconductor material. In some example embodiments, "having different crystal states" may indicate differences such as a crystalline or amorphous state, a single-crystal or polycrystalline state, or differences in grain size. In some example embodiments, the conductive spacer layer 251 and the channel layer 255 may have crystalline structures, with the conductive spacer layer 251 comprising a polycrystalline material and the channel layer 255 comprising a single-crystal material. For example, the conductive spacer layer 251 may comprise polycrystalline silicon, and the channel layer 255 may comprise single-crystal silicon. In some example embodiments, the grain size of the material included in the crystalline conductive spacer layer 251 may differ from the grain size of the material included in the crystalline channel layer 255. In some example embodiments, the grain size of the material included in the conductive spacer layer 251 may be smaller than the grain size of the material included in the channel layer 255. For example, the average grain size of the material included in the channel layer 255 may be at least five times the average grain size of the material included in the conductive spacer layer 251. In some example embodiments, the conductive spacer layer 251 may include a material having an amorphous structure, and the channel layer 255 may include a material having a crystalline structure. For example, the conductive spacer layer 251 may include amorphous silicon, and the channel layer 255 may include crystalline silicon. Based on the difference in crystal state between the conductive spacer layer 251 and the channel layer 255, a channel interface surface 250s may be formed. The channel interface surface 250s may be positioned at a level overlapping with the first interlayer insulating layer 220a. "Positioned at an overlapping level" may indicate that the elements overlap in a horizontal direction (e.g., the X or Y direction) parallel to the lower surface of the conductive layer CP. The channel interface surface 250s can be positioned at a level lower than the upper surface of the first interlayer insulating layer 220a and higher than the lower surface of the first interlayer insulating layer 220a. The channel interface surface 250s can have an outwardly curved shape that bends toward the conductive spacer layer 251, and the portion of the conductive spacer layer 251 that contacts the channel layer 255 can have an inwardly curved shape.

[0063] The conductive spacer layer 251 can form the outer region of the head portion CH_1 and can contact the conductive layer CP. A portion of the lower part of the conductive spacer layer 251 can extend into the through portion CH_2 and can contact the data storage structure 245 and the channel layer 255. The outer surface of the conductive spacer layer 251 can contact the conductive layer CP, and the inner surface of the conductive spacer layer 251 can contact the first buried insulating layer 247. The side surfaces of the conductive spacer layer 251 can have a stepped difference due to the first curved portion CH_sa. Figure 1DAs shown, in a plan view parallel to the lower surface of the conductive layer CP (e.g., viewed from the XY plane), at least a portion of the conductive spacer layer 251 may have an annular shape surrounding the first buried insulating layer 247. In some example embodiments, the conductive spacer layer 251 may have a shape such as a cylindrical or prismatic shape without the first buried insulating layer 247 at a level lower than the level of the first curved portion CH_sa, and may have a shape such as a frustoconical or truncated pyramidal shape at a level higher than the level of the first curved portion CH_sa. In the plan view, the first width W1 of the conductive spacer layer 251 may vary horizontally. The first width W1 of the conductive spacer layer 251 may be defined as the horizontal distance between the corresponding outer surfaces of the conductive spacer layer 251. The first width W1 of the conductive spacer layer 251 may increase downwards in portions other than the first curved portion CH_sa. The first width W1 of the conductive spacer layer 251 may have a minimum width W1a and a maximum width W1b in the portion having the first curved portion CH_sa. The first curved portion CH_sa may have a stepped difference due to the difference between the minimum width W1a and the maximum width W1b. The maximum width W1b of the conductive spacer layer 251 may be greater than the minimum width W2a of the channel layer 255, and may be less than the maximum width of the channel layer 255. The minimum width W1a of the conductive spacer layer 251 may be less than the minimum width W2a of the channel layer 255. The upper portion of the conductive spacer layer 251 may cover the upper surface of the first buried insulating layer 247, and the planar shape of the portion of the conductive spacer layer 251 covering the upper surface of the first buried insulating layer 247 may be one of a circular shape, an elliptical shape, or a polygonal shape. The lower end of the conductive spacer layer 251 may contact the channel layer 255, and the lower end of the conductive spacer layer 251 may be positioned at a level overlapping with the first interlayer insulating layer 220a. Because the conductive spacer layer 251 is formed using a different process than that used to form the channel layer 255, it is possible to control whether the conductive spacer layer 251 completely fills the space of the head portion CH_1, and to stably ensure the formation of the space for the first buried insulating layer 247. Furthermore, in the example embodiment, when the channel layer 255 is crystallized using a metal-induced lateral crystallization (MILC) process, residual metal particles can be prevented from diffusing into the conductive spacer layer 251. Therefore, it is possible to prevent the head portion CH_1 from breaking or isolating during the process, enabling the provision of semiconductor devices with improved reliability and integration density, and methods for manufacturing the same. A description of this will be provided in the subsequent description of the manufacturing method.

[0064] The channel layer 255 may include a folded portion 255a covering the lower surface of the first buried insulating layer 247 and the upper surface of the second buried insulating layer 249, and a channel portion 255b extending vertically (e.g., in the Z direction) in the through portion CH_2. The folded portion 255a may be positioned at a level overlapping with the first interlayer insulating layer 220a. That is, the folded portion 255a may be positioned at a level lower than the level of the upper surface of the first interlayer insulating layer 220a and higher than the level of the lower surface of the first interlayer insulating layer 220a. The folded portion 255a may be positioned at a level lower than the level of the lower surface of the conductive layer CP. The folded portion 255a may be positioned at a level higher than the level of the upper surface of the first gate electrode 230a. The upper surface of the folded portion 255a may contact the first buried insulating layer 247 and may have a shape that curves outward toward the first buried insulating layer 247 or the conductive layer CP. The lower surface of the folded portion 255a may contact the second buried insulation layer 249 and may have a shape that curves inward toward the second buried insulation layer 249. The first buried insulation layer 247 and the second buried insulation layer 249 may be spaced apart from each other by the folded portion 255a. In a plan view, the folded portion 255a may have a circular, elliptical, or polygonal shape.

[0065] The channel portion 255b may extend vertically from the lower end of the conductive spacer layer 251 and may extend to the lower end of the channel structure CH. The upper end of the channel portion 255b may contact the conductive spacer layer 251, and the portion of the channel portion 255b in contact with the conductive spacer layer 251 may be included in the channel interface surface 250s. In some example embodiments, the upper end of the channel portion 255b may be positioned at a level higher than the level of the upper end of the folded portion 255a. The lower end of the channel portion 255b may be positioned at the same level as the lower surface of the second interlayer insulating layer 220b. In some example embodiments, the channel portion 255b of the channel layer 255 may be formed in an annular shape surrounding the second buried insulating layer 249 therein, or may have a columnar shape such as a cylindrical or prismatic shape without the second buried insulating layer 249. In some example embodiments, when the channel layer 255 is crystallized using a metal-induced lateral crystallization (MILC) process, a portion of the metal particles used may remain in the channel layer 255. In some example embodiments, metal particles such as nickel (Ni), titanium (Ti), cobalt (Co), tungsten (W), platinum (Pt), or palladium (Pd) may remain in the channel layer 255. However, even in this case, it is possible to prevent the metal particles from diffusing into the conductive spacer layer 251, and the conductive spacer layer 251 may not contain metal particles. Therefore, a semiconductor device with improved reliability and integration density, as well as a method for manufacturing the semiconductor device, can be provided, and the relevant description will be given in the subsequent description of the manufacturing method.

[0066] In the plan view, the second width W2 of the channel layer 255 can vary according to different levels. The second width W2 of the channel layer 255 can be defined as the horizontal distance between the outer surfaces of the corresponding channel portions 255b. The second width W2 of the channel layer 255 can increase downwards. In some example embodiments, the portion of the channel layer 255 with the minimum width W2a can be positioned at a level overlapping with the folded portion 255a. The minimum width W2a of the channel layer 255 can be greater than the minimum width W1a of the conductive spacer layer 251, but can be less than the maximum width W1b of the conductive spacer layer 251. In some example embodiments, the maximum width of the channel layer 255 can be greater than the maximum width W1b of the conductive spacer layer 251. In some example embodiments, the maximum width of the channel layer 255 can be less than the maximum width W1b of the conductive spacer layer 251.

[0067] The channel pad 259 may be disposed in the lower part of the channel layer 255 within the channel structure CH. The channel pad 259 may cover the lower surface of the second buried insulating layer 249 and may be electrically connected to the channel layer 255. The channel pad 259 may comprise, for example, doped polysilicon.

[0068] The buried insulating layer 248 can fill the channel structure CH. The buried insulating layer 248 may include a first buried insulating layer 247 surrounded by the inner surface of the conductive spacer layer 251 and the upper surface of the folded portion 255a of the channel layer 255, and a second buried insulating layer 249 on the lower surface of the folded portion 255a of the channel layer 255 and the inner surface of the channel portion 255b. The first buried insulating layer 247 may be referred to as the spacer buried insulating layer 247, and the second buried insulating layer 249 may be referred to as the channel filling insulating layer 249. The first buried insulating layer 247 and the second buried insulating layer 249 may be spaced apart from each other by the folded portion 255a of the channel layer 255. A portion of the first buried insulating layer 247 may be positioned in the head portion CH_1 of the channel structure CH, and another portion may be positioned in the through portion CH_2 of the channel structure CH. The first buried insulating layer 247 may cover the inner surface of the conductive spacer layer 251 and the upper surface of the folded portion 255a of the channel layer 255. The second buried insulating layer 249 may be disposed in the through portion CH_2. The second buried insulating layer 249 may cover the lower surface of the folded portion 255a and the inner surface of the channel portion 255b. The first buried insulating layer 247 and the second buried insulating layer 249 may include an insulating material. For example, the first buried insulating layer 247 and the second buried insulating layer 249 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide. In some example embodiments, the first buried insulating layer 247 and the second buried insulating layer 249 may include the same material. In some example embodiments, the first buried insulating layer 247 and the second buried insulating layer 249 may include different materials. In some example embodiments, a first void 247V may be present in the first buried insulating layer 247. The first void 247V may be spaced apart from the conductive spacer layer 251. The size, location, and number of the first gap 247V can vary. The second gap 249V can exist within the second buried insulation layer 249. The second gap 249V can be spaced apart from the trench layer 255. The size, location, and number of the second gap 249V can vary.

[0069] Data storage structure 245 may be disposed between gate electrode 230 and channel layer 255. Data storage structure 245 may extend vertically on the outer surface of channel layer 255. Data storage structure 245 may cover at least a portion of the outer surface of channel layer 255. Data storage structure 245 may cover a portion of conductive spacer layer 251. Data storage structure 245 may cover the outer surface of the portion of conductive spacer layer 251 extending into through portion CH_2. The upper end of data storage structure 245 may contact conductive layer CP and may form a second bent portion CH_sb. Data storage structure 245 may be formed to cover the entire outer surface of conductive spacer layer 251 and may be partially removed during the process, thus forming the second bent portion CH_sb. Data storage structure 245 may include a tunnel layer 241, a charge storage layer 242, and a barrier layer 243 stacked sequentially from channel layer 255. The tunnel layer 241 can tunnel charges into the charge storage layer 242 and may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or combinations thereof. The charge storage layer 242 may be a charge trapping layer or a floating gate conductive layer. The barrier layer 243 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), a high-k dielectric material, or combinations thereof. According to an example embodiment, at least a portion of the data storage structure 245 may form a channel dielectric layer extending horizontally along the gate electrode 230.

[0070] A conductive layer CP can be disposed on a stacked structure ST. In some example embodiments, the conductive layer CP can be a plate-shaped structure covering the stacked structure ST and can be configured to have flat lower and upper surfaces. The conductive layer CP can be disposed on and in contact with the first interlayer insulating layer 220a of the stacked structure ST. The conductive layer CP can cover the upper portion of the channel structure CH. The conductive layer CP can cover the head portion CH_1 of the channel structure CH and can be in contact with the conductive spacer layer 251 included in the outer region of the head portion CH_1. In some example embodiments, the conductive layer CP can cover the upper portion of the isolation region MS. In some example embodiments, the conductive layer CP can be spaced apart from a portion of the channel structure CH and the isolation region MS, and an insulating pattern can be disposed on that portion. The conductive layer CP can include a semiconductor material. For example, the conductive layer CP can include semiconductor materials such as group IV semiconductors, group III-V compound semiconductors, or group II-VI compound semiconductors. For example, group IV semiconductors can include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). The conductive layer CP can be used as the common source line (CSL) of the semiconductor device 10. The conductive layer CP may include a silicon layer (e.g., a silicon layer with N-type conductivity). For example, the conductive layer CP can be provided by a crystalline semiconductor layer (e.g., a single-crystal silicon layer, a polycrystalline silicon layer, or an epitaxial layer doped with impurities). In some example embodiments, the conductive layer CP may conformally cover the upper surface of the stacked structure ST, the upper portion of the channel structure CH, and the isolation region MS on the stacked structure ST. In some example embodiments, the conductive layer CP may include multiple conductive layers comprising different materials. For example, the conductive layer CP may include a first conductive layer and a second conductive layer, the first conductive layer covering the upper surface of the stacked structure ST, the upper portion of the channel structure CH, and the upper portion of the isolation region MS, and the second conductive layer disposed on the first conductive layer and comprising a material different from the first conductive layer. The first conductive layer may include a semiconductor material (e.g., a group IV compound semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor). For example, a group IV semiconductor may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). The second conductive layer may include at least one of a metal-semiconductor compound, a metal-nitride, and a metal (e.g., tungsten (W), copper (Cu), aluminum (Al)). The second conductive layer may be arranged perpendicular to the first conductive layer. The second conductive layer may have a multilayer structure, but exemplary embodiments are not limited thereto. For example, it may include a layered structure comprising an ohmic contact layer, a conductive layer, and a diffusion barrier.

[0071] The second semiconductor structure S2 may also include source contact vias and source interconnects disposed on the conductive layer CP, and may also include a passivation layer for protecting the components.

[0072] Upper interconnect structures 271 and 272 can electrically connect the gate electrode 230 and the channel structure CH to the circuit element 120. Upper interconnect structures 271 and 272 can include protrusions 272 connected to the channel structure CH. The protrusions 272 connected to the channel structure CH can be connected to the channel pads 259 of the channel structure CH. The protrusions 272 connected to the channel structure CH can be electrically connected to the conductive structure 250 in the cell region via the channel pads 259 of the channel structure CH. Upper interconnect structures 271 and 272 can include conductive materials (e.g., tungsten (W), copper (Cu), or aluminum (Al)), and each element can also include a diffusion barrier including at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or tungsten nitride (WN). According to an example embodiment, the number and arrangement of the protrusions 272 and upper interconnects 271 included in the upper interconnect structures 271 and 272 can vary.

[0073] The upper bonding structure 280 can be connected to the upper interconnect structures 271 and 272. For example, the protrusion 272 can be electrically connected to the upper bonding structure 280. The upper bonding structure 280 may include an upper bonding via 282, an upper bonding pad 284, and an upper bonding insulating layer 286. The upper bonding via 282 can be connected to the upper interconnect structure 270. The upper bonding pad 284 can be connected to the upper bonding via 282. The upper bonding via 282 and the upper bonding pad 284 may include conductive materials (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), and each element may also include a diffusion barrier. The upper bonding insulating layer 286 may also be used as a diffusion barrier for the upper bonding pad 284, and may include at least one of SiCN, SiO, SiN, SiOC, SiON, or SiOCN. The thickness of the upper bonding insulating layer 286 may be less than the thickness of the upper bonding pad 284, but its exemplary embodiments are not limited thereto.

[0074] In the following description, references will no longer be provided. Figure 1A , Figure 1B , Figure 1C and Figure 1D The descriptions overlap.

[0075] Figure 2A This is an enlarged cross-sectional view showing a portion of a semiconductor device according to an example embodiment, illustrating its relationship with... Figure 1C The corresponding area.

[0076] Figure 2B It shows along Figure 2A A plan view of a portion of a semiconductor device according to an example embodiment, taken by lines Ia-Ia', Ib-Ib', Ic-Ic', and Id-Id'.

[0077] refer to Figure 2Aand Figure 2B ,and Figure 1C and Figure 1D Different example implementations exist, where at least a portion of the channel structure CH may be devoid of voids, or even if voids exist, they may be invisible. In some example implementations, a first void 247V may be present, while a second void 249V may be absent. Conversely, a second void 249V may be present, while a first void 247V may be absent. The presence, number, and size of the first void 247V and the second void 249V can vary depending on the filling amount and shape of the first buried insulating layer 247 and the second buried insulating layer 249.

[0078] Figure 3 This is an enlarged cross-sectional view showing a portion of a semiconductor device according to an example embodiment, illustrating its relationship with... Figure 1C The corresponding area.

[0079] refer to Figure 3 ,and Figure 1C Unlike the example embodiments described above, the conductive spacer layer 251 may include a first conductivity type impurity. The first conductivity type impurity may be a P-type impurity or an N-type impurity. The conductive spacer layer 251 may include silicon doped with the first conductivity type impurity. The conductive layer CP may include the same first conductivity type impurity as the impurity included in the conductive spacer layer 251. For example, when the conductive spacer layer 251 includes an N-type impurity (e.g., phosphorus (P), arsenic (As), or antimony (Sb)), the conductive layer CP may also include an N-type impurity (e.g., phosphorus (P), arsenic (As), or antimony (Sb)). Conversely, when the conductive spacer layer 251 includes a P-type impurity (e.g., boron (B)), the conductive layer CP may also include a P-type impurity (e.g., boron (B)). The impurities included in the conductive spacer layer 251 may be formed by doping during the process. In some example embodiments, the impurities included in the conductive spacer layer 251 may diffuse into the channel layer 255. When the channel layer 255 includes impurities, the concentration of the first type of impurities included in the conductive spacer layer 251 can be greater than the concentration of the first type of impurities included in the channel layer 255. Even when the channel layer 255 includes the first type of impurities, the concentration of the first type of impurities in the channel layer 255 can be significantly lower than the concentration of the first type of impurities included in the conductive spacer layer 251.

[0080] Figure 4 This is an enlarged cross-sectional view showing a portion of a semiconductor device according to an example embodiment, illustrating its relationship with... Figure 1C The corresponding area.

[0081] refer to Figure 4At least a portion of the channel structure CH can have different thicknesses for the conductive spacer layer 251 and the channel layer 255. Since the conductive spacer layer 251 and the channel layer 255 are formed by separate processes, they can be formed with different thicknesses. In some example embodiments, the first thickness T1 of the conductive spacer layer 251 can be less than the second thickness T2 of the channel layer 255. The conductive spacer layer 251 can be formed with a relatively thin first thickness T1 to avoid bonding at the first bent portion CH_sa of the head portion CH_1, and the channel layer 255 can be formed with a relatively thick second thickness T2 to improve functionality.

[0082] Figure 5A This is a cross-sectional view of a semiconductor device according to an example embodiment, showing the relationship with... Figure 1B The corresponding area.

[0083] Figure 5B This is a cross-sectional view showing a portion of a semiconductor device according to an example embodiment, illustrating... Figure 5A Region "B" in the text.

[0084] refer to Figure 5A and Figure 5B ,and Figure 1A , Figure 1B , Figure 1C and Figure 1D Unlike semiconductor device 10, the stacked structure ST of semiconductor device 10a may include multiple levels GS1, GS2, and GS3. In some example embodiments, the stacked structure ST may include three to five levels and may include, for example... Figure 5A The three layers are shown. The interlayer insulation layer 220 may include a third interlayer insulation layer 220c positioned at the bottom of each layer. In some example embodiments, the third interlayer insulation layer 220c may be formed to have a thickness greater than that of the intermediate interlayer insulation layer 225. Due to width differences or variations at the boundaries of each layer, the channel structure CH may include a third curved portion CH_sc. The isolation region MS may include a curved portion positioned at the same level as the third curved portion CH_sc.

[0085] Figure 6 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an example embodiment.

[0086] Figure 7 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment, showing... Figure 6 The process of forming the channel structure CH (S400).

[0087] Figure 8 , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16 , Figure 17A , Figure 18 , Figure 19 , Figure 20 and Figure 21A This is an enlarged cross-sectional view showing the process of manufacturing a semiconductor device according to an exemplary embodiment, in sequence, illustrating the relationship with... Figure 1B The corresponding area.

[0088] Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 17B and Figure 21B This is an enlarged cross-sectional view showing a portion of the process of manufacturing a semiconductor device according to an exemplary embodiment, illustrating the relationship with... Figure 1C The corresponding area is "A".

[0089] refer to Figure 6 and Figure 8 An etch stop structure 350 (S100) can be formed on the substrate 300.

[0090] The substrate 300 may include a semiconductor material (e.g., a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor).

[0091] An etch stop structure 350 can be formed by etching a portion of the substrate 300 and filling the etched area with an etch stop material. In some example embodiments, the etch stop structure 350 may have a downwardly decreasing width. The etch stop structure 350 may include a material that is etch-selective relative to the material included in the molded structure MT formed in subsequent processes. In some example embodiments, the etch stop structure 350 may include tungsten (W). It can be formed in the region corresponding to the head portion CH_1. Figure 1A , Figure 1B , Figure 1C and Figure 1D The channel structure CH in the middle.

[0092] refer to Figure 6 as well as Figure 9A and Figure 9BA molded structure MT can be formed (S200) by alternately stacking interlayer insulating layer 220 and sacrificial insulating layer 218 on substrate 300, and a channel hole CHH extending into the molded structure MT can be formed (S300).

[0093] At least a portion of the sacrificial insulating layer 218 can be replaced by a portion of the gate electrode 230 through a subsequent process. The sacrificial insulating layer 218 can be formed of a different material than the interlayer insulating layer 220. For example, the interlayer insulating layer 220 can be formed of at least one of silicon oxide or silicon nitride, and the sacrificial insulating layer 218 can be formed of a material other than the interlayer insulating layer 220, selected from silicon, silicon oxide, silicon carbide, or silicon nitride. In the example embodiment, the thickness of the interlayer insulating layer 220 can be different. Furthermore, the thicknesses of the interlayer insulating layer 220 and the sacrificial insulating layer 218, as well as the number of films included, can differ from the example shown.

[0094] The channel hole CHH can be formed by penetrating the molded structure MT in the vertical direction through the etch stop structure 350 formed on the substrate 300. The channel hole CHH can be formed by anisotropic etching of the molded structure MT using a mask pattern. By etching the etch stop structure 350, the channel hole CHH can be formed to have a uniform depth.

[0095] refer to Figure 10A and Figure 10B as well as Figure 6 and Figure 7 The channel hole CHH can be extended by removing the etch stop structure 350, and a data storage structure 245 can be formed in the channel hole CHH (S410).

[0096] The data storage structure 245 can be formed to have a uniform thickness within the channel via CHH. The data storage structure 245 may include multiple dielectric layers. The data storage structure 245 can be formed by sequentially depositing insulating material, including the multiple layers included in the data storage structure 245, within the channel via CHH.

[0097] refer to Figure 11A and Figure 11B as well as Figure 6 and Figure 7 A first semiconductor material layer 251P can be formed as a preliminary conductive spacer layer by depositing a first semiconductor material on the data storage structure 245 (S420).

[0098] A first semiconductor material layer 251P can be formed by depositing a semiconductor material such as polysilicon on the data storage structure 245. The first semiconductor material layer 251P can be formed to cover the data storage structure 245 to have a uniform thickness. By controlling the thickness of the first semiconductor material layer 251P, the aperture space H can be maintained to extend into the substrate 300.

[0099] refer to Figure 12A and Figure 12B as well as Figure 6 and Figure 7 A first buried insulating layer 247 can be formed on the first semiconductor material layer 251P (S430).

[0100] The first buried insulating layer 247 can be formed by filling the hole space H in the channel hole CHH with an insulating material and then removing a portion of the formed insulating material downwards. In some example embodiments, the channel hole CHH can be formed with a downwardly decreasing width, and the insulating material filling the hole space H can be removed from the top and etched to a level with a target width. The upper surface of the first buried insulating layer 247 can be formed at a level overlapping with the first interlayer insulating layer 220a. That is, the upper surface of the first buried insulating layer 247 can be formed at a level lower than the level of the upper surface of the first interlayer insulating layer 220a and higher than the level of the lower surface of the first interlayer insulating layer 220a.

[0101] refer to Figure 13A and Figure 13B as well as Figure 6 and Figure 7 The conductive spacer layer 251 can be formed by partially removing the first semiconductor material layer 251P (S440).

[0102] The conductive spacer layer 251 can be formed by partially removing the first semiconductor material layer 251P from its upper portion. The first semiconductor material layer 251P can be removed up to the upper surface of the first buried insulating layer 247. According to the etching method of partially removing the first semiconductor material layer 251P from its upper portion, the upper portion of the conductive spacer layer 251 can have an inwardly curved shape. In some example embodiments, the crystalline state of the material included in the conductive spacer layer 251 can be an amorphous state. In some example embodiments, the conductive spacer layer 251 can be crystallized (S445) by a process such as annealing, and in this case, the conductive spacer layer 251 can have a crystalline structure. In some example embodiments, the annealing process can be performed at a temperature of 500°C or higher (e.g., it can be performed at about 600°C). In some example embodiments, the process of crystallizing the conductive spacer layer 251 may not be performed.

[0103] refer to Figure 14A and Figure 14B as well as Figure 6 and Figure 7 A channel layer 255 can be formed on the conductive spacer layer 251 and the data storage structure 245 (S450).

[0104] The channel layer 255 can be formed by depositing semiconductor material on the conductive spacer layer 251, the first buried insulating layer 247, and the data storage structure 245. The channel layer 255 can be formed to uniformly cover the conductive spacer layer 251, the first buried insulating layer 247, and the data storage structure 245. The channel layer 255 may include a folded portion 255a covering the upper surface of the first buried insulating layer 247 and a channel portion 255b covering the data storage structure 245.

[0105] refer to Figure 15A and Figure 15B as well as Figure 6 and Figure 7 A second buried insulating layer 249 can be formed on the channel layer 255 (S460), the channel layer 255 can be crystallized (S470), and channel pads can be formed (S480). Accordingly, a channel structure CH can be formed (S400).

[0106] A second buried insulating layer 249 can be formed by filling the pore space H on the trench layer 255 with insulating material. The trench layer 255 can be crystallized by an annealing process or a metal-induced lateral crystallization (MILC) process.

[0107] In some example embodiments, the channel layer 255 can be crystallized by an annealing process. When the channel layer 255 is crystallized by an annealing process, the grain size of the channel layer 255 can be different from the grain size of the conductive spacer layer 251. That is, the channel layer 255 can have a crystal state different from the crystal state of the conductive spacer layer 251. When the process of crystallizing the conductive spacer layer 251 (S445) is not performed, the conductive spacer layer 251 can be crystallized together with the channel layer 255 by an annealing process. Even in this case, the conductive spacer layer 251 and the channel layer 255 formed by different processes can have different grain sizes. In some example embodiments, the grain size of the channel layer 255 can be larger than the grain size of the conductive spacer layer 251. For example, the grain size of the channel layer 255 can be at least five times the grain size of the conductive spacer layer 251. In some example implementations, the annealing process can be performed at 500°C or higher (e.g., at about 600°C).

[0108] In some example embodiments, the channel layer 255 can be crystallized using a metal-induced lateral crystallization (MILC) process. The MILC process may include, for example, forming a metal layer on the upper portion of the channel layer 255 in contact with the channel layer 255, performing a heat treatment on the metal layer to implant metal particles into the channel layer 255, and crystallizing the channel layer 255 from an amorphous state to a crystalline state (specifically, a single-crystal state) as the metal particles diffuse along the channel layer 255 toward the substrate 300. The diffusion of the metal particles that crystallize the channel layer 255 can proceed to the conductive spacer layer 251 crystallized in process S445. That is, the metal particles used in the MILC process can remain in the channel layer 255 and will not diffuse into the conductive spacer layer 251. Because the MILC process is performed to crystallize the amorphous state into a crystalline state, the diffusion of metal particles into the conductive spacer layer 251 can be prevented because the crystallization of the conductive spacer layer 251 is preferentially performed (S445). The channel layer 255 can be made into a single-crystal or near-single-crystal structure by the MILC process, and the conductive spacer layer 251, crystallized by the annealing process in process S445, can have a polycrystalline structure. Therefore, the channel layer 255 and the conductive spacer layer 251 can have different crystal states. The metal layer used in the MILC process can include, for example, nickel (Ni), titanium (Ti), cobalt (Co), tungsten (W), platinum (Pt), palladium (Pd), or combinations thereof, and the metal particles can be at least one of these metals. After crystallizing the channel layer 255 by the MILC process, a gettering process can be performed to remove the metal layer and the metal particles in the channel layer 255. In some example embodiments, trace amounts of metal particles may remain in the channel layer 255, but even in this case, the metal particles used in the MILC process will not be present in the conductive spacer layer 251. By preventing metal particles from remaining in the conductive spacer layer 251, defects such as breakage or isolation in the conductive spacer layer 251 can be prevented in subsequent processes. Since the conductive spacer layer 251 and the channel layer 255 have different crystal states, a channel interface surface 250s can exist between them.

[0109] The channel pad 259 may be formed on the second buried insulating layer 249 and may be in contact with the channel layer 255. The channel pad 259 may be formed of a conductive material (e.g., polysilicon).

[0110] pass Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A and Figure 15B The process described above can form a channel structure CH (S400) in the channel hole CHH.

[0111] refer to Figure 16 This can form an isolation opening OP corresponding to the isolation zone MS.

[0112] The isolation opening OP can be formed as a line intersecting the cell region and the extension region in the Y direction, and can penetrate the molded structure MT in the Z direction. The isolation opening OP can be formed to remove a portion of the substrate 300, thereby opening a portion of the substrate 300.

[0113] refer to Figure 17A and Figure 17B The sacrificial insulating layer 218 can be removed, the gate electrode 230 (S500) can be formed, and the insulating region SS can be formed.

[0114] The sacrificial insulating layer 218 can be selectively removed relative to the interlayer insulating layer 220 by performing wet etching using the isolation opening OP. The gate electrode 230 can be formed by depositing a conductive material on the region where the sacrificial insulating layer 218 has been removed. The conductive material may include metal, polysilicon, or metal silicide. In some example embodiments, a portion of the gate dielectric layer may be preferentially formed before forming the gate electrode 230. After forming the gate electrode 230, an isolation insulating layer 264 can be formed in the isolation opening OP corresponding to the isolation region MS, and the insulating region SS can be formed by etching at least one second gate electrode 230b.

[0115] refer to Figure 18 It can form an upper interconnection structure 271 and 272 including a protrusion 272 and an upper interconnection line 271, and can form an upper bonding structure 280.

[0116] Within the cell area, protrusions 272 can be formed to connect to the channel structure CH. The protrusions 272 can be vertically connected to the upper interconnect 271, and can be connected in a multi-layer manner via plugs.

[0117] Subsequently, the upper bonding structure 280 can be formed using a method similar to that used to form the lower bonding structure 180. Thus, a second semiconductor structure S2 (memory cell structure CELL) can be formed. During the manufacturing process of the semiconductor device 10, the second semiconductor structure S2 can be in a state that also includes the substrate 300.

[0118] refer to Figure 19 as well as Figure 6The second semiconductor structure S2 can be flipped up and down to expose the substrate 300 upwards, and can be bonded to the first semiconductor structure S1 (S600).

[0119] In the example implementation, the sequence of processes for bonding the second semiconductor structure S2 to the first semiconductor structure S1 can be performed after the processes described later (S700, S800, S900). For example, the second semiconductor structure S2 can be bonded to the first semiconductor structure S1 after the formation of the conductive layer CP (S900).

[0120] The first semiconductor structure S1 can be formed including circuit elements 120, a lower interconnect structure 130, a lower bonding structure 180, and a lower capping layer 190, which form a peripheral circuit structure PERI on a first substrate 101. First, a device isolation layer 110 can be formed in the first substrate 101, and a circuit gate dielectric layer 122 and a circuit gate electrode 124 can be sequentially formed on the first substrate 101. The device isolation layer 110 can be formed, for example, by a shallow trench isolation (STI) process. The circuit gate dielectric layer 122 can be formed on the first substrate 101, and the circuit gate electrode 124 can be formed on the circuit gate dielectric layer 122. The circuit gate dielectric layer 122 and the circuit gate electrode 124 can be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The circuit gate dielectric layer 122 can be formed of silicon oxide, and the circuit gate electrode 124 can be formed of at least one of polysilicon or metal silicide layers, but exemplary embodiments are not limited thereto. Subsequently, spacer layers 126 can be formed on both sides of the circuit gate dielectric layer 122 and the circuit gate electrode 124, and source / drain regions 105 can be formed by implanting impurities in the active region of the first substrate 101 on both sides of the circuit gate electrode 124.

[0121] The lower contact plug 135 of the lower interconnect structure 130 can be formed by forming a portion of the lower capping layer 190, removing a portion by etching, and filling it with conductive material. The lower interconnect 137 can be formed, for example, by depositing conductive material and patterning the material.

[0122] The lower bonding via 182 of the lower bonding structure 180 can be formed by forming a portion of the lower capping layer 190, removing a portion by etching, and filling it with conductive material. The lower bonding pad 184 can be formed, for example, by depositing conductive material and patterning the material. The lower bonding structure 180 can be formed, for example, by deposition or electroplating processes. The lower bonding insulating layer 186 can be formed by covering the upper surface and a portion of the side surface of the lower bonding pad 184 and performing a planarization process until the upper surface of the lower bonding pad 184 is exposed.

[0123] The lower capping layer 190 may include multiple insulating layers. A portion of the lower capping layer 190 may be formed in each of the processes forming the lower interconnect structure 130 and the lower bonding structure 180. Thus, a first semiconductor structure S1, namely the peripheral circuit structure PERI, can be formed. Since the process for the first semiconductor structure S1 is performed differently from the process for the second semiconductor structure S2, one of the processes may be performed preferentially or simultaneously.

[0124] The second semiconductor structure S2 (cell structure) can be flipped vertically, exposing the substrate 300 on top. The stacked structure ST can be positioned below the substrate 300, and the second semiconductor structure S2 can be bonded to the first semiconductor structure S1 (peripheral circuit structure PERI). The first semiconductor structure S1 and the second semiconductor structure S2 can be connected by applying pressure to bond the lower bonding pad 184 to the upper bonding pad 284. The lower bonding insulating layer 186 and the upper bonding insulating layer 286 can be connected by applying pressure. The second semiconductor structure S2 can be bonded to the first semiconductor structure S1, allowing the upper bonding pad 284 to face downwards. The first semiconductor structure S1 and the second semiconductor structure S2 can be directly bonded to each other without the need for an intermediate adhesive (e.g., an adhesive layer).

[0125] refer to Figure 20 and Figure 6 The substrate 300 (S700) can be removed.

[0126] The substrate 300 can be removed from the upper surface, for example, by a polishing process (e.g., a grinding process), and another portion can be removed by an etching process (e.g., wet etching). After removing the substrate 300, the upper end of the channel structure CH and the upper end of the isolation region MS can be exposed.

[0127] refer to Figure 21A and Figure 21B as well as Figure 6 By removing a portion of the data storage structure 245, the conductive spacer layer 251 can be exposed (S800).

[0128] The data storage structure 245 can be removed using photolithography and etching processes (e.g., wet etching and / or dry etching). This exposes a portion of the conductive spacer layer 251. The channel structure CH may include a head portion CH_1 exposed on the upper surface of the first interlayer insulating layer 220a and a through portion CH_2 extending into the stacked structure ST. As a portion of the data storage structure 245 is removed, a first bent portion CH_sa and a second bent portion CH_sb of the channel structure CH can be formed.

[0129] Please refer to the following text. Figure 1A , Figure 1B , Figure 1C and Figure 1D It can form a conductive layer CP (S900).

[0130] The conductive layer CP can be formed to cover the channel structure CH and the isolation region MS protruding from the upper surface of the first interlayer insulating layer 220a, as well as the first interlayer insulating layer 220a. The conductive layer CP can be formed by specifically depositing a crystalline silicon layer (e.g., a polycrystalline silicon layer). Therefore, it is possible to fabricate... Figure 1A , Figure 1B , Figure 1C and Figure 1D Semiconductor device 10 in the middle.

[0131] Figure 22 This is a diagram illustrating a data storage system including a semiconductor device according to an example embodiment.

[0132] refer to Figure 22 The data storage system 1000 may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The data storage system 1000 may be implemented as a storage device including one or more semiconductor devices 1100 or an electronic device including such a storage device. For example, the data storage system 1000 may be implemented as a solid-state drive (SSD), a universal serial bus (USB), a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0133] Semiconductor device 1100 can be implemented as a non-volatile memory device, for example, reference Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 2A , Figure 2B , Figure 3 , Figure 4 , Figure 5A and Figure 5BThe NAND flash memory device described in the foregoing example embodiments. Semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In the example embodiment, the first structure 1100F may be disposed on the side of the second structure 1100S. The first structure 1100F may be configured as a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and logic circuit 1130. The second structure 1100S may be configured as a memory cell structure including a bit line BL, a common source line CSL, a word line WL, a first upper gate line UL1 and a second upper gate line UL2, a first lower gate line LL1 and a second lower gate line LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0134] In the second structure 1100S, each memory cell string CSTR may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. In the example embodiment, the number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may vary.

[0135] In the example implementation, upper transistors UT1 and UT2 may include string select transistors, and lower transistors LT1 and LT2 may include ground select transistors. Lower gate lines LL1 and LL2 may be configured as gate electrodes of lower transistors LT1 and LT2, respectively. Word line WL may be configured as gate electrode 230 of memory cell transistor MCT, and upper gate lines UL1 and UL2 may be configured as gate electrodes of upper transistors UT1 and UT2, respectively.

[0136] In an example implementation, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground select transistor LT2 connected in series with each other. The upper transistors UT1 and UT2 may include a string select transistor UT1 and an upper erase control transistor UT2 connected in series with each other.

[0137] The common source line CSL, the first lower gate line LL1, the second lower gate line LL2, the word line WL, and the first upper gate line UL1 and the second upper gate line UL2 can be electrically connected to the decoder circuit 1110 via a first interconnect 1115 extending from the first structure 1100F to the second structure 1100S. The bit line BL can be electrically connected to the page buffer 1120 via a second interconnect 1125 extending from the first structure 1100F to the second structure 1100S.

[0138] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform control operations on at least one selected memory cell transistor among a plurality of memory cell transistors (MCTs). The decoder circuit 1110 and the page buffer 1120 can be controlled by logic circuit 1130. The semiconductor device 1100 can communicate with the controller 1200 via input / output pads 1101 electrically connected to the logic circuit 1130. The input / output pads 1101 can be electrically connected to the logic circuit 1130 via input / output interconnects 1135 extending from the first structure 1100F to the second structure 1100S.

[0139] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. In an example embodiment, the data storage system 1000 may include a plurality of semiconductor devices 1100, and in this case, the controller 1200 may control the plurality of semiconductor devices 1100.

[0140] Processor 1210 can control the operation of data storage system 1000, including controller 1200. Processor 1210 can operate according to predetermined firmware and can access semiconductor device 1100 by controlling NAND controller 1220. NAND controller 1220 may include controller interface 1221 for handling communication with semiconductor device 1100. Through controller interface 1221, control commands for controlling semiconductor device 1100, data to be written to memory cell transistors (MCTs) of semiconductor device 1100, and data to be read from memory cell transistors (MCTs) of semiconductor device 1100 can be transmitted. Host interface 1230 provides communication functionality between data storage system 1000 and external host. When a control command is received from external host through host interface 1230, processor 1210 can control semiconductor device 1100 in response to the control command.

[0141] Figure 23 This is a perspective view showing a data storage system including a semiconductor device according to an example embodiment.

[0142] refer to Figure 23 In some example implementations, the data storage system 2000 may include a motherboard 2001, a controller 2002 mounted on the motherboard 2001, one or more semiconductor packages 2003 and DRAM 2004. The semiconductor packages 2003 and DRAM 2004 may be connected to the controller 2002 via interconnect patterns 2005 formed on the motherboard 2001.

[0143] The motherboard 2001 may include a connector 2006, which includes a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the data storage system 2000 and the external host. In an example embodiment, the data storage system 2000 may communicate with the external host via one of the interfaces from Universal Serial Bus (USB), Peripheral Component Interconnect Fast (PCI-Fast), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Memory (UFS). In an example embodiment, the data storage system 2000 may operate via power supplied from the external host via the connector 2006. The data storage system 2000 may also include a power management integrated circuit (PMIC) for distributing power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0144] The controller 2002 can write data to or read data from the semiconductor package 2003, and can improve the operating speed of the data storage system 2000.

[0145] DRAM 2004 can be configured as a buffer memory to mitigate the speed difference between the semiconductor package 2003, which serves as data storage space, and an external host. The DRAM 2004 included in the data storage system 2000 can operate as a cache memory and can provide space for temporary data storage during control operations on the semiconductor package 2003. When the data storage system 2000 includes DRAM 2004, in addition to the NAND controller for controlling the semiconductor package 2003, the controller 2002 may also include a DRAM controller for controlling the DRAM 2004.

[0146] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be configured as a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, adhesive layers 2300 disposed on the lower surface of the semiconductor chips 2200, bonding structures 2400 electrically connecting the semiconductor chips 2200 to the package substrate 2100, and a molding layer 2500 covering the semiconductor chips 2200 and the bonding structures 2400 on the package substrate 2100.

[0147] The package substrate 2100 can be configured as a printed circuit board including on-package pads 2130. Each semiconductor chip 2200 may include input / output pads 2210. The input / output pads 2210 may correspond to... Figure 22 The input / output pads 1101 are included. Each semiconductor chip 2200 may include a gate stack structure 3210 and a channel structure 3220. Each semiconductor chip 2200 may include a reference. Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 2A , Figure 2B , Figure 3 , Figure 4 , Figure 5A and Figure 5B The semiconductor device described in the foregoing example embodiments.

[0148] In an example embodiment, the bonding structure 2400 can be configured to electrically connect the input / output pads 2210 to bonding wiring on the package pads 2130. Accordingly, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 can be electrically connected to each other via bonding wiring and can be electrically connected to the package pads 2130 on the package substrate 2100. In an example embodiment, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 can be electrically connected to each other via an interconnection structure including through-silicon vias (TSVs), rather than via the bonding structure 2400 of the bonding wiring method.

[0149] In some example implementations, the controller 2002 and the semiconductor chip 2200 may be included in a single package. In some example implementations, the controller 2002 and the semiconductor chip 2200 may be mounted on a different interposer substrate than the motherboard 2001, and the controller 2002 and the semiconductor chip 2200 may be interconnected with each other via interconnects formed on the interposer substrate.

[0150] According to the foregoing exemplary embodiments, in a structure in which two or more semiconductor structures are joined together, the channel structure may include a conductive spacer layer in contact with a conductive layer, and a channel layer extending into the gate electrode and the interlayer insulating layer. The channel layer may include a folded portion positioned at the level where the adjacent first interlayer insulating layer overlaps, thereby preventing defects in the conductive spacer layer during fabrication. Therefore, semiconductor devices with improved integration density and reliability, as well as data storage systems including such semiconductor devices, can be provided.

[0151] According to an exemplary embodiment of this disclosure, a method of manufacturing a semiconductor device includes: preparing a substrate including an etch stop structure on an upper surface; forming a molded structure by alternately stacking an interlayer insulating layer and a sacrificial insulating layer on the substrate; penetrating the molded structure to expose the etch stop structure, and forming a channel via including a head portion by removing the etch stop structure; forming a data storage structure in the channel via; forming a conductive spacer layer on the data storage structure and a first buried insulating layer on the conductive spacer layer in the head portion; and forming a channel layer covering the data storage structure, the conductive spacer layer and the first buried insulating layer, and a second buried insulating layer on the channel layer.

[0152] The channel layer and the conductive spacer layer have different crystal structures.

[0153] The channel layer has a single-crystal structure, while the conductive spacer layer has a polycrystalline structure.

[0154] The channel layer and the conductive spacer layer have a crystalline structure, and the grain size of the channel layer is larger than that of the conductive spacer layer.

[0155] The grain size of the channel layer is at least 5 times that of the grain size of the conductive spacer layer.

[0156] The method also includes crystallizing the channel layer by performing the crystallization of the channel layer through a metal-induced lateral crystallization (MILC) process.

[0157] The method further includes: crystallizing the conductive spacer layer prior to forming the channel layer, and performing the crystallization of the conductive spacer layer by an annealing process at 500°C or higher.

[0158] The method further includes crystallizing the channel layer, wherein the crystallization of the channel layer is performed by an annealing process at a temperature of 500°C or higher.

[0159] The method also includes: removing the substrate, removing a portion of the data storage structure, and exposing the conductive spacer layer.

[0160] The method further includes forming a conductive layer covering the conductive spacer layer after exposing the conductive spacer layer.

[0161] Although this specification contains numerous specific implementation details, these details should not be construed as limiting the scope of any invention or the scope that may be claimed, but rather as descriptions of features that may be specific to particular embodiments of a particular invention. Certain features described in this specification within the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented individually in multiple embodiments, or in any suitable sub-combination. Furthermore, although features may be described above as functioning in certain combinations, one or more features in a combination may be removed from the combination in some cases, and the combination may be for sub-combinations or variations thereof.

[0162] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and alterations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A semiconductor device, comprising: A first semiconductor structure includes a first substrate, circuit elements on the first substrate, a lower interconnect structure connected to the circuit elements, and a lower bonding structure connected to the lower interconnect structure. as well as A second semiconductor structure is connected to the first semiconductor structure. The second semiconductor structure includes: conductive layer A stacked structure, below the conductive layer, includes an interlayer insulating layer and a gate electrode stacked in a first direction perpendicular to the lower surface of the conductive layer. The upper interconnect structure is located below the stacked structure. The upper bonding structure is connected to the upper interconnect structure and bonded to the lower bonding structure, and The channel structure extends into the stacked structure in the first direction and protrudes to the upper surface of the stacked structure. Each of the channel structures includes a through portion extending into the stacked structure and a head portion protruding to the upper surface of the stacked structure. Each of the channel structures includes: A conductive spacer layer forms the outer region of the head portion and is in contact with the conductive layer. The first buried insulating layer is on the inner surface of the conductive spacer layer. The trench layer, in the through portion, includes a folded portion covering the lower surface of the first buried insulating layer, and a trench portion extending from the lower end of the conductive spacer layer in the first direction. A second buried insulation layer is located on the inner surface of the trench layer and is spaced apart from the first buried insulation layer. Data storage structure on the outer surface of the channel layer.

2. The semiconductor device according to claim 1, wherein, The channel layer and the conductive spacer layer have different crystal structures.

3. The semiconductor device according to claim 1, in, The channel layer has a single-crystal structure, and The conductive spacer layer has a polycrystalline structure.

4. The semiconductor device according to claim 1, in, The channel layer and the conductive spacer layer have a crystalline structure, and The grain size of the channel layer is larger than the grain size of the conductive spacer layer.

5. The semiconductor device according to claim 4, wherein, The grain size of the channel layer is at least five times the grain size of the conductive spacer layer.

6. The semiconductor device according to claim 1, wherein, The conductive spacer layer and the conductive layer comprise a semiconductor material containing impurities of a first conductivity type.

7. The semiconductor device according to claim 6, wherein, The concentration of impurities of the first conductivity type in the conductive spacer layer is greater than the concentration of impurities of the first conductivity type in the channel layer.

8. The semiconductor device according to claim 1, in, The stacked structure includes an uppermost interlayer insulating layer on the lower surface of the conductive layer, and The folded portion of the channel layer overlaps with the uppermost interlayer insulation layer in a direction perpendicular to the first direction.

9. The semiconductor device according to claim 1, wherein, The data storage structure covers a portion of the outer surface of the conductive spacer layer.

10. The semiconductor device according to claim 1, wherein, In each of the channel structures, the thickness of the conductive spacer layer is less than the thickness of the channel layer.

11. The semiconductor device according to claim 1, wherein, At least a portion of the trench structure includes a first void in the first buried insulation layer.

12. The semiconductor device according to claim 1, in, The stacked structure includes an uppermost interlayer insulating layer on the lower surface of the conductive layer, and The boundary surface between the conductive spacer layer and the channel layer overlaps with the uppermost interlayer insulating layer in a direction perpendicular to the first direction.

13. The semiconductor device according to claim 1, wherein, The upper end of the data storage structure is higher than the upper end of the channel layer.

14. A semiconductor device, comprising: Gate electrodes are spaced apart from each other in a first direction, and the gate electrodes include an uppermost gate electrode; A channel structure extending in the first direction and into the gate electrode, each channel structure including a channel layer, a channel-filling insulating layer on the inner surface of the channel layer, a data storage structure on the outer surface of the channel layer, and a conductive spacer layer on the channel layer. as well as A conductive layer is in contact with the conductive spacer layer of the channel structure on the uppermost gate electrode. Wherein, the channel layer of each of the channel structures includes: The channel portion extends in the first direction, and The folded portion bends from the channel portion at a level higher than the upper surface of the uppermost gate electrode, and covers the upper end of the channel-filling insulating layer. In a plan view parallel to the lower surface of the conductive layer, the minimum width of the channel layer is greater than the minimum width of the conductive spacer layer, but less than the maximum width of the conductive spacer layer.

15. The semiconductor device according to claim 14, in, Each of the channel structures includes a curved portion formed by a width step difference, and The curved portion includes a first curved portion located at a level overlapping with the conductive layer, and a second curved portion located at a level lower than the first curved portion and higher than the level of the upper surface of the uppermost gate electrode.

16. The semiconductor device according to claim 15, in, Each of the channel structures includes a through portion extending into the gate electrode and a head portion protruding into the conductive layer, and The second curved portion is located between the through portion and the head portion.

17. The semiconductor device according to claim 14, wherein, In the plan view, the folded portion has a circular, elliptical, or polygonal shape, and the data storage structure surrounds the folded portion.

18. The semiconductor device according to claim 14, wherein, In the plan view, the channel portion is filled with an insulating layer at a level lower than that of the folded portion.

19. The semiconductor device according to claim 14, wherein, The upper surface of the folded portion has an outwardly curved shape that protrudes toward the conductive layer.

20. A data storage system, comprising: A semiconductor memory device includes a first semiconductor structure, a second semiconductor structure, and input / output pads. The first semiconductor structure includes a substrate and circuit elements on the substrate. The second semiconductor structure is on the first semiconductor structure, and the input / output pads are electrically connected to the circuit elements. as well as The controller is electrically connected to the semiconductor memory device via the input / output pads and controls the semiconductor memory device. The second semiconductor structure includes: conductive layer A stacked structure, below the conductive layer, and including an interlayer insulating layer and a gate electrode stacked in a first direction perpendicular to the lower surface of the conductive layer, and The channel structure extends into the stacked structure in the first direction and protrudes to the upper surface of the stacked structure. Each of the channel structures includes a through portion extending into the stacked structure and a head portion protruding to the upper surface of the stacked structure. Each of the channel structures includes: A conductive spacer layer defines the outer region of the head portion and is in contact with the conductive layer. The first buried insulating layer is on the inner surface of the conductive spacer layer. The trench layer, in the through portion, includes a folded portion covering the lower surface of the first buried insulating layer, and a trench portion extending from the lower end of the conductive spacer layer in the first direction. A second buried insulation layer is located on the inner surface of the trench layer and is spaced apart from the first buried insulation layer. Data storage structure on the outer surface of the channel layer.

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