Semiconductor device and method of manufacturing the same

Abstract

The present application relates to a semiconductor device and a method of manufacturing the same. According to an embodiment of the present disclosure, a semiconductor device can include a first semiconductor structure including a peripheral circuit and a peripheral bonding pad connected to the peripheral circuit, and a second semiconductor structure including a cell bonding pad bonded to the peripheral bonding pad, a plurality of first wirings connected to the cell bonding pad, a plurality of spacers respectively disposed on side surfaces of the plurality of first wirings, and a first insulating layer covering side surfaces of the plurality of spacers and a lower surface of the plurality of first wirings, the first insulating layer having air gaps disposed between the plurality of spacers.

Description

Cross-reference to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2025-0052736, filed on April 23, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0002] Embodiments of this disclosure relate to a semiconductor device and a method for manufacturing the same. Background Technology

[0003] Due to their miniaturization, multifunctionality, and low manufacturing cost, memory devices have become key components in the electronics industry. With the development of the electronics industry, the integration level of memory devices is also increasing.

[0004] As the integration density of memory cells increases, the spacing between wirings in memory devices can be reduced. However, this reduced spacing can lead to interference between adjacent wirings. Summary of the Invention

[0005] The purposes of this disclosure are not limited to those mentioned herein, and other purposes not mentioned will be clearly understood by those skilled in the art based on the following description.

[0006] Embodiments of this disclosure may provide a semiconductor device and a method for manufacturing the same, wherein interference between wirings can be minimized.

[0007] Embodiments of this disclosure may provide a semiconductor device, including: a first semiconductor structure including peripheral circuitry and peripheral bonding pads connected to the peripheral circuitry; and a second semiconductor structure including unit bonding pads bonded to the peripheral bonding pads, a plurality of first wirings connected to the unit bonding pads, a plurality of spacers disposed on the side surfaces of the plurality of first wirings, and a first insulating layer covering the side surfaces of the plurality of spacers and the lower surfaces of the plurality of first wirings and having an air gap disposed between the plurality of spacers.

[0008] Embodiments of this disclosure may provide a semiconductor device, including: a first semiconductor structure including peripheral circuitry; and a second semiconductor structure bonded to the first semiconductor structure. The second semiconductor structure may include a plurality of first wirings, each first wiring including a first wiring portion and a second wiring portion continuous with the first wiring portion, the second wiring portion having a variable width, the maximum width of the second wiring portion being greater than the width of the first wiring portion; and a first insulating layer having an air gap disposed between the plurality of first wirings.

[0009] Embodiments of this disclosure may provide a method for manufacturing a semiconductor device, comprising: forming a plurality of first trenches in a second insulating layer on a substrate; forming a plurality of spacers on side surfaces of the plurality of first trenches respectively; forming a plurality of first wirings in the plurality of first trenches respectively; removing the insulating layer; and forming a first insulating layer having an air gap formed between the plurality of spacers.

[0010] According to embodiments of this disclosure, a semiconductor device and a method for manufacturing the same can be provided that minimize interference between wirings.

[0011] The effects of the embodiments disclosed herein are not limited to those described above, and those skilled in the art will clearly understand, based on the appended claims, additional effects not mentioned. Attached Figure Description

[0012] This disclosure will be more fully understood through the following detailed description and accompanying drawings; however, these detailed descriptions and drawings are provided for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0013] Figure 1 This is a cross-sectional view illustrating an example of a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 2 yes Figure 1 A magnified view of the central area 197.

[0015] Figure 3 yes Figure 1 A magnified view of the central area 199.

[0016] Figure 4 This is another cross-sectional view showing a semiconductor device according to an embodiment of the present disclosure.

[0017] Figures 5 to 19 This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0018] Figures 20 to 25 This is a cross-sectional view illustrating another example of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Detailed Implementation

[0019] In the following description of examples or embodiments of this disclosure, reference will be made to the accompanying drawings, in which specific examples or embodiments that may be implemented are illustrated by way of illustration, and wherein the same reference numerals and symbols may be used to denote the same or similar components even when they are shown in different drawings. Furthermore, in the following description of examples or embodiments of this disclosure, detailed descriptions of well-known functions and components incorporated herein are omitted where it is determined that the description might obscure the subject matter of some embodiments of this disclosure. The terms “comprising,” “having,” “containing,” “constituting,” “made of,” and “formed from” as used herein are generally intended to allow for the addition of additional components unless these terms are used in conjunction with the term “only.” As used herein, the singular forms are intended to include the plural forms unless the context clearly indicates otherwise.

[0020] Elements of this disclosure may be described using terms such as “first,” “second,” “A,” “B,” “(A),” or “(B).” These terms are not intended to define the nature, order, sequence, or number of elements, but are only used to distinguish the corresponding element from other elements.

[0021] When referring to a first element as "connected or coupled to," "in contact with," or "overlapping" with a second element, it should be understood that the first element can not only be "directly connected or coupled to" or "directly contact or overlap" with the second element, but also that a third element can be "inserted" between the first and second elements, or that the first and second elements can be "connected or coupled," "in contact with," or "overlapped" with each other through a fourth element. Here, the second element may be included in at least one of two or more elements that are "connected or coupled," "in contact with," or "overlap" with each other.

[0022] When time-relative terms (such as “after,” “following,” “next,” “before,” etc.) are used to describe a process or operation of an element or configuration, or a flow or step in an operation, process, or manufacturing method, these terms may be used to describe a discontinuous or non-sequential process or operation, unless used with the terms “directly” or “immediately following.”

[0023] Furthermore, when referring to any size, relative size, etc., it should be understood that the numerical or corresponding information of a component or feature (e.g., grade, range, etc.) includes tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if not explicitly stated. In addition, the word "may" fully encompasses all the meanings of the word "may".

[0024] Various embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0025] In the accompanying drawings, two directions parallel to the upper surface of the substrate are defined as the first direction FD and the second direction SD, respectively, and a direction projecting perpendicular to the upper surface of the substrate is defined as the third direction VD. The first direction FD and the second direction SD may be substantially perpendicular to each other. The third direction VD is perpendicular to both the first direction FD and the second direction SD. In the following description, the term "perpendicular" or "perpendicular direction" is used to indicate a direction substantially the same as the third direction VD. The directions indicated by the arrows in the figures and their opposite directions all indicate the same direction.

[0026] Figure 1 This is a cross-sectional view illustrating an example of a semiconductor device according to an embodiment of the present disclosure.

[0027] refer to Figure 1 The semiconductor device may include a cell region CA and a peripheral region PA. A memory cell array 141 may be disposed within the cell region CA. The peripheral region PA may be disposed around the cell region CA. The peripheral region PA may include circuitry and wiring for transmitting signals to the memory cell array 141, or various circuitry and wiring for connecting the semiconductor device to external devices.

[0028] The semiconductor device may include a first semiconductor structure S1 and a second semiconductor structure S2. The first semiconductor structure S1 and the second semiconductor structure S2 may be bonded to each other. Specifically, the lower surface of the second semiconductor structure S2 may be bonded to the upper surface of the first semiconductor structure S1. The interface between the first semiconductor structure S1 and the second semiconductor structure S2 may be referred to as the bonding interface.

[0029] The first semiconductor structure S1 of the semiconductor device may include a second substrate 100, a gate 101, wirings 102, 103 and 104, contacts 111, 112 and 113, peripheral bonding pads 133, peripheral bonding contacts 131, peripheral bonding insulating layer 132, a third insulating layer 120 and a fourth insulating layer 130. In one embodiment, the wirings 102, 103 and 104 and the contacts 111, 112 and 113 included in the first semiconductor structure S1 may be referred to as peripheral circuitry.

[0030] The second substrate 100 may include a semiconductor substrate, such as a silicon wafer or a silicon-on-insulator (SOI) wafer. The second substrate 100 may include a III-V compound semiconductor substrate, such as a gallium arsenide (GaAs) substrate. The second substrate 100 may include monocrystalline silicon, polycrystalline silicon, amorphous silicon, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, or combinations thereof.

[0031] A gate 101, first, second, and third contacts 111, 112, and 113, first, second, and third wirings 102, 103, and 104, and a third insulating layer 120 may be disposed on the second substrate 100. Contacts 111, 112, and 113 may be disposed between wirings 102, 103, and 104, or between the second wiring 102 and the second substrate 100. Contacts 111, 112, and 113 may be electrically connected to wirings 102, 103, and 104. The gate 101, the first contact 111, and the second wiring 102 may constitute a transistor.

[0032] The gate 101, contacts 111, 112, 113, and wiring 102, 103, 104 may include conductive materials, such as metals, metal oxides, metal nitrides, metal silicides, polysilicon, conductive carbon, or combinations thereof. The third insulating layer 120 may include silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric, or combinations thereof.

[0033] A fourth insulating layer 130 may be disposed on the third insulating layer 120 and the third wiring 104. A peripheral bonding contact 131 may be disposed in the fourth insulating layer 130. The peripheral bonding contact 131 may be connected to the corresponding third wiring 104.

[0034] A peripheral bonding insulating layer 132 may be disposed on the fourth insulating layer 130 and the peripheral bonding contact 131. A peripheral bonding pad 133 may be disposed in the peripheral bonding insulating layer 132. The peripheral bonding pad 133 may be connected to the corresponding peripheral bonding contact 131. The upper surface of the peripheral bonding pad 133 may be substantially coplanar with the upper surface of the peripheral bonding insulating layer 132.

[0035] The second semiconductor structure S2 may be disposed on the first semiconductor structure S1. The second semiconductor structure S2 may include wirings 154 and 181, spacers 152, a barrier layer 153, contacts 146, 148 and 171, a first insulating layer 155, a second insulating layer 150, a fifth insulating layer 147, a sixth insulating layer 145, a seventh insulating layer 170, an eighth insulating layer 180, a memory cell array 141, a first cell bonding insulating layer 160, a second cell bonding insulating layer 161, cell bonding contacts 159 and cell bonding pads 163.

[0036] In the cell region CA and the peripheral region PA, a second cell bonding insulating layer 161 may be disposed on the peripheral bonding insulating layer 132. A first cell bonding insulating layer 160 may be disposed on the second cell bonding insulating layer 161. Cell bonding pads 163 may be disposed in the first cell bonding insulating layer 160 and the second cell bonding insulating layer 161. The lower surface of the cell bonding pad 163 may be substantially coplanar with the lower surface of the second cell bonding insulating layer 161. The lower surface of the cell bonding pad 163 may contact the upper surface of the corresponding peripheral bonding pad 133. In one embodiment, the cell bonding pad 163 may be bonded to the peripheral bonding pad 133. The lower surface of the second cell bonding insulating layer 161 may contact the upper surface of the peripheral bonding insulating layer 132. In one embodiment, the second cell bonding insulating layer 161 may be bonded to the peripheral bonding insulating layer 132.

[0037] In the cell region CA and the peripheral region PA, a first insulating layer 155 and a cell bonding contact 159 may be disposed on a first cell bonding insulating layer 160 and a cell bonding pad 163. The cell bonding contact 159 may be connected to a corresponding cell bonding pad 163.

[0038] The peripheral bonding contact 131, unit bonding contact 159, peripheral bonding pad 133, and unit bonding pad 163 may include conductive materials, such as metals, metal oxides, metal nitrides, metal silicides, polysilicon, conductive carbon, or combinations thereof. In one embodiment, the peripheral bonding contact 131 and unit bonding contact 159 may include titanium nitride (TiN), tungsten (W), or combinations thereof. In one embodiment, the peripheral bonding pad 133 and unit bonding pad 163 may include tantalum nitride (TaN), copper, or combinations thereof. The peripheral bonding insulating layer 132, the first unit bonding insulating layer 160, the second unit bonding insulating layer 161, the first insulating layer 155, and the fourth insulating layer 130 may include silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric, or combinations thereof.

[0039] In the peripheral region PA, unit bonding contacts 159, wiring structures 198, and air gaps 156 may be disposed within the first insulating layer 155. The wiring structure 198 may include spacers 152, a barrier layer 153, and wiring 154, and is disposed on the unit bonding contact 159. Air gaps 156 may be disposed between the plurality of wiring structures 198. The upper surface of the unit bonding contact 159 may contact the lower surface of the wiring structure 198. Reference will be made below. Figure 2 The wiring structure is described in section 198. References will follow below. Figure 3 Describe air gap 156.

[0040] In the peripheral region PA, a fifth insulating layer 147 and a fifth contact 148 may be disposed on the first insulating layer 155 and the wiring structure 198. The fifth contact 148 may be connected to the wiring structure 198. A fourth contact 146 and a sixth contact 171 may be stacked sequentially on the fifth contact 148. The fourth contact 146 may be connected to the fifth contact 148. The sixth contact 171 may be connected to the fifth contact 148. A fifth wiring 181 may be connected to the corresponding sixth contact 171. The fourth contact 146, the fifth contact 148, the sixth contact 171, and the fifth wiring 181 may include conductive materials, such as metals, metal oxides, metal nitrides, metal silicides, polysilicon, conductive carbon, or combinations thereof. The fifth contact 148 may be disposed in the fifth insulating layer 147. The fourth contact 146 may be disposed in the sixth insulating layer 145. The sixth contact 171 may be disposed in the seventh insulating layer 170. The fifth wiring 181 may be disposed in the eighth insulating layer 180. The first insulating layer 155, the fifth insulating layer 147, the sixth insulating layer 145, the seventh insulating layer 170 and the eighth insulating layer 180 may include silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric or a combination thereof.

[0041] In the cell region CA, cell bonding contacts 159 may be disposed in a first insulating layer 155. A second insulating layer 150 and wiring structure 198 may be disposed on the first insulating layer 155. Wiring structure 198 may be disposed in the second insulating layer 150. The second insulating layer 150 may include silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, or a combination thereof. In one embodiment, the second insulating layer 150 may include silicon oxide.

[0042] In the cell region CA, a fifth insulating layer 147 and a fifth contact 148 may be disposed on the second insulating layer 150 and the wiring structure 198. The fifth contact 148 may be disposed in the fifth insulating layer 147. The fifth contact 148 may be connected to the wiring structure 198. The memory cell array 141 may be disposed on the fifth insulating layer 147 and the fifth contact 148.

[0043] The memory cell array 141 may include a stacked structure 149, a channel structure 190, and a source plate 142. In one embodiment, the stacked structure 149 may include interlayer insulating layers 143 (e.g., dielectric layers) and electrode layers 144 that are alternately stacked in a vertical direction.

[0044] The channel structure 190 can vertically penetrate the interlayer insulating layer 143 and the electrode layer 144. The channel structure 190 can extend vertically into the source plate 142. The upper surface of the channel structure 190 can be higher than the lower surface of the source plate 142 in the vertical direction. The lower surface of the channel structure 190 can be substantially coplanar with the lower surface of the lowest interlayer insulating layer 143 disposed at the bottom of the memory cell array 141.

[0045] The channel structure 190 can be connected to the corresponding fifth contact 148. The channel structure 190 can be connected to the first semiconductor structure S1 via the corresponding fifth contact 148, the wiring structure 198 corresponding to the fifth contact 148, the unit bonding pad 163 corresponding to the wiring structure 198, the peripheral bonding pad 133 connected to the unit bonding pad 163, and the peripheral bonding contact 131 corresponding to the peripheral bonding pad 133.

[0046] The channel structure 190 may include a core layer 191, a channel pattern 192, a gate insulating layer 193, and a drain pad 194. The drain pad 194 may contact the upper surface of the fifth contact 148. The core layer 191 may be disposed on the drain pad 194. The core layer 191 may extend vertically. The channel pattern 192 may surround the side and bottom surfaces of the core layer 191. The channel pattern 192 may extend vertically into the source plate 142. The gate insulating layer 193 may surround the channel pattern 192 and the side surfaces of the drain pad 194. The portion of the electrode layer 144, the gate insulating layer 193, and the channel pattern 192 that overlaps with the electrode layer 144 in a first direction or a second direction may constitute a memory cell.

[0047] The source plate 142 can be disposed on the uppermost interlayer insulating layer 143 of the memory cell array 141 and on the channel structure 190.

[0048] A seventh insulating layer 170 and a sixth contact 171 may be disposed on the source plate 142. The sixth contact 171 may perpendicularly penetrate the seventh insulating layer 170 to connect to the source plate 142. An eighth insulating layer 180 and a fifth wiring 181 may be disposed on the seventh insulating layer 170 and the sixth contact 171. The fifth wiring 181 may perpendicularly penetrate the eighth insulating layer 180 to connect to the sixth contact 171.

[0049] The fifth contact 148, electrode layer 144, drain pad 194, sixth contact 171, and fifth wiring 181 may include conductive materials, such as metals, metal oxides, metal nitrides, metal silicides, polysilicon, conductive carbon, or combinations thereof. The channel pattern 192 and source plate 142 may include semiconductor materials, such as polysilicon.

[0050] Figure 2 for Figure 1 Enlarged view of 197.

[0051] refer to Figure 2The wiring structure 198 may include a first wiring 154, a barrier layer 153, and a spacer 152. The barrier layer 153 may surround the side and top surfaces of the first wiring 154. The spacer 152 may be disposed on the side surface of the barrier layer 153. In one embodiment, the spacer 152 may be disposed on the side surface of the first wiring 154.

[0052] exist Figure 2 In the example shown, the first wiring 154 may include a first wiring portion 231 and a second wiring portion 232. The first wiring portion 231 may be located on the second wiring portion 232. The second wiring portion 232 may be continuous with the first wiring portion 231. The cross-sectional side surfaces of the first wiring portion 231 may be parallel to each other. The width d1 of the first wiring portion 231 in a first direction may be constant. The cross-sectional side surfaces of the second wiring portion 232 may not be parallel to each other, and the second wiring portion 232 may be bent outwards towards the bottom. The width d2 of the second wiring portion 232 in the first direction may increase towards the bottom. The maximum width d3 of the second wiring portion 232 in the first direction may be greater than the width of the first wiring portion 231 in the first direction. The first wiring 154 may include a conductive material, such as a metal, metal oxide, metal nitride, metal silicide, polysilicon, conductive carbon, or a combination thereof. In one embodiment, the first wiring 154 may include copper (Cu), copper-manganese alloy (CuMn), aluminum (Al), tungsten (W), or a combination thereof.

[0053] The barrier layer 153 includes a first barrier portion 221 and a second barrier portion 222. The first barrier portion 221 may be disposed on the side surface and the top surface of the first wiring portion 231. The second barrier portion 222 may be disposed on the side surface and the top surface of the second wiring portion 232. The second barrier portion 222 may protrude outward and to the bottom in a first direction or a second direction. The barrier layer 153 may include a conductive material, such as a metal, a metal oxide, a metal nitride, a metal silicide, polycrystalline silicon, conductive carbon, or a combination thereof. In one embodiment, the barrier layer 153 may include tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN), or a combination thereof.

[0054] exist Figure 2In the example shown, spacer 152 may be disposed on a side surface of the first wiring 154 or the barrier layer 153. Spacer 152 includes a first spacer portion 211 and a second spacer portion 212. The first spacer portion 211 may be disposed on a side surface of the first barrier portion 221. The second spacer portion 212 may be disposed on a side surface of the second barrier portion 222. The side surfaces of the first spacer portion 211 may be parallel to each other (e.g., having the same cross-sectional width along the entire length of the first spacer portion 211). The width d4 of the first spacer portion 211 in a first direction may be constant. The cross-section of the second spacer portion 212 may be curved outward towards the bottom and is not parallel. The width d5 ​​of the second spacer portion 212 in the first direction may decrease towards the bottom. The maximum width d6 of the second spacer portion 212 in the first direction may be less than the width d4 of the first spacer portion 211 in the first direction. Spacer 152 may include silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, or a combination thereof.

[0055] When a spacer 152 is provided on the side surface of the first wiring 154 or the barrier layer 153, leakage current can be prevented. Specifically, if the first insulating layer 155 is not deposited on the side surface of the first wiring 154 or the barrier layer 153, leakage current can occur in the first wiring 154. To prevent this, a spacer 152 can be provided on the side surface of the first wiring 154 or the barrier layer 153. In one embodiment, the breakdown voltage drop due to leakage current between the first wirings 154 can be controlled by providing the spacer 152.

[0056] The inner surface of the first blocking portion 221 is in contact with the first wiring portion 231. The outer surface of the first blocking portion 221 is in contact with the first spacer portion 211, the fifth insulating layer 147, and the fifth contact 148. The inner surface of the second blocking portion 222 is in contact with the first wiring portion 231 and the first insulating layer 155. The outer surface of the second blocking portion 222 is in contact with the second spacer portion 212 and the first insulating layer 155.

[0057] Figure 3 for Figure 1 Enlarged image of 199.

[0058] refer to Figure 3 An air gap 156 may be disposed within a first insulating layer 155 and may be located between adjacent wiring structures 198. The insulating material of the first insulating layer 155 may be located between the spacer 152 of the wiring structure 198 and the air gap 156. In one embodiment, the entire side surface of the air gap 156 may contact the insulating material of the first insulating layer 155. In another embodiment, a portion of the side surface of the air gap 156 may contact the side surface of the spacer 152.

[0059] The width d7 of the air gap 156 in the first direction can vary in the vertical direction. Specifically, the width d7 of the air gap 156 in the first direction can be maintained, increased, or decreased in the vertical direction. In one embodiment, the width d7 of the air gap 156 in the first direction can be repeatedly maintained, increased, and decreased along the vertical direction.

[0060] The first surface 301 and the second surface 302 may be located between a plurality of adjacent wiring structures 198. The first surface 301 may be located on the side surface of one of the adjacent wiring structures 198. The second surface 302 may be located on the side surface of another of the adjacent wiring structures 198. The first surface 301 and the second surface 302 may be surfaces coplanar with the lower surface of the fifth insulating layer 147. In one embodiment, the air gap 156 may contact the lower surface of the fifth insulating layer 147 in a portion other than the area corresponding to the first surface 301 and the second surface 302. In another embodiment, the air gap 156 may not contact the lower surface of the fifth insulating layer 147 (including the first surface 301 and the second surface 302).

[0061] Figure 4 Another example of a cross-sectional structure of a semiconductor device according to an embodiment of the present disclosure is shown.

[0062] refer to Figure 4 ,Apart from Figure 1 In addition to the structure shown, a ninth insulating layer 400 may be provided on the first unit bonding insulating layer 160 and the unit bonding pad 163. The first insulating layer 155 may be disposed on the ninth insulating layer 400. Unit bonding contacts 159 may be disposed within the first insulating layer 155 and the ninth insulating layer 400. The unit bonding contacts 159 may penetrate through the first insulating layer 155 and the ninth insulating layer 400. The lower surface of the unit bonding contacts 159 may be substantially coplanar with the lower surface of the ninth insulating layer 400.

[0063] The ninth insulating layer 400 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, a high-k dielectric, or a combination thereof. In one embodiment, the ninth insulating layer 400 may include an oxide.

[0064] Figures 5 to 19 An example of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown.

[0065] refer to Figure 5 A first substrate 500 is prepared. The first substrate 500 may include a semiconductor substrate, such as a silicon wafer or a silicon-on-insulator (SOI) wafer. The first substrate 500 may include a III-V compound semiconductor substrate such as gallium arsenide (GaAs). The first substrate 500 may include monocrystalline silicon, polycrystalline silicon, amorphous silicon, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, or combinations thereof.

[0066] In the cell region CA, an interlayer insulating layer (e.g., an interlayer dielectric layer) 143 and an electrode layer 144 may be alternately stacked on the first substrate 500 to form a stacked structure 149. A channel structure 190 may be formed to perpendicularly penetrate the interlayer insulating layer 143 and the electrode layer 144. In the peripheral region PA, a sixth insulating layer 145 may be formed on the first substrate 500. After forming the sixth insulating layer 145, a fourth contact 146 penetrating the sixth insulating layer 145 may be formed. The process for forming the fourth contact 146 may include forming an etched structure in the sixth insulating layer 145, depositing a conductive material, and performing a planarization process. The planarization process may include a polishing process or a chemical mechanical polishing (CMP) process. The upper surface of the sixth insulating layer 145 may be substantially coplanar with the upper surface of the fourth contact 146.

[0067] A fifth insulating layer 147 may be formed on the sixth insulating layer 145, the channel structure 190, and the interlayer insulating layer 143. In the cell region CA, a fifth contact 148 may be formed penetrating the fifth insulating layer 147. The fifth contact 148 may be connected to the corresponding channel structure 190. In the peripheral region PA, the fifth contact 148 may also be formed penetrating the fifth insulating layer 147. The process of forming the fifth contact 148 may include forming an etched structure in the fifth insulating layer 147, depositing a conductive material, and performing a planarization process. The planarization process may include a grinding process or a chemical mechanical polishing (CMP) process. The upper surface of the fifth insulating layer 147 may be substantially coplanar with the upper surface of the fifth contact 148.

[0068] refer to Figure 6 and Figure 7 A second insulating layer 150 may be formed on the fifth insulating layer 147 in the cell region CA and the peripheral region PA. A plurality of first trenches 700 may be formed in the region on the upper surface of the fifth contact 148 that contacts the second insulating layer 150. The process for forming the first trenches 700 may include a photolithography process or an etching process. For example, the process for forming the first trenches 700 may include coating an insulating material over the cell region CA and the peripheral region PA, and then removing a portion of the insulating material to form the trenches 700.

[0069] refer to Figure 8Spacers 152 may be formed on the sidewalls of each of the plurality of first trenches 700 in the cell region CA and the peripheral region PA, respectively. The process of forming the spacers 152 may include an etching process. For example, this process may include: depositing an insulating material over the cell region CA and the peripheral region PA of the second insulating layer 150; removing the insulating material located on the second insulating layer 150 including the first trench 700 along the vertical direction VD; and retaining the insulating material on the sidewalls of the first trench 700. As a result of the etching process, the upper width of each spacer 152 may be reduced in the vertical direction. The insulating material may include silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, or combinations thereof. In one embodiment, the ninth insulating layer 400 may include an oxide.

[0070] refer to Figure 9 In the cell region CA and the peripheral region PA, a barrier layer 153 and a first wiring 154 may be formed in the plurality of first trenches 700 of the second insulating layer 150, respectively. The barrier layer 153 and the first wiring 154 are located between spacers 152. The upper portion of the barrier layer 153 may protrude along a first direction FD or a second direction SD. The width of the upper portion of the first wiring 154 may increase along a vertical direction VD. The process of forming the barrier layer 153 and the first wiring 154 may include depositing a conductive material for each layer and performing a planarization process. The planarization process may include a polishing process or a chemical mechanical polishing (CMP) process. The conductive material may include metals, metal oxides, metal nitrides, metal silicides, polysilicon, conductive carbon, or combinations thereof. In one embodiment, the conductive material of the barrier layer 153 may include tantalum nitride (TaN), tungsten nitride (WN), or combinations thereof. In another embodiment, the conductive material for the first wiring 154 may include copper.

[0071] refer to Figure 10 In the peripheral region PA, the second insulating layer 150 can be removed. The process for removing the second insulating layer 150 may include a photolithography process or an etching process. When the spacer 152 is disposed on the side surface of the first wiring 154 or the barrier layer 153, the spacer 152 can prevent the first wiring 154 or the barrier layer 153 from being peeled off together with the second insulating layer 150 during the removal process of the second insulating layer 150.

[0072] refer to Figure 11In the cell region CA, a first insulating layer 155 may be formed on a second insulating layer 150 and a wiring structure 198 (including, for example, a first wiring 154, a barrier layer 153, and a spacer 152). In the peripheral region PA, the first insulating layer 155 may be formed on a fifth insulating layer 147 and a fifth contact 148. The process of forming the first insulating layer 155 may include depositing an insulating material and performing a planarization process. The planarization process may include a chemical mechanical polishing (CMP) process. The upper surface of the first insulating layer 155 may be planar. In one embodiment, the thickness from the interface between the first insulating layer 155 and the fifth insulating layer 147 to the upper surface of the first insulating layer 155 may range from 500 to 2000 angstroms (Å).

[0073] The insulating material of the first insulating layer 155 may have draping characteristics. The insulating material may be deposited on the upper and side surfaces of the wiring structure 198, and may form a draping shape between adjacent wiring structures 198. For example, the width of the insulating material deposited on the upper surface of the wiring structure 198 may be greater than the width of the insulating material deposited on its side surfaces. Therefore, the insulating material deposited on the upper surface of one wiring structure 198 among adjacent wiring structures 198 may be in contact with the insulating material on the upper surface of another adjacent wiring structure 198, while the insulating material deposited on the side surface of one wiring structure 198 among the plurality of adjacent wiring structures 198 may be spaced apart from the insulating material deposited on the side surface of another adjacent wiring structure 198. Thus, an air gap 156 may be formed between adjacent wiring structures 198. The insulating material may include silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, or combinations thereof.

[0074] refer to Figure 12 In the cell region CA and the peripheral region PA, a plurality of second trenches 1200 may be formed on the wiring structure 198 in the first insulating layer 155. The process for forming the second trenches 1200 may include photolithography or etching. This process exposes the upper surface of the first wiring 154.

[0075] refer to Figure 13 Within the cell region CA and the peripheral region PA, cell bonding contacts 159 connectable to the first wiring 154 may be formed in the first insulating layer 155. The process of forming the cell bonding contacts 159 may include depositing a conductive material and performing a planarization process. The planarization process may include a grinding process or a chemical mechanical polishing (CMP) process. The upper surface of the cell bonding contacts 159 may be substantially coplanar with the upper surface of the first insulating layer 155. The conductive material may include metals, metal oxides, metal nitrides, metal silicides, polysilicon, conductive carbon, or combinations thereof. In one embodiment, the cell bonding contacts 159 may include titanium nitride (TiN), tungsten (W), or combinations thereof.

[0076] refer to Figure 14 In the cell region CA and the peripheral region PA, a first cell bonding insulating layer 160 may be formed on the first insulating layer 155 and the cell bonding contact 159. A second cell bonding insulating layer 161 may be formed on the first cell bonding insulating layer 160. A third trench 1400 may be formed on the cell bonding contact 159 in the first cell bonding insulating layer 160 and the second cell bonding insulating layer 161. Through the process of forming the third trench 1400, the upper surface of the cell bonding contact 159 may be exposed to the outside. The process of forming the third trench 1400 may include a photolithography process or an etching process.

[0077] refer to Figure 15 In the cell region CA and the peripheral region PA, cell bonding pads 163 may be formed on cell bonding contacts 159. Cell bonding pads 163 may be formed to fill a third trench 1400 formed in the first cell bonding insulating layer 160 and the second cell bonding insulating layer 161. The process of forming cell bonding pads 163 may include depositing a conductive material and performing a planarization process. The planarization process may include a grinding process or a chemical mechanical polishing (CMP) process. The upper surface of the cell bonding pad 163 may be substantially coplanar with the upper surface of the second cell bonding insulating layer 161. The conductive material may include metals, metal oxides, metal nitrides, metal silicides, polysilicon, conductive carbon, or combinations thereof. In one embodiment, the cell bonding pad 163 may include tantalum nitride (TaN), copper (Cu), copper-manganese alloy (CuMn), or combinations thereof.

[0078] refer to Figure 16 A first semiconductor structure S1 is fabricated. The unit bonding pads 163 and the second unit bonding insulating layer 161 of the second semiconductor structure S2 can be bonded to the peripheral bonding pads 133 and the peripheral bonding insulating layer 132 of the first semiconductor structure S1. It should be noted that... Figure 16 The middle has reversed. Figure 15 The structure includes a unit bonding pad 163 bonded to a peripheral bonding pad 133. The peripheral bonding pad 133 may include tantalum nitride (TaN), copper (Cu), copper-manganese alloy (CuMn), or a combination thereof.

[0079] refer to Figure 17 and Figure 18 In the cell region CA and the peripheral region PA, the first substrate 500 can be removed. In one embodiment, the process for removing the first substrate 500 may include an etching process, a polishing process, or a chemical mechanical polishing (CMP) process. After removing the first substrate 500, a source plate 142 can be formed on the channel structure 190 and the interlayer insulating layer 143 in the cell region CA.

[0080] refer to Figure 19The seventh insulating layer 170 may be formed on the source plate 142 in the cell region CA and on the sixth insulating layer 145 and the fourth contact 146 in the peripheral region PA. The process for forming the seventh insulating layer 170 may include depositing insulating material and performing a planarization process. The planarization process may include a grinding process or a chemical mechanical polishing (CMP) process.

[0081] Refer again Figure 1 A sixth contact 171, penetrating the seventh insulating layer 170, may be formed in the unit region CA and the peripheral region PA. An eighth insulating layer 180 and a fifth wiring 181 may be formed on the sixth contact 171 and the seventh insulating layer 170. The process for forming the sixth contact 171 and the fifth wiring 181 may include an inlay process.

[0082] Figures 20 to 25 Other examples of a method for manufacturing a semiconductor device according to one embodiment of the present disclosure are shown.

[0083] Figure 20 The semiconductor device shown can be used with reference Figures 5 to 11 The same method described is used to form it.

[0084] refer to Figure 20 and Figure 21 After the upper surface of the first insulating layer 155 in the planarization unit region CA and the peripheral region PA, a ninth insulating layer 400 may be formed on the first insulating layer 155.

[0085] refer to Figure 22 A fourth trench 2200 on the wiring structure 198 (which includes, for example, a first wiring 154, a barrier layer 153, and a spacer 152) may be formed in a first insulating layer 155 and a ninth insulating layer 400 in the cell region CA and the peripheral region PA. The process for forming the fourth trench 2200 may include a photolithography process or an etching process.

[0086] refer to Figure 23 Unit bonding contacts 159, penetrating the first insulating layer 155 and the ninth insulating layer 400, can be formed in the unit region CA and the peripheral region PA. The process of forming the unit bonding contacts 159 may include depositing a conductive material to fill the fourth trench 2200 located in the first insulating layer 155 and the ninth insulating layer 400 with the conductive material, and then planarizing it. The planarization process may include a grinding process or a chemical mechanical polishing (CMP) process. After planarization, the upper surface of the unit bonding contact 159 may be substantially coplanar with the upper surface of the ninth insulating layer 400.

[0087] refer to Figure 24A first unit bonding insulating layer 160 may be formed on the ninth insulating layer 400 and the unit bonding contact 159 in the unit region CA and the peripheral region PA. A second unit bonding insulating layer 161 may be formed on the first unit bonding insulating layer 160. A third trench 1400 may be formed on the unit bonding contact 159 within the first unit bonding insulating layer 160 and the second unit bonding insulating layer 161. The process for forming the third trench 1400 may include a photolithography process or an etching process. Therefore, the upper part of the unit bonding contact 159 may be exposed to the outside.

[0088] refer to Figure 25 Unit bonding pads 163 may be formed in trenches 1400 within the first unit bonding insulating layer 160 and the second unit bonding insulating layer 161 in the unit region CA and the peripheral region PA. The process for forming the unit bonding pads 163 may include depositing a conductive material and performing a planarization process. The planarization process may include a grinding process or a chemical mechanical polishing (CMP) process. The upper surface of the unit bonding pads 163 may be substantially coplanar with the upper surface of the second unit bonding insulating layer 161.

[0089] Figure 25 Subsequent processes can adopt the same methods as... Figures 16 to 19 The same method described in [the document] is used.

[0090] According to embodiments of this disclosure, interference between adjacent wirings caused by reduced internal spacing within the semiconductor device can be minimized. Specifically, leakage current between the first wirings 154 can be minimized by providing spacers 152 on the side surface of the first wirings 154 or the barrier layer 153. Furthermore, parasitic capacitance between wirings can be reduced by forming air gaps 156 between the wiring structures 198. In the process of forming the air gap 156, the spacers 152 prevent the first wirings 154 and the barrier layer 153 from being stripped when the second insulating layer 150 is removed.

[0091] Although various embodiments of the disclosed technology have been described in particular and varying detail for illustrative purposes, those skilled in the art will understand that various modifications, additions and substitutions may be made based on the content disclosed or shown in this disclosure without departing from the spirit and scope of the invention as defined by the following claims.

Claims

1. A semiconductor device, comprising: The first semiconductor structure includes: Peripheral circuits, and Peripheral bonding pads, which are connected to the peripheral circuitry; and The second semiconductor structure includes: Unit bonding pads, which are bonded to the peripheral bonding pads. Multiple first wirings are connected to the cell bonding pads. Multiple spacers are respectively disposed on the side surfaces of the multiple first wirings, and A first insulating layer covers the side surfaces of the plurality of spacers and the lower surfaces of the plurality of first wirings, and has an air gap disposed between the plurality of spacers.

2. The semiconductor device according to claim 1, in, Each of the plurality of first wirings includes a first wiring portion and a second wiring portion continuous with the first wiring portion, and The second wiring portion has a variable width, and the maximum width of the second wiring portion is greater than the width of the first wiring portion.

3. The semiconductor device according to claim 2, further comprising: A barrier layer disposed between the side surfaces of the plurality of first wirings and the side surfaces of the plurality of spacers. The barrier layer includes: A first blocking portion is disposed on a side surface of the first wiring portion; and The second blocking portion is disposed on the side surface of the second wiring portion, and The second blocking portion protrudes more than the first blocking portion in the first direction.

4. The semiconductor device according to claim 3, in, The second blocking portion includes an inner surface and an outer surface, and The inner surface is in contact with the first insulating layer.

5. The semiconductor device according to claim 1, in, Each of the plurality of spacers includes: The first interval; and The second interval portion is continuous with the lower part of the first interval portion, and The maximum width of the second interval is less than the width of the first interval.

6. The semiconductor device according to claim 1, in, The plurality of first wirings includes two adjacent first wirings, and The upper surface of the first insulating layer disposed on the side surface of one of the two adjacent first wirings is separate from the upper surface of the first insulating layer disposed on the side surface of the other of the two adjacent first wirings.

7. The semiconductor device according to claim 1, in, The second semiconductor structure includes: A stacked structure in which multiple electrodes and insulating layers are stacked alternately; and A channel structure that penetrates the stacked structure, and At least one of the plurality of first wirings is connected to the channel structure.

8. The semiconductor device according to claim 1, in, The lower surface of the first insulating layer is flat.

9. The semiconductor device according to claim 1, in, The unit bonding pad is in contact with the lower surface of the first insulating layer.

10. A semiconductor device, comprising: A first semiconductor structure, which includes peripheral circuitry; as well as A second semiconductor structure, which is bonded to the first semiconductor structure. The second semiconductor structure includes: A plurality of first wirings, each first wiring including a first wiring portion and a second wiring portion continuous with the first wiring portion, the second wiring portion having a variable width, the maximum width of the second wiring portion being greater than the width of the first wiring portion; and A first insulating layer having an air gap disposed between the plurality of first wirings.

11. The semiconductor device according to claim 10, It also includes a barrier layer disposed on the side surfaces of the plurality of first wirings. in, The barrier layer includes: A first blocking portion is disposed on the side surface of the first wiring portion; and The second blocking portion is disposed on the side surface of the second wiring portion, and The second blocking portion protrudes more than the first blocking portion in the first direction.

12. The semiconductor device according to claim 10, in, The lower surface of the first insulating layer is flat.

13. The semiconductor device according to claim 10, Also includes: Multiple spacers are disposed on the side surfaces of the multiple first wirings. The plurality of spacers include: The first interval; and The second interval portion is continuous with the first interval portion, and The second interval portion has a variable width, and the maximum width of the second interval portion is less than the width of the first interval portion.

14. A method for manufacturing a semiconductor device, the method comprising: A plurality of first trenches are formed in a second insulating layer on a first substrate; Multiple spacers are formed on the side surfaces of the multiple first grooves respectively; Multiple first wirings are formed in the multiple first trenches respectively; Remove the second insulating layer; as well as A first insulating layer is formed, the first insulating layer having an air gap formed in the region between the plurality of spacers.

15. The method of claim 14, further comprising: The first insulating layer is formed to cover the side surface of each of the plurality of spacers and the lower surface of each of the plurality of first wirings.

16. The method of claim 14, further comprising: The first insulating layer is formed to cover the side surfaces of the plurality of first wirings, such that the first insulating layer on the opposite side surfaces of adjacent first wirings is spaced apart.

17. The method according to claim 14, in, Each of the plurality of spacers includes: The first interval; and The second interval portion is continuous with the first interval portion, and The second interval portion has a variable width, and the maximum width of the second interval portion is less than the width of the first interval portion.

18. The method according to claim 14, in, Each of the plurality of first wirings includes: First wiring section; and The second wiring section is continuous with the first wiring section, and The second wiring portion has a variable width, and the maximum width of the second wiring portion is greater than the width of the first wiring portion.

19. The method of claim 14, wherein, Forming the first insulating layer further includes: Depositing insulating material between the plurality of first wirings, and Flatten the upper part of the insulating material.

20. The method of claim 14, wherein, Forming the plurality of spacers further includes: Form a barrier layer, The barrier layer includes a first barrier portion and a second barrier portion continuous with the first barrier portion, and The second blocking portion protrudes more than the first blocking portion in the first direction.

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