Semiconductor element and method for manufacturing the same

Abstract

A semiconductor device and a method of fabricating the same are disclosed. The method includes providing a substrate including an alignment mark region and a resistive random access memory region, forming an interlayer dielectric layer on the substrate, forming a contact plug in the interlayer dielectric layer, forming a first lower electrode layer on the resistive random access memory region and the alignment mark region, removing the first lower electrode layer and the interlayer dielectric layer of the alignment mark region to form a recess, and planarizing the first lower electrode layer.

Description

Technical Field

[0001] This invention relates to a semiconductor device, and more particularly to a resistive random access memory device and its manufacturing method. Background Technology

[0002] Because non-volatile memory (NDRAM) retains data even after power is off, it is essential for many electronic products to maintain normal operation when powered on. Currently, one type of NDRAM being actively developed in the industry is resistive random access memory (RRAM), which offers advantages such as low write operation voltage, short write / erase time, long memory duration, non-destructive reading, multi-state storage, simple structure, and small footprint. Therefore, it is expected to become one of the most widely used NDRAM components in personal computers and electronic devices in the future.

[0003] In integrated circuit (IC) devices, resistive random access memory (RRAM) is a converged technology for next-generation non-volatile memory devices. Resistive random access memory is a memory structure comprising an array of resistive random access memory cells, each of which stores one bit of data using a resistance value rather than charge. Specifically, each resistive random access memory cell includes a resistive material layer whose resistance value can be adjusted to represent logic "0" or logic "1".

[0004] One way to optimize resistive random access memory cell arrays is to make them smaller and smaller. However, as the size decreases, the manufacturing process becomes more complex and costs increase. Therefore, how to improve the existing manufacturing process while maintaining product yield and reducing costs is a major challenge for the industry. Summary of the Invention

[0005] An embodiment of the present invention discloses a method for fabricating a resistive random access memory (RAM). The method mainly involves first providing a substrate including an alignment mark region and a resistive RAM region, then forming an interlayer dielectric layer on the substrate, forming a contact plug within the interlayer dielectric layer, forming a first lower electrode layer on the resistive RAM region and the alignment mark region, removing the first lower electrode layer and the interlayer dielectric layer from the alignment mark region to form a groove, and then planarizing the first lower electrode layer.

[0006] Another embodiment of the present invention discloses a resistive random access memory, which mainly includes an interlayer dielectric layer disposed on a substrate, a contact plug disposed within the interlayer dielectric layer, and a lower electrode disposed on the contact plug, wherein the lower electrode includes a first lower electrode layer and a second lower electrode layer, and the top surface of the first lower electrode layer includes a flat surface.

[0007] Another embodiment of the present invention discloses a resistive random access memory, which mainly includes an interlayer dielectric layer disposed on a substrate, a contact plug disposed within the interlayer dielectric layer, a lower electrode disposed on the contact plug, a resistive conversion layer disposed on the lower electrode, and an upper electrode disposed on the resistive conversion layer, wherein the upper electrode includes a first upper electrode and a second upper electrode disposed on the first upper electrode. Attached Figure Description

[0008] Figures 1 to 8 This is a schematic diagram illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention;

[0009] Figure 9 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention;

[0010] Figure 10 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention;

[0011] Figure 11 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention;

[0012] Figure 12 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention.

[0013] Symbol explanation:

[0014] 12: Base

[0015] 14: Interlayer dielectric layer

[0016] 16: Gate Structure

[0017] 18: Source / Drain Region

[0018] 20: Contact plug

[0019] 22: Barrier Layer

[0020] 24: Low-resistivity metal layer

[0021] 30: Lower electrode

[0022] 32: First lower electrode layer

[0023] 36: Groove

[0024] 42: Second lower electrode layer

[0025] 44: Impedance Transformation Layer

[0026] 46: Covering layer

[0027] 48: Upper electrode

[0028] 50: Resistive Random Access Memory

[0029] 52: Covering layer

[0030] 54: Intermetallic dielectric layer

[0031] 56: Metal interconnects

[0032] 58: Stop Layer

[0033] 60: Intermetallic dielectric layer

[0034] 62: Metal interconnects

[0035] 64: Contact hole conductor

[0036] 66: Trench conductor

[0037] 68: Stop Layer

[0038] 72: Alignment Marks

[0039] 84: Horizontal section

[0040] 86: Horizontal section

[0041] 88: Vertical section

[0042] 92: First upper electrode

[0043] 94: Second upper electrode

[0044] 102: Alignment Marker Area

[0045] 104: Resistive Random Access Memory Area

[0046] 106: Logic Area Detailed Implementation

[0047] Please refer to Figures 1 to 8 , Figures 1 to 8 This is a schematic diagram illustrating a method for fabricating a semiconductor device, or more specifically, a resistive random access memory device, according to an embodiment of the present invention. Figure 1As shown, a substrate 12 is first provided, for example, a substrate 12 made of semiconductor material, wherein the semiconductor material can be selected from the group consisting of silicon, germanium, silicon-germanium composite, silicon carbide, gallium arsenide, etc., and preferably an alignment mark (AM) region 102, a resistive random access memory region 104 and a logic region 106 are defined on the substrate 12.

[0048] The substrate 12 of the resistive random access memory region 104 and the logic region 106 may contain active (active) elements such as metal-oxide-semiconductor (MOS) transistors, passive (passive) elements, conductive layers, and dielectric layers such as interlayer dielectric (ILD) 14 covering the substrate. More specifically, the substrate 12 may contain planar or non-planar (such as fin structure transistors) MOS transistor elements, wherein the MOS transistor may contain a gate structure 16 (e.g., a metal gate), source / drain regions 18, spacers, epitaxial layers, contact hole etch stop layers, and other transistor elements. The interlayer dielectric layer 14 may be disposed on the substrate 12 and cover the MOS transistor, and multiple contact plugs 20 may be provided in the interlayer dielectric layer 14 to electrically connect the gate structure 16 and / or the source / drain regions 18 of the MOS transistor. Since the fabrication processes of planar or non-planar transistors and interlayer dielectric layers are well known in the art, they will not be described in detail here. It should be noted that at this stage, only an interlayer dielectric layer 14 is provided on the substrate 12 of the alignment mark area 102, but preferably no active or passive components are provided.

[0049] In this embodiment, the fabrication of each contact plug 20 can first involve a pattern transfer process. For example, a patterned mask (not shown) can be used to remove a portion of the interlayer dielectric layer 14 of the resistive random access memory region 104 to form contact holes (not shown) and expose the underlying source / drain regions 18. Then, the contact holes are filled with the desired metal or conductive material, such as a barrier layer 22 composed of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and a low-resistance metal layer 24 selected from low-resistance materials or combinations thereof, such as tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc. Next, a planarization process is performed, for example, using chemical mechanical polishing (CMP) to remove a portion of the metal material to form contact plugs 20 electrically connecting the source / drain regions 18 within the contact holes.

[0050] Next, an optional pattern transfer process can be performed, for example, by removing part of the contact plugs 20 using a patterned mask to form a groove directly above each contact plug 20, making the top surface of the remaining contact plugs 20 slightly lower than the top surface of the interlayer dielectric layers 14 on both sides. Then, a first lower electrode layer 32 is formed on the interlayer dielectric layer 14 of the alignment mark region 102, the resistive random access memory region 104, and the logic region 106, filling the groove directly above the contact plugs 20. In this embodiment, the first lower electrode layer 32 preferably comprises a metal nitride, such as titanium nitride (TiN), with a thickness preferably between 150 and 250 angstroms, and a nitrogen concentration or atomic percentage preferably between 40 and 60 at.

[0051] Subsequently, as Figure 2 As shown, a patterned mask (not shown) is first formed, for example, by patterning a photoresist onto the alignment mark region 102, the resistive random access memory region 104, and the first lower electrode layer 32 of the logic region 106. The patterned mask has an opening that exposes the surface of the first lower electrode layer 32 of the alignment mark region 102. Then, an etching process is performed using the patterned mask to remove a portion of the first lower electrode layer 32 and a portion of the interlayer dielectric layer 14 of the alignment mark region 102 to form a groove 36. Finally, oxygen is used to remove the patterned mask and expose the first lower electrode layer 32 again.

[0052] Then as Figure 3 As shown, a planarization process, such as chemical mechanical polishing (CMP), is performed to remove a portion of the first lower electrode layer 42 of the alignment mark region 102, the resistive random access memory region 104, and the logic region 106, thereby reducing its thickness. More specifically, the planarization process performed in this stage preferably removes all the first lower electrode layers 32 on both sides of the groove 36 in the alignment mark region 102, and even a portion of the interlayer dielectric layer 14, as well as a portion of the first lower electrode layer 42 on the surface of the interlayer dielectric layer 14 in the resistive random access memory region 104 and the logic region 106. In this embodiment, after a portion of the first lower electrode layer 42 is removed by a planarization process, the remaining thickness of the first lower electrode layer 42 on the surface of the interlayer dielectric layer between the resistive random access memory region 104 and the logic region 106 is preferably between 50 and 150 angstroms, and the top surface of the remaining interlayer dielectric layer 14 in the alignment mark region 102 is slightly lower than the top surface of the interlayer dielectric layer 14 between the resistive random access memory region 104 and the logic region 106.

[0053] Then as Figure 4As shown, a second lower electrode layer 42, a resistors-witching layer 44, a masking layer 46, and an upper electrode 48 are sequentially formed on the surface of the first lower electrode layer 32. In this embodiment, the resistors-witching layer 44 may include a metal oxide layer such as tantalum oxide (TaO) or hafnium oxide (HfO2), the masking layer 46 preferably includes a metal layer such as iridium (Ir), platinum (Pt), or gold (Au), and the upper electrode 48 preferably includes a metal nitride such as tantalum oxide (TaO) or titanium nitride (TiN). Furthermore, the second lower electrode layer 42 formed in this stage contains the same material as the first lower electrode layer 32 but with a different nitrogen concentration, and the thickness of the second lower electrode layer 42 is preferably less than the thickness of the first lower electrode layer 32. More specifically, the second lower electrode layer 42 preferably comprises a metal nitride such as titanium nitride (TiN), with a thickness preferably between 20 and 50 angstroms and a nitrogen concentration or atomic percentage preferably between 10 and 40 at.

[0054] like Figure 5 As shown, a patterned mask (not shown) such as a patterned photoresist can then be used to perform one or more etching processes to remove all the upper electrodes 48, all the masking layers 46, all the impedance conversion layers 44, all the second lower electrode layers 42, and all the first lower electrode layers 32 of the alignment mark region 102 and the logic region 106. At the same time, a portion of the upper electrodes 48, a portion of the masking layers 46, a portion of the impedance conversion layers 44, a portion of the second lower electrode layers 42, and a portion of the first lower electrode layers 32 of the resistive random access memory region 104 are removed, thereby exposing the surface of the interlayer dielectric layer 14 of the alignment mark region 102 and the logic region 106, and forming a resistive random access memory 50 by the patterned first lower electrode layer 32, the patterned second lower electrode layer 42, the patterned impedance conversion layer 44, the patterned masking layer 46, and the patterned upper electrodes 48 of the resistive random access memory region 104. Then a masking layer 52 is formed on the surface of the interlayer dielectric layer 14 of the alignment mark area 102 and in the groove 36, on the surface of the interlayer dielectric layer 14 of the resistive random access memory area 104 and on the resistive random access memory 50, and on the surface of the interlayer dielectric layer 14 of the logic area 106.

[0055] It should be noted that when the patterned portion of the upper electrode 48, part of the cover layer 46, part of the impedance conversion layer 44, part of the second lower electrode layer 42, and part of the first lower electrode layer 32 are used to form the resistive random access memory 50, a portion of the interlayer dielectric layer 14 on both sides of the resistive random access memory 50 may be selectively removed so that the top surface of the remaining interlayer dielectric layer 14 is slightly lower than the top surface of the first lower electrode layer 32 or even lower than the top surface of the contact plug 20. Thus, after the cover layer 52 is subsequently formed, the bottom surface of the cover layer 52 on both sides of the resistive random access memory 50 can vary depending on the height of the interlayer dielectric layer 14. For example, the bottom surface of the cover layer 52 on both sides of the resistive random access memory 50 can be flush with or lower than the bottom surface of the first lower electrode layer 32 or lower than the top surface of the contact plug 20; these are all within the scope of this invention.

[0056] Furthermore, the masking layer 52 preferably comprises a dielectric material such as silicon carbide (SiOC), silicon carbide (SiCN), or silicon nitride (SiN), and the etching process performed to pattern the resistive random access memory 50 in this stage may include reactive ion etching (RIE) and / or ion beam etching (IBE), but is not limited to these.

[0057] Subsequently, as Figure 6 As shown, an intermetallic dielectric layer 54 can be formed using a process such as flowable chemical vapor deposition (FCVD) to fill the grooves 36 on the alignment mark region 102, the resistive random access memory region 104, and the logic region 106, and to cover the resistive random access memory 50 and the interlayer dielectric layer 14. In this embodiment, the intermetallic dielectric layer 54 preferably comprises an ultra-low dielectric constant dielectric layer, such as a porous dielectric material, such as, but not limited to, silicon carbide (SiOC) or silicon carbide hydrogen (SiOCH).

[0058] Then as Figure 7 As shown, a planarization process is performed, for example, by using a chemical mechanical polishing (CMP) process to remove part of the intermetallic dielectric layer 54 so that the top of the intermetallic dielectric layer 54 of the alignment mark region 102, the resistive random access memory region 104 and the logic region 106 is approximately aligned with the top surface of the cover layer 52.

[0059] Next, a pattern transfer fabrication process is performed. For example, a patterned mask (not shown) can be used to remove part of the intermetallic dielectric layer 54 and part of the masking layer 52 of the logic region 106 to form contact holes (not shown) to expose the underlying contact plugs 20. Then, the contact holes are filled with the required metal material, such as a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from low-resistance materials or combinations thereof, such as tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc. Next, a planarization fabrication process is performed, such as a chemical mechanical polishing process to remove part of the metal material to form contact plugs or metal interconnects 56 that electrically connect the contact plugs 20 below within the contact holes. Then, a stop layer 58 is formed on the alignment mark region 102, the resistive random access memory region 104, and the intermetallic dielectric layer 54 of the logic region 106. The stop layer 58 may comprise, but is not limited to, a nitrogen-doped carbide (NDC), silicon nitride, silicon carbonnitride (SiCN), or silicon oxynitride (SiON).

[0060] Subsequently, as Figure 8As shown, another intermetallic dielectric layer 60 is formed on the surface of the stop layer 58. Then, one or more photolithography and etching processes are performed to remove portions of the intermetallic dielectric layer 60, the stop layer 58, and the masking layer 52 from the resistive random access memory region 104 and the logic region 106, forming contact holes (not shown). Next, conductive material is filled into the contact holes, and a planarization process such as CMP is used to form metal interconnects 62 connecting the upper electrode 48 and the metal interconnects 56 below. Then, another stop layer 68 is formed on the surface of the metal interconnects 62. As with the aforementioned metal interconnects 56, the metal interconnects 62 located within the intermetallic dielectric layer 60 can be embedded within the intermetallic dielectric layer 60 using a single damascene fabrication process or a double damascene fabrication process. For example, the metal interconnects 62 of the resistive random access memory area 104 and the logic area 106 may further include via conductors 64 connecting the underlying resistive random access memory 50 and the metal interconnects 56, and the trench conductors 66 are disposed on the via conductors 64. The metal interconnects 62 may further include a barrier layer and a metal layer. The barrier layer may be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), while the metal layer may be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt-tungsten phosphide (CoWP), etc., but is not limited to these.

[0061] In this embodiment, the intermetallic dielectric layer 60 preferably comprises an ultra-low dielectric constant dielectric layer, such as a porous dielectric material, but not limited to silicon oxycarbide (SiOC). The stop layer 68 may comprise, but is not limited to, a nitrogen-doped carbide layer (NDC), silicon nitride (SiN), or silicon nitride carbide (SiCN), and more preferably, silicon nitride, but is not limited thereto. This completes the fabrication of a semiconductor device according to an embodiment of the present invention.

[0062] Please refer to again Figure 8 , Figure 8 A schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention is also disclosed. For example... Figure 8As shown, the semiconductor device mainly includes an interlayer dielectric layer 14 disposed on the substrate 12 of the alignment mark region 102, the resistive random access memory region 104, and the logic region 106; an alignment mark 72 disposed on the alignment mark region 102; a contact plug 20 disposed within the interlayer dielectric layer 14 of the resistive random access memory region 104 and the logic region 106; a resistive random access memory 50 disposed on the contact plug 20 of the resistive random access memory region 104; a cover layer 52 disposed on the sidewall of the resistive random access memory 50 and extending to the surface of the interlayer dielectric layer 14 of the alignment mark region 102, the resistive random access memory region 104, and the logic region 106; a metal interconnect 56 disposed on the contact plug 20 of the logic region 106; and an interlayer dielectric layer 54 surrounding the resistive random access memory 50 and the metal interconnect 56.

[0063] In this embodiment, the alignment mark 72 of the alignment mark area 102 may include a groove 36 disposed in the interlayer dielectric layer 14, and the cover layer 52 covers the surface of the groove 36 and the surface of the interlayer dielectric layer 14 on both sides of the groove 36. Preferably, the top surface of the interlayer dielectric layer 14 of the alignment mark area 102 is slightly lower than the top surface of the interlayer dielectric layer 14 of the resistive random access memory area 104 and the logic area 106.

[0064] The resistive random access memory 50 of the resistive random access memory area 104 may include a lower electrode 30 disposed on the contact plug 20, a resistance conversion layer 44 disposed on the lower electrode 30, a cover layer 46 disposed on the resistance conversion layer 44, and an upper electrode 48 disposed on the cover layer 46. It should be noted that the lower electrode 30 in this embodiment preferably includes a double-layer structure, for example, a first lower electrode layer 32 and a second lower electrode layer 42 disposed on the first lower electrode layer 32. The first lower electrode layer 32 and the second lower electrode layer 42 preferably both contain metal nitrides, such as titanium nitride (TiN). The thickness of the first lower electrode layer 32 is greater than the thickness of the second lower electrode layer 42. The nitrogen concentration of the first lower electrode layer 32 is greater than the nitrogen concentration of the second lower electrode layer 42. The bottom surface of the first lower electrode layer 32 has a U-shape. The top surface of the first lower electrode layer 32 has a flat surface. The bottom surface of the second lower electrode layer 42 also has a flat surface. The sidewalls of the first lower electrode layer 32 are flush with the sidewalls of the second lower electrode layer 42.

[0065] In detail, the first lower electrode layer 32 is T-shaped, and its details include a horizontal portion 86 and a vertical portion 88 disposed below the horizontal portion 86, with the vertical portion 88 disposed directly above the contact plug 20. The second lower electrode layer 42 has a horizontal portion 84, wherein the sidewall of the horizontal portion 86 of the first lower electrode layer 32 preferably cuts into the sidewall of the horizontal portion 84 of the second lower electrode layer 42. In addition, the cover layer 52 is preferably disposed on the sidewall of the upper electrode 48 and extends downward to the surface of the interlayer dielectric layer 14 on both sides. The bottom surface of the lower electrode 30 directly above the contact plug 20 can be cut flush with, slightly lower than, or slightly higher than the bottom surface of the cover layer 52 on both sides of the contact plug 20, while the bottom surfaces of the lower electrodes 30 on both sides of the contact plug 20 can be cut flush with or higher than the bottom surface of the cover layer 52 on both sides of the contact plug 20.

[0066] Please continue to refer to Figure 9 , Figure 9 This is a schematic diagram of a semiconductor device according to an embodiment of the present invention. In order to highlight the various states of the upper electrode 48, the alignment mark region 102 is preferably omitted in this embodiment and subsequent embodiments. Figure 9 As shown, compared to the single-layer structure of the upper electrode 48 in the previous embodiment, the upper electrode 48 in this embodiment can be composed of more than one layer, such as a first upper electrode 92 and a second upper electrode 94. The lower first upper electrode 92 contains a metal nitride such as tantalum nitride (TaN), and the upper second upper electrode 94 contains titanium nitride (TiN). The first upper electrode 92 and the second upper electrode 94 can have the same or different thicknesses, and preferably neither the first upper electrode 92 nor the second upper electrode 94 contains a nitrogen concentration gradient. In other words, the nitrogen content at either the first upper electrode 92 or the second upper electrode 94 is preferably the same concentration, or the nitrogen concentration throughout the layer is evenly distributed. Furthermore, the first upper electrode 92 is preferably a tantalum-rich layer, with a nitrogen-to-tantalum ratio preferably of about 0.5 to 1, which can be used to reduce resistance and prevent the formation of tantalum oxide near the underlying cover layer 46. The second upper electrode 94 is preferably a nitrogen-rich layer, and the nitrogen concentration or atomic percentage of the second upper electrode 94 is preferably between 30 and 60 at%, which can also be used to reduce the resistance.

[0067] Please continue to refer to Figure 10 , Figure 10 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention. Figure 10As shown, the upper electrode 48 in this embodiment includes a first upper electrode 92 and a second upper electrode 94. The first upper electrode 92, located in the lower layer, contains a metal nitride such as tantalum nitride (TaN), and the second upper electrode 94, located in the upper layer, contains titanium nitride (TiN). The first upper electrode 92 and the second upper electrode 94 may have the same or different thicknesses, and the first upper electrode 92 contains a nitrogen concentration gradient, while the second upper electrode 94 does not. More specifically, the nitrogen concentration in the first upper electrode 92 is preferably non-uniformly distributed, and the nitrogen concentration in the first upper electrode 92 preferably increases from top to bottom, as indicated by the arrows in the figure. In other words, there is a higher nitrogen concentration near the bottom surface of the first upper electrode 92 and a lower nitrogen concentration near the top surface of the first upper electrode 92, or a lower tantalum concentration near the bottom surface of the first upper electrode 92 and a higher tantalum concentration near the top surface of the first upper electrode 92. In this embodiment, controlling the nitrogen concentration near the bottom surface of the first upper electrode 92 to a higher level can prevent oxygen from diffusing downwards to the covering layer 46 and forming tantalum oxide. The second upper electrode 94 is preferably a nitrogen-rich layer, and the nitrogen concentration or atomic percentage of the second upper electrode 94 is preferably between 30 and 60 at%, which can also be used to reduce the resistance.

[0068] Please continue to refer to Figure 11 , Figure 11 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention. Figure 11 As shown, the upper electrode 48 in this embodiment includes a first upper electrode 92 and a second upper electrode 94. The first upper electrode 92, located in the lower layer, contains a metal nitride such as tantalum nitride (TaN), and the second upper electrode 94, located in the upper layer, contains titanium nitride (TiN). The first upper electrode 92 and the second upper electrode 94 may have the same or different thicknesses. The first upper electrode 92 does not contain a nitrogen concentration gradient, but the second upper electrode 94 does. More specifically, the nitrogen concentration in the second upper electrode 94 is preferably unevenly distributed and preferably increases from top to bottom, as indicated by the arrows in the figure. In other words, there is a higher nitrogen concentration near the bottom surface of the second upper electrode 94 and a lower nitrogen concentration near the top surface, or a lower titanium concentration near the bottom surface and a higher titanium concentration near the top surface. In this embodiment, maintaining a higher nitrogen concentration near the bottom surface of the second upper electrode 94 prevents oxygen from diffusing downwards to the covering layer 46 and forming titanium oxide. The first upper electrode 92 is preferably a tantalum-rich layer with a nitrogen-to-tantalum ratio of about 0.5 to 1, which can be used to reduce the resistance and prevent the formation of tantalum oxide near the underlying cover layer 46.

[0069] Please continue to refer to Figure 12 , Figure 12 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention. Figure 12As shown, the upper electrode 48 in this embodiment includes a first upper electrode 92 and a second upper electrode 94. The first upper electrode 92, located in the lower layer, comprises a metal nitride such as tantalum nitride (TaN), and the second upper electrode 94, located in the upper layer, comprises titanium nitride (TiN). The first upper electrode 92 and the second upper electrode 94 may have the same or different thicknesses, and both the first upper electrode 92 and the second upper electrode 94 contain a nitrogen concentration gradient. More specifically, the nitrogen concentration in the first upper electrode 92 is preferably non-uniformly distributed, and the nitrogen concentration in the first upper electrode 92 preferably increases from top to bottom, as indicated by the arrows in the figure. In other words, there is a higher nitrogen concentration near the bottom surface of the first upper electrode 92 and a lower nitrogen concentration near the top surface of the first upper electrode 92, or a lower tantalum concentration near the bottom surface of the first upper electrode 92 and a higher tantalum concentration near the top surface of the first upper electrode 92.

[0070] Similarly, the nitrogen concentration in the second upper electrode 94 is preferably unevenly distributed and preferably increases from top to bottom, as shown by the arrows in the figure. In other words, there is a higher nitrogen concentration near the bottom surface of the second upper electrode 94 and a lower nitrogen concentration near the top surface of the second upper electrode 94, or a lower titanium concentration near the bottom surface of the second upper electrode 94 and a higher titanium concentration near the top surface of the second upper electrode 94. In this embodiment, maintaining a higher nitrogen concentration near the bottom surface of the first upper electrode 92 can prevent oxygen from diffusing downwards to the covering layer 46 to form tantalum oxide, and maintaining a higher nitrogen concentration near the bottom surface of the second upper electrode 94 can prevent oxygen from diffusing downwards to the covering layer 46 to form titanium oxide.

[0071] Generally, in the current fabrication of resistive random access memory (RAM) devices, a layer of tantalum nitride with a thickness of approximately 200 angstroms is typically used as the lower electrode before forming alignment marks. Considering that the high absorption coefficient or low penetration depth of this lower electrode material is unfavorable for the fabrication of alignment marks, this invention first covers a first lower electrode layer 32 made of titanium nitride (TiN) on the interlayer dielectric layer before forming the groove 36 for the alignment marks. A portion of the first lower electrode layer 32 and a portion of the interlayer dielectric layer 14 are removed using photolithography and etching processes to form the groove 36. Then, a second lower electrode layer 42, an impedance conversion layer 44, a masking layer 46, and an upper electrode 48 are sequentially formed using a patterning process to form the resistive RAM. Since titanium nitride has a significantly higher penetration depth and lower hardness compared to existing tantalum nitride, this invention can greatly improve the success rate of fabricating the groove 36 as the subsequent alignment mark, and it is easier to reduce its thickness and form a flat surface during subsequent planarization and polishing processes.

[0072] Furthermore, compared to existing methods that use a single material as the upper electrode, this invention can also be based on... Figures 9 to 12 In one embodiment, the upper electrode is fabricated using a composite material. The lower first upper electrode 92 comprises a metal nitride such as tantalum nitride (TaN), and the upper second upper electrode 94 comprises titanium nitride (TiN). The first upper electrode 92 and the second lower electrode 94 may contain a nitrogen concentration gradient, depending on the manufacturing process or product requirements. According to a preferred embodiment of the invention, the tantalum nitride (TaN) used in the lower first upper electrode 92 has stronger oxidation resistance than titanium nitride, while the upper second upper electrode 94 can reduce the element resistance or prevent oxygen from diffusing downwards to the cover layer 46 to form titanium oxide by adjusting the nitrogen concentration.

[0073] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A method for manufacturing a resistive random access memory, characterized in that, Include: The substrate includes an alignment mark area and a resistive random access memory area; An interlayer dielectric layer is formed on the substrate; A contact plug is formed within the interlayer dielectric layer; A first lower electrode layer is formed on the resistive random access memory region and the alignment mark region; Remove the first lower electrode layer and the interlayer dielectric layer of the alignment mark area to form a groove; and Planarize the first lower electrode layer.

2. The method of claim 1, further comprising: The first lower electrode layer and the interlayer dielectric layer are removed using a patterned mask to form the groove; Remove the patterned mask; and Planarize the first lower electrode layer.

3. The method of claim 1, further comprising: A second lower electrode layer is formed on the first lower electrode layer; A resistivity conversion layer is formed on the second lower electrode layer; An upper electrode is formed on the resistive conversion layer; The upper electrode, the resistivity conversion layer, the second lower electrode layer, and the first lower electrode layer are patterned. A masking layer is formed on the upper electrode and the interlayer dielectric layer; A first intermetallic dielectric layer is formed around the cover layer; A second intermetallic dielectric layer is formed on the first intermetallic dielectric layer; and A metal interconnect is formed within the second intermetallic dielectric layer and connected to the upper electrode.

4. The method of claim 3, wherein the first lower electrode layer and the second lower electrode layer have different thicknesses.

5. The method of claim 3, wherein the nitrogen concentration of the first lower electrode layer is greater than the nitrogen concentration of the second lower electrode layer.

6. The method of claim 3, wherein the upper electrode comprises: The first upper electrode; and The second upper electrode is disposed on the first upper electrode.

7. The method of claim 6, wherein the first upper electrode comprises tantalum nitride (TaN) and the second upper electrode comprises titanium nitride (TiN).

8. A resistive random access memory, characterized in that, Include: An interlayer dielectric layer is disposed on the substrate; Contact plugs are disposed within the interlayer dielectric layer; and A lower electrode is disposed on the contact plug, wherein the lower electrode comprises: A first lower electrode layer, wherein the top surface of the first lower electrode layer includes a flat surface; and Second lower electrode layer.

9. The resistive random access memory of claim 8, further comprising: A resistive conversion layer is disposed on the lower electrode; The upper electrode is disposed on the resistive conversion layer; A shielding layer is disposed next to the upper electrode; A first intermetallic dielectric layer surrounds the shielding layer; A second intermetallic dielectric layer is disposed on the first intermetallic dielectric layer; as well as The metal interconnect is located within the second intermetallic dielectric layer and connected to the upper electrode.

10. The resistive random access memory of claim 8, wherein the first lower electrode layer and the second lower electrode layer have different thicknesses.

11. The resistive random access memory of claim 8, wherein the thickness of the first lower electrode layer is greater than the thickness of the second lower electrode layer.

12. The resistive random access memory of claim 8, wherein the nitrogen concentration of the first lower electrode layer is greater than the nitrogen concentration of the second lower electrode layer.

13. The resistive random access memory of claim 8, wherein the first lower electrode layer comprises a T-shape.

14. The resistive random access memory of claim 8, wherein the sidewall of the first lower electrode layer is flush with the sidewall of the second lower electrode layer.

15. A resistive random access memory, characterized in that, Include: An interlayer dielectric layer is disposed on the substrate; Contact plugs are disposed within the interlayer dielectric layer; The lower electrode is located on the contact plug; A resistive switching layer is disposed on the lower electrode; and An upper electrode is disposed on the resistive switching layer, wherein the upper electrode comprises: First upper electrode; as well as The second upper electrode is disposed on the first upper electrode.

16. The resistive random access memory of claim 15, wherein the first upper electrode comprises tantalum nitride (TaN) and the second upper electrode comprises titanium nitride (TiN).

17. The resistive random access memory of claim 15, wherein the first upper electrode comprises a nitrogen concentration gradient.

18. The resistive random access memory of claim 15, wherein the second upper electrode comprises a nitrogen concentration gradient.

19. The resistive random access memory of claim 15, wherein the first upper electrode and the second upper electrode comprise a nitrogen concentration gradient.

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