Semiconductor device and method of manufacturing a semiconductor device

Abstract

The present application relates to a semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device includes: channel pillars arranged in a first direction and a second direction, each channel pillar including a first end portion, a second end portion, and a channel portion; a first gap fill insulating layer provided between the channel pillars adjacent to each other in the first direction; a first gate insulating layer provided between the channel pillars and the first gap fill insulating layer to surround the second end portion; a second gap fill insulating layer provided between the channel pillars adjacent to each other in the second direction; a second gate insulating layer provided between the channel pillars and the second gap fill insulating layer to cover the second end portion; a selection line surrounding sidewalls of the channel pillars arranged in the first direction; and a third gate insulating layer, each third gate insulating layer surrounding the channel portion and overlapping the first gate insulating layer and the second gate insulating layer.

Description

Cross-reference to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2025-0053052, filed on April 23, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0002] Embodiments of this disclosure relate to an electronic device, and more specifically, to a semiconductor device and a method of manufacturing the same. Background Technology

[0003] The integration density of semiconductor devices primarily depends on the area occupied by a single memory cell. In recent years, as improvements in the integration density of semiconductor devices with memory cells formed in a single layer on a substrate have reached their limits, a three-dimensional semiconductor device with stacked memory cells on a substrate has been proposed. Furthermore, various structures and fabrication methods have been developed to improve the operational reliability of such semiconductor devices. Summary of the Invention

[0004] In one embodiment, the semiconductor device may include: channel pillars arranged along a first direction and a second direction intersecting the first direction, each channel pillar including a first end, a second end, and a channel portion disposed between the first end and the second end; a first gap-filling insulating layer, each first gap-filling insulating layer disposed between a first pair of channel pillars adjacent to each other in the first direction; a first gate insulating layer, each first gate insulating layer disposed between a corresponding channel pillar and a corresponding first gap-filling insulating layer to cover the second end; a second gap-filling insulating layer, each second gap-filling insulating layer disposed between a second pair of channel pillars adjacent to each other in the second direction and extending in the first direction; a second gate insulating layer, each second gate insulating layer disposed between a corresponding channel pillar and a corresponding second gap-filling insulating layer to cover the second end; a select line, each select line surrounding a sidewall of a plurality of first channel pillars arranged and extending in the first direction; and a third gate insulating layer, each third gate insulating layer surrounding the channel portion of the plurality of first channel pillars and overlapping a corresponding first gate insulating layer and a second gate insulating layer.

[0005] In one embodiment, the semiconductor device may include: channel pillars arranged along a first direction and a second direction intersecting the first direction, each channel pillar including a first end, a second end, and a channel portion disposed between the first end and the second end; a fourth gate insulating layer covering corresponding sidewalls of the first end facing each other in the first direction; a fifth gate insulating layer covering corresponding sidewalls of the first end facing each other in the second direction; select lines, each select line extending along the first direction and surrounding the sidewalls of the first plurality of channel pillars arranged along the first direction; and third gate insulating layers, each third gate insulating layer surrounding the channel portion of the first plurality of channel pillars and overlapping with the corresponding fourth and fifth gate insulating layers.

[0006] In one embodiment, a method of manufacturing a semiconductor device may include: forming a channel layer; forming a channel pattern and a first trench by etching the channel layer, the channel pattern extending in a second direction, each first trench being formed between a pair of adjacent channel patterns in a first direction intersecting the second direction; forming an initial first gate insulating layer in the first trench; forming a first gap-fill insulating layer on the initial first gate insulating layer; forming a channel pillar, a second trench, and an intermediate first gate insulating layer by etching the channel pattern, the first gap-fill insulating layer, and the initial first gate insulating layer, the channel pillars being arranged in a first direction and a second direction, the second trench extending in the first direction; forming an initial second gate insulating layer in the second trench; and forming a channel pillar, a second trench, and an intermediate first gate insulating layer in the initial first trench. A second gap-filling insulating layer is formed on the second gate insulating layer; a third trench, a first gate insulating layer, and a second gate insulating layer are formed by etching the second gap-filling insulating layer, the initial second gate insulating layer, the first gap-filling insulating layer, and the intermediate first gate insulating layer, the third trench exposing the sidewalls of the channel pillars; an initial third gate insulating layer is formed in the third trench, the initial third gate insulating layer surrounding the sidewalls of the channel pillars; a selection line extending in a first direction is formed, each selection line surrounding a first plurality of channel pillars arranged in the first direction, the corresponding first gate insulating layer, second gate insulating layer, and third gate insulating layer being located between the selection line and the channel pillar, and a third gate insulating layer is formed by etching the initial third gate insulating layer.

[0007] In one embodiment, a method of manufacturing a semiconductor device may include: forming a channel layer; forming a first preliminary trench by etching the channel layer, the first preliminary trench extending along a second direction; forming a fourth gate insulating layer in the first preliminary trench; forming a channel pattern and a first trench by etching the fourth gate insulating layer and the channel layer, the channel pattern extending along the second direction, and the first trench disposed between the channel patterns; forming a first gate insulating layer and a first gap-fill insulating layer in the first trench; forming a channel pillar and a second trench by etching the channel pattern, the first gate insulating layer, the first gap-fill insulating layer and the fourth gate insulating layer, the channel pillar extending along the second direction. The second trench is arranged in two directions and a first direction intersecting the second direction, and the second trench extends along the first direction; a second gate insulating layer and a second gap filling insulating layer are formed in the second trench; a third trench is formed by etching the second gate insulating layer, the second gap filling insulating layer, the first gate insulating layer and the first gap filling insulating layer, the third trench exposes the sidewalls of the channel pillars; a third gate insulating layer is formed in the third trench, the third gate insulating layer overlaps with a fourth gate insulating layer; and a select line is formed, the select line extends in the first direction and surrounds the channel pillars arranged in the first direction, the first to fourth gate insulating layers are located between the select line and the channel pillars. Attached Figure Description

[0008] Figure 1 This is a schematic diagram illustrating the structure of a semiconductor device according to one embodiment.

[0009] Figure 2 This is a circuit diagram illustrating the configuration of a semiconductor device according to one embodiment.

[0010] Figures 3A to 3C This is a schematic diagram illustrating the structure of a semiconductor device according to one embodiment.

[0011] Figure 4A and Figure 4B This is a schematic diagram illustrating the structure of a semiconductor device according to one embodiment.

[0012] Figure 5A and Figure 5B This is a schematic diagram illustrating the structure of a semiconductor device according to one embodiment.

[0013] Figure 6 This is a schematic diagram illustrating the structure of a semiconductor device according to one embodiment.

[0014] Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A and Figure 12A , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B and Figure 12B as well as Figure 7C , Figure 8C , Figure 9C , Figure 10C , Figure 11C and Figure 12C This is a schematic diagram illustrating a method for manufacturing a semiconductor device according to one embodiment.

[0015] Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A and Figure 18A as well as Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B and Figure 18B This is a schematic diagram illustrating a method for manufacturing a semiconductor device according to one embodiment.

[0016] Figure 19A , Figure 19B , Figure 20A and Figure 20B This is a schematic diagram illustrating a method for manufacturing a semiconductor device according to one embodiment. Detailed Implementation

[0017] The various embodiments pertain to semiconductor devices with stable structures and improved properties, and methods for manufacturing the same.

[0018] By stacking memory cells in three dimensions, the integration density of semiconductor devices can be improved. This also provides semiconductor devices with a stable structure and improved reliability.

[0019] Some embodiments of this disclosure will now be described with reference to the accompanying drawings.

[0020] Figure 1 This is a schematic diagram illustrating the structure of a semiconductor device according to one embodiment.

[0021] refer to Figure 1 The semiconductor device may include a global line (GBL), a local line (LL), and a select transistor (ST). The select transistor (ST) is connected between the global line (GBL) and the local line (LL) and controls the connection between them. When the select transistor (ST) is turned on, the global line (GBL) and the local line (LL) are electrically connected; when the select transistor (ST) is turned off, the global line (GBL) and the local line (LL) are electrically disconnected. For example, the global line (GBL) may be a global bit line, and the local line (LL) may be a local bit line.

[0022] The select transistor ST may include a channel pillar CP. The select transistor ST may be located in the region where the channel pillar CP intersects with the select line SL. The channel pillar CP may include a first end E1, a second end E2, and a channel portion CHP located between the first end E1 and the second end E2. The first end E1 and the second end E2 may be junctions such as source and / or drain regions. The first end E1 may be connected to a local line LL, and the second end E2 may be connected to a global line GBL. The first end E1 may have a first width WA1, and the second end E2 may have a second width WB1, and the first width WA1 may be smaller than the second width WB1.

[0023] The selected transistor ST may include a gate insulating layer GL. The gate insulating layer GL may include a first gate insulating layer GLA, a second gate insulating layer GLB, and a third gate insulating layer GLC. The first gate insulating layer GLA may surround a first end E1, the second gate insulating layer GLB may surround a second end E2, and the third gate insulating layer GLC may surround a channel portion CHP. The sidewalls of the first gate insulating layer GLA may be substantially aligned with the sidewalls of the second end E2.

[0024] The third gate insulating layer GLC may overlap with the first gate insulating layer GLA, or with the second gate insulating layer GLB, or with both the first and second gate insulating layers GLA. For example, the third gate insulating layer GLC may surround the sidewall of the first gate insulating layer GLA. The third gate insulating layer GLC may surround the upper surface and sidewall of the second gate insulating layer GLB.

[0025] The select line SL may surround the sidewall of the channel pillar CP, and the first to third gate insulating layers GLA to GLC are located between the select line SL and the sidewall of the channel pillar CP. The upper surface of the third gate insulating layer GLC may be set at a level lower than the upper surface of the channel pillar CP, and may be set at a level substantially the same as the upper surface of the select line SL.

[0026] The gate insulating layer GL may have a first thickness TA between the first end E1 and the select line SL, a second thickness TB between the second end E2 and the select line SL, and a third thickness TC between the channel portion CHP and the select line SL. At least one of the first thickness TA and the second thickness TB may be greater than the third thickness TC.

[0027] Based on the above structure, the thickness of the gate insulating layer GL of the select transistor ST can be locally increased. Therefore, the occurrence of gate-induced drain leakage (GIDL) during the operation of the select transistor ST can be reduced.

[0028] Figure 2 A circuit diagram illustrating the structure of a semiconductor device according to one embodiment is provided. For the sake of brevity, content repeated from the previous description will be omitted below.

[0029] refer to Figure 2 The semiconductor device may include multiple global lines GBL0 to GBLk, multiple local lines LL00 to LLkm, multiple selection transistors ST00 to STkm, and multiple selection lines SL0 to SLm. The selection transistors ST00 to STkm may be arranged in a matrix and connected between the global lines GBL0 to GBLk and the local lines LL00 to LLkm, respectively. For example, the selection transistors ST00 to STkm may operate bidirectionally, allowing current to flow in both directions of the channel pillar CP.

[0030] With this circuit configuration, GIDL may occur during the conduction of the selected selection transistor ST11. An operating voltage is applied to the selected global line GBL1, and ground voltage is applied to the unselected global lines GBL0 and GBL2 to GBLk. A turn-on voltage is applied to the selected selection line SL1, and a turn-off voltage is applied to the unselected selection lines SL0 and SL2 to SLm. In this case, GIDL may occur in the unselected transistors ST10 and ST12 to ST1m connected to the selected global line GBL1.

[0031] Therefore, according to embodiments of this disclosure, by locally increasing the thickness of the gate insulating layer GL of the select transistors ST00 to STkm, the occurrence of GIDL can be reduced. (See again...) Figure 1 The selector transistor ST can operate bidirectionally, and depending on the operating direction of the selector transistor ST, either the first end E1 or the second end E2 can be used as the drain region. The thickness of the gate insulating layer GL in the drain region can be increased by overlapping the first gate insulating layer GLA with the third gate insulating layer GLC, or by overlapping the second gate insulating layer GLB with the third gate insulating layer GLC.

[0032] When the thickness of the gate insulating layer GL is relatively small, the electric field strength applied to the channel pillar CP increases, generating multiple electron-hole pairs and leading to GIDL. Conversely, when the thickness of the gate insulating layer GL is relatively large, the electric field strength applied to the gate insulating layer GL increases, while the electric field strength applied to the channel pillar CP decreases. In this case, the generation of electron-hole pairs decreases, and GIDL also decreases. Therefore, by increasing the thickness of the gate insulating layer GL at the first end E1 and the second end E2, the generation of GIDL can be reduced.

[0033] For reference, the thickness of the gate insulating layer GL can be increased only at the first end E1, or only at the second end E2. For example, when the selected transistor ST operates in one direction, the thickness of the gate insulating layer GL corresponding to the drain region can be increased.

[0034] Figures 3A to 3CThis is a schematic diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure. Figure 3A This is a floor plan. Figure 3B For along Figure 3A A cross-sectional view taken from line A-A' in the diagram. Figure 3C For along Figure 3A The cross-sectional view taken by line B-B' in the diagram. For the sake of brevity, content that is repeated above will be omitted in the following text.

[0035] refer to Figures 3A to 3C The semiconductor device may include a channel pillar CP, a first gate insulating layer GL31, a second gate insulating layer GL32, a third gate insulating layer GL33, a first gap-filling insulating layer GF31, a second gap-filling insulating layer GF32, and a select line 36. The semiconductor device may also include a fourth gate insulating layer GL34, a fifth gate insulating layer GL35, a third gap-filling insulating layer GF33, an insulating layer 38, a global line 30, and a local line 37.

[0036] The channel posts CP can be arranged along a first direction I and a second direction II intersecting the first direction I. Each channel post CP can have a column shape extending along a third direction III. The third direction III can be a direction perpendicular to the first direction I and the second direction II. In the cross-section defined by the first direction I and the second direction II, the channel posts CP can have a shape such as circular, elliptical, or polygonal. For example, the cross-section of the channel post CP can be rectangular. Each channel post CP can include a first end E1, a second end E2, and a channel portion CHP. The width of the first end E1 can be smaller than the width of the second end E2.

[0037] In the first direction I, the first pair of adjacent trench posts CP can be spaced apart by a first distance D1, and in the second direction II, the second pair of adjacent trench posts CP can be spaced apart by a second distance D2. The first distance D1 can be less than the second distance D2.

[0038] A global line (e.g., a global bit line) 30 may be disposed below a channel post CP. The global line 30 may extend along a second direction II, and each global line 30 may connect to a plurality of channel posts CP arranged along the second direction II. The global line 30 may connect to a second end E2.

[0039] A first gap-filling insulating layer GF31 may be disposed between adjacent channel pillars CP in the first direction I and between adjacent global lines 30 in the first direction I. For example, each first gap-filling insulating layer GF31 may be disposed between a first pair of adjacent channel pillars CP in the first direction I and between a pair of adjacent global lines 30 in the first direction I. A first gate insulating layer GL31 may be disposed between a channel pillar CP and a first gap-filling insulating layer GF31 to cover the second end E2. For example, each first gate insulating layer GL31 may be disposed between a corresponding (e.g., contacting) channel pillar CP and a corresponding (e.g., contacting) first gap-filling insulating layer GF31 to cover the second end E2 of the corresponding channel pillar CP. The first gate insulating layer GL31 may cover the sidewalls of the second end E2 facing each other in the first direction I. The first gate insulating layer GL31 may extend between the global line 30 and the first gap-filling insulating layer GF31 and may surround the lower surface of the first gap-filling insulating layer GF31.

[0040] Each first gate insulating layer GL31 may include an insulating material such as an oxide or a nitride. For example, each first gate insulating layer GL31 may include SiOx, AlOx, TiOx, HfOx, LaOx, ZrOx, IGZO, ITO, IZO, InOx, SiN, etc.

[0041] The second gap-filling insulating layer GF32 may be disposed between adjacent channel pillars CP in the second direction II and may extend along the first direction I. For example, each second gap-filling insulating layer GF32 may be disposed between a second pair of adjacent channel pillars CP in the second direction II and may extend along the first direction I. Each second gate insulating layer GL32 may be disposed between a channel pillar CP and a second gap-filling insulating layer GF32 to cover the second end E2. For example, each second gate insulating layer GL32 may be disposed between a corresponding (e.g., contacting) channel pillar CP and a corresponding (e.g., contacting) second gap-filling insulating layer GF32 to cover the second end E2 of the corresponding channel pillar CP. The second gate insulating layer GL32 may cover the sidewalls of the second end E2 facing each other in the second direction II. The second gate insulating layer GL32 may extend between the global line 30 and the second gap-filling insulating layer GF32 and may surround the lower surface of the second gap-filling insulating layer GF32.

[0042] Each second gate insulating layer GL32 may include an insulating material such as an oxide or nitride. For example, each second gate insulating layer GL32 may include SiOx, AlOx, TiOx, HfOx, LaOx, ZrOx, IGZO, ITO, IZO, InOx, SiN, etc.

[0043] Select lines 36 may surround the sidewalls of channel pillars CP arranged along the first direction I and may extend along the first direction I. For example, each select line 36 may surround the sidewalls of a plurality of channel pillars CP arranged along the first direction I and may extend along the first direction I. A third gate insulating layer GL33 may be disposed between the channel pillars CP and the select lines 36 to surround the channel portion CHP. The third gate insulating layer GL33 may overlap with the first gate insulating layer GL31 and the second gate insulating layer GL32. For example, each third gate insulating layer GL33 may surround the channel portion CHP of a plurality of channel pillars CP arranged along the first direction I and overlap with the corresponding (e.g., contacting) first gate insulating layer GL31 and second gate insulating layer GL32. Each third gate insulating layer GL33 may include an insulating material such as an oxide or nitride. For example, each third gate insulating layer GL33 may include SiOx, AlOx, TiOx, HfOx, LaOx, ZrOx, IGZO, ITO, IZO, InOx, SiN, etc.

[0044] Select lines 36 may surround the sidewalls of channel pillars CP arranged along the first direction I, with first to third gate insulating layers GL31 to GL33 located between the select lines 36 and the sidewalls of the channel pillars CP. For example, each select line 36 may surround the sidewalls of multiple channel pillars CP arranged along the first direction I, with corresponding (e.g., contacting or adjacent) first, second, and third gate insulating layers GL31, GL32, and GL33 located between the select lines 36 and the sidewalls of the channel pillars CP. Each select line 36 may include a conductive material, such as a metal or a metal nitride. For example, each select line 36 may include TiN, W, WSIN, WN, etc.

[0045] The upper surface of the first gap-filling insulating layer GF31 may be disposed at a lower level than the upper surface of the first gate insulating layer GL31. The upper surface of the second gap-filling insulating layer GF32 may be disposed at a lower level than the upper surface of the second gate insulating layer GL32. The third gate insulating layer GL33 may extend along the surfaces of the first gate insulating layer GL31, the first gap-filling insulating layer GF31, the second gate insulating layer GL32, and the second gap-filling insulating layer GF32.

[0046] Each third gate insulating layer GL33 may include a first portion GL33A and a second portion GL33B. The first portion GL33A surrounds the channel portion CHP of a corresponding (e.g., contacted) channel pillar CP, and the second portion GL33B covers a corresponding (e.g., contacted) first gate insulating layer GL31 and a corresponding second gate insulating layer GL32. A portion 36A of the select line 36 corresponding to the first portion GL33A may have a first width W11, and a portion 36B of the select line 36 corresponding to the second portion GL33B may have a second width W12 smaller than the first width W11. For example, each select line 36 may have a first portion 36A that is covered by a first portion GL33A of a corresponding (e.g., contacted) third gate insulating layer GL33 and has a first width W11. Furthermore, each select line 36 may have a second portion 36B that is covered by a second portion GL33B of a corresponding third gate insulating layer GL33 and has a second width W12 smaller than the first width W11.

[0047] A third gap-filling insulating layer GF33 may be disposed between adjacent channel posts CP in the first direction I and between adjacent channel posts CP in the second direction II, to surround the first end E1. For example, the third gap-filling insulating layer GF33 may be disposed between a first plurality of adjacent channel posts CP in the first direction I and between a second plurality of adjacent channel posts CP in the second direction II, to surround the first end E1 of a corresponding (e.g., adjacent) channel post CP. The third gap-filling insulating layer GF33 may extend between adjacent select lines (e.g., a pair of select lines) 36 in the second direction II.

[0048] A fourth gate insulating layer GL34 may cover the sidewalls of the first end E1 that face each other in the first direction I. For example, the fourth gate insulating layer GL34 may cover the corresponding sidewalls of the first end E1 that face each other in the first direction I. The fourth gate insulating layer GL34 may be disposed between the channel pillar CP and the third gap-filling insulating layer GF33 and overlap with the third gate insulating layer GL33. For example, each fourth gate insulating layer GL34 may be disposed between a corresponding (e.g., contacting) channel pillar CP and a corresponding (e.g., contacting) third gap-filling insulating layer GF33 and overlap with a corresponding (e.g., contacting) third gate insulating layer GL33. Each fourth gate insulating layer GL34 may include an insulating material, such as an oxide or nitride. For example, each fourth gate insulating layer GL34 may include SiOx, AlOx, TiOx, HfOx, LaOx, ZrOx, IGZO, ITO, IZO, InOx, SiN, etc.

[0049] A fifth gate insulating layer GL35 may cover the sidewalls of the first end E1 that face each other in the second direction II. For example, the fifth gate insulating layer GL35 may cover the corresponding sidewalls of the first end E1 that face each other in the second direction II. The fifth gate insulating layer GL35 may be disposed between the channel pillar CP and the third gap-filling insulating layer GF33 and overlap with the third gate insulating layer GL33. For example, each fifth gate insulating layer GL35 may be disposed between a corresponding (e.g., contacting) channel pillar CP and a corresponding (e.g., contacting) third gap-filling insulating layer GF33 and overlap with a corresponding (e.g., contacting) third gate insulating layer GL33. Each fifth gate insulating layer GL35 may include an insulating material such as an oxide or nitride. For example, each fifth gate insulating layer GL35 may include SiOx, AlOx, TiOx, HfOx, LaOx, ZrOx, IGZO, ITO, IZO, InOx, SiN, etc.

[0050] Local lines (e.g., local bit lines) 37 may be connected to the channel post CP, respectively. For reference, the reference numeral "37" may indicate a portion of a local line or a contact plug for connecting the local line and the channel post CP to each other. Local line 37 may be connected to a first end E1 of the channel post CP, and local line 30 may be connected to a second end E2 of the channel post CP. An insulating layer 38 may be filled between the local lines 37.

[0051] According to the above structure, by overlapping the first gate insulating layer GL31 and the second gate insulating layer GL32 with the third gate insulating layer GL33, and by overlapping the fourth gate insulating layer GL34 and the fifth gate insulating layer GL35 with the third gate insulating layer GL33, the thickness of the gate insulating layer can be locally increased. Specifically, the thickness of this gate insulating layer, including the first, second, third, fourth, and fifth gate insulating layers GL31, GL32, GL33, GL34, and GL35, can be increased in the region overlapping with the drain region of the select transistor ST. Therefore, the occurrence of GIDL during the operation of the select transistor ST can be reduced.

[0052] Figure 4A and Figure 4B This is a schematic diagram illustrating the structure of a semiconductor device according to one embodiment. For the sake of brevity, any parts overlapping with the foregoing will be omitted below.

[0053] refer to Figure 4A and Figure 4BThe semiconductor device may include a channel pillar CP, a third gate insulating layer GL43, a fourth gate insulating layer GL44, a fifth gate insulating layer GL45, and a select line 46. The semiconductor device may also include a first gate insulating layer GL41, a second gate insulating layer GL42, a first gap-filling insulating layer GF41, a second gap-filling insulating layer GF42, a third gap-filling insulating layer GF43, a global line 40, a local line 47, and an insulating layer 48.

[0054] The channel posts CP can be arranged along a first direction I and a second direction II intersecting the first direction I. Each channel post CP may include a first end E1, a second end E2, and a channel portion CHP. A global line 40 may be disposed below the channel posts CP. The global line 40 may extend along the second direction II, and each global line 40 may connect to a plurality of channel posts CP arranged along the second direction II.

[0055] A first gap-filling insulating layer GF41 may be disposed between adjacent channel pillars CP in the first direction I and between adjacent global lines 40 in the first direction I. For example, each first gap-filling insulating layer GF41 may be disposed between a first pair of adjacent channel pillars CP in the first direction I and between a pair of adjacent global lines 40 in the first direction I. A first gate insulating layer GL41 may be disposed between a channel pillar CP and a first gap-filling insulating layer GF41 to cover the second end E2. For example, each first gate insulating layer GL41 may be disposed between a corresponding (e.g., contacting) channel pillar CP and a corresponding (e.g., contacting) first gap-filling insulating layer GF41 to cover the second end E2 of the corresponding channel pillar CP. The upper surface of the first gap-filling insulating layer GF41 may be substantially at the same level as the upper surface of the first gate insulating layer GL41. For example, the horizontal difference between the upper surface of the first gap-filling insulating layer GF41 and the upper surface of the first gate insulating layer GL41 may be equal to or less than 5%, 3% or 1% of the average height of the first gap-filling insulating layer GF41 and the first gate insulating layer GL41 in the third direction III.

[0056] The second gap-filling insulating layer GF42 may be disposed between adjacent channel pillars CP in the second direction II and may extend in the first direction I. For example, each second gap-filling insulating layer GF42 may be disposed between a second pair of adjacent channel pillars CP in the second direction II and may extend in the first direction I. The second gate insulating layer GL42 may be disposed between the channel pillar CP and the second gap-filling insulating layer GF42 to cover the second end E2. For example, each second gate insulating layer GL42 may be disposed between a corresponding (e.g., contacting) channel pillar CP and a corresponding (e.g., contacting) second gap-filling insulating layer GF42 to cover the second end E2 of the corresponding channel pillar CP. The upper surface of the second gap-filling insulating layer GF42 may be disposed at substantially the same level as the upper surface of the second gate insulating layer GL42.

[0057] A fourth gate insulating layer GL44 may cover the sidewalls of the first end E1 that face each other in the first direction I. For example, the fourth gate insulating layer GL44 may cover the corresponding sidewalls of the first end E1 that face each other in the first direction I. The fourth gate insulating layer GL44 may be disposed between the channel pillar CP and the third gap-filling insulating layer GF43, and may overlap with the third gate insulating layer GL43. For example, each fourth gate insulating layer GL44 may be disposed between a corresponding (e.g., contacting) channel pillar CP and a corresponding (e.g., contacting) third gap-filling insulating layer GF43, and may overlap with a corresponding (e.g., contacting) third gate insulating layer GL43.

[0058] The fifth gate insulating layer GL45 may cover the sidewalls of the first end E1 that face each other in the second direction II. For example, the fifth gate insulating layer GL45 may cover the corresponding sidewalls of the first end E1 that face each other in the second direction II. The fifth gate insulating layer GL45 may be disposed between the channel pillar CP and the third gap-filling insulating layer GF43, and may overlap with the third gate insulating layer GL43. For example, each fifth gate insulating layer GL45 may be disposed between a corresponding (e.g., contacting) channel pillar CP and a corresponding (e.g., contacting) third gap-filling insulating layer GF43, and may overlap with a corresponding (e.g., contacting) third gate insulating layer GL43.

[0059] Select lines 46 may surround the sidewalls of channel pillars CP arranged along the first direction I and may extend along the first direction I. For example, each select line 46 may surround the sidewalls of multiple channel pillars CP arranged along the first direction I and may extend along the first direction I. A third gate insulating layer GL43 may be disposed between the channel pillars CP and the select lines 46 to surround the channel portion CHP. For example, each third gate insulating layer GL43 may surround the channel portion CHP of multiple channel pillars CP arranged along the first direction I and overlap with corresponding (e.g., contacting) fourth gate insulating layers GL44 and fifth gate insulating layers GL45. Select lines 46 may surround the sidewalls of the channel pillars CP arranged along the first direction I, and third to fifth gate insulating layers GL43 to GL45 are located between the select lines 46 and the sidewalls of the channel pillars CP. For example, each select line 46 may surround the sidewall of a plurality of channel pillars CP arranged along the first direction I, and the corresponding (e.g., contacting or adjacent) third, fourth and fifth gate insulating layers GL43, GL44 and GL45 are located between the select line 46 and the sidewall of the channel pillar CP.

[0060] A third gap-filling insulating layer GF43 may be disposed between adjacent channel posts CP in the first direction I and between adjacent channel posts CP in the second direction II, to surround the first end E1. For example, the third gap-filling insulating layer GF43 may be disposed between a first pair of adjacent channel posts CP in the first direction I and between a second pair of adjacent channel posts CP in the second direction II, to surround the first end E1 of a corresponding (e.g., adjacent) channel post CP. The third gap-filling insulating layer GF43 may extend between adjacent select lines (e.g., a pair of select lines) 46 in the second direction II.

[0061] Local lines (e.g., local bit lines) 47 may be connected to the channel post CP. Local lines 47 may be connected to a first end E1 of the channel post CP, and global lines 40 may be connected to a second end E2 of the channel post CP. An insulating layer 48 may be filled between the local lines 47.

[0062] According to the above structure, by overlapping the fourth gate insulating layer GL44 and the fifth gate insulating layer GL45 with the third gate insulating layer GL43, the thickness of the gate insulating layer can be locally increased, thereby reducing the occurrence of GIDL during the operation of the select transistor ST.

[0063] Figure 5A and Figure 5B This is a schematic diagram illustrating the structure of a semiconductor device according to one embodiment. For the sake of brevity, any parts overlapping with the foregoing will be omitted below.

[0064] refer to Figure 5A and Figure 5BThe semiconductor device may include a channel pillar CP, a first gate insulating layer GL51, a second gate insulating layer GL52, a third gate insulating layer GL53, a first gap-filling insulating layer GF51, a second gap-filling insulating layer GF52, and a select line 56. The semiconductor device may also include a third gap-filling insulating layer GF53, a global line 50, a local line 57, and an insulating layer 58.

[0065] The channel posts CP can be arranged along a first direction I and a second direction II intersecting the first direction I. Each channel post CP may include a first end E1, a second end E2, and a channel portion CHP. A global line 50 may be disposed below the channel posts CP. The global line 50 may extend along the second direction II, and each global line 50 may connect to a plurality of channel posts CP arranged along the second direction II.

[0066] The first gap-filling insulating layer GF51 may be disposed between adjacent channel pillars CP in the first direction I and between adjacent global lines 50 in the first direction I. A first gate insulating layer GL51 may be disposed between the channel pillars CP and the first gap-filling insulating layer GF51 to cover the second end E2. The upper surface of the first gap-filling insulating layer GF51 may be disposed at a level lower than the upper surface of the first gate insulating layer GL51.

[0067] The second gap-filling insulating layer GF52 may be disposed between adjacent channel pillars CP in the second direction II and may extend along the first direction I. The second gate insulating layer GL52 may be disposed between the channel pillars CP and the second gap-filling insulating layer GF52 to cover the second end E2. The upper surface of the second gap-filling insulating layer GF52 may be disposed at a level lower than the upper surface of the second gate insulating layer GL52.

[0068] The select line 56 may surround the sidewall of the channel pillars CP arranged along the first direction I and may extend along the first direction I. A third gate insulating layer GL53 may be disposed between the channel pillars CP and the select line 56 to surround the channel portion CHP. The select line 56 may surround the sidewall of the channel pillars CP arranged along the first direction I, and the first to third gate insulating layers GL51 to GL53 are located between the select line 56 and the sidewall of the channel pillars CP.

[0069] A third gap-filling insulating layer GF53 may be disposed between adjacent channel posts CP in the first direction I and between adjacent channel posts CP in the second direction II, to surround the first end E1. The third gap-filling insulating layer GF53 may extend between adjacent select lines (e.g., a pair of select lines) 56 in the second direction II.

[0070] Local lines (e.g., local bit lines) 57 may be connected to the channel post CP. Local lines 57 may be connected to a first end E1 of the channel post CP, and global lines 50 may be connected to a second end E2 of the channel post CP. An insulating layer 58 may be filled between the local lines 57.

[0071] According to the above structure, by overlapping the first gate insulating layer GL51 and the second gate insulating layer GL52 with the third gate insulating layer GL53, the thickness of the gate insulating layer can be locally increased. Therefore, the occurrence of GIDL during the operation of the select transistor ST can be reduced.

[0072] Figure 6 This is a schematic diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure. For the sake of brevity, portions that are repetitive with the foregoing will be omitted below.

[0073] refer to Figure 6 Semiconductor devices may include global bit lines (GBBL), select lines (SL), local bit lines (LBL), stacked blocks (STK), memory cells (MC), and interlayer insulating layers (IL).

[0074] The select line SL can be set on the global bit line GBBL, and the select transistor ST can be set in the region where the global bit line GBBL and the select line SL intersect.

[0075] A stacked STK may be disposed on an interlayer insulating layer IL. The stacked STK may include alternately stacked word lines WL and an insulating layer 62. A local bit line LBL may extend along a third direction III through the stacked STK. A memory cell MC may be disposed in the region where the local bit line LBL intersects with the word line 61. Memory cells MC may be stacked along the local bit line LBL, and memory cells MC stacked along the same local bit line LBL may constitute a memory unit MU.

[0076] Each memory cell MC may include a first electrode 63, a variable resistance layer 64, and a second electrode 65. The second electrode 65 may surround the sidewall of a local bit line LBL. The variable resistance layer 64 may be disposed between the local bit line LBL and the word line WL. The first electrode 63 may be disposed between the variable resistance layer 64 and the word line WL.

[0077] The variable resistance layer 64 may have the characteristic of reversibly switching between different resistance states according to the voltage or current applied to the storage cell MC. For example, when the variable resistance layer 64 is in a low resistance state, it can store the data "1", while when the variable resistance layer 64 is in a high resistance state, it can store the data "0".

[0078] For example, the variable resistance layer 64 may include a resistive material. Electrical pathways are created or eliminated in the variable resistance layer 64, thereby enabling data storage. For example, the variable resistance layer 64 may include a transition metal oxide, or a metal oxide such as a perovskite-based material.

[0079] For example, the variable resistance layer 64 may have a magnetic tunnel junction (MTJ) structure, which includes a magnetized fixed layer, a tunnel barrier layer, and a magnetized free layer. Data can be stored based on the change in the magnetization direction of the magnetized free layer relative to the magnetization direction of the magnetized fixed layer. For example, both the magnetized fixed layer and the magnetized free layer may include magnetic materials, while the tunnel barrier layer may include a metal oxide.

[0080] For example, the variable resistance layer 64 may comprise a phase change material or a chalcogenide-based material. The variable resistance layer 64 can change its phase state according to a programmed operation. For example, the variable resistance layer 64 can be changed to a low-resistance crystalline state by a set operation. For example, the variable resistance layer 64 can be changed to a high-resistance amorphous state by a reset operation. Therefore, data can be stored in the memory cell MC by utilizing the resistance difference generated according to the phase state of the variable resistance layer 64.

[0081] For example, the variable resistance layer 64 may comprise a variable resistance material whose resistance changes but does not undergo a phase transition, or it may comprise a chalcogenide-based material. The variable resistance layer 64 may retain its phase state after a programming operation. For example, the variable resistance layer 64 may be amorphous and may remain amorphous without becoming crystalline after a programming operation. The threshold voltage of the memory cell MC may vary depending on the programming voltage applied to the memory cell MC, and the memory cell MC may be programmed into at least two states. For example, the memory cell MC may be programmed into a set state or a reset state using programming voltages with different polarities. Therefore, data can be stored in the memory cell MC by utilizing the difference in its threshold voltage.

[0082] According to the above structure, the selection transistor ST can be connected between the global bit line GBBL and the local bit line LBL, and the selection transistor ST can be used to select the memory cell MU.

[0083] Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A and Figure 12A , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B and Figure 12B ,as well as Figure 7C , Figure 8C , Figure 9C , Figure 10C , Figure 11C and Figure 12C This is a schematic diagram illustrating a method for manufacturing a semiconductor device according to one embodiment. Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A and Figure 12A It's a floor plan. Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B and Figure 12B They are along Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A and Figure 12A A cross-sectional view taken from line C-C'. Figure 7C , Figure 8C , Figure 9C , Figure 10C , Figure 11C and Figure 12C respectively along Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A and Figure 12A The cross-sectional view taken by line D-D'. For the sake of brevity, content that is repeated in the previous description will be omitted in the following text.

[0084] refer to Figures 7A to 7C A channel layer is formed on the conductive layer, and a hard mask 72 is formed on the channel layer. Subsequently, the channel layer and the conductive layer are etched using the hard mask 72 as an etching barrier to form a channel pattern 71 and a global line 70. The channel pattern 71 and the global line 70 may extend along a second direction II. First trenches T1 may be formed between the channel patterns 71 and between the global lines 70. For example, each first trench T1 may be formed between a pair of adjacent channel patterns 71 along a first direction I intersecting the second direction II. The first trenches T1 may extend along the second direction II.

[0085] Subsequently, a first gate insulating layer (or initial first gate insulating layer) 73 may be formed in the first trench T1. The first gate insulating layer 73 may be formed along the contours of the global line 70, the channel pattern 71, and the hard mask 72. Subsequently, a first gap-fill insulating layer 74 may be formed on the first gate insulating layer 73. The first gap-fill insulating layer 74 may be formed to fill the first trench T1.

[0086] refer to Figures 8A to 8CThe second trench T2 extending along the first direction I can be formed by etching the channel pattern 71, the first gap-filling insulating layer 74, and the first gate insulating layer 73. For example, the channel pillars 71A, the second trench T2, and the intermediate first gate insulating layer 73A can be formed by etching the channel pattern 71, the first gap-filling insulating layer 74, and the initial first gate insulating layer 73. The channel pattern 71 can be separated into channel pillars 71A by the second trench T2. The channel pillars 71A can be arranged along the first direction I and the second direction II. The channel pillars 71A can be spaced apart from each other by a second distance D2 in the second direction II, and can be spaced apart from each other by a first distance D1 in the first direction I that is less than the second distance D2. The first gap-filling insulating layer 74A and the intermediate first gate insulating layer 73A can be separated by the second trench T2.

[0087] Subsequently, a second gate insulating layer (or an initial second gate insulating layer) 75 may be formed in the second trench T2. The second gate insulating layer 75 may be formed along the surfaces of the channel pillar 71A, the global line 70, and the hard mask 72. Subsequently, a second gap-fill insulating layer 76 may be formed on the second gate insulating layer 75. The second gap-fill insulating layer 76 may fill the second trench T2.

[0088] refer to Figures 9A to 9C The third trench T3 can be formed by etching the second gap-filling insulating layer 76, the second gate insulating layer 75, the first gap-filling insulating layer 74A, and the first gate insulating layer 73A. For example, the third trench T3, the first gate insulating layer 73B, and the second gate insulating layer 75A can be formed by etching the second gap-filling insulating layer 76, the initial second gate insulating layer 75, the first gap-filling insulating layer 74A, and the intermediate first gate insulating layer 73A. The sidewalls of the channel pillar 71A can be exposed through the third trench T3. The upper surfaces of the first gap-filling insulating layer 74B and the first gate insulating layer 73B can be set at substantially the same level. The upper surfaces of the second gap-filling insulating layer 76A and the second gate insulating layer 75A can also be set at substantially the same level.

[0089] refer to Figures 10A to 10C The first gap-filling insulating layer 74B and the second gap-filling insulating layer 76A can be selectively etched. Thus, the upper surface of the first gap-filling insulating layer (or the etched first gap-filling insulating layer) 74C can be positioned at a lower level than the upper surface of the first gate insulating layer 73B. The upper surface of the second gap-filling insulating layer (or the etched second gap-filling insulating layer) 76B can be positioned at a lower level than the upper surface of the second gate insulating layer 75A.

[0090] refer to Figures 11A to 11CA third gate insulating layer (or an initial third gate insulating layer) 77 may be formed in the third trench T3. The third gate insulating layer 77 may be formed along the contours of the channel pillar 71A, the first gate insulating layer 73B, the first gap-fill insulating layer 74C, the second gate insulating layer 75A, the second gap-fill insulating layer 76B, and the hard mask 72. For example, the initial third gate insulating layer 77 may extend along the surfaces of the first gate insulating layer 73B, the etched first gap-fill insulating layer 74C, the second gate insulating layer 75A, and the etched second gap-fill insulating layer 76B. The third gate insulating layer 77 may surround the sidewalls of the channel pillar 71A and may overlap with the first gate insulating layer 73B and the second gate insulating layer 75A.

[0091] Subsequently, a conductive layer 78 may be formed on the third gate insulating layer 77. The conductive layer 78 may fill a portion of the third trench T3. The third trench T3 may have a first width W1 between adjacent channel pillars 71A in the first direction I. The third trench T3 may have a second width W2 between adjacent channel pillars 71A in the second direction II, the second width W2 being greater than the first width W1. The conductive layer 78 may be deposited along the contour of the third gate insulating layer 77 and may substantially completely fill the third trench T3 between adjacent channel pillars 71A in the first direction I. However, the third trench T3 may have a large width between adjacent channel pillars 71A in the second direction II, so the third trench T3 may be partially filled by the conductive layer 78.

[0092] refer to Figures 12A to 12C The select line 78A can be formed by etching the conductive layer 78. The third gate insulating layer 77A can be formed by etching the third gate insulating layer 77. The select line 78A can surround the sidewalls of the channel pillars 71A arranged along the first direction I and extend along the first direction I. The select line 78A can surround the sidewalls of the channel pillars 71A, and the first gate insulating layer 73B, the second gate insulating layer 75A and the third gate insulating layer 77A are located between the select line 78A and the sidewalls of the channel pillars 71A. For example, each select line 78A can surround a plurality of channel pillars 71A arranged along the first direction I, and the corresponding first, second and third gate insulating layers 73B, 75A and 77A are located between the select line 78A and the channel pillars 71A.

[0093] Subsequently, despite Figures 12A to 12CNot shown, but local lines (e.g., local bit lines) can be formed, each connected to the channel post 71A and extending along a third direction III. The third direction III may intersect with the first direction I and the second direction II. For example, an alternating stack of first and second material layers can be formed on the channel post 71A. Subsequently, holes extending through the stack and exposing the channel post 71A can be formed. A groove can then be formed by etching the first material layer, and a first electrode layer and a variable resistance layer can be formed in the groove. Local lines can then be formed in the holes. Each local line may have a pillar shape and fill the hole. The first material layer can then be replaced with a word line.

[0094] According to the method described above, the third gate insulating layer 77A can be formed to overlap with the corresponding (e.g., contacting) first gate insulating layer 73B and second gate insulating layer 75A. Therefore, the thickness of the gate insulating layer of the selection transistor can be locally increased.

[0095] Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A and Figure 18A as well as Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B and Figure 18B This is a schematic diagram illustrating a method for manufacturing a semiconductor device according to one embodiment. For the sake of brevity, content that is repeated in the previous description will be omitted below.

[0096] refer to Figure 13A and Figure 13B A channel layer 81 is formed on the conductive layer 80, and a hard mask 82 is formed on the channel layer 81. A first preliminary trench PT1 is then formed by etching the channel layer 81 using the hard mask 82 as an etching barrier. The first preliminary trench PT1 can be formed by etching a portion of the thickness of the channel layer 81. The first preliminary trench PT1 can extend along a second direction II. Subsequently, a fourth gate insulating layer (or initial fourth gate insulating layer) 83 can be formed in the first preliminary trench PT1. The fourth gate insulating layer 83 can be formed along the contours of the channel layer 81 and the hard mask 82.

[0097] refer to Figure 14A and Figure 14B The fourth gate insulating layer 83A and the channel pattern 81A can be formed by etching the initial fourth gate insulating layer 83 and the channel layer 81. Subsequently, the global line 80A can be formed by etching the conductive layer 80. Thus, the first trench T1 can be formed.

[0098] The channel pattern 81A, global line 80A, and first trench T1 may extend along the second direction II. The fourth gate insulating layer 83A may surround the upper sidewall of the channel pattern 81A. The lower width of the channel pattern 81A may be greater than the upper width of the channel pattern 81A, and the width difference between the upper and lower parts of the channel pattern 81A may correspond to the thickness of the fourth gate insulating layer 83A.

[0099] Subsequently, a first gate insulating layer (or initial first gate insulating layer) 84 may be formed in the first trench T1. The first gate insulating layer 84 may be formed along the contours of the global line 80A, the channel pattern 81A, the fourth gate insulating layer 83A, and the hard mask 82. Subsequently, a first gap-fill insulating layer 85 may be formed on the first gate insulating layer 84. The first gap-fill insulating layer 85 may be formed to fill the first trench T1.

[0100] refer to Figure 15A and Figure 15B The second initial trench PT2 can be formed by etching the hard mask 82, the channel pattern 81A, the first gap-filling insulating layer 85, the initial first gate insulating layer 84, and the fourth gate insulating layer 83A. The second initial trench PT2 can be formed by etching a portion of the thickness of the channel pattern 81A. The second initial trench PT2 can extend along the first direction I. Subsequently, a fifth gate insulating layer (or an initial fifth gate insulating layer) 86 can be formed in the second initial trench PT2. The fifth gate insulating layer 86 can be formed along the contours of the channel pattern 81A and the hard mask 82.

[0101] refer to Figure 16A and Figure 16B The channel pillar 81B, the fifth gate insulating layer 86A, and the second trench T2 can be formed by etching the channel pattern 81A, the initial fifth gate insulating layer 86, the first gate insulating layer 84, and the first gap-filling insulating layer 85. The channel pillar 81B can be arranged along a first direction I and a second direction II. The second trench T2 can extend along the first direction I.

[0102] The channel pillar 81B may have a rectangular plane and may include a first sidewall facing each other in a first direction I and a second sidewall facing each other in a second direction II. A fourth gate insulating layer 83A may be formed on the first sidewall of the channel pillar 81B, and a fifth gate insulating layer 86A may be formed on the second sidewall of the channel pillar 81B. The lower width of the channel pillar 81B may be greater than the upper width of the channel pillar 81B. The width difference between the upper and lower portions of the channel pillar 81B in the first direction I may correspond to the thickness of the fourth gate insulating layer 83A, and the width difference between the upper and lower portions of the channel pillar 81B in the second direction II may correspond to the thickness of the fifth gate insulating layer 86A.

[0103] Subsequently, a second gate insulating layer 87 may be formed in the second trench T2. The second gate insulating layer 87 may be formed along the surfaces of the hard mask 82, the fifth gate insulating layer 86A, the channel pillar 81B, and the global line 80A. Subsequently, a second gap-fill insulating layer 88 may be formed on the second gate insulating layer 87. The second gap-fill insulating layer 88 may fill the second trench T2.

[0104] refer to Figure 17A and Figure 17B The third trench T3 can be formed by etching the second gap-filling insulating layer 88, the second gate insulating layer 87, the first gap-filling insulating layer 85, and the first gate insulating layer 84. The fourth gate insulating layer 83A and the fifth gate insulating layer 86A can be exposed through the third trench T3. The sidewalls of the channel pillar 81B can be exposed through the third trench T3. The sidewalls of the channel pillar 81B can be exposed between the first gate insulating layer 84A and the fourth gate insulating layer 83A, and between the second gate insulating layer 87A and the fifth gate insulating layer 86A.

[0105] The upper surface of the first gap-filling insulating layer 85A and the upper surface of the first gate insulating layer 84A may be substantially the same or different from each other. Similarly, the upper surface of the second gap-filling insulating layer 88A and the upper surface of the second gate insulating layer 87A may be substantially the same or different from each other. For example, the upper surface of the first gap-filling insulating layer 85A may be at a lower level than the upper surface of the first gate insulating layer 84A. The upper surface of the second gap-filling insulating layer 88A may be at a lower level than the upper surface of the second gate insulating layer 87A.

[0106] refer to Figure 18A and Figure 18B A third gate insulating layer 89 and a select line 90 may be formed in the third trench T3. The third gate insulating layer 89 may overlap with the first gate insulating layer 84A, the second gate insulating layer 87A, the fourth gate insulating layer 83A, and the fifth gate insulating layer 86A. For example, each third gate insulating layer 89 may overlap with a corresponding (e.g., contacting) fourth gate insulating layer 83A and fifth gate insulating layer 86A.

[0107] According to the above method, the third gate insulating layer 89 can be formed to overlap with the first, second, fourth, and fifth gate insulating layers 84A, 87A, 83A, and 86A. Therefore, the thickness of the gate insulating layer of the select transistor can be locally increased.

[0108] Figure 19A , Figure 19B , Figure 20A and Figure 20B This is a schematic diagram illustrating a method for manufacturing a semiconductor device according to one embodiment. For the sake of brevity, content that is repeated in the previous description will be omitted below.

[0109] refer to Figure 19A and Figure 19B It can form a global line 100, a channel pillar 110, a hard mask 120, a first gate insulating layer 140, a first gap filling insulating layer 150, a second gate insulating layer 170, a second gap filling insulating layer 180, a fourth gate insulating layer 130, and a fifth gate insulating layer 160.

[0110] Subsequently, a third trench T3 can be formed by etching the second gap-filling insulating layer 180, the second gate insulating layer 170, the first gap-filling insulating layer 150, and the first gate insulating layer 140. The fourth gate insulating layer 130 and the fifth gate insulating layer 160 can be exposed through the third trench T3. The sidewalls of the channel pillar 110 can be exposed through the third trench T3. The sidewalls of the channel pillar 110 can be exposed between the first gate insulating layer 140 and the fourth gate insulating layer 130, and between the second gate insulating layer 170 and the fifth gate insulating layer 160. The upper surfaces of the first gap-filling insulating layer 150 and the first gate insulating layer 140 can be substantially at the same level as each other. The upper surfaces of the second gap-filling insulating layer 180 and the second gate insulating layer 170 can be substantially at the same level or at different levels as each other.

[0111] refer to Figure 20A and Figure 20B A third gate insulating layer 190 and a select line 200 may be formed in the third trench T3. The third gate insulating layer 190 may overlap with the fourth gate insulating layer 130 and the fifth gate insulating layer 160.

[0112] According to the method described above, the third gate insulating layer 190 can be formed to overlap with the fourth gate insulating layer 130 and the fifth gate insulating layer 160. Therefore, the thickness of the gate insulating layer of the selection transistor can be locally increased.

[0113] Although some embodiments of this disclosure have been described above with reference to the accompanying drawings, the various embodiments of this disclosure are not limited to the embodiments described above. Those skilled in the art to which this disclosure pertains can make various types of substitutions, modifications, changes, and combinations to these embodiments, and such substitutions, modifications, changes, and combinations are embodiments of this disclosure.

Claims

1. A semiconductor device, comprising: The channel posts are arranged along a first direction and a second direction intersecting the first direction, each of the channel posts including a first end, a second end, and a channel portion disposed between the first end and the second end; A first gap is filled with an insulating layer, each of the first gaps filled with an insulating layer being disposed between the first pair of trench posts, the first pair of trench posts being adjacent to each other in the first direction; A first gate insulating layer, each of the first gate insulating layers being disposed between a corresponding channel pillar and a corresponding first gap filling insulating layer to cover the second end; A second gap filling insulating layer is disposed between the second pair of trench posts, the second pair of trench posts being adjacent to each other in the second direction and extending along the first direction; A second gate insulating layer, each of the second gate insulating layers being disposed between a corresponding channel pillar and a corresponding second gap filling insulating layer to cover the second end; Selection lines, each of the selection lines surrounding the sidewall of the first plurality of channel posts, the first plurality of channel posts being arranged along and extending along the first direction; as well as A third gate insulating layer, each of the third gate insulating layers surrounding the channel portion of the first plurality of channel pillars and overlapping with the corresponding first gate insulating layer and second gate insulating layer.

2. The semiconductor device according to claim 1, wherein, Each of the select lines surrounds the sidewall of the first plurality of channel pillars arranged along the first direction, and the corresponding first gate insulating layer, second gate insulating layer and third gate insulating layer are located between the select line and the sidewall of the first plurality of channel pillars.

3. The semiconductor device according to claim 1, wherein, The upper surface of the first gap-filling insulating layer is disposed at a lower level than the upper surface of the first gate insulating layer, and The upper surface of the second gap-filling insulating layer is positioned at a lower level than the upper surface of the second gate insulating layer.

4. The semiconductor device according to claim 3, wherein, The third gate insulating layer extends along the surfaces of the first gate insulating layer, the first gap-filling insulating layer, the second gate insulating layer, and the second gap-filling insulating layer.

5. The semiconductor device according to claim 1, wherein, Each of the third gate insulating layers includes: The first part, which surrounds the channel portion corresponding to one of the channel posts; and The second part covers a corresponding first gate insulating layer and a corresponding second gate insulating layer.

6. The semiconductor device according to claim 5, wherein, Each of the select lines has a first portion, the first portion being covered by a corresponding first portion of the third gate insulating layer, and having a first width, and Each of the selection lines has a second portion, which is covered by a corresponding second portion of the third gate insulating layer, and has a second width that is smaller than the first width.

7. The semiconductor device of claim 1, further comprising a third gap-filling insulating layer disposed between the first pair of channel posts and between the second pair of channel posts to surround the first end of a corresponding one of the channel posts, the first pair of channel posts being adjacent to each other in the first direction and the second pair of channel posts being adjacent to each other in the second direction.

8. The semiconductor device according to claim 7, wherein, The third gap-filling insulating layer extends between a pair of select lines, which are adjacent to each other in the second direction.

9. The semiconductor device of claim 1, further comprising a fourth gate insulating layer covering corresponding sidewalls of the first end facing each other in the first direction. in, Each of the third gate insulating layers overlaps with a corresponding fourth gate insulating layer.

10. The semiconductor device of claim 1, further comprising a fifth gate insulating layer covering corresponding sidewalls of the first end facing each other in the second direction. in, Each of the third gate insulating layers overlaps with a corresponding fifth gate insulating layer.

11. The semiconductor device according to claim 1, wherein, The first pair of trench posts are spaced apart by a first distance, and the second pair of trench posts are spaced apart by a second distance, wherein the first distance is less than the second distance.

12. The semiconductor device according to claim 1, further comprising: The letter lines are stacked on top of the channel posts; Local bit lines, which respectively extend through the word lines and connect to the channel posts; as well as Global bit lines are disposed below the channel posts, and each of the global bit lines is connected to a second plurality of the channel posts arranged along the second direction.

13. A semiconductor device, comprising: The channel posts are arranged along a first direction and a second direction intersecting the first direction, each channel post including a first end, a second end, and a channel portion disposed between the first end and the second end; A fourth gate insulating layer covers the corresponding sidewalls of the first end that face each other in the first direction; A fifth gate insulating layer covers the corresponding sidewalls of the first end that face each other in the second direction; Selection lines, each of the selection lines extending along the first direction and surrounding the sidewalls of the first plurality of channel posts arranged along the first direction; and A third gate insulating layer, each of the third gate insulating layers surrounding the channel portion of the first plurality of channel pillars, and overlapping with the corresponding fourth gate insulating layer and the fifth gate insulating layer.

14. The semiconductor device according to claim 13, further comprising: A first gap is filled with an insulating layer, each of the first gaps filled with an insulating layer being disposed between the first pair of trench posts, the first pair of trench posts being adjacent to each other in the first direction; A first gate insulating layer, each of the first gate insulating layers being disposed between a corresponding channel pillar and a corresponding first gap filling insulating layer to cover the second end; A second gap filling insulating layer is disposed between the second pair of trench posts, the second pair of trench posts being adjacent to each other in the second direction and extending along the first direction; as well as A second gate insulating layer, each of the second gate insulating layers being disposed between a corresponding channel pillar and a corresponding second gap-filling insulating layer to cover the second end.

15. The semiconductor device according to claim 14, wherein, Each of the third gate insulating layers overlaps with a corresponding first gate insulating layer and a corresponding second gate insulating layer.

16. The semiconductor device according to claim 13, wherein, Each of the select lines surrounds the sidewall of the first plurality of channel pillars arranged along the first direction, and the corresponding third gate insulating layer, the fourth gate insulating layer and the fifth gate insulating layer are located between the select line and the sidewall of the first plurality of channel pillars.

17. The semiconductor device according to claim 13, wherein, The first end has a first width and the second end has a second width, wherein the first width is smaller than the second width.

18. The semiconductor device according to claim 13, wherein, The first pair of trench posts are spaced apart by a first distance, and the second pair of trench posts arranged along the second direction are spaced apart by a second distance, wherein the first distance is less than the second distance.

19. The semiconductor device of claim 13, further comprising: The letter lines are stacked on top of the channel posts; Local bit lines, which respectively extend through the word lines and connect to the channel posts; as well as Global bit lines are disposed below the channel posts, and each of the global bit lines is connected to a second plurality of the channel posts arranged along the second direction.

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