Three-dimensional memory, system-in-package structure and electronic device

Abstract

The application discloses a three-dimensional memory, a system-level packaging structure and an electronic device, and relates to the technical field of semiconductors. The three-dimensional memory comprises a first chip and a second chip. The first chip comprises a plurality of first pads. The second chip comprises a first substrate, a plurality of second pads and a plurality of through holes. The through holes penetrate the first substrate. A plurality of conductive parts that are independent of each other are arranged in the through holes. Any conductive part is connected between at least one second pad and at least one first pad. The first chip and the second chip are interconnected through the conductive parts. By integrating a plurality of independent conductive parts in the same through hole, signals are transmitted through each conductive part at a lower rate. The signals can be transmitted between the first chip and the second chip in a multi-line, low-rate mode. Therefore, the signal crosstalk problem can be effectively improved, and the performance and cost-effectiveness of the three-dimensional memory are improved while the total bandwidth remains unchanged.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a three-dimensional memory, a system-in-package structure, and an electronic device. Background Technology

[0002] With the continuous evolution of memory products, 3D memory has attracted widespread attention because it effectively utilizes chip area and improves storage density and performance by stacking multiple chips. However, when 3D memory is working, signal crosstalk usually occurs when transmitting signals between different chips, especially during high-speed signal transmission. Summary of the Invention

[0003] This application provides a three-dimensional memory, a system-in-package structure, and an electronic device to improve the signal crosstalk problem that exists when transmitting signals between different chips.

[0004] In a first aspect, embodiments of this application provide a three-dimensional memory, comprising: a first chip and a second chip. The first chip includes a plurality of first pads, and the second chip is stacked on the first chip. The second chip includes a first substrate, a plurality of second pads, and a plurality of vias penetrating the first substrate. Each via has a plurality of independent conductive portions disposed therein, and each conductive portion connects at least one second pad to at least one first pad. This configuration allows the first chip and the second chip to be interconnected via conductive portions. Furthermore, by integrating multiple independent conductive portions into the same via and transmitting signals through each conductive portion at a lower rate—that is, treating each conductive portion as an independent channel—signal transmission between the first chip and the second chip can be performed in a multi-track, low-rate mode. This effectively improves signal crosstalk while maintaining the total bandwidth, thereby enhancing the performance and cost-effectiveness of the three-dimensional memory.

[0005] In one possible implementation, the via can be a through silicon via (TSV). Since TSV technology is relatively mature, it makes the implementation of vias relatively simple, thereby reducing design difficulty and production costs.

[0006] In one possible implementation, along the radial direction of the through-hole, one of the plurality of conductive portions is at least partially disposed around the outside of another conductive portion, which can make full use of the limited space in the through-hole and achieve a more compact layout. Furthermore, a first insulating dielectric layer is disposed between adjacent conductive portions, which can effectively isolate adjacent conductive portions and reduce short-circuit problems.

[0007] In one possible implementation, along the radial direction of the through-hole, one conductive portion is disposed around the outside of another conductive portion, i.e., along the extension direction of the through-hole, one conductive portion is columnar to form an inner channel, and the other conductive portion is tubular to form an outer channel, such that the conductive portions in the same through-hole form a coaxial structure, further forming multiple channels within a limited space. Furthermore, this coaxial structure can be formed in the same process step, reducing the complexity of the manufacturing process.

[0008] In one possible implementation, the shape of the outer contour of any conductive part in the radial direction of the through hole includes, but is not limited to, a circle, an ellipse, a square, a rectangle, etc.

[0009] In one possible implementation, the three-dimensional memory includes a plurality of second chips to further improve storage density and performance. The plurality of second chips includes a first second chip and a second second chip, with the first second chip disposed between the second second chip and the first chip. Furthermore, the vias in the first second chip are first vias, and the vias in the second second chip are second vias. Each second via corresponds to one of the first vias in the subset of first vias, and the conductive portion in the second via is connected to the conductive portion in the corresponding first via. This allows the second vias in the second second chip to communicate with the first vias in the first second chip, enabling connection to a first pad via the conductive portion in the first via, thereby facilitating signal transmission between the first chip and the second second chip.

[0010] In one possible implementation, the plurality of conductive portions in the first through-hole include a first first conductive portion and a second first conductive portion, with the second first conductive portion surrounding the outside of the first first conductive portion to form a coaxial structure. Similarly, the plurality of conductive portions in the second through-hole include a first second conductive portion and a second second conductive portion, with the second second conductive portion surrounding the outside of the first second conductive portion to form a coaxial structure. Furthermore, one of the first and second second conductive portions is connected to the first first conductive portion, and the other of the first and second second conductive portions is connected to the second first conductive portion. This allows for a one-to-one correspondence between the conductive portions in the first and second through-holes.

[0011] In one possible implementation, the first second conductive part in any second through hole is connected to the first first conductive part in the corresponding first through hole, and the second second conductive part in any second through hole is connected to the second first conductive part in the corresponding first through hole. This configuration allows columnar second conductive parts and columnar first conductive parts to be interconnected, as well as tubular second conductive parts and tubular first conductive parts to be interconnected, so as to connect the inner and outer channels of two adjacent second chips respectively, reducing interconnection complexity and design difficulty.

[0012] In one possible implementation, the first second conductive part in any second through hole is connected to the second first conductive part in the corresponding first through hole, and the second second conductive part in any second through hole is connected to the first first conductive part in the corresponding first through hole. This configuration allows the columnar second conductive part and the tubular first conductive part to be interconnected, as well as the tubular second conductive part and the columnar first conductive part to be interconnected, so as to interleave the inner and outer channels of two adjacent second chips, improve channel characteristics, achieve better channel matching, and improve signal integrity.

[0013] In one possible implementation, the first second conductive portion in a portion of the second through-hole is connected to the second first conductive portion, and the second second conductive portion in a portion of the second through-hole is connected to the first first conductive portion. Furthermore, the first second conductive portion in another portion of the second through-hole is connected to the first first conductive portion, and the second second conductive portion in another portion of the second through-hole is connected to the second first conductive portion. Therefore, for high-speed channels, this method of connecting the conductive portions in the second through-hole can achieve better signal integrity and improved channel characteristics. For low-speed channels, this method of connecting the conductive portions in the other portion of the second through-hole can achieve better cost-effectiveness. Thus, both better channel characteristics and cost can be balanced.

[0014] In one possible implementation, the second chip is a memory chip, comprising multiple memory cells, each corresponding to multiple vias, and the vias for each memory cell are independent of each other. This allows each memory cell to be connected to a first pad through conductive portions in the multiple vias, thereby achieving connection to the input / output (IO) interface in the first chip. This not only enables parallel transmission of multiple signals but also improves area utilization while reducing the number of vias.

[0015] In one possible implementation, the second chip adjacent to the first chip further includes a plurality of first transmission circuits and a plurality of second transmission circuits. Any conductive portion is connected to at least one second pad via a first transmission circuit, and any conductive portion is connected to at least one first pad via a second transmission circuit. Furthermore, the first transmission circuit includes: a first transmitter, an inverter, a delay unit, a second transmitter, and an adder. The input terminals of the first transmitter and the inverter are both connected to at least one second pad. The output terminal of the first transmitter is connected to the first input terminal of the adder. The output terminal of the inverter is connected to the input terminal of the delay unit. The output terminal of the delay unit is connected to the input terminal of the second transmitter. The output terminal of the second transmitter is connected to the second input terminal of the adder. The output terminal of the adder is connected to the conductive portion. Furthermore, the second transmission circuit includes a subtractor, a receiver, an edge detector, and an AND gate. The first input of the subtractor is connected to a conductive portion, the input of the edge detector is connected to another conductive portion, the output of the edge detector is connected to one input of the AND gate, the output of the AND gate is connected to the second input of the subtractor, the output of the subtractor is connected to the input of the receiver, and the output of the receiver is connected to at least one first pad. Thus, by configuring the first and second transmission circuits together, the rising positive pulse signal caused by capacitive crosstalk can be improved, or even eliminated.

[0016] In one possible implementation, the three-dimensional memory is a high-bandwidth memory (HBM) to be used in fields such as high-performance computing, artificial intelligence (AI), and graphics processing to meet the demand for computing efficiency.

[0017] In one possible implementation, the first chip is a logic chip, and the second chip is a memory chip. The first chip includes multiple input / output interfaces, each of which is connected to a conductive portion in at least one through-hole via a first pad. Thus, when the three-dimensional memory is operating, a multi-track, low-speed mode can be used, inputting and outputting signals through the input / output interfaces to perform read and write operations.

[0018] Secondly, this application provides a system-in-package (SIP) structure, which includes a packaging substrate, a processor, and a three-dimensional memory; the three-dimensional memory and the processor are packaged on the packaging substrate. The three-dimensional memory is the same as that in the first aspect or the embodiments thereof. Because the three-dimensional memory in the embodiments of this application has good performance, the system-in-package structure having this three-dimensional memory also has good performance.

[0019] Thirdly, this application provides an electronic device comprising: a circuit board and electronic components, wherein the electronic components are disposed on the circuit board and include a three-dimensional memory and / or a system-in-package (SIP) structure. The three-dimensional memory is the three-dimensional memory of the first aspect or the embodiments thereof, and the SIP structure is the SIP structure of the second aspect or the embodiments thereof. Because three-dimensional memory and SIP structure have good performance, electronic devices having one or more of these components also have good performance.

[0020] Furthermore, the technical effects of the corresponding solutions in the second and third aspects can be referred to the technical effects that can be obtained by the corresponding solutions in the first aspect, and the repetitions will not be detailed. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the structure of an electronic device in an embodiment of this application;

[0022] Figure 2 This is a schematic diagram of a system-level encapsulation structure in an embodiment of this application;

[0023] Figure 3A This is a schematic diagram of a three-dimensional memory structure in an embodiment of this application;

[0024] Figure 3B This is a schematic diagram of a three-dimensional structure of the three-dimensional memory in an embodiment of this application;

[0025] Figure 4A This is a schematic diagram of a through hole along its radial direction in an embodiment of this application;

[0026] Figure 4B This is a three-dimensional structural schematic diagram of a through hole in an embodiment of this application;

[0027] Figure 5A This is a top view schematic diagram of another through hole in the radial direction of the embodiment of this application;

[0028] Figure 5B This is another three-dimensional structural schematic diagram of the through hole in the embodiments of this application;

[0029] Figure 6 This is a schematic diagram of the structure of the second chip in an embodiment of this application;

[0030] Figure 7A This is a schematic diagram of another structure of the three-dimensional memory in the embodiments of this application;

[0031] Figure 7B This is a schematic diagram of another three-dimensional structure of the three-dimensional memory in the embodiments of this application;

[0032] Figure 8A This is a three-dimensional structural schematic diagram of the first through hole and the second through hole in an embodiment of this application;

[0033] Figure 8B This is another three-dimensional structural diagram of the first through hole and the second through hole in the embodiments of this application;

[0034] Figure 9 This is a circuit diagram of one embodiment of the present application;

[0035] Figure 10 This is a signal timing diagram in one embodiment of this application.

[0036] Figure label:

[0037] 10 - Electronic device; 11 - Packaging substrate; 12 - Processor; 13 - Memory; 14 - Interposer; 15 - First interconnect structure; 16 - Second interconnect structure; 17 - Third interconnect structure; 18 - Fourth interconnect structure; 20 - Circuit board; 30 - Housing; 100 - First chip; 110 - First pad; 120 - I / O interface; 130 - Multiplexer; 140 - Fifth interconnect structure; 200 / 200_1 / 200_2 / 200_3 / 200_4 - Second chip; 200a - First second chip; 200b - Second second chip; 210 - First substrate; 220 - Second pad; 230 - Semiconductor device layer; 240 - Interconnect layer; 310 - Through-hole; 310a - First through-hole; 310b - Second through-hole; 311_1 / 311_2 - Conductive portion; 311a_1 - First first conductive portion; 311a_2 - Second first conductive portion; 311b_1 - First second conductive portion; 311b_2 - Second second conductive portion; 410 - First isolation dielectric layer; 420 - Second isolation dielectric layer; 510 - First transmission circuit; 511 - First transmitter; 512 - Inverter; 513 - Delay unit; 514 - Second transmitter; 515 - Adder; 520 - Second transmission circuit. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The specific operational methods in the method embodiments can also be applied to the device embodiments or system embodiments. It should be noted that in the description of this application, "multiple" can be understood as "at least two". Furthermore, it should be understood that in the description of this application, terms such as "first" and "second" are used only for distinguishing purposes and should not be construed as indicating or implying relative importance, nor as indicating or implying order.

[0039] It should be noted that the same reference numerals in the accompanying drawings of this application denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms expressing position and direction described in this application are illustrative based on the accompanying drawings, but may be modified as needed, and all modifications are included within the scope of protection of this application. The accompanying drawings of this application are for illustrating relative positional relationships only and do not represent actual scale.

[0040] The three-dimensional memory provided in this application embodiment can be applied to electronic devices capable of storage functions. For example, the three-dimensional memory can be directly applied to electronic devices or applied to the system-in-package (SIP) structure of electronic devices. Electronic devices include, but are not limited to, terminal devices and communication devices. Terminal devices include, but are not limited to, mobile phones, computers, televisions, set-top boxes, watches, personal computers (PCs), wearable devices, and in-vehicle devices. Communication devices include, but are not limited to, wireless networks, fixed networks, servers, and smart broadband. It is understood that the specific implementation of the three-dimensional memory can be flexibly set according to the actual application scenario and is not limited herein.

[0041] The three-dimensional memory, system-in-package structure, and electronic device provided in the embodiments of this application are described below with reference to the accompanying drawings.

[0042] Figure 1 This is a schematic diagram of the structure of an electronic device according to an embodiment of this application. (Refer to...) Figure 1 The electronic device includes an electronic component 10 and a circuit board 20. The electronic component 10 is disposed on and connected to the circuit board 20. For example, the electronic component 10 can be fixed to the circuit board 20 by bonding or other connection methods to achieve an electrical connection between the electronic component 10 and the circuit board 20, thereby transmitting signals.

[0043] For example, the electronic device may also include a housing 30 having an accommodating space, in which a circuit board 20 is disposed and fixed to the housing 30. Furthermore, the circuit board 20 may include, but is not limited to, a printed circuit board (PCB).

[0044] As an example, electronic device 10 may include a memory. Exemplarily, since three-dimensional memory significantly improves storage density and performance through a vertical stacking process, the memory includes, but is not limited to, the three-dimensional memory provided in the embodiments of this application.

[0045] As yet another example, electronic device 10 may also include a system-in-package (SIP) structure. For example, see reference... Figure 2 , Figure 2This is a schematic diagram of a system-in-package (SIP) structure according to an embodiment of this application. The SIP structure may include a package substrate 11, a processor 12, and a memory 13. The memory 13 and the processor 12 are packaged on the package substrate 11, which can achieve tight packaging of the memory 13 and the processor 12, reducing data transmission distance and lowering latency. Exemplarily, the package substrate 11 can be connected to the circuit board 20 through a first interconnect structure 15. Exemplarily, the SIP structure may also include an interposer (e.g., a silicon interposer) 14. The memory 13 and the processor 12 are disposed on and connected to the interposer 14. For example, the memory 13 can be connected to the interposer through a second interconnect structure 16, and the processor 12 can be connected to the interposer through a third interconnect structure 17, so that the memory 13 and the processor 12 can be interconnected through the interposer 14 for signal transmission. Furthermore, the interposer 14 can be connected to the package substrate 11, for example, through a fourth interconnect structure 18.

[0046] For example, any one of the first interconnect structure 15 to the fourth interconnect structure 18 includes, but is not limited to, solder balls, bumps, microbumps, etc.

[0047] For example, the memory 13 includes, but is not limited to, the three-dimensional memory provided in the embodiments of this application, and the processor 12 includes, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), an AI processor, a digital signal processor (DSP), and a neural network processor, so that the three-dimensional memory in the embodiments of this application can be applied to fields such as high-performance computing, AI, and graphics processing to meet the requirements for computing efficiency.

[0048] As another example, the electronic device 10 may include both a three-dimensional memory and a system-in-package structure.

[0049] Understandably, 3D memory, by stacking multiple chips, can effectively utilize chip area and improve storage density and performance. Furthermore, signals are typically transmitted between chips via interconnects. However, the spacing between these interconnects is limited, leading to signal crosstalk issues when transmitting signals (especially high-speed signals). Moreover, with a fixed total number of I / O interfaces in the 3D memory, the signal transmission rate between chips increases with bandwidth, resulting in gradually intensifying signal crosstalk between interconnects. Therefore, effectively mitigating signal crosstalk while maintaining a constant total bandwidth is a significant challenge. To address this, this application provides a 3D memory that effectively mitigates signal crosstalk while maintaining a constant total bandwidth, thereby improving the performance and cost-effectiveness of the 3D memory.

[0050] Figure 3A This is a schematic diagram of a three-dimensional memory structure in an embodiment of this application. Figure 3B This is a schematic diagram of a three-dimensional structure of the three-dimensional memory in an embodiment of this application. Figure 4A This is a schematic diagram of a through hole along its radial direction in an embodiment of this application. Figure 4B This is a three-dimensional structural schematic diagram of a through hole in an embodiment of this application, with reference to... Figure 3A and Figure 3B , Figure 4A and Figure 4B The three-dimensional memory in this embodiment may include a first chip 100 and a second chip 200. The first chip 100 includes a plurality of first pads 110, and the second chip 200 is stacked on the first chip 100. The second chip 200 includes a first substrate 210, a plurality of second pads 220, and a plurality of through holes 310. The plurality of through holes 310 can penetrate the first substrate 210. Each through hole 310 is provided with a plurality of independent conductive parts (e.g., 311_1, 311_2), and each conductive part (e.g., 311_1, 311_2) is connected between at least one second pad 220 and at least one first pad 110. This configuration allows the first chip 100 and the second chip 200 to be interconnected via conductive parts (e.g., 311_1, 311_2). Furthermore, by integrating multiple independent conductive parts (e.g., 311_1, 311_2) into the same via 310 and transmitting signals through each conductive part (e.g., 311_1, 311_2) at a lower rate, i.e., treating each conductive part (e.g., 311_1, 311_2) as an independent channel, a multi-channel, low-rate signal transmission mode can be used between the first chip 100 and the second chip 200. This effectively improves the signal crosstalk problem while maintaining the total bandwidth, thereby enhancing the performance and cost-effectiveness of the three-dimensional memory.

[0051] Furthermore, in this embodiment, by integrating multiple independent conductive parts into the same through-hole 310, any through-hole 310 in this embodiment can effectively perform the functions of multiple through-holes 310 in related technologies. This improves the area utilization of the through-hole 310 while maintaining the total bandwidth, maximizing the saving of the total area of ​​the through-holes 310 and further enhancing the performance and cost-effectiveness of the 3D memory. For example, in this embodiment, if two conductive parts are provided within one through-hole 310, and the remaining structure of the 3D memory in this embodiment is substantially the same as that in related technologies, the number of through-holes 310 required in this embodiment can be reduced by half compared to the number of through-holes 310 in related technologies. Other cases can be deduced similarly, and specific details are not elaborated here.

[0052] In some embodiments, the signals transmitted by the I / O interface may include: data queue (DQ) signals, command address (CA) signals, clock (CK) signals, test signals (e.g., debug access (DA) signals), etc. The conductive portions in this embodiment can be used to transmit one or more of the following: data signals, command address signals, clock signals, and test signals. Therefore, these signals can be transmitted between the first chip 100 and the second chip 200 through the conductive portions (e.g., 311_1, 311_2) in the via 310, reducing signal latency. Exemplarily, the conductive portions in the same via 310 are used to transmit the same type of signal. For example, at least some conductive portions in the via 310 can be used to transmit data signals, or at least some conductive portions in the via 310 can be used to transmit command address signals, or at least some conductive portions in the via 310 can be used to transmit clock signals, or at least some conductive portions in the via 310 can be used to transmit test signals. Alternatively, the multiple vias 310 in the second chip 200 can be allocated among data signals, command address signals, clock signals, and test signals. For example, any conductive part in the first via 310 can be used to transmit data signals, any conductive part in the second via 310 can be used to transmit command address signals, any conductive part in the third via 310 can be used to transmit clock signals, and any conductive part in the fourth via 310 can be used to transmit test signals.

[0053] It is understood that the radial direction F1 of the via 310 can refer to a direction perpendicular to the extending direction F2 of the via 310 (or the stacking direction of the first chip 100 and the second chip 200). Furthermore, to clearly illustrate the structure of the via 310 in the embodiments of this application, Figure 3A The illustration uses four through holes 310 as an example. Figure 3B The following illustration uses sixteen through-holes 310 as an example. In some embodiments, based on the requirements of inter-chip interconnection and bandwidth, the specific number of through-holes 310 in the second chip 200 can be flexibly designed according to the actual application scenario, and the implementation of these through-holes 310 can be based on the implementation of the through-holes 310 in the embodiments of this application. Furthermore, Figure 3A and Figure 3B A solid line with a one-way arrow represents an electrical signal flow.

[0054] In one embodiment of this application, the through hole 310 can be a TSV (Through-Screen Via) technology. Since TSV technology is relatively mature, implementing the through hole 310 is relatively simple, thereby reducing design difficulty and production costs. In other embodiments of this application, the through hole 310 can also be formed using other through-hole technologies, and no limitation is made here.

[0055] In one embodiment of this application, any conductive part (e.g., 311_1, 311_2) can be connected between a second pad 220 and a first pad 110; alternatively, any conductive part (e.g., 311_1, 311_2) can be connected between a second pad 220 and multiple first pads 110; or alternatively, any conductive part (e.g., 311_1, 311_2) can be connected between multiple second pads 220 and a first pad 110. In practical applications, the number of first pads 110 and second pads 220 that any conductive part (e.g., 311_1, 311_2) can connect to can be flexibly designed according to the actual application scenario, and is not limited here.

[0056] In one embodiment of this application, reference is made to... Figure 4A and Figure 4B Taking one conductive part 311_1 and another conductive part 311_2 among multiple conductive parts as an example, along the radial direction F1 of the through hole 310, one of the multiple conductive parts 311_1 can be at least partially disposed around the outside of another conductive part 311_2, thereby making full use of the limited space in the through hole 310 and achieving a more compact layout. Furthermore, a first insulating dielectric layer 410 is disposed between adjacent conductive parts 311_1 and 311_2, which can effectively isolate adjacent conductive parts and reduce short-circuit problems.

[0057] For example, the material of the first isolation dielectric layer 410 is a dielectric material. For instance, the material of the first isolation dielectric layer 410 is a dielectric material with a low dielectric constant (K), which can reduce the coupling capacitance between adjacent conductive portions 311_1 and 311_2. For example, the dielectric material forming the first isolation dielectric layer 410 includes, but is not limited to, oxides (e.g., SiO2).

[0058] For example, refer to Figure 4A and Figure 4BAlong the radial direction F1 of the through hole 310, the conductive part 311_2 can be disposed around the outside of the conductive part 311_1. That is, in the radial direction of the through hole 310, the conductive part 311_2 is a closed annular structure, and along the extension direction F2 of the through hole 310, the conductive part 311_1 is columnar to form an inner channel, and the conductive part 311_2 is tubular to form an outer channel, so that the conductive parts 311_1 and 311_2 form a coaxial structure, and multiple channels can be formed in a limited space. Furthermore, the coaxial structure of the conductive parts 311_1 and 311_2 can be formed in the same process step, reducing the complexity of the manufacturing process.

[0059] For example, in the radial direction F2 of the through hole 310, the shape of the outer contour of any conductive part (e.g., 311_1, 311_2) includes, but is not limited to, a circle, an ellipse, a square, a rectangle, etc., and is not limited here.

[0060] Understandably, in order to clearly demonstrate the structure of the conductive portion in the through-hole 310 in the embodiments of this application, Figures 3A to 4B The illustration takes two conductive portions 311_1 and 311_2 in the through hole 310 as an example. In other embodiments of this application, three, four or more conductive portions may be provided in the through hole 310, all of which are based on the structure of conductive portions 311_1 and 311_2 in the embodiments of this application. Furthermore, in other embodiments of this application, the conductive portion 311_2 may also be partially disposed around the outside of the conductive portion 311_1 along the radial direction F1 of the through hole 310, that is, the conductive portion 311_2 has a non-closed structure in the radial direction F1 of the through hole 310, thereby forming multiple channels in a limited space. In addition, other conductive portions 311_2 may be additionally provided in the area outside the conductive portion 311_1 that is not provided with the conductive portion 311_2, further making full use of the limited space in the through hole 310 and achieving a more compact layout.

[0061] In one embodiment of this application, reference is made to... Figures 3A to 4B At least one conductive part (e.g., 311_2) can be in direct contact with the sidewall of the through hole 310, thereby enabling the formation of multiple channels within a limited space and improving the area utilization of the through hole 310. For example, the conductive part 311_2 can be in direct contact with the sidewall of the through hole 310. Or, refer to... Figure 5A and Figure 5B , Figure 5A This is a top view schematic diagram of another through hole along its radial direction in an embodiment of this application. Figure 5BThis is another three-dimensional structural diagram of the through hole in this application embodiment. A second insulating dielectric layer 420 is provided between the through hole 310 and multiple conductive parts (e.g., 311_1, 311_2). This prevents the conductive parts from directly contacting the sidewall of the through hole 310, thereby reducing leakage current and improving electrical performance. Exemplarily, the second insulating dielectric layer 420 and the first insulating dielectric layer 410 can be made of the same dielectric material, thus enabling the second insulating dielectric layer 420 and the first insulating dielectric layer 410 to be formed in the same step, reducing the complexity of the manufacturing process and lowering production costs.

[0062] The above are examples illustrating some implementation methods of the conductive part in the embodiments of this application. In specific implementation, the implementation method of the conductive part is not limited to the above-mentioned methods provided in the embodiments of this disclosure, and may also be other implementation methods known to those skilled in the art based on the inventive concept of this application. No specific limitation is made here.

[0063] In one embodiment of this application, reference is made to... Figure 3A The second chip 200 may further include a semiconductor device layer 230 and an interconnect layer 240, with the semiconductor device layer 230 located between the first substrate 210 and the interconnect layer 240. A second pad 220 is disposed on the side of the first functional layer facing away from the first substrate 210. To connect the second pad 220 to the first pad 110, the via 310 can penetrate not only the first substrate 210 but also the first functional layer, thereby connecting the first pad 110 and the second pad 220 through a conductive portion. In other embodiments of this application, the via 310 may only penetrate the first substrate 210.

[0064] In one embodiment of this application, reference is made to... Figure 3A The first chip 100 can be a logic die, and the second chip 200 can be a memory chip. For example, the first chip 100 can have multiple I / O interfaces 120, each I / O interface 120 can be correspondingly configured to one or more vias 310, and each I / O interface 120 can be connected to the conductive part in the corresponding via 310 through a first pad 110. Thus, when the three-dimensional memory is working, a multi-track, low-speed mode can be adopted, and input / output signals can be used through the I / O interfaces 120 to perform read and write operations. Exemplarily, the I / O interfaces 120 include, but are not limited to, general-purpose input / output (GIO) interfaces.

[0065] For example, memory chips include, but are not limited to, volatile memory chips and non-volatile memory chips. Volatile memory chips are, for example, Dynamic Random Access Memory (DRAM) chips and Static Random Access Memory (SRAM) chips. Non-volatile memory chips are, for example, Phase-change Random Access Memory (PRAM) chips, Magnetoresistive Random Access Memory (MRAM) chips, Ferroelectric Random Access Memory (FeRAM) chips, and Resistive Random Access Memory (RRAM) chips.

[0066] For example, refer to Figure 3A The size of the first chip 100 can be larger than the size of the second chip 200. Alternatively, the size of the first chip 100 can be smaller than or equal to the size of the second chip 200.

[0067] In three-dimensional memory, memory chips typically have storage banks to store data, thus enabling data storage. For example, refer to... Figure 6 , Figure 6 This is a schematic diagram of a second chip in an embodiment of this application. The second chip 200 may have multiple memory cells 250, each of which can be formed in the semiconductor device layer 230. Furthermore, each memory cell 250 is provided with multiple vias 310, and the vias 310 corresponding to each memory cell 250 are independent of each other. Thus, each memory cell 250 is connected to the first pad 110 through the conductive portions in the multiple vias 310, thereby achieving connection with the I / O interface 120. This not only enables parallel transmission of multiple signals but also improves area utilization while reducing the number of vias 310.

[0068] For example, the multiple vias 310 corresponding to the multiple memory cells 250 can be arranged in an array to form a via array 310, thereby enabling read and write operations to be performed on the memory cells 250 through the via array 310. In other embodiments of this application, the multiple vias 310 corresponding to the multiple memory cells 250 can also adopt other arrangements, which are not limited here.

[0069] For example, the projections of the plurality of vias 310 corresponding to the memory cell 250 onto the orthographic projection of the memory cell 250 onto the first chip 100 may not overlap. Alternatively, the projections of the plurality of vias 310 corresponding to the memory cell 250 onto the first chip 100 may fall within the orthographic projection of the memory cell 250 onto the first chip 100, which can further reduce the area of ​​the second chip.

[0070] Exemplarily, the first chip 100 may also have a plurality of fifth interconnect structures 140 on the side facing away from the second chip 200. These plurality of I / O interfaces 120 are connected one-to-one with the plurality of fifth interconnect structures 140, thereby achieving electrical connection with the circuit board 20 through the fifth interconnect structures 140. Exemplarily, when the three-dimensional memory in this embodiment is directly disposed on the circuit board 20, the fifth interconnect structure 140 can be electrically connected to the circuit board 20. Alternatively, when the three-dimensional memory in this embodiment is applied to a system-in-package structure, the fifth interconnect structure 140 can serve as a second interconnect structure 16 to achieve electrical connection with the package substrate 11.

[0071] For example, the first chip 100 may also have a plurality of multiplexers 130, with each of the plurality of I / O interfaces 120 corresponding one-to-one with the plurality of multiplexers 130. Any I / O interface 120 can be connected to the conductive portion in the corresponding plurality of vias 310 through the corresponding multiplexer 130 and the first pad 110. This reduces the number of I / O interfaces 120, saving 3D memory area and reducing cost. For example, the multiplexer 130 can be an n:1 multiplexer 130, where n is an integer greater than 1, for example, n is 2, 3, 4, 6, 8 or more, and is not specifically limited here.

[0072] Understandably, the first chip 100 and the second chip 200 can both be memory chips, thus stacking multiple memory chips to improve storage density and performance.

[0073] In the three-dimensional memory of this application embodiment, reference is made to... Figure 3A and Figure 3B A second chip 200 can be stacked on the first chip 100, or multiple second chips 200 can be stacked on the first chip 100, further improving storage density and performance. For example, refer to... Figure 7A and Figure 7B , Figure 7A This is a schematic diagram of yet another structure of the three-dimensional memory in the embodiments of this application. Figure 7B This is a schematic diagram of another three-dimensional structure of the three-dimensional memory in the embodiments of this application, referring to... Figure 7A and Figure 7BThe three-dimensional memory may include multiple second chips 200_1, 200_2, 200_3, and 200_4. Second chip 200_1 is disposed between second chip 200_2 and first chip 100; second chip 200_2 is disposed between second chip 200_3 and first chip 100; and second chip 200_3 is disposed between second chip 200_4 and first chip 100, thereby stacking second chips 200_1 to 200_4 sequentially on the first chip 100. It is understood that this arrangement is for illustrative purposes only, to clearly demonstrate the structure of the multiple second chips 200 in this embodiment. Figure 7A and Figure 7B The illustration takes stacking four second chips 200_1 to 200_4 as an example. In other embodiments of this application, the number of stacked second chips 200 can be two, three, five, six, eight or more, which can be flexibly designed according to the actual application scenario, and will not be elaborated here.

[0074] In one embodiment of this application, by stacking multiple second chips 200 on a first chip 100, a three-dimensional memory can be formed as an HBM for application in fields such as high-performance computing, AI, and graphics processing.

[0075] In one embodiment of this application, reference is made to... Figure 7A and Figure 7B Taking second chip 200_1 as the first second chip 200a and second chip 200_2 as the second second chip 200b as an example, the through hole 310 in second chip 200_1 is the first through hole 310a, and the through hole 310 in second chip 200_2 is the second through hole 310b. Each second through hole 310b corresponds to one of the first through holes 310a in the portion of the first through holes 310a. That is, second chip 200_1 has two portions of first through holes 310a; one portion of the first through holes 310a corresponds one-to-one with the second through holes 310b, while the other portion of the first through holes 310a and the second through holes 310b in second chip 200_2 are independently configured. Furthermore, the conductive portion in any second through hole 310b can be connected to the conductive portion in the corresponding first through hole 310a, thereby enabling the second pad 220 in the second chip 200_2 to be connected to the first pad 110 in the first chip 100 through the conductive portion in the first through hole 310a, so as to realize signal transmission between the first chip 100 and the second chip 200_2.

[0076] For example, refer to Figure 8A and Figure 8B , Figure 8A This is a three-dimensional structural diagram of the first through hole and the second through hole in an embodiment of this application. Figure 8BThis is a schematic diagram of another three-dimensional structure of the first through hole and the second through hole in an embodiment of this application. The plurality of conductive portions in the first through hole 310a include a first first conductive portion 311a_1 and a second first conductive portion 311a_2, with the second first conductive portion 311a_2 surrounding the outside of the first first conductive portion 311a_1, thus forming a coaxial structure among the conductive portions in the first through hole 310a. Similarly, the plurality of conductive portions in the second through hole 310b include a first second conductive portion 311b_1 and a second second conductive portion 311b_2, with the second second conductive portion 311b_2 surrounding the outside of the first second conductive portion 311b_1, also forming a coaxial structure among the conductive portions in the first through hole 310a. Furthermore, one of the first second conductive portion 311b_1 and the second second conductive portion 311b_2 is connected to the first first conductive portion 311a_1, and the other of the first second conductive portion 311b_1 and the second second conductive portion 311b_2 is connected to the second first conductive portion 311a_2. Thus, a one-to-one correspondence can be achieved between the conductive portions in the first through hole 310a and the conductive portions in the second through hole 310b.

[0077] As an example, refer to Figure 8A The first second conductive part 311b_1 in any second through hole 310b is connected to the first first conductive part 311a_1 in the corresponding first through hole 310a, and the second second conductive part 311b_2 in any second through hole 310b is connected to the second first conductive part 311a_2 in the corresponding first through hole 310a. With this configuration, columnar second conductive parts and columnar first conductive parts can be connected to each other, and tubular second conductive parts and tubular first conductive parts can be connected to each other, so as to connect the inner channel and outer channel of two adjacent second chips 200 respectively, reducing interconnection complexity and design difficulty.

[0078] As yet another example, see Figure 8B The first second conductive part 311b_1 in any second through hole 310b is connected to the second first conductive part 311a_2 in the corresponding first through hole 310a, and the second second conductive part 311b_2 in any second through hole 310b is connected to the first first conductive part 311a_1 in the corresponding first through hole 310a. With this configuration, the columnar second conductive part and the tubular first conductive part can be connected to each other, and the tubular second conductive part and the columnar first conductive part can be connected to each other, so as to interleave the inner and outer channels of two adjacent second chips 200, improve the channel characteristics, achieve better channel matching, and improve signal integrity.

[0079] As yet another example, see Figure 8A and Figure 8B Alternatively, the first second conductive part 311b_1 in a portion of the second through hole 310b can be connected to the second first conductive part 311a_2 in the corresponding first through hole 310a, and the second second conductive part 311b_2 in the portion of the second through hole 310b can be connected to the first first conductive part 311a_1 in the corresponding first through hole 310a, so that the portion of the second through hole 310b is alternately connected to the inner and outer channels in the corresponding first through hole 310a. Furthermore, the first second conductive part 311b_1 in another portion of the second through hole 310b can be connected to the first first conductive part 311a_1 in the corresponding first through hole 310a, and the second second conductive part 311b_2 in the other portion of the second through hole 310b can be connected to the second first conductive part 311a_2 in the corresponding first through hole 310a, so that the portion of the second through hole 310b is respectively connected to the inner and outer channels in the corresponding first through hole 310a.

[0080] In some embodiments, since interconnected conductive parts can act as independent channels, and the conductive parts in the same via 310 are independent channels, the structures of the conductive parts in the same via 310 are different during signal transmission, resulting in inconsistent resistance between different channels in the same via 310. Furthermore, the three-dimensional memory in this embodiment can have high-speed channels and low-speed channels. High-speed channels typically focus on signal integrity (e.g., impedance matching), while low-speed channels typically focus on cost. Exemplarily, high-speed channels may include channels for transmitting data signals, channels for transmitting command address signals, and channels for transmitting clock signals; low-speed channels may include channels for transmitting test signals. Based on this, for high-speed channels, a method can be adopted... Figure 8B The conductive connection method shown is implemented to achieve better signal integrity and improve channel characteristics. For low-speed channels, the following can be used: Figure 8A The conductive connection method shown is implemented to achieve better cost-effectiveness. This allows for a balance between better channel characteristics and lower cost.

[0081] It is understood that, in order to clearly illustrate the connection relationship of the conductive parts in adjacent second chips 200 in the embodiments of this application, the above illustration uses second chip 200_1 as the first second chip 200a and second chip 200_2 as the second second chip 200b as an example. In other embodiments of this application, second chip 200_2 may also be the first second chip 200a and second chip 200_3 may be the second second chip 200b. Alternatively, second chip 200_3 may also be the first second chip 200a and second chip 200_4 may be the second second chip 200b. Furthermore, the implementation of second chips 200_2 to 200_4 can be based on the implementation where second chip 200_1 is the first second chip 200a and second chip 200_2 is the second second chip 200b, and the specifics will not be elaborated here.

[0082] Understandably, Figure 8A and Figure 8B The solid line connecting the two conductive parts is not a real signal line in the three-dimensional memory, but represents that the two conductive parts are electrically connected.

[0083] Since all conductive parts in the same channel need to transmit signals and their spacing is small, the channel characteristics are mainly capacitive crosstalk. Capacitive crosstalk exhibits the characteristics of far-end crosstalk (FEXT), typically resulting in a rising positive pulse signal. Furthermore, the larger the dynamic voltage of the signal transmitted through the channel, the greater the instantaneous coupling noise; the smaller the spacing between conductive parts, the larger the coupling capacitance, and the greater the instantaneous coupling noise; the faster the signal transmission speed, the greater the coupling current noise. To improve the rising positive pulse signal caused by capacitive crosstalk, in one embodiment of this application, referring to... Figure 9 , Figure 9 As shown in the circuit diagram of an embodiment of this application, the second chip 200 adjacent to the first chip 100 further includes multiple first transmission circuits 510 and multiple second transmission circuits 520. Any conductive part (e.g., 311_1, 311_2) is connected to at least one second pad 220 through a first transmission circuit 510, and any conductive part is connected to at least one first pad 110 through a second transmission circuit 520. Thus, by configuring the first transmission circuits 510 and the second transmission circuits 520 together, the rising positive pulse signal caused by capacitive crosstalk can be improved, or even the positive pulse signal can be eliminated.

[0084] For example, refer to Figure 9The first transmission circuit 510 includes: a first transmitter (Tx) 511, an inverter 512, a delay 513, a second transmitter 514, and an adder 515. The input terminals of the first transmitter 511 and the inverter 512 are both connected to at least one second pad 220. The output terminal of the first transmitter 511 is connected to the first input terminal of the adder 515. The output terminal of the inverter 512 is connected to the input terminal of the delay 513. The output terminal of the delay 513 is connected to the input terminal of the second transmitter 514. The output terminal of the second transmitter 514 is connected to the second input terminal of the adder 515. The output terminal of the adder 515 is connected to a conductive part (e.g., 311_1). Therefore, the function of the first transmission circuit 510 can be realized through the first transmitter 511, inverter 512, delay unit 513, second transmitter 514 and adder 515. Furthermore, since the architecture of the transmitter, inverter 512, delay unit 513 and adder 515 is relatively mature, the implementation of the first transmission circuit 510 can be relatively simple, thereby reducing the design difficulty and production cost.

[0085] For example, delay unit 513 is used to extend the signal at its input end for a certain period of time before outputting it. For example, delay unit 513 includes, but is not limited to, a feed-forward equalizer (FFE).

[0086] For example, refer to Figure 9 The second transmission circuit 520 includes a subtractor 521, a receiver (Rx) 522, an edge detector (ED) 523, and an AND gate 524. The first input terminal of the subtractor 521 is connected to a conductive part (e.g., 311_1), the input terminal of the edge detector 523 is connected to another conductive part (e.g., 311_2), the output terminal of the edge detector 523 is connected to one input terminal of the AND gate 524, the output terminal of the AND gate 524 is connected to the second input terminal of the subtractor 521, the output terminal of the subtractor 521 is connected to the input terminal of the receiver 522, and the output terminal of the receiver 522 is connected to at least one first pad 110. Therefore, the function of the second transmission circuit 520 can be realized through the subtractor 521, receiver 522, edge detector 523 and AND gate 524. Furthermore, since the architecture of the subtractor 521, receiver 522, edge detector 523 and AND gate 524 is relatively mature, the implementation of the second transmission circuit 520 can be relatively simple, thereby reducing the design difficulty and production cost.

[0087] For example, edge detector 523 is used to detect level transitions (rising edge, falling edge, or both) of the input signal and outputs a corresponding pulse signal. Furthermore, another input of AND gate 524 is used to receive a fixed pulse signal VPH, allowing AND gate 524 to output a pulse signal based on the received signal.

[0088] The following uses the first transmission circuit 510 and the second transmission circuit 520 corresponding to the conductive part 311_1 as examples, combined with Figure 10 The signal timing diagram illustrates the operation of the first transmission circuit 510 and the second transmission circuit 520 in this embodiment. Wherein, S 220 S represents the signal transmitted on the second pad 220. 512 The signal S represents the output of inverter 512. 513 The signal S represents the output of delay unit 513. 515 The signal S represents the output of adder 515. 110 This represents the signal transmitted on the first pad 110.

[0089] In the first transmission circuit 510 corresponding to the conductive part 311_1, the second pad 220 receives the input signal S. 220 Signal S 220 After passing through the first transmitter 511, the signal is input to the first input terminal of the adder 515. Furthermore, the signal S... 220 After being inverted by inverter 512, signal S is obtained. 512 Signal S 512 After a certain delay by delay unit 513, signal S is obtained. 513 Signal S 513 The signal passes through the second transmitter 514 and is input to the second input terminal of the adder 515. The adder 515 adds the signals from its first and second input terminals and outputs a signal S. 515 .

[0090] Signal S 515 After transmission through conductive part 311_1, the signal enters the first input terminal of subtractor 521. Edge detector 523 detects the level transition of the signal output from conductive part 311_2 and outputs a corresponding pulse signal. AND gate 524 combines the received signal and outputs a positive pulse signal related to capacitive crosstalk to the second input terminal of subtractor 521. Subtractor 521 subtracts the signal at its first input terminal from the signal at its second output terminal to remove the positive pulse signal caused by capacitive crosstalk, and outputs the signal to the input terminal of receiver 522, so that it can be output to the first pad 110 through receiver 522. Thus, the rising positive pulse signal caused by capacitive crosstalk can be improved or even eliminated.

[0091] The above description is only a specific implementation of this application, but the protection scope of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the protection scope of this application.

Claims

1. A three-dimensional memory, characterized in that, include: The first chip includes multiple first pads; The second chip is stacked on the first chip. The second chip includes a first substrate, a plurality of second pads and a plurality of through holes. The plurality of through holes penetrate the first substrate. Each of the through holes is provided with a plurality of independent conductive parts. Each of the conductive parts is connected between at least one second pad and at least one first pad.

2. The three-dimensional memory according to claim 1, characterized in that, Along the radial direction of the through hole, one of the plurality of conductive portions is at least partially disposed around the outside of another conductive portion, and a first insulating dielectric layer is disposed between adjacent conductive portions.

3. The three-dimensional memory according to claim 1 or 2, characterized in that, The three-dimensional memory includes a plurality of second chips, the plurality of second chips including a first second chip and a second second chip, the first second chip being disposed between the second second chip and the first chip; The through-hole in the first second chip is a first through-hole, and the through-hole in the second second chip is a second through-hole. Each second through-hole is correspondingly provided with one of the first through-holes in a portion of the first through-holes, and the conductive part in the second through-hole is connected to the conductive part in the corresponding first through-hole.

4. The three-dimensional memory according to claim 3, characterized in that, The plurality of conductive portions in the first through hole include a first first conductive portion and a second first conductive portion, wherein the second first conductive portion is disposed around the outside of the first first conductive portion; The plurality of conductive portions in the second through hole include a first second conductive portion and a second second conductive portion, wherein the second second conductive portion is disposed around the outside of the first second conductive portion; One of the first and second conductive parts is connected to the first conductive part, and the other of the first and second conductive parts is connected to the second conductive part.

5. The three-dimensional memory according to claim 4, characterized in that, The first second conductive portion in a portion of the second through hole is connected to the second first conductive portion, and the second second conductive portion in a portion of the second through hole is connected to the first first conductive portion; In another portion of the second through hole, the first second conductive portion is connected to the first first conductive portion, and in the other portion of the second through hole, the second second conductive portion is connected to the second first conductive portion.

6. The three-dimensional memory according to any one of claims 1-5, characterized in that, The second chip is a memory chip, which includes multiple memory cells. Each memory cell is provided with multiple vias, and the vias corresponding to each memory cell are independent of each other.

7. The three-dimensional memory according to any one of claims 1-6, characterized in that, The second chip adjacent to the first chip further includes a plurality of first transmission circuits and a plurality of second transmission circuits. Any of the conductive parts is connected to the at least one second pad through a first transmission circuit, and any of the conductive parts is connected to the at least one first pad through a second transmission circuit. The first transmission circuit includes: a first transmitter, an inverter, a delay unit, a second transmitter, and an adder. The input terminals of the first transmitter and the inverter are both connected to the at least one second pad. The output terminal of the first transmitter is connected to the first input terminal of the adder. The output terminal of the inverter is connected to the input terminal of the delay unit. The output terminal of the delay unit is connected to the input terminal of the second transmitter. The output terminal of the second transmitter is connected to the second input terminal of the adder. The output terminal of the adder is connected to the conductive part. The second transmission circuit includes a subtractor, a receiver, an edge detector, and an AND gate. The first input terminal of the subtractor is connected to the conductive part, the input terminal of the edge detector is connected to another conductive part, the output terminal of the edge detector is connected to one input terminal of the AND gate, the output terminal of the AND gate is connected to the second input terminal of the subtractor, the output terminal of the subtractor is connected to the input terminal of the receiver, and the output terminal of the receiver is connected to the at least one first pad.

8. The three-dimensional memory according to any one of claims 1-7, characterized in that, The three-dimensional memory is a high-bandwidth memory.

9. The three-dimensional memory according to claim 8, characterized in that, The first chip is a logic chip, and the second chip is a memory chip. The first chip includes multiple input / output interfaces, and any one of the input / output interfaces is connected to the conductive part in at least one through hole through the first pad.

10. A system-level packaging structure, characterized in that, It includes a packaging substrate, a processor, and a three-dimensional memory as described in any one of claims 1-9; the three-dimensional memory and the processor are packaged on the packaging substrate.

11. An electronic device, characterized in that, include: A circuit board and electronic devices, the electronic devices being connected to the circuit board, the electronic devices comprising: a three-dimensional memory as described in any one of claims 1-8, and / or, a system-in-package structure as described in claim 9.

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