Semiconductor device

Abstract

A semiconductor device includes a logic die, a first via extending into at least a portion of the logic die, an upper pad on an upper surface of the logic die, a lower pad below a lower surface of the logic die and electrically connected to the first via, and a plurality of memory dies stacked on the logic die, wherein the logic die includes a first substrate including a first surface and a second surface opposite the first surface, a first transistor on the first surface of the first substrate, a second substrate including a third surface and a fourth surface facing the first surface of the first substrate, a second transistor on the third surface of the second substrate, and an internal via extending into the second substrate, wherein the first transistor and the second transistor are connected by the internal via.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] For semiconductor packages installed in electronic devices, higher performance and / or larger capacity may be required. Therefore, semiconductor packages comprising multiple dies have been developed, and the transmission and reception of signals between these dies has become increasingly complex. For example, semiconductor packages can be implemented as high-bandwidth memory (HBM). Summary of the Invention

[0003] Various aspects of this disclosure provide a semiconductor device with improved electrical characteristics and integration density.

[0004] Various aspects of this disclosure provide a method for manufacturing semiconductor devices with improved electrical characteristics and integration density.

[0005] According to some embodiments of this disclosure, a semiconductor device may include: a logic die; a first via extending into at least a portion of the logic die; an upper pad on an upper surface of the logic die; a lower pad below a lower surface of the logic die and electrically connected to the first via; and a plurality of memory dies stacked on the logic die, wherein the logic die includes: a first substrate including a first surface and a second surface opposite to the first surface; a first transistor on the first surface of the first substrate; a second substrate including a third surface and a fourth surface opposite to the third surface and facing the first surface of the first substrate; a second transistor on the third surface of the second substrate; and an internal via extending into the second substrate, wherein the first transistor and the second transistor are connected through the internal via.

[0006] According to some embodiments of this disclosure, a semiconductor device may include: a first substrate including a first surface and a second surface opposite to the first surface; a first transistor on the first surface of the first substrate and including a first source / drain pattern and a second source / drain pattern; a first power line electrically connected to the first source / drain pattern, wherein the first power line is below the second surface of the first substrate; a second substrate including a third surface and a fourth surface opposite to the third surface and facing the first surface of the first substrate; a second transistor on the third surface of the second substrate and including a third source / drain pattern and a fourth source / drain pattern; a second power line electrically connected to the third source / drain pattern and below the fourth surface of the second substrate; a plurality of vias extending in a direction perpendicular to the first surface of the first substrate and extending into each of the first substrate and the second substrate; and a first internal via extending into the second substrate, wherein the first transistor and the second transistor are electrically connected through the first internal via.

[0007] According to some embodiments of this disclosure, a semiconductor device may include: a first substrate including a first surface and a second surface opposite to the first surface; a first transistor on the first surface of the first substrate and including a first source / drain pattern and a second source / drain pattern; a first power line electrically connected to the first source / drain pattern and below the second surface of the first substrate; a second substrate including a third surface and a fourth surface opposite to the third surface and facing the first surface of the first substrate; a second transistor on the third surface of the second substrate and including a third source / drain pattern and a fourth source / drain pattern; a first internal via extending into the second substrate, wherein the second source / drain pattern of the first transistor and the fourth source / drain pattern of the second transistor are electrically connected through the first internal via; an interlayer insulating layer below the second surface of the first substrate; a lower pad below the lower surface of the interlayer insulating layer; and a first wiring structure in the interlayer insulating layer and electrically connected to the first power line and the lower pad.

[0008] According to some embodiments of this disclosure, by forming a first transistor and a second transistor in a single die and arranging internal vias connecting the first transistor and the second transistor, the signal path from the first transistor to the second transistor can be shortened. This can improve the efficiency of signal transmission and reception from the first transistor to the second transistor.

[0009] According to some embodiments of this disclosure, by forming a first transistor disposed on a first substrate and a second transistor disposed on a second substrate in a single die, the thickness of the semiconductor device can be reduced and the integration density can be increased. Attached Figure Description

[0010] The above and other embodiments and features of this disclosure will become clearer by referring to the accompanying drawings, which describe exemplary embodiments of the present disclosure in detail. Figure 1 Semiconductor devices according to some embodiments of the present disclosure are shown; Figure 2 This is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure; Figures 3 to 5 Semiconductor devices according to some embodiments of the present disclosure are shown; Figure 6 This is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure; Figure 7 This is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure; Figure 8 This is a diagram illustrating a semiconductor device according to some embodiments of the present disclosure; Figure 9 This is a diagram illustrating a semiconductor device according to some embodiments of the present disclosure; Figure 10 This is a diagram illustrating a semiconductor device according to some embodiments of the present disclosure; Figure 11 This is a diagram illustrating a semiconductor package according to some embodiments of the present disclosure; Figure 12 This is a diagram illustrating a semiconductor package according to some embodiments of the present disclosure; Figures 13 to 18 This is a diagram illustrating a method of manufacturing a semiconductor device according to some embodiments of the present disclosure; Figures 19 to 23 This is a diagram illustrating a method of manufacturing a semiconductor device according to some embodiments of the present disclosure; Figures 24 to 28 This is a diagram illustrating a method of manufacturing a semiconductor device according to some embodiments of the present disclosure. Detailed Implementation

[0011] In this disclosure, the terms "upper," "lower," "upper surface," and "lower surface" are used for ease of description and are not restrictive. The terms "upper," "lower," "upper surface," and "lower surface" are described relative to the accompanying drawings, and if the drawings are rotated, the terms indicating the upper and lower relationships may change accordingly.

[0012] Although terms such as "first" and "second" are used in this disclosure to describe various elements or components, the elements or components are not limited by these terms. These terms are used only to distinguish one element or component from another. Within the technical spirit of this disclosure, a first element or first component may be a second element or second component.

[0013] In the following, a semiconductor device and a method of manufacturing the semiconductor device according to some embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0014] Figure 1 Semiconductor devices according to some embodiments of the present disclosure are shown.

[0015] Reference Figure 1 According to some embodiments, a semiconductor device may include an interposer 3000, a logic die 1000, a plurality of memory dies 2000, a plurality of through-holes 400, and a plurality of pads 450.

[0016] Intermediate layer 3000 can connect logic die 1000 to host die (e.g., Figure 11 The host die 1200 can be used, and multiple memory dies 2000 can also be connected to the host die. Multiple through-holes 400 and multiple pads 450 can be electrically connected between the interposer 3000 and the logic die 1000, and between the interposer 3000 and the multiple memory dies 2000. In this disclosure, a phrase connecting one structure to another can include physical and / or electrical connections. In some embodiments, a phrase connecting one structure to another can include a direct electrical connection or an indirect electrical connection via another structure interposed between the structures.

[0017] Logic die 1000 can be stacked on interposer 3000. Logic die 1000 can be electrically connected to interposer 3000. Logic die 1000 can send signals to and receive signals from host die through interposer 3000. Logic die 1000 can send signals to and receive signals from multiple memory dies 2000 through multiple vias 400 and multiple pads 450.

[0018] The logic die 1000 may include multiple semiconductor structures. For example, the logic die 1000 may include a first semiconductor structure 100 and a second semiconductor structure 200. The first semiconductor structure 100 and the second semiconductor structure 200 may include different integrated circuits. The detailed structure of the logic die 1000 will be described later.

[0019] Multiple memory dies 2000 may be stacked on a logic die 1000. Each memory die 2000 may include a memory device layer. The integrated circuit of the memory device layer of each memory die 2000 may include volatile memory devices (such as dynamic random access memory (DRAM) and static random access memory (SRAM)) and non-volatile memory devices (such as phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), resistive random access memory (ReRAM), and flash memory). For example, by including multiple channels, each with its own independent interface, multiple memory dies 2000 may constitute a high-bandwidth memory (HBM) type memory device with increased bandwidth.

[0020] As the number of memory dies 2000 increases, the performance of the memory device (e.g., bandwidth and storage capacity) can be further enhanced. Although the number of memory dies 2000 stacked on the logic die 1000 is shown as four, this disclosure is not limited thereto.

[0021] Multiple through-holes 400 can penetrate the logic die 1000 and the multiple memory dies 2000. For example, each through-hole 400 can penetrate at least a portion of the logic die 1000. Each through-hole 400 can penetrate at least a portion of each memory die 2000. In some embodiments, the multiple through-holes 400 may not be located in the uppermost memory die 2000 among the multiple memory dies 2000.

[0022] Multiple pads 450 may be disposed at the ends of multiple through-holes 400. For example, multiple pads 450 may be disposed at both ends of multiple through-holes 400. The multiple pads 450 may be electrically connected to the multiple through-holes 400. For example, the connection may be made through a wiring structure between the multiple pads 450 and the multiple through-holes 400. However, this disclosure is not limited thereto. For example, the multiple pads 450 may be directly connected to the multiple through-holes 400.

[0023] Multiple through-holes 400 and multiple pads 450 can be used as signal paths between components. For example, multiple through-holes 400 and multiple pads 450 can be used as signal paths between multiple memory dies 2000, logic dies 1000 and interposers 3000.

[0024] Figure 2 This is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure.

[0025] Reference Figure 2According to some embodiments, the semiconductor device may include a logic die 1000, a via 310, an upper pad 350, and a lower pad 340. The logic die 1000 may include a first semiconductor structure 100, a second semiconductor structure 200, and a first internal via 220. The second semiconductor structure 200 may be stacked on the first semiconductor structure 100.

[0026] The first semiconductor structure 100 may include a first substrate 110, a first transistor 140, a first wiring structure 170, and a first interlayer insulating layer 180.

[0027] The first substrate 110 may be bulk silicon or silicon-on-insulator (SOI). Alternatively, the first substrate 110 may comprise a single-element semiconductor (such as silicon, germanium) or various compound semiconductor materials (such as silicon-germanium (SiGe), silicon-germanium-on-insulator (SGOI), indium antimonide (InSb), lead telluride (PbTe), indium arsenide (InAs), indium phosphide (InP), gallium arsenide (GaAs), gallium antimonide (GaSb), or silicon carbide (SiC)). However, this disclosure is not limited thereto.

[0028] The first substrate 110 may include a first surface 110_A and a second surface 110_B opposite to the first surface 110_A. The first surface 110_A of the first substrate 110 may be the surface on which the first transistor 140 is disposed. The first surface 110_A of the first substrate 110 may be referred to as the front side of the first substrate 110. The second surface 110_B of the first substrate 110 may be referred to as the back side of the first substrate 110.

[0029] The first transistor 140 may be disposed on the first surface 110_A of the first substrate 110. The first transistor 140 may include a gate electrode, a gate insulating film, and a source / drain pattern. The first transistor 140 may include a planar MOSFET, a FinFET with a finned active region, a multi-bridge channel FET (MBCFET) including multiple channels vertically stacked on the active region, or a gate-surrounded transistor, or a vertical FET (VFET), but this disclosure is not limited thereto.

[0030] A first interlayer insulating layer 180 may be disposed on a first surface 110_A of the first substrate 110. The first interlayer insulating layer 180 may cover the first transistor 140. A first wiring structure 170 may be disposed in the first interlayer insulating layer 180. The first wiring structure 170 may be connected to the first transistor 140. For example, the first wiring structure 170 may be connected to the source / drain pattern and / or gate electrode of the first transistor 140.

[0031] The first wiring structure 170 may include multiple wiring layers. The number of wiring layers may vary depending on the design. In some embodiments, the thickness of each wiring layer of the first wiring structure 170 may be different. For example, the thickness of a wiring layer disposed adjacent to the first surface 110_A of the first substrate 110 may be less than the thickness of a wiring layer disposed further away from the first surface 110_A of the first substrate 110. However, this disclosure is not limited thereto.

[0032] The second semiconductor structure 200 may include a second substrate 210, a second transistor 240, a second wiring structure 270, and a second interlayer insulating layer 280.

[0033] The second substrate 210 may be bulk silicon or SOI. Alternatively, the second substrate 210 may comprise a single-element semiconductor (such as silicon, germanium) or various compound semiconductor materials (such as silicon-germanium (SiGe), silicon-germanium-on-insulator (SGOI), indium antimonide (InSb), lead telluride (PbTe), indium arsenide (InAs), indium phosphide (InP), gallium arsenide (GaAs), gallium antimonide (GaSb), or silicon carbide (SiC)). However, this disclosure is not limited thereto.

[0034] The second substrate 210 may include a third surface 210_A and a fourth surface 210_B opposite to the third surface 210_A. The third surface 210_A of the second substrate 210 may be the surface on which the second transistor 240 is disposed. The fourth surface 210_B of the second substrate 210 may face the first surface 110_A of the first substrate 110. The third surface 210_A of the second substrate 210 may be referred to as the front side of the second substrate 210. The fourth surface 210_B of the second substrate 210 may be referred to as the back side of the second substrate 210.

[0035] The second substrate 210 may be disposed on the first interlayer insulating layer 180. The second substrate 210 may contact the first interlayer insulating layer 180. For example, the fourth surface 210_B of the second substrate 210 may contact the upper surface of the first interlayer insulating layer 180.

[0036] In some embodiments, the logic die 1000 of the semiconductor device may further include a device isolation film 215. The device isolation film 215 may be disposed on the upper surface of the first interlayer insulating layer 180. A second substrate 210 may surround the device isolation film 215. In some embodiments, the lower surface of the device isolation film 215 may be disposed in the same plane as the lower surface of the second substrate 210. In other words, the distance from the third surface 210_A to the fourth surface 210_B of the second substrate 210 may be equal to the distance from the third surface 210_A to the lower surface of the device isolation film 215. Here, "equal to" can mean equal within a range including process tolerances.

[0037] The second transistor 240 may be disposed on the third surface 210_A of the second substrate 210. The second transistor 240 may include a gate electrode, a gate insulating film, and a source / drain pattern. The second transistor 240 may include a planar MOSFET, a FinFET with a finned active region, an MBCFET or a gate-surrounded transistor including multiple channels vertically stacked on the active region, or a VFET, but this disclosure is not limited thereto.

[0038] A second interlayer insulating layer 280 may be disposed on the third surface 210_A of the second substrate 210. The second interlayer insulating layer 280 may cover the second transistor 240. A second wiring structure 270 may be disposed in the second interlayer insulating layer 280. The second wiring structure 270 may be connected to the second transistor 240. For example, the second wiring structure 270 may be connected to the source / drain pattern and / or gate electrode of the second transistor 240.

[0039] The second wiring structure 270 may include multiple wiring layers. The number of wiring layers may vary depending on the design. In some embodiments, the thickness of each wiring layer of the second wiring structure 270 may be different. For example, the thickness of a wiring layer disposed adjacent to the third surface 210_A of the second substrate 210 may be less than the thickness of a wiring layer disposed further away from the third surface 210_A of the second substrate 210. However, this disclosure is not limited thereto.

[0040] Multiple first transistors 140 can be configured, and the multiple first transistors 140 can constitute a first integrated circuit. The first integrated circuit can be, for example, a neural processing unit (NPU), a microprocessor, a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a cryptographic processor, an application processor (AP), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), or a memory controller, but this disclosure is not limited thereto.

[0041] The first integrated circuit can perform arithmetic operations, logical operations, vector and matrix operations, and conditional operations, and can be coupled with multiple memory dies (e.g., Figure 1 The computation is processed directly at a location adjacent to the memory die 2000 to reduce bandwidth consumption. The first integrated circuit may also include control functions (such as instruction decoding, memory access control, and scheduling) and may include error handling functions. However, this disclosure is not limited thereto.

[0042] In some embodiments, the first integrated circuit can perform data compression and decompression functions. The first integrated circuit can analyze multiple memory dies (e.g., Figure 1The first integrated circuit (BIC) can detect redundant or repetitive patterns in the data stored in the memory die (2000), and can store those patterns in compressed form according to a compression algorithm or restore them if necessary. These functions can improve storage space efficiency and reduce the amount of data transferred between internal and external memories, thereby contributing to bandwidth and power consumption reduction. Compression schemes can be implemented in various forms, such as run-length encoding, dictionary-based compression, and lossless or lossy compression algorithms. The first integrated circuit can execute these algorithms through hardware logic or a microcontroller, and can verify the integrity of the compressed data through hashing or checksum calculation. In some embodiments, the first integrated circuit can perform a lightweight pattern analysis function that automatically determines whether compression should be applied based on the data type. However, this disclosure is not limited thereto.

[0043] In some embodiments, the first integrated circuit can perform artificial intelligence (AI) based inference functions, such as neural network computation, vector computation, and similarity determination, using algorithms such as lightweight neural networks, decision trees, and logistic regression. In some embodiments, the first integrated circuit can be implemented on multiple memory dies ( Figure 1 The weights, biases, activation functions, etc., required for AI operations (such as data classification, feature extraction, and similarity search) are stored and used in the memory dies 2000, and optimized computational structures including integer-based operations, quantization, and pruning techniques can be used. This lightweight AI processing capability achieves both high-speed processing and low-power operation by directly performing data analysis and preprocessing in locations adjacent to multiple memory dies 2000.

[0044] Multiple second transistors 240 can be configured, and these multiple second transistors 240 can constitute a second integrated circuit. The second integrated circuit can perform relay operations from the host die (e.g., Figure 11 The second integrated circuit can receive data, address, and control signals from multiple memory dies (e.g., host die 1200). Figure 1 The second integrated circuit (2000) can reorder or route signals received from the host die to a specific channel and can also perform retiming functions for delay compensation. In some embodiments, the second integrated circuit can perform conversion between external and internal interfaces, power distribution, and data integrity guarantees based on error correction codes (ECC). Additionally, the second integrated circuit can interpret commands received from the host die and perform dispatch control based on the interpreted commands, or it can perform clock synchronization and temperature and status monitoring functions. However, this disclosure is not limited thereto.

[0045] Although the plurality of first transistors 140 have been described as constituting a first integrated circuit, and the plurality of second transistors 240 have been described as constituting a second integrated circuit, this disclosure is not limited thereto. For example, some of the plurality of first transistors 140 may constitute a first integrated circuit, and others of the plurality of first transistors 140 may constitute a second integrated circuit. Therefore, the first semiconductor structure 100 may include both a first integrated circuit and a second integrated circuit. Similarly, some of the plurality of second transistors 240 may constitute a second integrated circuit, and the remaining transistors of the plurality of second transistors 240 may constitute a first integrated circuit. Therefore, the second semiconductor structure 200 may include both a first integrated circuit and a second integrated circuit.

[0046] The first internal through-hole 220 may extend in a direction perpendicular to the first surface 110_A of the first substrate 110. The first internal through-hole 220 may penetrate the second substrate 210. For example, the first internal through-hole 220 may penetrate the third surface 210_A and the fourth surface 210_B of the second substrate 210.

[0047] In some embodiments, the first internal via 220 can electrically connect the first transistor 140 and the second transistor 240. One end of the first internal via 220 can be electrically connected to the second wiring structure 270 and the second transistor 240. The other end of the first internal via 220 can be electrically connected to the first wiring structure 170 and the first transistor 140. Therefore, the first transistor 140 can send signals to and receive signals from the second transistor 240 through the first internal via 220.

[0048] The through-hole 310 can extend in a direction perpendicular to the first surface 110_A of the first substrate 110. The through-hole 310 can penetrate the first substrate 110, the first interlayer insulating layer 180, and the second substrate 210. One end of the through-hole 310 can be disposed in the second interlayer insulating layer 280. A second wiring structure 270 can be disposed on the through-hole 310. The second wiring structure 270 can be disposed between the through-hole 310 and the upper pad 350. The upper pad 350 can be disposed on the upper surface of the logic die 1000. The lower pad 340 can be disposed below the lower surface of the logic die 1000. The through-hole 310 can correspond to... Figure 1 The through-hole component 400, and each of the upper pad 350 and the lower pad 340 can correspond to Figure 1 The pad is 450.

[0049] In some embodiments, the width of the through-hole 310 may not be uniform. For example, the width of the through-hole 310 may decrease as the through-hole 310 approaches the second surface 110_B of the first substrate 110. In terms of cross-sectional shape, the through-hole 310 may have a tapered shape.

[0050] The via 310 can be electrically connected to the second transistor 240 via the second wiring structure 270. Although the via 310 is shown as being directly connected to the lower pad 340, this disclosure is not limited thereto. For example, a wiring structure can be provided between the via 310 and the lower pad 340, and the via 310 can be electrically connected to the lower pad 340 via the wiring structure. The lower pad 340 can receive signals from an external structure (e.g., an interposer). Signals can be supplied to the second transistor 240 via the lower pad 340, the via 310, and the second wiring structure 270. Signals supplied to the second transistor 240 can be transmitted to the upper pad 350 via the second wiring structure 270, or can be supplied to the first transistor 140 via the first internal via 220 and the first wiring structure 170.

[0051] Although only one of each of the through-hole 310, upper pad 350, and lower pad 340 is shown, this disclosure is not limited thereto. For example, the through-hole 310, upper pad 350, and lower pad 340 may each be provided as multiples.

[0052] Each of the through-hole 310, the upper pad 350, and the lower pad 340 may include a conductive material. Each of the through-hole 310, the upper pad 350, and the lower pad 340 may include, for example, aluminum (Al), gold (Au), cobalt (Co), copper (Cu), nickel (Ni), lead (Pb), tantalum (Ta), tellurium (Te), titanium (Ti), tungsten (W), or combinations thereof.

[0053] A liner layer 320 may be disposed on the sidewall of the through-hole member 310. The liner layer 320 may surround the through-hole member 310. The liner layer 320 may be disposed between the through-hole member 310 and the first substrate 110, and between the through-hole member 310 and the second substrate 210. In some embodiments, the liner layer 320 may be disposed below the second surface 110_B of the first substrate 110. However, this disclosure is not limited thereto. The liner layer 320 may include an insulating material.

[0054] Each of the first interlayer insulating layer 180 and the second interlayer insulating layer 280 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material. For example, the low-k material may include tetraethyl orthosilicate fluorinated silicate (FTEOS), silsesquioxane (HSQ), bisbenzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilborate (TMSB), di-tert-butoxydiacetic acid (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), polyimide nanofoams such as polypropylene oxide, carbon-doped silica (CDO), organosilicon glass (OSG), SiLK, amorphous fluorinated carbon, silica aerogel, silica degel, mesoporous silica, or combinations thereof. However, this disclosure is not limited thereto.

[0055] As the integration density of semiconductor devices increases and the functionality becomes more advanced, the complexity of transmitting and receiving signals also increases accordingly. For example, as the number of interconnect paths between adjacent dies increases, signal transmission and reception efficiency may decrease. According to some embodiments, a semiconductor device can form a first transistor 140 and a second transistor 240 on a single die, and arrange a first internal via 220 connecting the first transistor 140 and the second transistor 240, thereby shortening the signal path from the first transistor 140 to the second transistor 240. As a result, signal transmission and reception efficiency from the first transistor 140 to the second transistor 240 can be improved, and the electrical characteristics of the semiconductor device can be enhanced.

[0056] In some embodiments, by forming a first transistor 140 disposed on a first substrate 110 and a second transistor 240 disposed on a second substrate 210 in a single die, the thickness of the semiconductor device can be reduced. Therefore, the integration density of the semiconductor device can be increased. Here, the thickness can be the thickness in the direction perpendicular to the first surface 110_A of the first substrate 110.

[0057] Figures 3 to 5 Semiconductor devices according to some embodiments of the present disclosure are illustrated. For reference, Figure 3 This is a plan view illustrating a logic die 1000 according to some embodiments, and Figure 4 and Figure 5 They are along Figure 3 The cross-sectional views are taken from lines A-A' and B-B'. For ease of explanation, the main description will be based on the reference. Figure 2 Constructions other than those described.

[0058] Reference Figures 3 to 5According to some embodiments, a semiconductor device may include a logic die 1000, a first through-hole 312, a second through-hole 314, a first upper pad 352, a second upper pad 354, a first lower pad 342, and a second lower pad 344.

[0059] The logic die 1000 may include a first semiconductor structure 100 and a second semiconductor structure 200.

[0060] The first semiconductor structure 100 may include a first substrate 110, a first transistor 140, a first wiring structure 170, a first interlayer insulating layer 180, a second internal via 120, a first power line 195, a third wiring structure 370, and a third interlayer insulating layer 380.

[0061] The first transistor 140 may be disposed on the first surface 110_A of the first substrate 110. The first transistor 140 may include a first source / drain pattern 141, a second source / drain pattern 142, a first gate electrode 145, and a first channel pattern.

[0062] A first wiring structure 170 may be disposed on the first transistor 140. The first wiring structure 170 may be connected to each of the first source / drain pattern 141 and the second source / drain pattern 142. For example, the first wiring structure 170 may electrically connect the first source / drain pattern 141 and the second internal via 120. The first wiring structure 170 may electrically connect the second source / drain pattern 142 and the first internal via 220. The first wiring structure 170 may be connected to the first gate electrode 145.

[0063] The second internal via 120 may be spaced apart from the first source / drain pattern 141. The second internal via 120 may extend in a direction perpendicular to the first surface 110_A of the first substrate 110. The second internal via 120 may be connected to the first wiring structure 170 and the first power line 195. In some embodiments, the width of the second internal via 120 may not be uniform. For example, the width of the second internal via 120 may increase as the second internal via 120 extends away from the second substrate 210. Here, the width may be the width in a direction parallel to the first surface 110_A of the first substrate 110.

[0064] A first power line 195 may be disposed below the second surface 110_B of the first substrate 110. The first power line 195 may be disposed within the third interlayer insulating layer 380. The first power line 195 may extend in a direction parallel to the second surface 110_B of the first substrate 110. In some embodiments, power (e.g., VDD, VSS, or GND) can be supplied to the first transistor 140 via the first power line 195. By providing signal traces on the first surface 110_A of the first substrate 110 and power traces on the second surface 110_B of the first substrate 110, the wiring of the semiconductor device can be effectively designed. Therefore, the electrical characteristics and integration density of the semiconductor device can be improved.

[0065] In some embodiments, the second internal through-hole 120 may be omitted. In this case, for example, source / drain contacts may be formed below the first source / drain pattern 141. The source / drain contacts may penetrate the first substrate 110 and may directly connect the first source / drain pattern 141 and the first power line 195.

[0066] The third interlayer insulating layer 380 may be disposed below the second surface 110_B of the first substrate 110. The first power line 195 and the third wiring structure 370 may be disposed within the third interlayer insulating layer 380. The lower surface of the third interlayer insulating layer 380 may be the lower surface of the logic die 1000. The third wiring structure 370 may be connected to the first power line 195. The material description of the third interlayer insulating layer 380 may be the same as that of the first interlayer insulating layer 180.

[0067] The second semiconductor structure 200 may include a second substrate 210, a second transistor 240, a second wiring structure 270, and a second interlayer insulating layer 280.

[0068] The second transistor 240 may be disposed on the third surface 210_A of the second substrate 210. The second transistor 240 may include a third source / drain pattern 241, a fourth source / drain pattern 242, a second gate electrode 245, and a second channel pattern.

[0069] The second wiring structure 270 can be disposed on the second transistor 240. The second wiring structure 270 can be connected to each of the fourth source / drain pattern 242 and the third internal via 255. For example, as... Figure 4 As shown, the second wiring structure 270 can electrically connect the third internal through-hole component 255 and the first through-hole component 312. For example... Figure 5 As shown, the second wiring structure 270 can electrically connect the fourth source / drain pattern 242 and the second via 314. The second wiring structure 270 can be connected to the second gate electrode 245.

[0070] The third internal via 255 may be spaced apart from the third source / drain pattern 241. The third internal via 255 may extend in a direction perpendicular to the first surface 110_A of the first substrate 110. The third internal via 255 may be connected to the second wiring structure 270 and the second power line 295. In some embodiments, the width of the third internal via 255 may not be uniform. For example, the width of the third internal via 255 may increase as it extends away from the first substrate 110. Here, the width may be the width in a direction parallel to the first surface 110_A of the first substrate 110.

[0071] The second power line 295 may be disposed below the fourth surface 210_B of the second substrate 210. The second power line 295 may be disposed within the first interlayer insulating layer 180. The second power line 295 may extend in a direction parallel to the fourth surface 210_B of the second substrate 210. In some embodiments, power (e.g., VDD, VSS, or GND) can be supplied to the second transistor 240 via the second power line 295. By providing signal traces on the third surface 210_A of the second substrate 210 and power traces on the fourth surface 210_B of the second substrate 210, the wiring of the semiconductor device can be designed efficiently.

[0072] The lower source / drain contact 250 can be disposed below the third source / drain pattern 241. The lower source / drain contact 250 can penetrate the second substrate 210. The lower source / drain contact 250 can electrically connect the third source / drain pattern 241 and the second power line 295.

[0073] The first through-hole 312 and the second through-hole 314 may extend in a direction perpendicular to the first surface 110_A of the first substrate 110. The first through-hole 312 and the second through-hole 314 may penetrate the first substrate 110 and the second substrate 210. Since the shapes of the first through-hole 312 and the second through-hole 314 are described as the same, the description will focus on the first through-hole 312.

[0074] The first through-hole 312 may include a first portion P1 and a second portion P2. The first portion P1 of the first through-hole 312 may be disposed in the third interlayer insulating layer 380. The second portion P2 of the first through-hole 312 may penetrate the first substrate 110 and the second substrate 210. The first portion P1 and the second portion P2 of the first through-hole 312 may be distinguished by their inclination. In terms of cross-section, the inclination of the sidewall of the first portion P1 of the first through-hole 312 may be different from the inclination of the sidewall of the second portion P2 of the first through-hole 312. The width of the first portion P1 of the first through-hole 312 may increase as the first through-hole 312 extends toward the lower surface of the logic die 1000. The width of the second portion P2 of the first through-hole 312 may decrease as the first through-hole 312 extends toward the lower surface of the logic die 1000. Here, the width may be the width in the direction parallel to the first surface 110_A of the first substrate 110.

[0075] The first through-hole 312 can be electrically connected to each of the first upper pad 352 and the first lower pad 342. For example, the first through-hole 312 can be electrically connected to the first upper pad 352 via a second wiring structure 270. The first through-hole 312 can be electrically connected to the first lower pad 342 via a third wiring structure 370. In some embodiments, the first through-hole 312 can be electrically connected to the second power line 295 via the second wiring structure 270 and the third internal through-hole 255. Signals can be supplied to the second transistor 240 via the first through-hole 312, the second wiring structure 270, the third internal through-hole 255, and the second power line 295. Signals can be supplied to the outside via the first through-hole 312, the second wiring structure 270, and the first upper pad 352.

[0076] The second via 314 can be electrically connected to the second lower pad 344. For example, the second via 314 can be electrically connected to the second lower pad 344 via a third wiring structure 370. In some embodiments, the second via 314 can be electrically connected to the fourth source / drain pattern 242 via a second wiring structure 270. Signals can be supplied to the second transistor 240 via the second via 314 and the second wiring structure 270. The signals supplied to the second transistor 240 can be transmitted to the second upper pad 354 via the second wiring structure 270, or can be supplied to the first transistor 140 via the first internal via 220 and the first wiring structure 170.

[0077] The first upper pad 352 and the second upper pad 354 may be disposed on the upper surface of the logic die 1000. The first lower pad 342 and the second lower pad 344 may be disposed on the lower surface of the logic die 1000. Although the number of upper pads 352 and 354 and lower pads 342 and 344 are shown as two each, this disclosure is not limited thereto.

[0078] Figure 6 This is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. For ease of explanation, the description will mainly focus on the references to... Figures 2 to 5 Constructions other than those described. For reference. Figure 6 It can correspond to along Figure 3 A cross-sectional view taken from line A-A'.

[0079] Reference Figure 6 In a semiconductor device according to some embodiments, a third wiring structure 370 may be connected to a first through-hole 312. One end of the first through-hole 312 may be electrically connected to a first power line 195 via the third wiring structure 370. The other end of the first through-hole 312 may be electrically connected to a second power line 295 via a second wiring structure 270 and a third internal through-hole 255. For example, the first through-hole 312 may be electrically connected to each of the first power line 195 and the second power line 295. Therefore, the same power signal may be supplied to each of the first transistor 140 and the second transistor 240.

[0080] Figure 7 This is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. For ease of explanation, the description will mainly focus on the references to... Figures 2 to 5 Constructions other than those described. For reference. Figure 7 It can correspond to along Figure 3 A cross-sectional view taken from line A-A'.

[0081] Reference Figure 7 The semiconductor device according to some embodiments may also include a third lower pad 346.

[0082] The third lower pad 346 can be located below the lower surface of the logic die 1000. For example, the third lower pad 346 can be located below the lower surface of the third interlayer insulating layer 380. The third lower pad 346 can be spaced apart from the first lower pad 342. The third wiring structure 370 can be connected to the third lower pad 346. The third lower pad 346 can be electrically connected to the first power line 195 through the third wiring structure 370.

[0083] In some embodiments, the third lower pad 346 can be directly electrically connected to the first power line 195 via the third wiring structure 370. Here, "direct electrical connection" can mean an electrical connection without passing through a separate component. For example, the first power line 195 can be electrically connected to the third lower pad 346 via the third wiring structure 370 without passing through the first through-hole 312. Therefore, the path of the power signal supplied through the first power line 195 can be shortened.

[0084] Figure 8This is a diagram illustrating a semiconductor device according to some embodiments of the present disclosure. For ease of explanation, the description will mainly focus on the references to... Figure 2 Constructions other than those described.

[0085] Reference Figure 8 According to some embodiments, the semiconductor device may include a logic die 1000, an upper pad 350, a lower pad 340, and a bump 360. The logic die 1000 may include a first semiconductor structure 100 and a second semiconductor structure 200.

[0086] The first semiconductor structure 100 may include a first substrate 110, a first transistor 140, a first wiring structure 170, a first interlayer insulating layer 180, and a lower via 318.

[0087] The lower via 318 can penetrate a portion of the first interlayer insulating layer 180 and the first substrate 110. One end of the lower via 318 can be disposed in the first interlayer insulating layer 180 and on the first wiring structure 170. The lower via 318 can be electrically connected to the first wiring structure 170. The other end of the lower via 318 can penetrate the first substrate 110. A lower pad 340 can be disposed on the other end of the lower via 318. The lower via 318 can be electrically connected to the lower pad 340. A pad layer 322 can be disposed on the sidewall of the lower via 318 and on the second surface 110_B of the first substrate 110.

[0088] In some embodiments, the logic die 1000 of the semiconductor device may further include a lower device isolation film 115. The lower device isolation film 115 may be disposed in a first substrate 110. The first substrate 110 may surround the sidewalls of the lower device isolation film 115. In some embodiments, the upper surface of the lower device isolation film 115 may be disposed in the same plane as the first surface 110_A of the first substrate 110. The lower surface of the lower device isolation film 115 may be disposed in the same plane as the second surface 110_B of the first substrate 110. However, this disclosure is not limited thereto.

[0089] Bump 360 may be disposed below lower pad 340. Bump 360 may be electrically connected to lower pad 340. Bump 360 may transmit signals supplied from an external source to lower pad 340. Bump 360 may be a solder bump comprising a low-melting-point metal (e.g., tin (Sn) or a tin alloy), but this disclosure is not limited thereto. Bump 360 may have various shapes, such as pads, spheres, needles, or pillars. Bump 360 may be formed as a single layer or multiple layers. When bump 360 is formed as a single layer, bump 360 may comprise Sn-Ag solder or copper (Cu). However, this disclosure is not limited thereto.

[0090] The second semiconductor structure 200 may include a second substrate 210, a second transistor 240, a second wiring structure 270, and a second interlayer insulating layer 280.

[0091] The second wiring structure 270 can be electrically connected to the upper pad 350. The upper pad 350 can be electrically connected to the second transistor 240 through the second wiring structure 270. In some embodiments, signals can be supplied to the second transistor 240 through the upper pad 350 and the second wiring structure 270. Alternatively, signals can be transmitted from the second transistor 240 to the upper pad 350 through the second wiring structure 270.

[0092] Figure 9 This is a diagram illustrating a semiconductor device according to some embodiments of the present disclosure. For ease of explanation, the description will mainly focus on the references to... Figure 1 and Figure 2 Constructions other than those described.

[0093] Reference Figure 9 A semiconductor device according to some embodiments may include a first semiconductor structure 100, a second semiconductor structure 200, a plurality of memory dies 2000, an interposer 3000, a plurality of through-holes 400 and a plurality of pads 450.

[0094] The second semiconductor structure 200 can be stacked on the interposer layer 3000. The second semiconductor structure 200 may include a second integrated circuit. The description of the second integrated circuit can be referenced. Figure 2 The description provided is the same. In some embodiments, the second semiconductor structure 200 may be referred to as a buffer die.

[0095] A first semiconductor structure 100 may be stacked on a second semiconductor structure 200. The first semiconductor structure 100 may be spaced apart from the second semiconductor structure 200. A plurality of pads 450 may be disposed between the first semiconductor structure 100 and the second semiconductor structure 200. The first semiconductor structure 100 may include a first integrated circuit. A description of the first integrated circuit may be referenced. Figure 2 The description provided is the same. In some embodiments, the first semiconductor structure 100 may be referred to as a processor die.

[0096] Multiple memory dies 2000 can be stacked on the first semiconductor structure 100. Each of the first semiconductor structure 100, the second semiconductor structure 200, and the memory dies 2000 can be electrically connected through multiple vias 400 and multiple pads 450. By providing multiple memory dies 2000 on the first semiconductor structure 100, the signal path between the first semiconductor structure 100 and the multiple memory dies 2000 can be shortened.

[0097] Although the first semiconductor structure 100 is shown disposed beneath a plurality of memory dies 2000, this disclosure is not limited thereto. For example, the first semiconductor structure 100 may be disposed between two memory dies in the plurality of memory dies 2000. In some embodiments, the number of first semiconductor structures 100 may be plurality.

[0098] Figure 10 This is a diagram illustrating a semiconductor device according to some embodiments of the present disclosure. For ease of explanation, the description will mainly focus on the references to... Figure 1 and Figure 2 Constructions other than those described.

[0099] Reference Figure 10 A semiconductor device according to some embodiments may include a first semiconductor structure 100, a second semiconductor structure 200, a plurality of memory dies 2000, an interposer 3000, a plurality of through-holes 400 and a plurality of pads 450.

[0100] The second semiconductor structure 200 can be stacked on the interposer layer 3000. The second semiconductor structure 200 may include a second integrated circuit. The description of the second integrated circuit can be referenced. Figure 2 The description provided is the same. In some embodiments, the second semiconductor structure 200 may be referred to as a buffer die.

[0101] Multiple memory dies 2000 can be stacked on the second semiconductor structure 200. A first semiconductor structure 100 can be stacked on the multiple memory dies 2000. The first semiconductor structure 100 can be stacked on the topmost memory die among the multiple memory dies 2000. The first semiconductor structure 100 may include a first integrated circuit. The description of the first integrated circuit can be referenced. Figure 2 The description provided is the same. In some embodiments, the first semiconductor structure 100 may be referred to as a processor die.

[0102] Each of the first semiconductor structure 100, the second semiconductor structure 200, and the memory die 2000 can be electrically connected through a plurality of through-holes 400 and a plurality of pads 450. By placing the first semiconductor structure 100 on the plurality of memory dies 2000, the signal path between the first semiconductor structure 100 and the plurality of memory dies 2000 can be shortened.

[0103] In some embodiments, by providing the first semiconductor structure 100 on top of the plurality of memory dies 2000, the plurality of vias 400 may not be provided in the first semiconductor structure 100. As a result, the region in the first semiconductor structure 100 where the plurality of vias 400 are provided is unnecessary, and the first integrated circuit can be provided in that region. In some embodiments, by providing the first semiconductor structure 100 on top of the plurality of memory dies 2000, heat generated in the first semiconductor structure 100 can be easily dissipated to the outside.

[0104] Figure 11 This is a diagram illustrating a semiconductor package according to some embodiments of the present disclosure.

[0105] Reference Figure 11 The semiconductor package may include a stacked memory device 1100, a host die 1200, an interposer 1300, and a package substrate 1400. The stacked memory device 1100 may be a reference... Figures 1 to 10 Any of the described memory devices may include logic die 1000 and memory dies 1120 to 1150. Each of memory dies 1120 to 1150 may include a memory cell array. Logic die 1000 may be a reference... Figures 1 to 8 Any of the logic dies 1000 described. The logic die 1000 can be electrically connected to the physical layer (PHY) 1210 of the host die 1200 via an interposer layer 1300. The stacked memory device 1100 can receive signals from or send signals to the host die 1200 via the second semiconductor structure 200 of the logic die 1000.

[0106] The second semiconductor structure 200 of the logic die 1000 provides an access path for sending and receiving signals with the stacked memory device 1100 without passing through the host die 1200. The second semiconductor structure 200 of the logic die 1000 may include a through-hole 1101 capable of direct communication with an external device. Signals and data received at the second semiconductor structure 200 can be transmitted through the through-hole 1101 to multiple memory dies 1120 to 1150. Data read from the multiple memory dies 1120 to 1150 can be transmitted through the through-hole 1101 and the second semiconductor structure 200 to an external device.

[0107] Logic die 1000 and multiple memory dies 1120 to 1150 can be electrically connected via vias 1101 and bumps 1102. Logic die 1000 can receive signals from host die 1200 provided to each channel via channel-assigned bumps 1102. Although vias 1101 are shown as being directly connected to bumps 1102, this disclosure is not limited thereto. For example, pads may be provided between each bump 1102 and each via 1101.

[0108] The host die 1200 can execute applications supported by a semiconductor package by using a stacked memory device 1100. For example, the host die 1200 may include at least one processor (such as a CPU, AP, GPU, NPU, Tensor Processing Unit (TPU), Vision Processing Unit (VPU), Image Signal Processor (ISP), or DSP) and can perform dedicated computing.

[0109] The host die 1200 may include a physical layer 1210 and a memory controller 1220. The physical layer 1210 may include I / O circuitry for sending signals to and receiving signals from the logic die 1000 of the stacked memory device 1100. The host die 1200 may provide various signals to the logic die 1000 via the physical layer 1210. Signals provided to the logic die 1000 may be transmitted to multiple memory dies 1120 to 1150 via the interface circuitry and vias 1101 of the logic die 1000.

[0110] The memory controller 1220 can control the overall operation of the stacked memory device 1100. The memory controller 1220 can send signals to the stacked memory device 1100 for controlling the stacked memory device 1100 via the physical layer 1210. Alternatively or additionally, the memory controller 1220 can be included in the logic die 1000. For example, a portion of the memory controller 1220 can be included in the first semiconductor structure 100 of the logic die 1000.

[0111] Intermediate layer 1300 can connect stacked memory device 1100 to host die 1200. Intermediate layer 1300 can connect the logic die 1000 of stacked memory device 1100 to the physical layer 1210 of host die 1200 and can provide physical paths formed using conductive material. Therefore, stacked memory device 1100 and host die 1200 can be stacked on intermediate layer 1300 and can send and receive signals to each other.

[0112] Bump 1103 may be attached to the upper surface of package substrate 1400, and solder ball 1104 may be attached to the lower surface of package substrate 1400. For example, bump 1103 may be a flip chip bump. Intermediate layer 1300 may be stacked on package substrate 1400 via bump 1103. Semiconductor package 1000 may send signals to and receive signals from another external package or semiconductor device via solder ball 1104. For example, package substrate 1400 may be a printed circuit board (PCB).

[0113] Figure 12 This is a diagram illustrating a semiconductor package according to some embodiments of the present disclosure.

[0114] Reference Figure 12 The semiconductor package 1 may include a stacked memory device 2100 and a host die 2400. The stacked memory device 2100 and the host die 2400 may be stacked on an interposer 2300, and the interposer 2300 may be stacked on a package substrate 2200. The semiconductor package 1 may send signals to and receive signals from another external package or semiconductor device via solder balls attached to the lower surface of the package substrate 2200.

[0115] Each stacked memory device 2100 may be implemented based on the HBM standard. However, this disclosure is not limited thereto, and each stacked memory device 2100 may be implemented based on GDDR, HMC, or wide I / O standards. Each stacked memory device 2100 may correspond to Figure 11 Stacked memory device 1100.

[0116] The host die 2400 can be implemented as a system-on-a-chip (SoC), which includes at least one processor such as a CPU, AP, GPU, or NPU. The host die 2400 can correspond to... Figure 11 The host chip is 1200.

[0117] Figures 13 to 18 This is a diagram illustrating a method of manufacturing a semiconductor device according to some embodiments of the present disclosure. For ease of illustration, descriptions and references are omitted or simplified. Figure 2 The constructed described are the same as the constructed.

[0118] Reference Figure 13 According to some embodiments, the method of manufacturing a semiconductor device can form a first semiconductor structure 100 and a second semiconductor structure 200 on different wafers.

[0119] A first semiconductor structure 100 may be formed on a first wafer. For example, a first substrate 110 may be formed on the first wafer, and a first transistor 140, a first wiring structure 170, and a first interlayer insulating layer 180 may be formed on the first substrate 110.

[0120] A second semiconductor structure 200 may be formed on a second wafer. For example, a second substrate 210 may be formed on the second wafer, and a second transistor 240, a second wiring structure 270, and a second interlayer insulating layer 280 may be formed on the second substrate 210. In some embodiments, a device isolation film 215 may be formed in the second substrate 210.

[0121] Reference Figure 14 The second semiconductor structure 200 can be rotated, and a portion of the second substrate 210 can be removed. Specifically, the wafer carrier WC can support and rotate the second semiconductor structure 200. Specifically, the second semiconductor structure 200 can be rotated via the wafer carrier WC such that the fourth surface 210_B of the second substrate 210 is at the uppermost position. Then, a portion of the second substrate 210 can be removed, thereby reducing the thickness of the second substrate 210. Here, the thickness can be the thickness in the direction perpendicular to the third surface 210_A of the second substrate 210.

[0122] In some embodiments, the thickness of the second substrate 210 can be reduced by performing a chemical mechanical polishing (CMP) process on the second substrate 210. For example, the device isolation film 215 can be used as a stop element in the CMP process. However, this disclosure is not limited thereto. In the CMP process for reducing the thickness of the second substrate 210, methods using an SOI substrate or a doping gradient of the substrate can be performed.

[0123] Reference Figure 15 It can be combined with the first semiconductor structure 100 and the second semiconductor structure 200.

[0124] Specifically, the fourth surface 210_B of the second substrate 210 can be disposed on the first interlayer insulating layer 180 of the first semiconductor structure 100. In some embodiments, a dielectric layer can be formed on the fourth surface 210_B of the second substrate 210 of the second semiconductor structure 200. Then, the dielectric layer and the first interlayer insulating layer 180 can be bonded by dielectric-to-dielectric bonding. However, this disclosure is not limited thereto.

[0125] Reference Figure 16A first internal via 220 can be formed penetrating the second substrate 210, and a second wiring structure 270 can be connected to the first internal via 220. The first internal via 220 can extend in a direction perpendicular to the third surface 210_A of the second substrate 210 and can be connected to the first wiring structure 170. The first transistor 140 can be electrically connected to the second transistor 240 through the first internal via 220.

[0126] Reference Figure 17 A through-hole 310 can be formed, and a second wiring structure 270 can be connected to the through-hole 310. The through-hole 310 can extend in a direction perpendicular to the third surface 210_A of the second substrate 210 and can penetrate the second substrate 210, the first interlayer insulating layer 180, and the first substrate 110. Before forming the through-hole 310, a pad layer 320 can be formed, and the through-hole 310 can be formed in the pad layer 320. Then, a wiring layer of the second wiring structure 270 can be formed to connect to the through-hole 310. Then, an upper pad 350 can be formed on the upper surface of the second interlayer insulating layer 280. The upper pad 350 can be electrically connected to the through-hole 310 through the second wiring structure 270.

[0127] Reference Figure 18 The logic die 1000 can be rotated, and a lower pad 340 can be formed on the second surface 110_B of the first substrate 110. The lower pad 340 can be electrically connected to the via 310. In some embodiments, a wiring structure can be formed between the lower pad 340 and the via 310. The lower pad 340 and the via 310 can be electrically connected through the wiring structure.

[0128] Figures 19 to 23 This is a diagram illustrating a method of manufacturing a semiconductor device according to some embodiments of the present disclosure. For reference only. Figures 19 to 23 It can correspond to along Figure 3 The cross-sectional view taken by line A-A'. For ease of explanation, descriptions and references are omitted or simplified. Figures 2 to 5 The constructions described are the same constructions.

[0129] Reference Figure 19 According to some embodiments, the method of manufacturing a semiconductor device can form a first semiconductor structure 100 and a second semiconductor structure 200 on different wafers.

[0130] A first semiconductor structure 100 may be formed on a first wafer. For example, a first substrate 110 may be formed on the first wafer, and a first transistor 140, a first wiring structure 170, and a first interlayer insulating layer 180 may be formed on the first substrate 110. The first transistor 140 may include a first source / drain pattern 141, a second source / drain pattern 142, and a first gate electrode 145.

[0131] A second semiconductor structure 200 can be formed on a second wafer. For example, a second substrate 210 can be formed on the second wafer, and a second transistor 240, a second wiring structure 270, and a second interlayer insulating layer 280 can be formed on the second substrate 210. The second transistor 240 may include a third source / drain pattern 241, a fourth source / drain pattern 242, and a second gate electrode 245.

[0132] Reference Figure 20 The second semiconductor structure 200 can be rotated, a lower source / drain contact 250 can be formed on the third source / drain pattern 241, and a second power line 295 can be formed.

[0133] Specifically, the second semiconductor structure 200 can be rotated via the wafer carrier WC so that the fourth surface 210_B of the second substrate 210 is at the top. Then, a lower source / drain contact 250 can be formed, penetrating the second substrate 210 and connecting to the third source / drain pattern 241. Then, a pre-first interlayer insulating layer 180_P and a second power line 295 can be formed. The second power line 295 can be formed in the pre-first interlayer insulating layer 180_P.

[0134] In some embodiments, a portion of the second substrate 210 may be removed before forming the lower source / drain contacts 250, thereby reducing the thickness of the second substrate 210. For example, the thickness of the second substrate 210 may be reduced by performing a CMP process on the second substrate 210. The CMP process may use a device isolation film, an SOI substrate, or a doping gradient of the substrate.

[0135] Reference Figure 21 It can be combined with the first semiconductor structure 100 and the second semiconductor structure 200.

[0136] Specifically, the pre-first interlayer insulating layer 180_P of the second semiconductor structure 200 can be disposed on the first interlayer insulating layer 180 of the first semiconductor structure 100. The first interlayer insulating layer 180 and the pre-first interlayer insulating layer 180_P can be joined by dielectric-to-dielectric bonding.

[0137] Then, a first internal via 220 and a third internal via 255 can be formed. The first internal via 220 can penetrate the second substrate 210 and can be connected to the first wiring structure 170. The third internal via 255 can penetrate the second substrate 210 and can be connected to the second power line 295. Then, a wiring layer of the second wiring structure 270 can be formed to connect to the first internal via 220 and the third internal via 255, respectively.

[0138] Reference Figure 22 A first through-hole 312 and a second through-hole 314 can be formed, and a second wiring structure 270 can be connected to the first through-hole 312 and the second through-hole 314. Each of the first through-hole 312 and the second through-hole 314 can penetrate the second substrate 210, the first interlayer insulating layer 180, and the first surface 110_A of the first substrate 110. One end of each of the first through-hole 312 and the second through-hole 314 can be disposed in the first substrate 110. Before forming the first through-hole 312 and the second through-hole 314, a pad layer 320 can be formed, and the first through-hole 312 and the second through-hole 314 can be formed in the pad layer 320.

[0139] Then, a wiring layer of the second wiring structure 270 can be formed to connect to the first through-hole 312 and the second through-hole 314. Then, a first upper pad 352 and a second upper pad 354 can be formed on the upper surface of the second interlayer insulating layer 280. The first upper pad 352 can be electrically connected to the first through-hole 312 through the second wiring structure 270, and the second upper pad 354 can be electrically connected to the second through-hole 314 through the second wiring structure 270.

[0140] Reference Figure 23 It can rotate the logic die 1000 and form a second internal through-hole 120, a first power line 195 and a third wiring structure 370.

[0141] Specifically, the logic die 1000 can be rotated so that the second surface 110_B of the first substrate 110 is at the top. Then, a portion of the first substrate 110 can be removed to reduce the thickness of the first substrate 110. Then, a second internal via 120 can be formed that penetrates the first substrate 110 and connects to the first wiring structure 170. The second internal via 120 can be electrically connected to the first source / drain pattern 141 through the first wiring structure 170.

[0142] Then, a first power line 195 can be formed on the second internal through-hole 120. The first power line 195 can be connected to the second internal through-hole 120. Then, a first portion P1 of the first through-hole 312 and a first portion of the second through-hole 314 can be formed. Therefore, portions with different inclinations, namely the first portion and the second portion, can be formed for each of the first through-hole 312 and the second through-hole 314. Then, a third wiring structure 370 can be formed. The third wiring structure 370 can be connected to the first power line 195 and each of the first through-hole 312 and the second through-hole 314. Then, a first lower pad 342 and a second lower pad 344 can be formed on the third interlayer insulating layer 380.

[0143] Figures 24 to 28 This is a diagram illustrating a method of manufacturing a semiconductor device according to some embodiments of the present disclosure. For ease of illustration, descriptions and references are omitted or simplified. Figure 8 and Figures 13 to 18 The constructed described are the same as the constructed.

[0144] Reference Figure 24 According to some embodiments, the method of manufacturing a semiconductor device can form a first semiconductor structure 100 and a second semiconductor structure 200 on different wafers.

[0145] A first semiconductor structure 100 may be formed on a first wafer. For example, a first substrate 110 may be formed on the first wafer, and a first transistor 140, a first wiring structure 170, and a first interlayer insulating layer 180 may be formed on the first substrate 110. In some embodiments, a lower device isolation film 115 may be formed in the first substrate 110.

[0146] A second semiconductor structure 200 may be formed on a second wafer. For example, a second substrate 210 may be formed on the second wafer, and a second transistor 240, a second wiring structure 270, and a second interlayer insulating layer 280 may be formed on the second substrate 210. In some embodiments, a device isolation film 215 may be formed in the second substrate 210.

[0147] Reference Figure 25 A portion of the second substrate 210 can be removed, and the first semiconductor structure 100 and the second semiconductor structure 200 can be bonded. The method for removing a portion of the second substrate 210 can be compared with the reference method. Figure 14 The method described is the same. The method of joining the first semiconductor structure 100 and the second semiconductor structure 200 can be the same as that described above. Figure 15 The methods used to describe them are the same.

[0148] Reference Figure 26A first internal via 220 can be formed that penetrates the second substrate 210, and a second wiring structure 270 can be connected to the first internal via 220. The first transistor 140 can be electrically connected to the second transistor 240 through the first internal via 220.

[0149] Reference Figure 27 An upper pad 350 can be formed on the upper surface of the second semiconductor structure 200. The upper pad 350 can be disposed on the upper surface of the second interlayer insulating layer 280. A wiring layer of the second wiring structure 270 can be formed to connect to the upper pad 350. The upper pad 350 can be electrically connected to the second transistor 240 through the second wiring structure 270.

[0150] Reference Figure 28 A portion of the first substrate 110 can be removed, and a lower through-hole 318, a lower pad 340, and a bump 360 can be formed.

[0151] For example, the first semiconductor structure 100 and the second semiconductor structure 200 can be rotated so that the second surface 110_B of the first substrate 110 is at the uppermost position. Then, a portion of the first substrate 110 can be removed. In the process of removing the first substrate 110, the lower device isolation film 115 can be used as a stop.

[0152] Then, a trench can be formed in the first substrate 110 and the first interlayer insulating layer 180. The bottom surface of the trench can expose the first wiring structure 170. Then, a pad layer 322 can be formed on the sidewalls of the trench and on the second surface 110_B of the first substrate 110. The pad layer 322 may include an insulating material. Then, a lower via 318 can be formed in the trench. The lower via 318 can be electrically connected to the first wiring structure 170. Then, a lower pad 340 and a bump 360 can be formed on the lower via 318.

[0153] According to some embodiments of the present disclosure, a method of manufacturing a semiconductor device includes: forming a first semiconductor structure including a first substrate and a first transistor; forming a second semiconductor structure including a second substrate and a second transistor; bonding the first semiconductor structure and the second semiconductor structure; forming an internal through-hole that electrically connects the first transistor and the second transistor; and forming a through-hole that penetrates the first substrate and the second substrate.

[0154] In some embodiments, the internal through-hole can penetrate the first substrate.

[0155] In some embodiments, bonding the first semiconductor structure and the second semiconductor structure may include: removing a portion of the second substrate and bonding the second semiconductor structure onto the interlayer insulating layer of the first semiconductor structure.

[0156] In some embodiments, the method of manufacturing a semiconductor device may further include forming a lower pad and an upper pad connected to a through-hole.

[0157] In some embodiments, forming a second semiconductor structure including a second substrate and a second transistor may include: forming a second transistor on the second substrate; forming a lower source / drain contact that penetrates the second substrate and is electrically connected to the second transistor; and forming a first power line on the lower source / drain contact.

[0158] In some embodiments, the method of manufacturing a semiconductor device may further include: forming a first wiring structure electrically connected to a first power line and disposed on a second transistor before forming a through-hole.

[0159] In some embodiments, the method of manufacturing a semiconductor device may further include forming a second power line on the back surface of a first substrate.

[0160] In some embodiments, the method of manufacturing a semiconductor device may further include: forming a second wiring structure connected to a second power line and a lower pad connected to the second wiring structure.

[0161] In some embodiments, the method of manufacturing a semiconductor device may further include: exposing a via by removing a portion of a first substrate and forming a portion of a via in an interlayer insulating layer disposed on the back surface of the first substrate.

[0162] In some embodiments, the through-hole may include a first portion disposed in an interlayer insulating layer and a second portion penetrating a first substrate and a second substrate, and the inclination of the sidewall of the first portion may be different from the inclination of the sidewall of the second portion.

[0163] Although this disclosure contains numerous specific implementation details, these details should not be construed as limiting the scope of any invention or the scope of what may be claimed, but rather as descriptions of features that may be specific to a particular embodiment of the invention. Some features described in the context of separate embodiments in this specification may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately in multiple embodiments, or in any suitable sub-combination. Furthermore, although features may be described above as operating in certain combinations, in some cases one or more features in a combination may be removed from that combination, and the combination may be for sub-combinations or variations thereof.

[0164] Although specific embodiments of this disclosure have been described with reference to the accompanying drawings, those skilled in the art will understand that this disclosure can be implemented in other specific forms without altering the technical concept or essential characteristics of the disclosure. Therefore, it should be understood that the above embodiments are illustrative in all respects and not restrictive.

Claims

1. A semiconductor device, comprising: Logic dies; A first through-hole extends into at least a portion of the logic die; Upper pads, which are located on the upper surface of the logic die; The lower pad is located below the lower surface of the logic die and is electrically connected to the first through-hole. as well as Multiple memory dies are stacked on the logic die. The logic die includes: A first substrate includes a first surface and a second surface opposite to the first surface; A first transistor is located on a first surface of the first substrate; The second substrate includes a third surface and a fourth surface opposite to the third surface and facing the first surface of the first substrate; A second transistor, which is located on the third surface of the second substrate; and An internal through-hole extends into the second substrate, wherein the first transistor and the second transistor are connected through the internal through-hole.

2. The semiconductor device of claim 1, wherein, The first through-hole extends into the first substrate and the second substrate.

3. The semiconductor device as claimed in claim 1, wherein, The logic die includes a first interlayer insulating layer on a first surface of the first substrate, and The fourth surface of the second substrate is in contact with the first interlayer insulating layer.

4. The semiconductor device of claim 3, wherein, The first through-hole extends into the first interlayer insulation layer.

5. The semiconductor device of claim 3, wherein, The logic die includes a device isolation film on the first interlayer insulating layer, and The second substrate is located on the outer side of the isolation membrane of the device.

6. The semiconductor device of claim 1, wherein, The logic die includes a first wiring structure on the first transistor and a second wiring structure on the second transistor, and The internal through-hole is located between the first wiring structure and the second wiring structure.

7. The semiconductor device of claim 1, including an interposer layer below the logic die and electrically connected to the lower pad.

8. The semiconductor device of claim 7, wherein, The first transistor is electrically connected to the controller through the interposer layer.

9. The semiconductor device of claim 1, wherein, The first transistor is configured as part of a first integrated circuit, which includes data compression functionality and artificial intelligence-based inference functionality. The second transistor is configured as part of a second integrated circuit, which includes a signal relay function.

10. A semiconductor device, comprising: A first substrate includes a first surface and a second surface opposite to the first surface; A first transistor is located on a first surface of the first substrate and includes a first source / drain pattern and a second source / drain pattern. A first power line is electrically connected to the first source / drain pattern, wherein the first power line is below the second surface of the first substrate; The second substrate includes a third surface and a fourth surface opposite to the third surface and facing the first surface of the first substrate; The second transistor is located on the third surface of the second substrate and includes a third source / drain pattern and a fourth source / drain pattern. The second power line is electrically connected to the third source / drain pattern and is located below the fourth surface of the second substrate; A plurality of through-holes extending in a direction perpendicular to a first surface of the first substrate and extending into each of the first substrate and the second substrate; and A first internal via extends into the second substrate, wherein the first transistor and the second transistor are electrically connected through the first internal via.

11. The semiconductor device of claim 10, wherein, The plurality of through-hole components includes a first through-hole component and a second through-hole component. The first through-hole component is electrically connected to the second power line, and The second through-hole is electrically connected to the fourth source / drain pattern of the second transistor.

12. The semiconductor device of claim 10, further comprising a lower source / drain contact below the third source / drain pattern of the second transistor and extending into at least a portion of the second substrate. in, The lower source / drain contact is electrically connected to the third source / drain pattern and the second power line.

13. The semiconductor device of claim 10, further comprising a second internal via spaced apart from the first source / drain pattern of the first transistor and extending into the first substrate. in, The second internal through-hole is electrically connected to the first source / drain pattern and the first power line.

14. The semiconductor device of claim 10, wherein, One of the plurality of through-hole components is electrically connected to each of the first power line and the second power line.

15. The semiconductor device of claim 10, comprising: An interlayer insulating layer is located below the second surface of the first substrate; as well as The first and second lower pads are located below the lower surface of the interlayer insulating layer. The plurality of through-hole components include a first through-hole component and a second through-hole component. The first through-hole component is electrically connected to the first lower pad, and The second through-hole component is electrically connected to the second lower pad.

16. The semiconductor device of claim 15, wherein, The first through-hole includes a first portion in the interlayer insulating layer and a second portion extending into the first substrate and the second substrate, and The inclination of the sidewall of the first part is different from that of the sidewall of the second part.

17. A semiconductor device, comprising: A first substrate includes a first surface and a second surface opposite to the first surface; A first transistor is located on a first surface of the first substrate and includes a first source / drain pattern and a second source / drain pattern. A first power line is electrically connected to the first source / drain pattern and is located below the second surface of the first substrate; The second substrate includes a third surface and a fourth surface opposite to the third surface and facing the first surface of the first substrate; The second transistor is located on the third surface of the second substrate and includes a third source / drain pattern and a fourth source / drain pattern. A first internal via extends into the second substrate, wherein a second source / drain pattern of the first transistor and a fourth source / drain pattern of the second transistor are electrically connected through the first internal via. An interlayer insulating layer is located below the second surface of the first substrate; The lower pad is located below the lower surface of the interlayer insulating layer; and A first wiring structure is located within the interlayer insulation layer and is electrically connected to the first power line and the lower pad.

18. The semiconductor device of claim 17, comprising: The second power line is located below the fourth surface of the second substrate and is electrically connected to the third source / drain pattern of the second transistor.

19. The semiconductor device of claim 17, comprising: Lower source / drain contacts extend into the first substrate and are electrically connected to the first source / drain pattern of the first transistor and the first power line; A second interlayer insulating layer is located on the third surface of the second substrate; The upper pad is located on the upper surface of the second interlayer insulating layer; as well as A second wiring structure is provided on the second transistor, wherein the third source / drain pattern of the second transistor and the upper pad are electrically connected through the second wiring structure.

20. The semiconductor device of claim 17, comprising a through-hole extending into the first substrate and the second substrate and electrically connected to the first wiring structure.

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