Method of manufacturing a semiconductor device and apparatus for manufacturing a semiconductor device

Abstract

Provided are a method for manufacturing a semiconductor device and an apparatus for manufacturing a semiconductor device, relating to the technical field of semiconductor technology. The method comprises: forming a via along a first direction in a stack structure, the via can be a blind via which does not penetrate the stack structure, or can be a through via which penetrates the stack structure; and forming a conductive layer on a hole wall of the via; wherein, in the process of forming the conductive layer, a target reagent is introduced into the via, and the target reagent can adjust different formation speeds of the conductive layer on different regions of the hole wall, so as to gradually increase the thickness of the conductive layer along the first direction. In this way, it is favorable to reduce the probability of occurrence of defects such as holes in the semiconductor device, and improve the performance and service life of the semiconductor device. Moreover, the foregoing method can be well compatible with the current conventional deposition mode, and has great market potential.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to methods and apparatus for fabricating semiconductor devices. Background Technology

[0002] The development of semiconductor technology is extremely crucial. It is not only the core driving force for the upgrading and progress of the industry itself, but also a powerful guarantee for the continuous advancement of electronification and digitalization.

[0003] However, current semiconductor device fabrication processes have significant drawbacks. Semiconductor devices fabricated using these processes are prone to generating a large number of uncontrolled and unevenly distributed holes or defects, which affect the performance and lifespan of the semiconductor devices.

[0004] Therefore, there is an urgent need to improve the methods for fabricating semiconductor devices in order to promote the further development of semiconductor technology. Summary of the Invention

[0005] This application provides a method and apparatus for fabricating semiconductor devices, which can reduce the probability of defects such as voids and flaws in semiconductor devices, thereby improving the performance and lifespan of semiconductor devices.

[0006] A first aspect provides a method for fabricating a semiconductor device. The method includes: providing a stacked structure for fabricating the semiconductor device; forming vias along a first direction in the stacked structure, the vias being either blind vias that do not penetrate the stacked structure or through-holes that penetrate the stacked structure; forming a conductive layer on the wall of the via; wherein, during the formation of the conductive layer, a target reagent is introduced into the via, the target reagent being able to adjust different formation rates of the conductive layer in different regions of the via wall, so as to achieve a gradual increase in the thickness of the conductive layer along the first direction.

[0007] Currently, the thickness of conductive layers formed by deposition and other methods typically increases gradually along the first direction. If deposition continues, vias are prone to premature sealing, resulting in a step coverage issue. This leads to a large number of uncontrolled and unevenly distributed holes or defects in the fabricated semiconductor device, affecting its performance and lifespan. To better distinguish between the conductive layers prepared by the method of this application embodiment and conventional deposition methods, in the following analysis, the conductive layer prepared by the method of this application embodiment will be referred to as a conductive layer, and the conductive layer prepared by conventional deposition methods will be referred to as a conventional conductive layer.

[0008] In the method for fabricating semiconductor devices provided in this application, a conductive layer is formed on the wall of a via, and a target reagent is introduced into the via to cause differentiated growth of the conductive layer in different regions of the via wall. The thickness of the conductive layer gradually increases along a first direction. Furthermore, a conventional conductive layer can be selectively formed on the side of the conductive layer away from the via wall. As analyzed above, the thickness of the conventional conductive layer gradually decreases along the first direction. In short, the thickness of the conductive layer and the conventional conductive layer show opposite trends along the first direction, and the process of forming the conductive layer is equivalent to reverse-utilizing the step coverage during the formation of the conventional conductive layer. This helps reduce the probability of defects such as voids and flaws in the semiconductor device, improves the density and uniformity of the semiconductor device, and thus improves the performance and lifespan of the semiconductor device. Moreover, the aforementioned method is highly compatible with current conventional deposition methods and has significant market potential.

[0009] In one possible implementation, the target reagent includes an inhibitor, the concentration of which gradually decreases along a first direction.

[0010] During the formation of the conductive layer, an inhibitor is introduced into the via. Treating the conductive layer with the inhibitor allows for control of the growth rate of the conductive layer in different regions of the via wall, enabling differentiated growth in these regions. Furthermore, as the inhibitor concentration gradually decreases along the first direction, the inhibitory effect on the conductive layer gradually weakens along the same direction. Regions with strong inhibition exhibit slower growth rates, while regions with weak inhibition show faster growth rates. This, in turn, facilitates a gradual increase in the thickness of the conductive layer along the first direction.

[0011] In one possible implementation, the target reagent includes an etchant, the concentration of which gradually decreases along a first direction.

[0012] During the formation of the conductive layer, an etchant is introduced into the via. By treating the conductive layer with the etchant, the etching degree of the conductive layer in different areas of the via wall can be controlled, thereby controlling the thickness of the conductive layer in different areas of the via wall. Furthermore, since the concentration of the etchant gradually decreases along the first direction, the etching effect of the etchant on the conductive layer gradually weakens along the first direction. Areas with a strong etching effect can etch away more material of the conductive layer; areas with a weak etching effect can etch away less material of the conductive layer. This facilitates a gradual increase in the thickness of the conductive layer along the first direction.

[0013] In one possible implementation, a conventional conductive layer is formed on the side of the conductive layer away from the via wall, and the thickness of the conventional conductive layer gradually decreases along a first direction to obtain a conductive pillar penetrating the via. To better distinguish between the conductive pillars prepared by the method provided in this application embodiment and those prepared by conventional deposition methods, in the following analysis, the conductive pillar prepared by the method of this application embodiment will be referred to as a conductive pillar, and the conductive pillar prepared by conventional deposition methods will be referred to as a conventional conductive pillar.

[0014] As can be seen from the above analysis, the thickness of conventional conductive layers formed by deposition and other methods usually increases gradually along the first direction. If deposition is continued to obtain conventional conductive pillars, they have a large number of uncontrolled and unevenly distributed pores or defects inside.

[0015] Using the method provided in this application embodiment, the thickness of the conductive layer shows a trend of gradually increasing along the first direction, while the thickness of the conventional conductive layer shows a trend of gradually decreasing along the first direction. The trends of change in the thickness of the conductive layer and the conventional conductive layer are exactly opposite. As a result, the conductive pillar prepared using the method provided in this application embodiment has good density and uniformity.

[0016] In one possible implementation, before forming a conductive layer on the via wall, the method for fabricating the semiconductor device further includes: sequentially forming an electrode layer and a ferroelectric layer on the via wall; forming the conductive layer on the via wall includes: forming a conductive layer on the side of the ferroelectric layer away from the electrode layer. The electrode layer, ferroelectric layer, and conductive layer are stacked sequentially. In this embodiment, the semiconductor device is a ferroelectric memory, the conductive pillar in this embodiment can serve as a first electrode in the ferroelectric memory, the electrode layer in this embodiment can serve as a second electrode in the ferroelectric memory, and the ferroelectric layer in this embodiment can serve as a ferroelectric layer in the ferroelectric memory.

[0017] As the foregoing analysis shows, currently fabricated semiconductor devices have a large number of uncontrolled and unevenly distributed holes or defects. These holes or defects are mainly concentrated in the first electrode (conductive pillar), which disrupts the continuity and uniformity of the first electrode. These areas of holes or defects become stress concentration areas, effectively worsening the stress conditions between the first electrode and the ferroelectric layer. This leads to at least one of the following problems: First, poor stress distribution affects the polarization characteristics of the ferroelectric layer, resulting in decreased storage capacity and data read / write accuracy of the ferroelectric memory. Second, poor stress distribution affects the structural stability of the ferroelectric memory, reducing its performance stability during long-term use and shortening its lifespan. Third, a large number of holes or defects in the first electrode increase its resistivity, affecting the performance of the ferroelectric memory.

[0018] The semiconductor device (ferroelectric memory) prepared in this application embodiment exhibits a conductive layer thickness that changes in the opposite direction to that of a conventional conductive layer along the first direction. This reduces the likelihood of premature via sealing, minimizing the formation of voids and defects in the semiconductor device and conductive pillars, resulting in excellent density and uniformity. Consequently, a superior stress distribution exists between the first electrode and the ferroelectric layer, leading to improved performance stability and lifespan of the ferroelectric memory. The method for preparing semiconductor devices provided in this application embodiment facilitates improved yield rates for ferroelectric memory preparation, enabling efficient and low-cost manufacturing of a new generation of stable, high-performance, high-density ferroelectric memories.

[0019] In one possible implementation, the ferroelectric layer is made of hafnium-based ferroelectric material. The ferroelectric layer corresponding to hafnium-based ferroelectric material can be called a hafnium-based ferroelectric layer, and the ferroelectric memory corresponding to hafnium-based ferroelectric material can be called a hafnium-based ferroelectric memory.

[0020] When the first electrode (conductive post) of a ferroelectric memory has numerous voids, defects, or other defects, its performance stability is significantly reduced. This instability directly affects the hafnium-based ferroelectric layer. Because hafnium-based ferroelectric materials are stress-sensitive, the hafnium-based ferroelectric layer is highly susceptible to stress, leading to a marked deterioration in its performance stability and a significant shortening of the hafnium-based ferroelectric memory's lifespan. However, the semiconductor device (hafnium-based ferroelectric memory) prepared in this application is less prone to voids and defects in its first electrode. While maintaining superior performance, this significantly improves the performance stability and lifespan of the hafnium-based ferroelectric memory.

[0021] In one possible implementation, a plurality of vias are formed along a first direction in the stacked structure, and the plurality of vias are arranged in close packing. When the semiconductor device is used as a ferroelectric memory, the ferroelectric memory includes a plurality of memory cells, and a single memory cell may include a first electrode, a ferroelectric layer, a second electrode within the via, and may also include other components.

[0022] The first electrode fabricated using current processes has numerous uncontrolled and unevenly distributed voids or defects, resulting in poor continuity and uniformity. Furthermore, the direct contact between the first electrode and the ferroelectric layer contributes to the poor continuity and uniformity of the ferroelectric layer itself. Consequently, the multiple memory cells within the ferroelectric memory exhibit significant differences, leading to poor uniformity and negatively impacting data storage and retrieval, reliability and stability, device performance, and lifespan.

[0023] The semiconductor device (ferroelectric memory) prepared in the embodiments of this application is less prone to defects and other adverse phenomena such as holes in the first electrode, the differences between multiple memory cells in the ferroelectric memory are small, the uniformity of the ferroelectric memory is better, and the performance stability, reliability and service life of the ferroelectric memory can be improved.

[0024] In one possible implementation, forming a conductive layer on the wall of a via includes: forming a first sub-layer of the conductive layer on the wall of the via; introducing a first target reagent into the via, wherein the target reagent includes a first target reagent comprising an inhibitor and / or an etchant; and forming a second sub-layer of the conductive layer on the side of the first sub-layer away from the wall of the via.

[0025] After the first sublayer of the conductive layer is formed on the hole wall, a first target reagent is introduced into the via. The first target reagent can adjust the different formation rates of the first sublayer of the conductive layer in different regions of the hole wall. This scheme can be used to describe the process of atomic layer deposition, which typically deposits one monoatom layer at a time. The first target reagent can be introduced after each monoatom layer is formed, or after a portion of the monoatom layers have been formed.

[0026] In one possible implementation, prior to forming the first sublayer of the conductive layer, the method further includes: introducing a second target reagent into the via, wherein the target reagent includes a second target reagent, which includes an inhibitor.

[0027] Before forming the first sublayer of the conductive layer on the hole wall, a second target reagent is introduced into the via. The second target reagent can adjust the different formation rates of the first sublayer of the conductive layer in different regions of the hole wall. In this scheme, after treatment with the second target reagent, the thickness of the first sublayer of the conductive layer along the first direction can gradually increase, remain approximately unchanged, or gradually decrease.

[0028] In one possible implementation, forming a conductive layer on the wall of a via includes: introducing a third target reagent into the via, wherein the target reagent includes a third target reagent, the third target reagent including an inhibitor; forming a first sublayer of the conductive layer on the wall of the via, the thickness of the first sublayer of the conductive layer gradually increasing along a first direction; and forming a second sublayer of the conductive layer on the wall of the via.

[0029] Before forming a conductive layer on the via wall, a third target reagent is introduced into the via. This third target reagent can adjust the different formation rates of the conductive layer in different regions of the via wall. The main difference from the previous possible implementation is that in this scheme, before the formation of the first sub-layer of the conductive layer, the via wall is treated with the third target reagent. The result is that the thickness of the first sub-layer of the conductive layer gradually increases along the first direction, and the first sub-layer of the conductive layer is not treated with the first target reagent. In the previous possible implementation, before the formation of the first sub-layer of the conductive layer, the via wall is treated with the third target reagent. The result is that the thickness of the first sub-layer of the conductive layer is not limited, and the first sub-layer of the conductive layer is treated with the first target reagent.

[0030] In a second aspect, an apparatus for fabricating a semiconductor device is provided. The apparatus includes a first conduit and a second conduit. The first conduit is configured to supply a conductive material to a via along a first direction, the conductive material being used to form a conductive layer. The second conduit is configured to supply a target reagent to the via along the first direction, the target reagent controlling the differentiated growth of the conductive layer on different regions of the via wall, causing the thickness of the conductive layer to gradually increase along the first direction.

[0031] Conductive material is supplied to the via along a first direction through a first conduit. The conductive material deposits on the via wall to form a conductive layer, the thickness of which gradually decreases along the first direction. A target reagent is supplied to the via along the first direction through a second conduit. The target reagent controls the differentiated growth of the conductive layer in different regions of the via wall, causing the thickness of the conductive layer to gradually increase along the first direction. Alternatively, the conductive material can be used to form a conventional conductive layer on the side of the conductive layer away from the via wall, with the thickness of the conventional conductive layer gradually decreasing along the first direction. In this way, semiconductor devices fabricated by the aforementioned apparatus are less prone to defects such as voids and pores, exhibiting superior performance and lifespan. Furthermore, the aforementioned apparatus only requires the addition of a second conduit for supplying the target reagent to a conventional fabrication apparatus, making it highly compatible with current conventional fabrication equipment and possessing significant market potential.

[0032] In one possible implementation, the target reagent includes an inhibitor and / or an etchant. The second conduit can be used to deliver either the inhibitor or the etchant, and may also include two branch conduits to deliver both the inhibitor and the etchant simultaneously.

[0033] In one possible implementation, the device further includes a third conduit and a fourth conduit. The third conduit is configured to supply electrode material to the via for forming an electrode layer on the via wall. The fourth conduit is configured to supply ferroelectric material to the via for forming a ferroelectric layer on the electrode layer.

[0034] Electrode material is supplied to the via through a third conduit, and the electrode material can be deposited on the via wall to form an electrode layer; ferroelectric material is supplied to the via through a fourth conduit, and the ferroelectric material can be deposited on the electrode layer to form a ferroelectric layer; thus, the semiconductor device fabricated using this device can be used as a ferroelectric memory. For a description of the semiconductor device as a ferroelectric memory, please refer to the first aspect, which will not be repeated here.

[0035] In one possible implementation, the ferroelectric material includes hafnium-based ferroelectric materials. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 These are schematic diagrams of the structures of some electronic devices;

[0038] Figure 2 Flowcharts for fabricating some semiconductor devices provided in the embodiments of this application;

[0039] Figure 3 This is a schematic diagram of the structure for fabricating some semiconductor devices provided in the embodiments of this application;

[0040] Figure 4 This application provides schematic diagrams illustrating the fabrication of other semiconductor devices.

[0041] Figure 5 This application provides schematic diagrams illustrating the fabrication of further semiconductor devices.

[0042] Figure 6 Flowcharts for fabricating other semiconductor devices provided in the embodiments of this application;

[0043] Figure 7 This application provides schematic diagrams illustrating the fabrication of further semiconductor devices.

[0044] Figure 8 Here are some schematic diagrams showing the structures used to fabricate semiconductor devices;

[0045] Figure 9 Cross-sectional views of some semiconductor devices provided in the embodiments of this application;

[0046] Figure 10 Top views of some semiconductor devices provided in the embodiments of this application;

[0047] Figure 11 Top views of other semiconductor devices provided in the embodiments of this application;

[0048] Figure 12 A top view of some semiconductor devices;

[0049] Figure 13 Top view of some other semiconductor devices;

[0050] Figure 14 Schematic diagrams of some apparatuses for fabricating semiconductor devices provided in the embodiments of this application;

[0051] Figure 15 This is a schematic diagram of the structure of some other apparatuses for fabricating semiconductor devices provided in the embodiments of this application.

[0052] Figure label:

[0053] 1-Electronic equipment; 10-Semiconductor devices; 20-Circuit boards; 30-Processors.

[0054] 100 - Stacked structure; 200 - Via; 310 - Conductive layer; 320 - Conventional conductive layer; 400 - Inhibitor; 500 - Etching agent; 600 - Conductive pillar; 700 - Electrode layer; 800 - Ferroelectric layer; A-plate - Support plate.

[0055] 1100 - First channel; 1100a - Conductive material containment area; 1200 - Second channel; 1200a - Target reagent containment area; 1300 - Third channel; 1300a - Electrode material containment area; 1400 - Fourth channel; 1400a - Ferroelectric material containment area; 2000 - Preparation area. Detailed Implementation

[0056] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the embodiments of this application, and not all embodiments.

[0057] In the following, the terms "first," "second," etc., are used only for descriptive purposes to distinguish identical or similar items that have substantially the same function and effect, and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the embodiments of this application, the term "connection" should be interpreted broadly; unless otherwise explicitly specified and limited, "connection" can be a direct connection or an indirect connection through an intermediate medium.

[0058] To facilitate understanding of the semiconductor devices provided in the embodiments of this application, the application devices of the semiconductor devices are described below.

[0059] Semiconductor devices are widely used in various electronic devices, such as servers, cloud computing electronic devices, AI electronic devices, optical communication devices, mobile phones, tablet personal computers, laptop computers, personal digital assistants (PDAs), cameras, personal computers, laptops, automotive equipment, wearable devices, augmented reality (AR) glasses, AR headsets, virtual reality (VR) glasses, or VR headsets, and other devices that require data processing / storage / transmission and reception.

[0060] Figure 1 This is a schematic diagram of the structure of some electronic devices 1.

[0061] refer to Figure 1 The electronic device 1 includes a semiconductor device 10 and a circuit board 20, and signal transmission can be performed between the semiconductor device 10 and the circuit board 20.

[0062] The semiconductor device 10 can be used as a device with various functions. The semiconductor device 10 provided in this application embodiment is applicable to the following situations where, during the fabrication process of the semiconductor device 10, it is necessary to fill the vias to obtain conductive pillars. In some examples, the semiconductor device 10 can be used as a memory; during the fabrication of the memory, it is necessary to fill the vias to obtain electrodes or other functional intercalation layers. In other examples, the semiconductor device 10 can be used as a power chip; in the multilayer metal interconnect process for fabricating the power chip, it is necessary to etch the interlayer dielectric to form vias, and then fill the vias with conductive material to form conductive pillars. Of course, the above are merely examples; the semiconductor device 10 provided in this application embodiment can also be used as a device with other functions, as long as it meets the requirement of filling the vias to obtain conductive pillars during its fabrication process.

[0063] The following explanation uses semiconductor device 10 as an example of a memory device:

[0064] The memory plays a crucial role in electronic device 1, serving to store data and program instructions. For example, the memory can be used to perform write or read operations; when the memory performs a write operation, it can store information; when the memory performs a read operation, it can retrieve the information stored in the memory.

[0065] The memory in the aforementioned electronic device 1 can be a three-dimensional memory. Three-dimensional memories include three-dimensional flash memory, three-dimensional ferroelectric memory (3D FRAM), three-dimensional phase-change memory (3D PCM), or three-dimensional magnetoresistive memory (3D MRAM), etc.

[0066] For example, a three-dimensional memory could be a three-dimensional flash memory, which uses silicon nitride, silicon oxide, or similar materials as charge storage media, storing data by controlling the charge on a floating gate. Another example is a three-dimensional ferroelectric memory, where the ferroelectric material can be lead zirconate titanate (PZT) or barium titanate (BaTiO3), etc. Ferroelectric materials possess a unique ferroelectric effect, storing data by changing their polarization state. Yet another example is a three-dimensional phase-change memory, based on chalcogenide compounds such as germanium-antimony-tellurium (Ge-Sb-Te) alloys, where heating causes the phase-change material to transition between crystalline and amorphous states to represent different data states. Finally, a three-dimensional magnetoresistive memory could be a three-dimensional magnetic tunnel junction (MTJ) material, composed of a ferromagnetic layer, an insulating layer, and another ferromagnetic layer; the resistance of the tunnel junction is controlled by changing the magnetization direction of the ferromagnetic layer, thereby storing and retrieving data.

[0067] When the semiconductor device 10 is a memory, the electronic device 1 may also include a controller 30, which is connected to the circuit board 20. For example... Figure 1 As shown, the controller 30 can be located outside the memory, with both the controller 30 and the memory connected to the circuit board 20 to establish signal connections between them; alternatively, the controller 30 can be located inside the memory, serving as part of it. During the startup or operation of the electronic device 1, the controller 30 reads data and instructions from the memory to perform various operations. The performance of the memory affects its ability to read data and instructions, thereby impacting the operating speed, responsiveness, and data processing efficiency of the electronic device 1.

[0068] Those skilled in the art will understand that the structure of the electronic device 1 shown in the foregoing figures does not constitute a limitation on the electronic device 1, and the electronic device 1 may include, but is not limited to, other electronic devices. Figure 1 Other components, such as electronic device 1, may also include input modules (e.g., keyboard, mouse, microphone, camera, etc.), output devices (e.g., monitor, printer, headphones, etc.), power management modules (e.g., battery, charging circuit, etc.), sensors, and other components, which are not limited in this application embodiment.

[0069] The development of semiconductor technology is extremely crucial. It is not only the core driving force for the upgrading and progress of the industry itself, but also a powerful guarantee for the continuous advancement of electronification and digitalization.

[0070] The following explanation uses semiconductor devices as an example of memory: The rapid development of cutting-edge technologies such as the Internet of Things, artificial intelligence, and big data analytics all rely on the rapid acquisition, transmission, and analysis of massive amounts of data. In this process, memory performance plays a crucial role. Only high-performance memory can ensure efficient data storage and rapid retrieval, meeting the speed and capacity requirements of the aforementioned technologies. As these technologies continue to innovate and information systems evolve towards greater complexity and power, their demands on memory performance are also increasing.

[0071] However, current memory fabrication processes have significant drawbacks. Memory chips produced using these processes are highly susceptible to defects such as voids and flaws, which negatively impact their performance and lifespan. In some cases, electrodes are crucial components of the memory, and their quality plays a decisive role in its performance. Currently, electrodes are typically formed within vias. However, due to defects in the fabrication process, these electrodes are prone to developing numerous uncontrolled and unevenly distributed voids, resulting in poor memory performance and a shorter lifespan.

[0072] Based on this, embodiments of this application provide a method for fabricating a semiconductor device 10 and an apparatus for fabricating a semiconductor device 10.

[0073] Figure 2 A flowchart illustrating the fabrication of some semiconductor devices 10 provided in this application embodiment. Figures 3 to 5 This is a schematic diagram of the structure for fabricating some semiconductor devices 10 provided in the embodiments of this application.

[0074] This application provides a method for fabricating a semiconductor device 10, referring to... Figure 2 The method for fabricating semiconductor device 10 includes:

[0075] S100: Provides a stacked structure for fabricating semiconductor devices.

[0076] In some embodiments, the stacked structure 100 may include a structure formed by stacking multiple material layers in sequence. The multiple material layers may include material layers such as substrate, dielectric layer, metal interconnect layer, device layer formed of semiconductor material, etc. The material layers in the stacked structure 100 are usually arranged according to the functions that the semiconductor device 10 needs to achieve.

[0077] In some examples, the semiconductor device 10 serves as a memory, and the stacked structure 100 can be two or more material layers stacked in a periodic manner. For example, the stacked structure 100 can be a structure formed by periodically stacking an oxide layer and a silicon nitride layer. It is understood that periodic stacking means that the oxide layer and the silicon nitride layer are stacked and arranged alternately. In other examples, the semiconductor device 10 serves as a power chip, and the stacked structure 100 can include a substrate and multiple functional layers (buffer layer, active layer, barrier layer, etc.) epitaxially formed on the substrate.

[0078] S200: A via is formed in the stacked structure along the first direction.

[0079] In this step, refer to Figure 3 and Figure 4 The via 200 in the stacked structure 100 can be a blind via that does not penetrate the stacked structure 100; Reference Figure 5 The via 200 in the stacked structure 100 can also be a through hole that penetrates the stacked structure 100. This application does not specifically limit the shape of the via 200; the shape of the via 200 can be set according to actual needs. In some examples, the cross-section of the via 200 can be circular, square, or other shapes.

[0080] In some embodiments, reference Figures 3 to 5 The first direction can be the same as the thickness direction of the stacked structure 100. For example, the stacked structure 100 has a first surface and a second surface arranged opposite to each other. The first surface and the second surface are the two surfaces with the largest area in the stacked structure 100. Let the direction from the first surface to the second surface be the second direction. The first direction and the second direction are the same, that is, the first direction is the same as the thickness direction of the stacked structure 100.

[0081] In other embodiments, the first direction may form an angle with the thickness direction of the stacked structure 100. For example, the stacked structure 100 has a first surface and a second surface arranged opposite to each other. The first surface and the second surface can be the two surfaces with the largest area in the stacked structure 100. The direction from the first surface to the second surface is the second direction, and the first direction and the second direction form an angle, that is, the first direction and the thickness direction of the stacked structure 100 form an angle. The embodiments of this application do not limit the size of the angle between the first direction and the second direction. Those skilled in the art can choose according to actual needs, such as 1 degree, 2 degrees, 3 degrees, or 4 degrees.

[0082] In some embodiments, methods for forming vias 200 along a first direction in the stacked structure 100 include: deep reactive ion etching (DRIE), photo-assisted electrochemical etching (PAECE), laser drilling, photolithography, etching, etc. Taking laser drilling as an example, laser drilling mainly involves irradiating the material of a designated area of ​​the stacked structure 100 along the first direction with a high-energy laser to melt and evaporate the material, thereby obtaining the via 200.

[0083] S300: A conductive layer is formed on the wall of the via, and the thickness of the conductive layer gradually increases along the first direction.

[0084] In this step, refer to Figures 3 to 5 In steps (2), (3) and (4), a conductive layer 310 is formed on the wall of the via 200; wherein, during the formation of the conductive layer 310, a target reagent is introduced into the via 200, and the target reagent can adjust the different formation rates of the conductive layer 310 in different regions of the wall, so that the thickness of the conductive layer 310 gradually increases along the first direction.

[0085] Currently, the thickness of the conductive layer 310 formed by deposition or other methods typically increases gradually along the first direction. If deposition continues, vias are prone to premature sealing, resulting in differences in step coverage. This leads to a large number of uncontrolled and unevenly distributed holes or defects in the fabricated semiconductor device 10, affecting its performance and lifespan. To better distinguish between the conductive layers prepared by the method of this application embodiment and conventional deposition methods, in the following analysis, the conductive layer prepared by the method of this application embodiment will be referred to as conductive layer 310, and the conductive layer prepared by conventional deposition methods will be referred to as conventional conductive layer 320.

[0086] In the method for fabricating a semiconductor device 10 provided in this application embodiment, a conductive layer 310 is formed on the wall of a via, and a target reagent is introduced into the via to cause differential growth of the conductive layer 310 in different regions of the via wall. The thickness of the conductive layer 310 gradually increases along a first direction. Furthermore, a conventional conductive layer 320 can be selectively formed on the side of the conductive layer 310 away from the via wall. As analyzed above, the thickness of the conventional conductive layer 320 gradually decreases along the first direction. In short, the thickness of the conductive layer 310 and the conventional conductive layer 320 show opposite trends along the first direction. The process of forming the conductive layer 310 is equivalent to reverse-utilizing the step coverage during the formation of the conventional conductive layer 320. This helps reduce the probability of defects such as voids and flaws in the semiconductor device 10, improves the density and uniformity of the semiconductor device 10, and thus improves the performance and lifespan of the semiconductor device 10. Moreover, the aforementioned method is highly compatible with current conventional deposition methods and has significant market potential.

[0087] In some embodiments, the via 200 in step S300 can be Figure 3 , Figure 4 The blind hole shown can also be Figure 5 The through hole shown. The main difference is: Figure 3 , Figure 4 The blind hole shown can be deposited directly from the opening side of the blind hole to obtain the conductive layer 310; Figure 5 The through-hole shown typically requires a support plate A to seal one side of the through-hole, and then deposition to be performed on the side away from the support plate A, so that the preparation process of forming the conductive layer 310 can be completed smoothly.

[0088] In some examples, reference Figure 3 (2) Figure 4 In step (2), a conductive layer 310 is deposited on the wall of the blind via to form a portion of the blind via area, and the blind via is not pre-sealed. In other embodiments, refer to Figure 5 In step (2), one end of the through hole is set on the support plate A, and a conductive layer 310 is deposited on the hole wall from the other end of the through hole. The conductive layer 310 occupies part of the through hole area, and the through hole is not pre-sealed. In this embodiment, the specific thickness of the conductive layer 310 is not specifically limited, as long as the thickness of the conductive layer 310 in the via 200 (blind hole or through hole) is less than the diameter of the via 200. In other words, step S300 does not pre-seal the via 200, and a new conductive layer can be formed on the side of the conductive layer 310 away from the hole wall through secondary deposition or multiple deposition.

[0089] Premature sealing of via 200 refers to the situation where, during the deposition of the conductive layer 310 on the wall of via 200, the deposited material prematurely forms a closed structure at the opening or a specific location of the via 200 before the target area is fully filled or reaches the expected deposition state. For example, when the semiconductor device 10 is a memory and the conductive layer 310 is part of an electrode, during the deposition of via 200, the filling rate at the top of via 200 is usually faster, while the filling rate at the bottom of via 200 is usually slower. Before the bottom of via 200 is completely filled, the top of via 200 is sealed by the deposited material, forming premature sealing of via 200, thereby creating voids or defects at the bottom of via 200.

[0090] During the deposition of conductive materials onto vias 200, step coverage variation is a common problem. Step coverage variation refers to the difference in coverage uniformity between different parts of a step when depositing on a surface with steps or morphological changes. In this application, this corresponds to the difference in coverage uniformity between different regions of the via wall when depositing on it. The following example illustrates the step coverage variation in detail using a specific deposition method:

[0091] For example, the conductive layer 310 in step S300 is prepared using chemical vapor deposition (CVD). CVD mainly relies on the chemical reaction of gaseous reactants on the pore walls of the via 200 to generate solid deposits. During the preparation process, the gaseous reactants first diffuse to the pore walls of the via 200, and then undergo adsorption, reaction, and desorption steps. However, due to the long diffusion path in the via 200, the concentration of the gaseous reactants gradually decreases along the first direction, resulting in a lower deposition rate at the bottom of the via 200 than at the top. This causes the thickness of the conductive layer 310 to gradually decrease along the first direction, meaning that the step coverage varies in different regions of the pore wall of the via 200. In the method provided in this embodiment, during the formation of the conductive layer 310, a target reagent is introduced into the via 200. The target reagent can adjust the different formation rates of the conductive layer 310 in different regions of the pore wall, causing the thickness of the conductive layer 310 to gradually increase along the first direction.

[0092] For another example, the conductive layer 310 in step S300 is prepared using physical vapor deposition (PVD). The particles generated by PVD typically have high energy and directionality. During the preparation process, these ions usually transport along a first direction, thus they tend to deposit at the opening of the via 200 rather than reaching its depth. This results in a lower deposition rate at the bottom of the via 200 compared to the top, causing the thickness of the conductive layer 310 to gradually decrease along the first direction. In other words, the step coverage varies in different regions of the via wall. However, in the method provided in this embodiment, during the formation of the conductive layer 310, a target reagent is introduced into the via 200. This target reagent can adjust the different formation rates of the conductive layer 310 in different regions of the via wall, causing the thickness of the conductive layer 310 to gradually increase along the first direction.

[0093] For example, the conductive layer 310 in step S300 is prepared using atomic layer deposition (ALD). ALD mainly achieves precise growth of the conductive layer 310 by controlling the pulse time and cycle number of the precursor. However, when the process conditions are not suitable, the deposition rate at the bottom of the via 200 may be lower than that at the top of the via 200, resulting in the thickness of the conductive layer 310 gradually decreasing along the first direction, i.e., the step coverage of different regions on the via wall of the via 200 varies. In the method provided in this application embodiment, during the formation of the conductive layer 310, a target reagent is introduced into the via 200. The target reagent can adjust the different formation rates of the conductive layer 310 on different regions of the via wall, so that the thickness of the conductive layer 310 gradually increases along the first direction.

[0094] In this embodiment, the top and bottom of the via 200 are arranged sequentially along a first direction. For example, refer to... Figure 3 and Figure 4 When via 200 is a blind via, the top of via 200 is the opening area of ​​the blind via, and the bottom of via 200 is the bottom area of ​​the blind via. For example, refer to... Figure 5 When via 200 is a through hole, the top of via 200 is the area for forward deposition (the area away from the support plate A), and the bottom of via 200 is the area for backward deposition (the area close to the support plate A).

[0095] In the embodiments of this application, "the thickness of A generally shows a trend of gradually decreasing / gradually increasing along the first direction" means that when the thickness of A is observed and measured along the first direction, it generally exhibits a trend of gradually decreasing / gradually increasing thickness. However, this decrease / increase is not a strictly monotonically decreasing / monotonically increasing trend. For example, in the first direction, the thickness measurement value of most areas of A decreases sequentially. Only in certain small areas may the thickness value increase slightly or remain unchanged, but these local changes do not affect the overall trend of gradually decreasing thickness.

[0096] In the embodiments of this application, "the thickness of A remains substantially constant along the first direction" means that when the thickness of A is observed and measured along the first direction, it generally exhibits a state of constant thickness, but this constant thickness is not strictly speaking flush.

[0097] In some embodiments, reference Figure 3 In (3), the target reagent includes inhibitor 400, and the concentration of inhibitor 400 gradually decreases along the first direction.

[0098] During the formation of the conductive layer 310, an inhibitor 400 is introduced into the via 200. Treating the conductive layer 310 with the inhibitor 400 allows for control of the growth rate of the conductive layer 310 in different regions of the via wall, enabling differentiated growth of the conductive layer 310 in these regions. Furthermore, as the concentration of the inhibitor 400 gradually decreases along the first direction, the inhibitory effect on the conductive layer 310 gradually weakens along the same direction. Regions with strong inhibitory effects exhibit slower growth rates of the conductive layer 310, while regions with weak inhibitory effects show faster growth rates. This facilitates a gradual increase in the thickness of the conductive layer 310 along the first direction.

[0099] Furthermore, the strength of the inhibition effect is generally proportional to the quality of the conductive layer 310. This is because treating the via wall of the via 200 with inhibitor 400 reduces defects and impurities in the conductive layer 310. Regions of the conductive layer 310 with a stronger inhibition effect exhibit better crystallinity, purity, and density, thereby improving the electrical, mechanical, and stability properties of the conductive layer 310. Therefore, treating the via wall of the via 200 with inhibitor 400 can improve the electrical, mechanical, and stability properties of the conductive layer 310, especially significantly improving the electrical, mechanical, and stability properties of the conductive layer 310 on top of the via 200.

[0100] In some examples, the type of inhibitor 400 can be selected based on the raw materials used to prepare the conductive layer 310. For example, when the material of the conductive layer 310 is tungsten W, the first precursor is a tungsten-containing precursor (e.g., tungsten hexafluoride WF6), and the second precursor is a reducing agent (hydrogen H2), the corresponding inhibitor 400 can be bis(dimethylamino)dimethylsilane (C6H2O). 18 N2Si, also known as a BDMADMS inhibitor. For example, when the conductive layer 310 is made of copper (Cu), the first precursor is an organocopper compound (e.g., copper acetylacetonate Cu(acac)2), and the second precursor is a reducing agent (hydrogen H2), the corresponding inhibitor 400 can be a BDMADMS inhibitor. This application does not limit the specific type of inhibitor 400; those skilled in the art can select one according to the actual situation.

[0101] In some embodiments, reference Figure 4 (3) and Figure 5 In (3), the target reagent includes etchant 500, and the concentration of etchant 500 gradually decreases along the first direction.

[0102] During the formation of the conductive layer 310, an etchant 500 is introduced into the via 200. By treating the conductive layer 310 with the etchant 500, the etching degree of the conductive layer 310 in different areas of the via wall can be controlled, thereby controlling the thickness of the conductive layer 310 in different areas of the via wall. Furthermore, since the concentration of the etchant 500 gradually decreases along the first direction, the etching effect of the etchant 500 on the conductive layer 310 gradually weakens along the first direction. Areas with a strong etching effect can etch away more material of the conductive layer 310; areas with a weak etching effect can etch away less material of the conductive layer 310. This facilitates a gradual increase in the thickness of the conductive layer 310 along the first direction.

[0103] In some examples, the type of etchant 500 used in the etching process can be selected based on the raw materials used to prepare the conductive layer 310.

[0104] For example, when the conductive layer 310 is made of tungsten (W), the first precursor is a tungsten-containing precursor (e.g., tungsten hexafluoride WF6), and the second precursor is a reducing agent (hydrogen H2), the corresponding etchant 500 can be sulfur hexafluoride (SF6) etchant. As another example, when the conductive layer 310 is made of copper (Cu), the first precursor is an organic copper compound (e.g., copper acetylacetonate Cu(acac)2), and the second precursor is a reducing agent (hydrogen H2), the corresponding etchant 500 can be sulfur hexafluoride etchant. This application does not limit the specific type of etchant 500; those skilled in the art can select it according to actual circumstances.

[0105] Figure 6The flowcharts for fabricating other semiconductor devices provided in the embodiments of this application are shown.

[0106] In some embodiments, reference Figure 6 Step S300 may include:

[0107] S1: The first sublayer of the conductive layer is formed on the wall of the via.

[0108] In this step, a first sub-layer of conductive layer 310 is formed on the hole wall of via 200 using current deposition or other methods, and the thickness of the first sub-layer of conductive layer 310 shows a trend of gradually decreasing along the first direction.

[0109] In some embodiments, the first sublayer of the conductive layer 310 is formed in step S1 by means of chemical vapor deposition, physical vapor deposition, or atomic layer deposition, etc.

[0110] In some embodiments, before step S1, step S300 further includes:

[0111] S4: Introduce the second target reagent into the through hole.

[0112] In this step, refer to Figures 3 to 5 In step (1), before forming the conductive layer 310 on the hole wall, the hole wall is treated with a second target reagent. The second target reagent can adjust the different formation rates of the first sublayer of the conductive layer 310 in different regions of the hole wall. The target reagent includes a second target reagent, which includes an inhibitor 400. The description of the inhibitor 400 in the second target reagent can be referred to the inhibitor 400 in the target reagent in the foregoing embodiment.

[0113] The following example provides a detailed explanation of the effect of step S4 (hereinafter referred to as the second inhibition treatment):

[0114] In some examples, reference Figure 3 In (2), the second inhibition treatment has a larger inhibition gradient along the first direction. The inhibition effect of the first sublayer of the conductive layer 310 on the top wall of the via 200 is significantly greater than that of the first sublayer of the conductive layer 310 on the bottom wall of the via 200. After the second inhibition treatment of the via wall of the via 200 is performed using the second target reagent, the first sublayer of the conductive layer 310 can show that the thickness of the first sublayer of the conductive layer 310 generally shows a gradually increasing trend along the first direction.

[0115] In other examples, the second suppression treatment has a moderate suppression gradient along the first direction. The suppression effect of the first sublayer of the conductive layer 310 on the top wall of the via 200 is moderately greater than that of the first sublayer of the conductive layer 310 on the bottom wall of the via 200. After the second suppression treatment of the via wall of the via 200 with the second target reagent, the first sublayer of the conductive layer 310 can exhibit that, along the first direction, the thickness of the first sublayer of the conductive layer 310 remains approximately unchanged.

[0116] In yet another example, refer to Figure 4 (2) and Figure 5 In (2), the second inhibition treatment has a smaller inhibition gradient along the first direction. The inhibition effect of the first sublayer of the conductive layer 310 on the top wall of the via 200 is slightly greater than that of the first sublayer of the conductive layer 310 on the bottom wall of the via 200. After the second inhibition treatment is performed on the wall of the via 200 using the second target reagent, the first sublayer of the conductive layer 310 can show that, along the first direction, the thickness of the first sublayer of the conductive layer 310 generally shows a gradually decreasing trend.

[0117] In other words, by controlling the effect of the second inhibition treatment, the thickness distribution of the first sublayer of the conductive layer 310 can be controlled. This application does not impose any special limitations on the effect of the second inhibition treatment on the second target reagent; those skilled in the art can freely choose the appropriate effect of the second inhibition treatment according to actual needs.

[0118] S2: Introduce a first target reagent into the via, the first target reagent including inhibitor and / or etchant.

[0119] In this step, the target reagent in step S300 includes a first target reagent, which includes an inhibitor and / or an etchant. After the first sublayer of the conductive layer 310 is formed on the hole wall, the first target reagent is introduced into the via 200. The first target reagent can adjust the different formation rates of the first sublayer of the conductive layer 310 in different regions of the hole wall, so as to achieve a gradual increase in the thickness of the first sublayer of the conductive layer 310 along the first direction.

[0120] refer to Figure 3 In (3) and (4), when the first target reagent is inhibitor 400, the first sublayer of conductive layer 310 is treated with inhibitor 400, which can be called the first inhibition treatment; the inhibitor 400 in the first inhibition treatment can control the growth rate of the first sublayer of conductive layer 310 in different regions of the pore wall, so as to achieve a gradual increase in the thickness of the first sublayer of conductive layer 310 along the first direction. Reference Figure 4 and Figure 5In (3) and (4), when the first target reagent is etchant 500, the first sub-layer of the conductive layer 310 is treated with etchant 500, which can be called etching treatment; the etchant 500 in the etching treatment can control the etching degree of the first sub-layer of the conductive layer 310 in different areas of the hole wall, so as to realize that the thickness of the first sub-layer of the conductive layer 310 gradually increases along the first direction.

[0121] In some embodiments, the conductive layer 310 is prepared by atomic layer deposition, comprising the following steps: (1) introducing a first precursor into the deposition reaction chamber, the first precursor adsorbing onto the inner wall of the via 200 in molecular form to form a monolayer; introducing an inert gas to purge the deposition reaction chamber to remove the first precursor and other byproducts that did not participate in the reaction; (2) after purging, introducing a second precursor into the deposition reaction chamber, the second precursor reacting with the first precursor to obtain the conductive layer 310; introducing an inert gas to purge the deposition reaction chamber to remove the second precursor and other byproducts that did not participate in the reaction; (3) introducing an inhibitor 400 and / or an etchant 500 into the deposition reaction chamber, the concentration of the inhibitor 400 and / or the etchant 500 gradually decreasing along a first direction.

[0122] Using atomic layer deposition (ALD), only one atomic layer can typically be obtained in a single deposition. Therefore, after the reaction of the second and first precursors, the deposition reaction chamber can be purged with an inert gas, and step S2 can be repeated multiple times to obtain the conductive column 600.

[0123] In some examples, when step S1 is repeated multiple times, the first sublayer of the conductive layer 310 prepared in the previous step S1 can be treated with the first target reagent before the next cycle of step S1. Of course, the treatment can be performed before a portion of the S1 cycles, or before all of the S1 cycles. In this way, multiple treatments with the first target reagent can further improve the filling density and uniformity of the conductive pillars 600 in the via 200.

[0124] In other words, the first target reagent can be used for multiple treatments according to actual needs to maximize the filling density and uniformity of the conductive column 600. This application does not limit the specific number of treatments in its embodiments.

[0125] In some examples, the descriptions of the inhibitor 400 and etchant 500 in the first target reagent can be found in the descriptions of the inhibitor 400 and etchant 500 in the aforementioned target reagent.

[0126] S3: A second sublayer, which forms a conductive layer, is formed on the side of the first sublayer away from the hole wall.

[0127] In this step, a second sublayer of the conductive layer 310 is formed on the side of the first sublayer away from the hole wall using current deposition or other methods. Alternatively, the second sublayer can be treated with the first target reagent.

[0128] Figure 7 This is a schematic diagram of the structure for fabricating some semiconductor devices 10 according to an embodiment of this application.

[0129] In some embodiments, reference Figure 7 Step S300 may include:

[0130] S10: Introduce a third target reagent, including an inhibitor, into the well.

[0131] In this step, refer to Figure 7 In (1), the target reagent includes a third target reagent, which includes an inhibitor 400. Before the conductive layer 310 is formed on the hole wall, the third target reagent is introduced into the via 200. The third target reagent can adjust the different formation rates of the conductive layer 310 in different regions of the hole wall.

[0132] For a description of the inhibitor 400 in the third target reagent, please refer to the inhibitor 400 in the aforementioned target reagent.

[0133] S20: A first sub-layer of a conductive layer is formed on the wall of the via, and the thickness of the first sub-layer of the conductive layer gradually increases along the first direction.

[0134] In this plan, refer to Figure 7 In (1) and (2), before the first sublayer of the conductive layer 310 is formed, the hole wall is treated with a third target reagent. The result of the treatment is that the thickness of the first sublayer of the conductive layer 310 gradually increases along the first direction.

[0135] In some embodiments, an atomic layer deposition method is used to prepare the conductive layer 310. The preparation method may include the following steps: (1) introducing a third target reagent into the deposition reaction chamber, so that the concentration of the third target reagent gradually decreases along a first direction; introducing an inert gas to purge the deposition reaction chamber (also known as purging); (2) introducing a first precursor into the deposition reaction chamber (the introduction process can also be called pulse purging), the first precursor will be adsorbed on the inner wall of the via 200 in molecular form to form a monolayer; introducing an inert gas to purge the deposition reaction chamber (also known as purging) to remove the first precursor and other byproducts that have not participated in the reaction; (3) after purging, introducing a second precursor into the deposition reaction chamber, the second precursor will react with the first precursor to obtain the conductive layer 310.

[0136] It needs to be explained that, in Figures 3 to 5 , Figure 7 In this design, neither the first nor the second sublayer is presented; instead, a conductive layer 310 and a conventional conductive layer 320 are presented.

[0137] S30: A second sublayer of conductive layer is formed on the wall of the via.

[0138] In some embodiments, reference Figures 3 to 5 (5) and (6) in the middle, and Figure 7 In steps (3) and (4), a conventional conductive layer 320 is formed on the side of the conductive layer 310 away from the hole wall to obtain a conductive pillar 600 that penetrates the via 200. Thus, the conductive pillar 600 has excellent density and uniformity.

[0139] Figure 8 A schematic diagram of the structure for fabricating some semiconductor devices 10.

[0140] In other embodiments, reference is made to... Figure 8 In step (1), conductive material is continuously filled into the via 200 using methods such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition to prepare a conductive pillar 600 in the via 200, that is, the conductive pillar 600 is directly formed in the via 200 using the aforementioned deposition method. The following risks may arise:

[0141] As the foregoing analysis shows, filling via 200 with conductive material using methods such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition results in the conductive layer 310 at the top of via 200 always being thicker than the conductive layer 310 at the bottom. Therefore, if this method is continuously used to fill via 200 with conductive material, it is highly likely that there will be excessive conductive material in the top region of via 200, causing the via 200 to close prematurely while the bottom region remains unfilled. (Refer to...) Figure 8 In (2), there will be a large number of uncontrolled and unevenly distributed holes at the bottom of the via 200.

[0142] For example, in this embodiment, the semiconductor device 10 serves as a memory, and the conductive post 600 serves as the first electrode in the memory. The first electrode prepared using the aforementioned method has a large number of uncontrolled and unevenly distributed voids, which severely damage the original good structure of the first electrode. On the one hand, the voids greatly reduce the structural stability of the first electrode, making it more susceptible to external interference and failure during operation, resulting in poor memory reliability. This increases the risk of data loss or errors and significantly shortens the lifespan of the memory. On the other hand, the voids hinder the smooth transmission of current, reduce the conductivity of the first electrode, severely impair the memory's storage performance, and reduce the accuracy and efficiency of data storage.

[0143] Figure 9 Cross-sectional views of some semiconductor devices 10 provided in the embodiments of this application; Figure 10 A top view of some semiconductor devices 10 provided in the embodiments of this application.

[0144] In some embodiments, reference Figure 9 and Figure 10 Before forming the conductive layer 310 within the via 200, the method for fabricating the semiconductor device 10 further includes: sequentially forming an electrode layer 700 and a ferroelectric layer 800 on the via wall of the via 200; forming the conductive layer 310 within the via 200 includes: forming the conductive layer 310 on the side of the ferroelectric layer 800 away from the electrode layer 700. In this embodiment, the semiconductor device 10 is a ferroelectric memory, the conductive pillar 600 is a first electrode in the ferroelectric memory, the electrode layer 700 is a second electrode in the ferroelectric memory, and the ferroelectric layer 800 is a ferroelectric layer in the ferroelectric memory. Furthermore, the stacked structure 100 can be a structure formed by periodically stacking silicon oxide layers and silicon nitride layers.

[0145] The first electrode (conductive post 600) is usually made of a different material than the ferroelectric layer 800. This difference in materials leads to a difference in their coefficients of thermal expansion. When the temperature changes, the first electrode and the ferroelectric layer 800 will expand or contract to different degrees due to their different coefficients of thermal expansion. Furthermore, because the first electrode and the ferroelectric layer 800 are in direct contact, any structural deformation of the first electrode will directly affect the ferroelectric layer 800, meaning that the first electrode will apply stress to the ferroelectric layer 800.

[0146] As the foregoing analysis shows, the first electrode (conductive post 600) fabricated using the current process has a large number of uncontrolled and unevenly distributed voids or defects. The presence of these voids or defects disrupts the continuity and uniformity of the first electrode, and these areas become stress concentration zones, effectively worsening the stress conditions between the first electrode and the ferroelectric layer 800. This leads to at least one of the following problems: First, the poor stress distribution affects the polarization characteristics of the ferroelectric layer 800, resulting in a decrease in the storage capacity and data read / write accuracy of the ferroelectric memory; second, the poor stress distribution affects the structural stability of the ferroelectric memory, reducing its performance stability during long-term use and shortening its lifespan; third, the presence of numerous voids or defects in the first electrode increases its resistivity, affecting the performance of the ferroelectric memory. The semiconductor device 10 (ferroelectric memory) prepared in this embodiment is less prone to defects such as voids and flaws in its first electrode (conductive post 600). It also exhibits a superior stress distribution between the first electrode and the ferroelectric layer, resulting in superior density and uniformity, as well as better performance stability and lifespan. The method for preparing the semiconductor device 10 provided in this embodiment improves the yield of ferroelectric memory preparation, enabling efficient and low-cost manufacturing of a new generation of stable, high-performance, high-density ferroelectric memories.

[0147] In some embodiments, the material of the ferroelectric layer 800 includes hafnium-based ferroelectric materials, such as zirconium hafnium oxide (HfZrO4, HZO). The ferroelectric layer 800 in this embodiment can also be referred to as a hafnium-based ferroelectric layer, and the ferroelectric memory corresponding to the hafnium-based ferroelectric material can be referred to as a hafnium-based ferroelectric memory.

[0148] Hafnium-based ferroelectric materials, with their unique material properties, endow ferroelectric memories containing them with many significant advantages. These ferroelectric memories feature high read / write speeds, non-volatility, and low power consumption, and are compatible with complementary metal-oxide-semiconductor (CMOS) fabrication processes, making them a promising candidate for next-generation high-performance memory devices.

[0149] However, hafnium-based ferroelectric materials are stress-sensitive ferroelectric materials, and stress has a greater impact on the hafnium-based ferroelectric layer compared to other materials. When the first electrode (conductive post 600) of the ferroelectric memory has a large number of holes, defects, and other defects, the performance stability of the first electrode will be greatly reduced. The instability of the first electrode will directly affect the hafnium-based ferroelectric layer. Since hafnium-based ferroelectric materials are stress-sensitive ferroelectric materials, the hafnium-based ferroelectric layer is highly susceptible to stress, resulting in a significant deterioration in the performance stability of the ferroelectric layer and a significant shortening of the service life of the hafnium-based ferroelectric memory. In contrast, the semiconductor device 10 (hafnium-based ferroelectric memory) prepared in the embodiments of this application is less prone to holes and defects in the first electrode (conductive post 600), and the hafnium-based ferroelectric layer has superior performance stability, which is beneficial to improving the service life of the ferroelectric memory. In short, the method for preparing the semiconductor device 10 provided in the embodiments of this application is particularly suitable for semiconductor devices 10 corresponding to hafnium-based ferroelectric materials.

[0150] In some embodiments, the thickness of the ferroelectric layer 800 is 3 nanometers to 20 nanometers, for example, 3 nanometers, 3 nanometers, 5 nanometers, 8 nanometers, 12 nanometers, 15 nanometers, or 20 nanometers. In some embodiments, the method of forming the ferroelectric layer 800 on the hole wall of the electrode layer 700 away from the via 200 includes one or more of chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In some embodiments, a functional intercalation layer may be provided between the ferroelectric layer 800 and the first electrode; a functional intercalation layer may also be provided between the ferroelectric layer 800 and the second electrode. The functional intercalation layer may be niobium oxide / titanium oxide (NbO / TiO), etc., and the thickness of the functional intercalation layer may be 1 nanometer to 5 nanometers, for example, 1 nanometer, 2 nanometers, 3 nanometers, 4 nanometers, or 5 nanometers.

[0151] In some embodiments, the electrode layer 700 may be made of one or more of titanium nitride (TiN), silver (Ag), gold (Au), and tungsten. Thus, the electrode layer 700 exhibits excellent chemical stability and conductivity, and can be used as a second electrode in a ferroelectric memory. In some embodiments, the method for forming the electrode layer 700 on the wall of the via 200 includes one or more of chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0152] Figure 11 Top view of some other semiconductor devices 10 provided in the embodiments of this application. Figure 12 A top view of some semiconductor devices 10; Figure 13 This is a top view of some other semiconductor devices 10. Among them, Figures 11 to 13 The filling gas flow is not part of the semiconductor device 10. The filling gas flow can be used to clean components such as the first electrode (conductive pillar 600), the ferroelectric layer 800, and the second electrode (electrode layer 700).

[0153] In some embodiments, reference Figure 11 In the stacked structure 100, a plurality of vias 200 are formed along a first direction, and the plurality of vias 200 are arranged in close packing. When the semiconductor device 10 is used as a ferroelectric memory, the ferroelectric memory includes a plurality of memory cells, and the memory cells can store one bit or more bits of data; a single memory cell may include a first electrode, a ferroelectric layer 800, a second electrode within a single via 200, and may also include other components.

[0154] As the foregoing analysis shows, the first electrode (conductive post 600) fabricated using the current process has numerous uncontrolled and unevenly distributed voids or defects, resulting in poor continuity and uniformity. Furthermore, the direct contact between the first electrode and the ferroelectric layer 800 contributes to the poor continuity and uniformity of the ferroelectric layer 800. Consequently, the multiple memory cells within the ferroelectric memory exhibit significant differences, leading to poor uniformity and negatively impacting data storage and retrieval, reliability and stability, device performance, and lifespan.

[0155] In the semiconductor device 10 (ferroelectric memory) prepared in the embodiments of this application, the first electrode (conductive post 600) is less prone to defects such as holes and flaws. The differences between multiple memory cells in the ferroelectric memory are small, and the uniformity of the ferroelectric memory is better, which can improve the performance stability, reliability and service life of the ferroelectric memory.

[0156] In other embodiments, reference is made to Figure 12 The semiconductor device 10 (ferroelectric memory) has a plurality of vias 200 along a first direction, and the plurality of vias 200 are arranged in a non-close-packed manner. Since the plurality of vias 200 in the semiconductor device 10 are arranged in a non-close-packed manner, the number of non-close-packed vias 200 is lower than the number of close-packed vias 200 in the same setting area. As a result, the number of memory cells in the ferroelectric memory is reduced, thereby reducing the memory performance of the ferroelectric memory.

[0157] In contrast, in the method for preparing a semiconductor device 10 (ferroelectric memory) provided in the embodiments of this application, the multiple vias 200 are arranged in close packing, and the ferroelectric memory has a larger number of memory cells, which can improve the storage performance of the ferroelectric memory.

[0158] In the embodiments of this application, a non-closely packed distribution refers to a spatial arrangement where the multiple vias 200 are relatively loosely spaced, with large intervals or gaps between different vias 200. A closely packed distribution refers to a spatial arrangement where the multiple vias 200 are relatively tightly spaced, with small intervals or gaps between different vias 200.

[0159] In other embodiments, reference is made to Figure 13The semiconductor device 10 (ferroelectric memory) has a plurality of vias 200 along a first direction, the plurality of vias 200 being arranged in a non-close-packed manner, and the conductive pillars 600 in the plurality of vias 200 having a small cross-section. For example, the vias 200 are cylindrical, and the larger the critical dimension (CD) of the vias 200, the smaller the cross-section of the conductive pillars 600.

[0160] During the filling process, the size of the via 200 is generally inversely proportional to the filling difficulty; that is, the larger the size of the via 200, the easier the filling is, and the smaller the size of the via 200, the more difficult the filling is. As a result, since the cross-section of the conductive post 600 in this scheme is small, it will further increase the difficulty of depositing the conductive post 600.

[0161] Furthermore, if the cross-section of the conductive pillar 600 is set to be large to reduce the difficulty of depositing the conductive pillar 600, the conductive pillar 600 will occupy the position of the ferroelectric layer, thereby causing a significant reduction in the storage density of the ferroelectric memory.

[0162] In the method for preparing the semiconductor device 10 (ferroelectric memory) provided in the embodiments of this application, the cross-section of the conductive pillar 600 can be ensured to be moderate and the deposition difficulty of the conductive pillar 600 is low. Under the premise that the ferroelectric memory has a better storage density, the difficulty of preparing the conductive pillar 600 can be reduced.

[0163] In other embodiments, the semiconductor device 10 (ferroelectric memory) has a plurality of vias 200 along a first direction, with a large pitch between adjacent vias. This reduces the difficulty of filling, but results in less data in the vias, leading to a significant decrease in the storage density of the ferroelectric memory.

[0164] Figure 14 and Figure 15 This is a schematic diagram of the structure of some apparatuses for fabricating semiconductor devices 10 provided in the embodiments of this application.

[0165] This application provides an apparatus for fabricating a semiconductor device 10, with reference to... Figure 14 The device includes a first conduit 1100 and a second conduit 1200; the first conduit 1100 is configured to direct to... Figure 3 The via 200 in the middle supplies conductive material, which is used to form such as Figure 3 The conductive layer 310 in the middle; the second channel 1200 is configured to supply the target reagent to the via 200 along the first direction, and the target reagent will control the conductive layer 310 on different regions of the via wall to grow differentially, so that the thickness of the conductive layer 310 gradually increases along the first direction.

[0166] Conductive material is supplied to the via 200 along a first direction through a first conduit 1100. The conductive material is deposited on the via wall of the via 200 to form a conductive layer 310, the thickness of which gradually decreases along the first direction. A target reagent is supplied to the via 200 along the first direction through a second conduit 1200. The target reagent controls the differentiated growth of the conductive layer 310 in different regions of the via wall, causing the thickness of the conductive layer 310 to gradually increase along the first direction. Furthermore, the conductive material can also be used to form a conductive layer 310 on the side of the conductive layer 310 away from the via wall, such as... Figure 3 The conventional conductive layer 320 has a thickness that gradually decreases along the first direction. As a result, the semiconductor device 10 fabricated by the aforementioned apparatus is less prone to defects such as voids and pores, exhibiting superior performance and lifespan. Furthermore, the aforementioned apparatus only requires the addition of a second conduit 1200 for supplying the target reagent to a conventional fabrication apparatus, making it highly compatible with current conventional fabrication equipment and possessing significant market potential.

[0167] In some examples, the apparatus for fabricating the semiconductor device 10 further includes a conductive material receiving region 1100a, which is connected to a first conduit 1100, through which conductive material in the conductive material receiving region 1100a can be conveyed to a via 200. In some examples, the apparatus for fabricating the semiconductor device 10 further includes a target reagent receiving region 1200a, which is connected to the first conduit 1100, through which target reagent in the target reagent receiving region 1200a can be conveyed to a via 200 via a second conduit 1200.

[0168] The conductive material receiving area 1100a and the target reagent receiving area 1200a may be integrated into the aforementioned device or may not be integrated into the aforementioned device. In other words, the conductive material receiving area 1100a and the target reagent receiving area 1200a may exist as part of the aforementioned device or as an external supply device other than the aforementioned device.

[0169] In some embodiments, the target reagent includes inhibitor 400 and / or etchant 500. For a description of inhibitor 400 and etchant 500, please refer to the foregoing embodiments, and will not be repeated here.

[0170] Furthermore, when the second conduit 1200 is used to supply the inhibitor 400 and / or the etchant 500, the apparatus can implement the first method for fabricating the semiconductor device 10. When the second conduit 1200 is used to supply the inhibitor 400, the apparatus can implement the second method for fabricating the semiconductor device 10.

[0171] In some embodiments, reference Figure 15The apparatus for fabricating the semiconductor device 10 further includes a third conduit 1300 and a fourth conduit 1400; the third conduit 1300 is configured to supply electrode material to the via 200, the electrode material being used to form, for example, on the wall of the via 200. Figure 9 Electrode layer 700; fourth conduit 1400 is configured to supply ferroelectric material to via 200, the ferroelectric material being used to form on electrode layer 700 such as Figure 9 The ferroelectric layer in the middle is 800.

[0172] Electrode material is supplied to via 200 through a third conduit 1300, and the electrode material can be deposited on the wall of via 200 to form an electrode layer 700; ferroelectric material is supplied to via 200 through a fourth conduit 1400, and the ferroelectric material can be deposited on the electrode layer to form a ferroelectric layer 800; thus, the semiconductor device 10 fabricated using this device can be used as a ferroelectric memory. A description of the semiconductor device 10 as a ferroelectric memory can be found in the first aspect, and will not be repeated here.

[0173] In some examples, the apparatus for fabricating the semiconductor device 10 further includes an electrode material receiving region 1300a, which is connected to a third conduit 1300, through which electrode material in the electrode material receiving region 1300a can be transported to a via 200. In some examples, the apparatus for fabricating the semiconductor device 10 further includes a ferroelectric material receiving region 1400a, which is connected to the third conduit 1300, through which ferroelectric material in the ferroelectric material receiving region 1400a can be transported to a via 200 via a fourth conduit 1400.

[0174] The electrode material receiving region 1300a and the ferroelectric material receiving region 1400a may be integrated into the aforementioned device or may not be integrated into the aforementioned device. In other words, the electrode material receiving region 1300a and the ferroelectric material receiving region 1400a may exist as part of the aforementioned device or as an external supply device other than the aforementioned device.

[0175] In some embodiments, reference Figure 14 and Figure 15 The apparatus for fabricating the semiconductor device 10 also includes a fabrication region 2000, in which the process of fabricating the semiconductor device 10 can be completed. In some examples, refer to... Figure 14 The preparation region 2000 can be connected to the first channel 1100 and the second channel 1200. In some examples, refer to... Figure 15 The preparation area 2000 can be connected to the first channel 1100, the second channel 1200, the third channel 1300, and the fourth channel 1400.

[0176] In some embodiments, the ferroelectric material includes hafnium-based ferroelectric materials. For a description of hafnium-based ferroelectric materials, please refer to the foregoing embodiments; further details will not be repeated here.

[0177] Although this application has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made thereto without departing from the spirit and scope of this application. Accordingly, this specification and drawings are merely exemplary illustrations of this application as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of this application. Clearly, those skilled in the art can make various alterations and modifications to this application without departing from the spirit and scope of this application. Thus, if such modifications and modifications of this application fall within the scope of the claims of this application and their equivalents, this application is also intended to include such modifications and modifications.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A stacked structure is provided for fabricating the semiconductor device; A via is formed in the stacked structure along the first direction; A conductive layer is formed on the wall of the via; wherein, during the formation of the conductive layer, a target reagent is introduced into the via, causing the thickness of the conductive layer to gradually increase along the first direction.

2. The method according to claim 1, characterized in that, The target reagent includes an inhibitor, the concentration of which gradually decreases along the first direction.

3. The method according to claim 1 or 2, characterized in that, The target reagent includes an etchant, the concentration of which gradually decreases along the first direction.

4. The method according to any one of claims 1-3, characterized in that, Before forming the conductive layer on the wall of the via, the method further includes: sequentially forming an electrode layer and a ferroelectric layer on the wall of the via; Forming the conductive layer on the wall of the via includes forming the conductive layer on the side of the ferroelectric layer away from the electrode layer.

5. The method according to claim 4, characterized in that, The ferroelectric layer is made of hafnium-based ferroelectric material.

6. The method according to claim 4 or 5, characterized in that, A plurality of vias are formed in the stacked structure along the first direction, and the plurality of vias are arranged in a close-packed manner.

7. The method according to any one of claims 1-6, characterized in that, The first target reagent in the target reagent includes an inhibitor and / or an etchant; The conductive layer is formed on the wall of the via, comprising: A first sub-layer of the conductive layer is formed on the wall of the via; The first target reagent is introduced into the through hole; A second sublayer of the conductive layer is formed on the side of the first sublayer away from the hole wall.

8. The method according to claim 7, characterized in that, The second target reagent in the target reagent includes an inhibitor; Before forming the first sublayer of the conductive layer, the method further includes: The second target reagent is introduced into the through hole.

9. An apparatus for fabricating a semiconductor device, characterized in that, include: A first conduit is configured to supply conductive material to a via along a first direction, the conductive material being used to form a conductive layer; The second conduit is configured to supply the target reagent to the via along the first direction, such that the thickness of the conductive layer gradually increases along the first direction.

10. The apparatus according to claim 9, characterized in that, The target reagent includes inhibitors and / or etching agents.

11. The apparatus according to claim 9 or 10, characterized in that, The device further includes: A third conduit is configured to supply electrode material to the via, the electrode material being used to form an electrode layer on the wall of the via; A fourth conduit is configured to supply ferroelectric material to the via, the ferroelectric material being used to form a ferroelectric layer on the electrode layer.

12. The apparatus according to claim 11, characterized in that, The ferroelectric materials include hafnium-based ferroelectric materials.

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